DEMO MANUAL DC1370A LTC2262-14/-12, LTC2261-14/-12, LTC2260-14/-12, LTC2259-14/-12, LTC2258-14/-12, LTC2257-14/-12, LTC2256-14/-12, 14-/12-Bit, 25Msps to 150Msps ADCs DeScriPtion Demonstration circuit 1370A supports a family of 14-/12-Bit Several versions of the 1370A demo board supporting the 25Msps to 150Msps ADCs. Each assembly features one LTC2262 14-/12-Bit series of A/D converters are listed in of the following devices: LTC2262-14, LTC2262-12 Table 1. Depending on the required resolution and sample LTC2261-14, LTC2261-12, LTC2260-14, LTC2260-12, rate, the DC1370A is supplied with the appropriate ADC. LTC2259-14, LTC2259-12, LTC2258-14, LTC2258-12, The circuitry on the analog inputs is optimized for analog LTC2257-14, LTC2257-12, LTC2256-14, LTC2256-12, high input frequencies from 5MHz to 170MHz. Refer to the speed, high dynamic range ADCs. data sheet for proper input networks for different input frequencies. Demonstration circuit 1370A supports the LTC2262 family full rate CMOS, and DDR CMOS output mode. This family Design files for this circuit board are available at of ADCs is also supported by demonstration circuit 1369, http://www.linear.com/demo which is compatible with DDR LVDS output modes. L, LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks and QuikEval and PScope are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Performance Summary (T = 25°C) A PARAMETER CONDITIONS VALUE Supply Voltage – DC1370A Depending on Sampling Rate and the A/D Converter Optimized for 3.6V Provided, this Supply Must Provide up to 150mA [3.5V ⇔ 6.0V Min/Max] Analog Input Range Depending on SENSE Pin Voltage 1V to 2V P-P P-P Logic Input Voltages Minimum Logic High 1.3V Maximum Logic Low 0.6V Logic Output Voltages (OV = 1.8V)) Minimum High Level Output Voltage 1.750V (1.790V Typical) DD Maximum Low Level Output Voltage 0.050V (0.010V Typical) Sampling Frequency (Convert Clock Frequency) See Table 1 Convert Clock Level Single-Ended Encode Mode (ENC – Tied to GND) 0V to 3.6V Convert Clock Level Differential Encode Mode (ENC – Not Tied to GND) 0.2V to 3.6V Resolution See Table 1 Input Frequency Range See Table 1 SFDR See Applicable Data Sheet SNR See Applicable Data Sheet dc1730afa 1

DEMO MANUAL DC1370A Quick Start ProceDure Table 1. DC1370A Variants DC1370A VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY 1370A-A LTC2261-14 14-Bit 125Msps 5MHz to 170MHz 1370A-B LTC2260-14 14-Bit 105Msps 5MHz to 170MHz 1370A-C LTC2259-14 14-Bit 80Msps 5MHz to 170MHz 1370A-D LTC2258-14 14-Bit 65Msps 5MHz to 170MHz 1370A-E LTC2257-14 14-Bit 40Msps 5MHz to 170MHz 1370A-F LTC2256-14 14-Bit 25Msps 5MHz to 170MHz 1370A-G LTC2261-12 12-Bit 125Msps 5MHz to 170MHz 1370A-H LTC2260-12 12-Bit 105Msps 5MHz to 170MHz 1370A-I LTC2259-12 12-Bit 80Msps 5MHz to 170MHz 1370A-J LTC2258-12 12-Bit 65Msps 5MHz to 170MHz 1370A-K LTC2257-12 12-Bit 40Msps 5MHz to 170MHz 1370A-L LTC2256-12 12-Bit 25Msps 5MHz to 170MHz 1370A-M LTC2262-14 14-Bit 150Msps 5MHz to 170MHz 1370A-N LTC2262-12 12-Bit 150Msps 5MHz to 170MHz Demonstration circuit 1370A is easy to set up to evaluate Applying Power and Signals to the DC1370A the performance of the LTC2262 A/D converters. Refer to Demonstration Circuit Figure 1 for proper measurement equipment setup and If a DC890 is used to acquire data from the DC1370A, follow the procedure: the DC890 must FIRST be connected to a powered USB port or provided an external 6V to 9V BEFORE applying Setup 3.6V to 6.0V across the pins marked V+ and GND on the If a DC890 QuikEval™II Data Acquisition and Collection DC1370A. DC1370A requires 3.6V for proper operation. System was supplied with the DC1370A demonstration Regulators on the board produce the voltages required for circuit, follow the DC890 Quick Start Guide to install the the ADC. The DC1370A demonstration circuit requires up required software and for connecting the DC890 to the to 150mA depending on the sampling rate and the A/D DC1370A and to a PC. converter supplied. The DC890 data collection board is powered by the USB DC1370A Demonstration Circuit Board Jumpers cable and does not require an external power supply unless The DC1370A demonstration circuit board should have it must be connected to the PC through an un-powered the following jumper settings as default positions: (as hub, in which case it must be supplied an external 6V to per Figure 1) 9V on turrets G7(+) and G1(–) or the adjacent 2.1mm JP2: PAR/SER: Selects Parallel or Serial programming power jack. mode. (Default - Serial) Analog Input Network JP3: Duty Cycle Stabilizer: Enables/Disable Duty Cycle For optimal distortion and noise performance the RC Stabilizer. (Default - Enable) network on the analog inputs may need to be optimized JP4: SHDN: Enables and disables the LTC2262. for different analog input frequencies. For input frequen- (Default - Enable) cies above 170MHz, refer to the LTC2262 data sheet for a proper input network. Other input networks may be more appropriate for input frequencies less that 5MHz. dc1730afa 2

DEMO MANUAL DC1370A Quick Start ProceDure 3.5V to 6V JUMPERS ARE SHOWN IN DEFAULT POSITIONS + ANALOG INPUT N PARALLEL DATA OUTPUT TO DC890 PARALLEL/SERIAL PROGRAMMING MODE DUTY CYCLE STABILIZER SHDN SINGLE ENDED ENCODE CLOCK Figure 1. DC1370A Setup In almost all cases, filters will be required on both analog amplifier, and a relatively lower Q filter used between the input and encode clock to provide data sheet SNR. In the amplifier and the demo circuit. case of the DC1370A the bandpass filter used for the clock should be used prior to the DC1075A. Encode Clock The filters should be located close to the inputs to avoid NOTE: Apply an encode clock to the SMA connector on reflections from impedance discontinuities at the driven the DC1370A demonstration circuit board marked J7. end of a long transmission line. Most filters do not present As a default the DC1370A is populated to have a single 50Ω outside the passband. In some cases, 3dB to 10dB ended input. pads may be required to obtain low distortion. For the best noise performance, the ENCODE INPUT must If your generator cannot deliver full-scale signals without be driven with a very low jitter, square wave source. The distortion, you may benefit from a medium power amplifier amplitude should be large, up to 3VP-P or 13dBm. When based on a Gallium Arsenide gain block prior to the final using a sinusoidal signal generator a squaring circuit can filter. This is particularly true at higher frequencies where be used. Linear Technology also provides demo board IC based operational amplifiers may be unable to deliver DC1075A that divides a high frequency sine wave by four, the combination of low noise figure and High IP3 point producing a low jitter square wave for best results with required. A high order filter can be used prior to this final the LTC2262 family. dc1730afa 3

DEMO MANUAL DC1370A Quick Start ProceDure Using bandpass filters on the clock and the analog input will Manual Configuration settings: improve the noise performance by reducing the wideband Bits: 14 (or 12 for 12-bit parts) noise power of the signals. In the case of the DC1370A a bandpass filter used for the clock should be used prior Alignment: 14 to the DC1075A. Data sheet FFT plots are taken with 10 FPGA Ld: CMOS pole LC filters made by TTE (Los Angeles, CA) to suppress Channs: 2 signal generator harmonics, nonharmonically related spurs and broadband noise. Low phase noise Agilent 8644B Bipolar: Unchecked generators are used with TTE bandpass filters for both Positive-Edge Clk: Checked the clock input and the analog input. Apply the analog input signal of interest to the SMA con- nectors on the DC1370A demonstration circuit board marked J5 A +. These inputs are capacitive coupled to IN balun transformers ETC1-1-13. An internally generated conversion clock output is avail- able on J1 which could be collected via a logic analyzer, or other data collection system if populated with a SAMTEC MEC8-150 type connector or collected by the DC890 QuikEval™II Data Acquisition Board using PScope™ software. Software The DC890 is controlled by the PScope System Software provided or downloaded from the Linear Technology Figure 2. ADC Configuration website at http://www.linear.com/software/. If a DC890 was provided, follow the DC890 Quick Start Guide and the instructions below. If everything is hooked up properly, powered and a suit- able convert clock is present, clicking the Collect button To start the data collection software if PScope.exe is in- should result in time and frequency plots displayed in stalled (by default) in \Program Files\LTC\PScope\, double the PScope window. Additional information and help for click the PScope Icon or bring up the run window under PScope is available in the DC890 Quick Start Guide and in the start menu and browse to the PScope directory and the online help available within the PScope program itself. select PScope. If the DC1370A demonstration circuit is properly connected Serial Programming to the DC890, PScope should automatically detect the PScope has the ability to program the DC1370A board DC1370A, and configure itself accordingly. If necessary serially through the DC890. There are several options the procedure below explains how to manually configure available in the LTC2262 family that are only available PScope. through serially programming. PScope allows all of these Under the Configure menu, go to ADC Configuration.... features to be tested. Check the Config Manually box and use the following These options are available by first clicking on the Set configuration options, see Figure 2: Demo Board Options icon on the PScope toolbar (Figure 3). dc1730afa 4

DEMO MANUAL DC1370A Quick Start ProceDure Clock Inversion: Selects the polarity of the CLKOUT signal • Normal (Default): Normal CLKOUT polarity • Inverted: CLKOUT polarity is inverted Figure 3. PScope Toolbar Clock Delay: Selects the phase delay of the CLKOUT signal: This will bring up the menu shown in figure 4. • None (Default): No CLKOUT delay • 45 deg: CLKOUT delayed by 45 degrees • 90 deg: CLKOUT delayed by 90 degrees • 135 deg: CLKOUT delayed by 135 degrees Clock Duty Cycle: Enable or disables Duty Cycle Stabilizer • Stabilizer off (Default): Duty Cycle Stabilizer Disabled • Stabilizer on: Duty Cycle Stabilizer Enabled Output Current: Selects the LVDS output drive current. This option is not used on the DC1370A • 1.75mA (Default): LVDS output driver current • 2.1mA: LVDS output driver current • 2.5mA: LVDS output driver current • 3.0mA: LVDS output driver current • 3.5mA: LVDS output driver current • 4.0mA: LVDS output driver current • 4.5mA: LVDS output driver current Figure 4. Demo Board Configuration Options Internal Termination: Enables LVDS Internal Termination. This option is not used on the DC1370A This menu allows any of the options available for the • Off (Default): Disables internal termination LTC2262 family to be programmed serially. The LTC2262 • On: Enables internal termination family has the following options: Outputs: Enables Digital Outputs Power Control: Selects between normal operation, nap, and sleep modes • Enabled (Default): Enables digital outputs • Normal (Default): Entire ADC is powered, and active • Disabled: Disables digital outputs • Nap: ADC core powers down while references stay active • Shutdown: The entire ADC is powered down dc1730afa 5

DEMO MANUAL DC1370A Quick Start ProceDure Output Mode: Selects Digital Output Mode Alternate Bit: Alternate Bit Polarity (ABP) Mode • Full Rate (Default): Full rate CMOS output mode • Off (Default): Disables alternate bit polarity • Double LVDS: double data rate LVDS output mode • On: Enables alternate bit polarity (Before enabling ABP, (This mode is not supported by the DC1370A, please be sure the part is in offset binary mode) use the DC1369) • Randomizer: Enables Data Output Randomizer • Double CMOS: double data rate CMOS output mode • Off (Default): Disables data output randomizer Test Pattern: Selects Digital Output Test Patterns • On: Enables data output randomizer • Off (Default): ADC data presented at output • Two’s complement: Enables Two’s Complement Mode • All out =1: All digital outputs are 1 • Off (Default): Selects offset binary mode • All out = 0: All digital outputs are 0 • On: Selects two’s complement mode • Checkerboard: OF, and D13-D0 Alternate between 101 Once the desired settings are selected hit OK and PScope 0101 1010 0101 and 010 1010 0101 1010 on alternat- will automatically update the register of the device on the ing samples DC1370A demo board. • Alternating: Digital outputs alternate between all 1’s and all 0’s on alternating samples dc1730afa 6

DEMO MANUAL DC1370A PartS LiSt ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER 1 0 C1 CAP, 0402 OPTION OPTION 2 12 C2, C3, C6, C7, C38, C39, C52, CAP, 0402, 0.01µF, 10%, 16V, X7R AVX 0402YC103KAT C53, C58, C60, C61, C63 3 2 C10, C9 CAP, 0402, 8.2pF, 5%, 50V, COG AVX 04025A8R2JAT2A 4 6 C12, C15, C18, C19, C21, C37 CAP, 0402, 0.1µF, 10%, 10V, X5R TDK C1005X5R1A104K 5 3 C13, C17, C23 CAP, 0402, 1µF, 10%, 10V, X5R TDK C1005X5R1A105K 6 3 C14, C22, C57 CAP, 0603, 1µF, 10%, 16V, X7R TDK C1608X7R1C105K 7 1 C20 CAP, 0402, 1µF, 10%, 10V, X5R MURATA GRM155R61A105KE15D 8 1 C24 CAP, 0603, 4.7µF, 20%, 6.3V, X5R TDK C1608X5R0J475MT 9 13 C26–C36, C40, C56 CAP, 0603, 0.1µF, 10%, 50V, X7R TDK C1608X7R1H104K 10 1 C51 CAP, 0402, 4.7pF, ±0.25pF, 50V, NPO AVX 04025A4R7CAT2A 11 3 C54, C55, C59 CAP, 1206, 22µF, 10%, 6.3V, X5R AVX 12066D226KAT2A 12 9 R9, R10, R46, R48, R54, R56, RES, 0402, 0Ω JUMPER VISHAY CRCW04020000Z0ED C62, C64, R75 13 1 D1 DIODE, SCHOTTKY SOT-23 AVAGO HSMS-2822 14 3 JP2, JP3, JP4 HEADER, 3-PIN, 2mm SAMTEC TMM-103-02-L-S 15 3 J5, J7, J9 CONN, BNC, SMA 50Ω EDGE-LANCH E.F.JOHNSON, 142-0701-851 16 1 J8 HEADER, 2 × 7, 2mm MOLEX 87331-1420 17 1 L1 IND, 0603, 56µH, 5% MURATA LQP18MN56NG02D 18 3 L2, L3, L4 FERRITE BEAD, 1206 MURATA BLM31PG330SN1L 19 1 L5 IND, 0603 BEAD OPTION 20 0 L6 IND, 0603 OPT OPTION 21 6 RN1, RN2, RN3, RN4, RN5, RN6 RES ARRAY, 33Ω VISHAY CRA04SS08333R0JTD 22 2 R1,R2 RES, 0402, 301Ω, 1%, 1/16W VISHAY CRCW0402301RFKED 23 0 R4, R5, R49, R52, R53, R55, RES, 0402 OPTION OPTION R57, R74 24 1 R6 RES, 0402, 10kΩ, 5%, 1/16W VISHAY CRCW040210K0JNED 25 1 R7 RES, 0402, 64.9kΩ, 1%, 1/16W VISHAY CRCW040264K9FKED 26 2 R8, R47 RES, 0402, 100kΩ, 1%, 1/16W YAGEO RC0402FR-07100KL 27 4 R14, R33, R34, R35 RES, 0402, 1kΩ, 5%, 1/16W PANASONIC ERJ-2GEJ102X 28 1 R16 RES, 0402, 100Ω, 5%, 1/16W VISHAY CRCW0402100RJNED 29 1 R24 RES, 0402, 100kΩ, 5%, 1/16W VISHAY CRCW0402100KJNED 30 3 R25, R26, R29 RES, 0603, 4.99kΩ, 1%, 1/16W AAC CR16-4991FM 31 3 R36, R44, R45 RES, 0402, 86.6Ω, 1%, 1/16W VISHAY CRCW040286R6FKED 32 2 R40, R39 RES, 0402, 24.9Ω, 1%, 1/16W YAGEO RC0402FR-0724R9FL 33 1 R50 IND, 36nH COILCRAFT 0402CS-36NXJB 34 1 R51 RES, 0402, 301Ω, 1%, 1/16W OPTION OPTION 35 5 TP1, TP2, TP3, TP4, TP5 TURRETS MILLMAX 2501-2-00-80-00-00-07-0 36 1 T1 XFMR, 1:1 MACOM MABA-007159-000000 37 1 T2 XFMR, 1:1 CT M/A-C0M MABAES0060 38 1 T3 XFMR, 1:4 CT COILCRAFT WBC4-1WLB 39 1 U1 IC, 24LC025-I/ST MICROCHIP TECH. 24LC025-I/ST 40 2 U7, U3 IC, BI-DIRECTIONAL INTERFACE FAIRCHILD FXLH42245 dc1730afa 7

DEMO MANUAL DC1370A PartS LiSt 41 1 U4 IC, LDO Micropower Regulators LINEAR TECH. LT1763CDE-1.8 42 1 U5 IC, 8-BIT, I/0 EXPANDER PHILIPS SEMI PCF8574TS/3 43 2 U10, U6 IC, LDO Micropower Regulators LINEAR TECH. LT1763CDE 44 1 U8 IC, ULP INVERTER FAIRCHILD NC7SP14P5X 45 1 U9 IC, EEPROM MICROCHIP TECH. 24LC32A-I/ST 46 3 XJP2, XJP3, XJP4 SHUNT, 2mm SAMTEC 2SN-BK-G 47 4 STANDOFF, SNAP ON KEYSTONE_8831 Schematic Diagram dc1730afa 8

DEMO MANUAL DC1370A Schematic Diagram D C B A RRR 21REVISION HISTORYREVISION HISTORYREVISION HISTORYDESCRIPTIONDATEAPPROVEDECOREVDESCRIPTIONDATEAPPROVEDECOREVDESCRIPTIONDATEAPPROVEDECOREV 333PROTO08/20/08PROTO08/20/08PROTO08/20/08 Change05/21/12Clarence M.3.1 OVDD+3.3V U3U343122FXLH42245FXLH42245P1EDGE-CON-100P1EDGE-CON-100ABB321CCCD13A0B0CCC21204D12VVVB1A119543D11B2A261865D10A3B317787D9B4A4168109D8B5A51591211+CLKB6A610141413-CLKA7B721615TR221817DDDDOE2019NNNNGGGG22212423123526251112282730293231OVDD3433+3.3V36353837U7U74039FXLH42245FXLH422454312242414443ABB3214645CCCD7A0B0CCC2044847D6VVVB1A11955049D5B2A26185251D4A3B31775453D3B4A41685655D2B5A51595857D1B6A610146059D0A7B726261TR226463DDDDOE6665NNNNGGGG68677069123572711112747376757877+3.3V80798281U8U8848358685VSSNC7SP14P5XNC7SP14P5X8887SCL249089ENABLE9291SDA9493VCC_IN9695R294.99K1%R294.99K1%39897+3.3V10099ENABLE R24R24100K100KC560.1uFC560.1uF U924LC32A-I/STU924LC32A-I/ST18VCC_INA0VCC27VSSA1WP36SCLA2SCL45SDAOXA2A3SDA 12FAST DAACS BOARD ID CIRCUITRYRN133RN133618VSSCS427SCK736SDI545SD0C270.1uFC270.1uFVCC_IN10C52C52C53C53911U124LC025-I/STU124LC025-I/ST0.01uF0.01uF0.01uF0.01uFR254.99K1%R254.99K1%1812SCLA0VCC27A1WP36SCLVCC_INA2SCL45SDASDAA3SDA14SCLVSSR264.99K1%R264.99K1%SDA CONTRACT NO.CONTRACT NO.CONTRACT NO.1630 McCarthy Blvd.1630 McCarthy Blvd.1630 McCarthy Blvd.Milpitas, CA 95035Milpitas, CA 95035Milpitas, CA 95035Phone: (408)432-1900Phone: (408)432-1900Phone: (408)432-1900APPROVALSAPPROVALSAPPROVALSDATEDATEDATETECHNOLOGYTECHNOLOGYTECHNOLOGYFax: (408)434-0507Fax: (408)434-0507Fax: (408)434-0507DRAWNDRAWNDRAWNMI10/31/07MI10/31/07MI10/31/07TITLETITLETITLESCH, LTC2261CUJ, HIGH SPEED LOW POWESCH, LTC2261CUJ, HIGH SPEED LOW POWESCH, LTC2261CUJ, HIGH SPEED LOW POWECHECKEDCHECKEDCHECKED125MSPS ADC FAMILY, CMOS125MSPS ADC FAMILY, CMOS125MSPS ADC FAMILY, CMOSAPPROVEDAPPROVEDAPPROVEDENGINEERENGINEERENGINEERSIZESIZESIZECAGE CODECAGE CODECAGE CODEDWG NODWG NODWG NOREVREVREVDESIGNERDESIGNERDESIGNERDC1370ADC1370ADC1370A333 05/22/12 06:30:3505/22/12 06:30:3505/22/12 06:30:35NONENONENONESCALE:FILENAME:SCALE:FILENAME:SCALE:FILENAME:SHEET1370A-3.DSNSHEET1370A-3.DSNSHEET1370A-3.DSNOFOFOF12121221 8765OVDDRN433RN433 RN533RN53318273645 OVDD J8J8VUNREG5V CSSCK/SCLMOSI/SDAMISO EEVCCEESDAEESCLEEGND DDDNNNNCGGG 8331 SCKSDISD0+3.3VR610KR610K CS 1234 8765 3 RN333RN33318273645 21343333 10231111DDDD30D929D828CLKOUT+27CLKOUT-26OVDDOVDD25OGND24D723D622D521D4 0123DDDD 7890RN633RN63311121234 VDDVDD R35R35R34R341K1K1K1KJP4JP4JP3JP311ENENENEN22CSSDI 33DISDISDISDIS SHDNSHDNDUTY CYCLE STAB.DUTY CYCLE STAB. +3.3VU5U5PCF8574TS/3PCF8574TS/35RN233RN23310181DP0INT1127DP1V12236SCLP2SCL14445SDAP3SDA163P4NC178P5NC19P6206P7A0718DA1NC913NA2NCG 5OX401 3 54This circuit is proprietary to Linear Technology and suppliedThis circuit is proprietary to Linear Technology and suppliedThis circuit is proprietary to Linear Technology and suppliedfor use with Linear Technology parts.for use with Linear Technology parts.for use with Linear Technology parts.VDDCustomer Notice:Customer Notice:Customer Notice:Linear Technology has made a best effort toLinear Technology has made a best effort toLinear Technology has made a best effort todesign a circuit that meets customer-supplied specifications;design a circuit that meets customer-supplied specifications;design a circuit that meets customer-supplied specifications;however, it remains the customers responsibility to verify properhowever, it remains the customers responsibility to verify properhowever, it remains the customers responsibility to verify properR14R14and reliable operation in the actual application, Componentand reliable operation in the actual application, Componentand reliable operation in the actual application, Component1K1Ksubstitution and printed circuit board layout may significantlysubstitution and printed circuit board layout may significantlysubstitution and printed circuit board layout may significantlyTP1TP1affect circuit performance or reliability. Contact Linearaffect circuit performance or reliability. Contact Linearaffect circuit performance or reliability. Contact LinearApplications Engineering for assistance.Applications Engineering for assistance.Applications Engineering for assistance.EXT REFEXT REFC17C17R90R90 1uF1uFR4586.61%R4586.61% T1T1R39R39T2T2MABA-007159-000000MABA-007159-00000024.924.9C6C6L1L1MABAES0060MABAES00601%1%56uH56uHJ5J512AIN+AIN+0.01uF0.01uFC13C132R36R36R44R44C12C1286.686.6R40R4086.686.6C7C70.1uF0.1uF1%1%24.924.91%1%0.01uF0.01uF11%1%1uF1uFC9C9R16R16C10C10C23C238.2pF8.2pF1001008.2pF8.2pF 1uF1uFVDDR100R100**U2U2VDDC51C51957680333334C26C26C33C33C18C18C19C19MFED-+FFES0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF4.7pF4.7pF0.1uF0.1uFDCOORNVV1VEAIN+S2AIN-3+3.3VGNDC15C154REFH5C36C36C32C32C28C28C31C31C34C34C30C300.1uF0.1uFC40C40C35C35C29C29REFHC20C2060.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uFREFL1uF1uFC21C217REFL80.1uF0.1uFPAR/SERPAR/SERTP4TP49GNDVDD10VDDVDDVDDL5BEADL5BEADR57OPTR57OPT+-DOCCKINSNNCDDG2CEESSSC61C610.01uF0.01uF1234561R560R560R480R48011111141 R74R74R49R49R5OPTR5OPTOPTOPTOPTOPT1%1%C64C6412T3T3R2R2K0C20.01uFC20.01uFR5036nHR5036nHWBC4-1WLWBC4-1WLJ7J7L6L6301301ISCDD1%1%ENC+ENC+CSSSR51R51OPTOPTOPTOPT3C62C62212C3C3212R1R1C1C120.01uF0.01uFD1D1C63C633013011HSMS-2822HSMS-28221%1%OPTOPT1R52R520.01uF0.01uF1OPTOPTR4OPTR4OPTR55OPTR55OPTJ9J9ENC-ENC-2C60C60R540R540R53OPTR53OPTR75R75000.01uF0.01uF1%1%1 VDD R33R331K1KJP2JP2VDDVINU4LT1763CDE-1.8U4LT1763CDE-1.8L2L2TP2TP21BEADBEAD102V+V+PARPARINOUT1132PAR/SERINOUTC14C14C24C24C54C543.5V - 6V5123SERSERSENSENC11uF1uF4.7uF4.7uFTP3TP3C38C3822uF22uFNC4GNDGNDNC90.01uF0.01uFNC6PAR/SERPAR/SERBYP78TP5TP5GNDSHDN+3.3VGNDGNDL3BEADL3BEADU6LT1763CDEU6LT1763CDE 102R764.9K1%R764.9K1%R8100K1%R8100K1%INOUT113INOUTOVDDC22C22512SENSENC11uF1uFL4L4NCC37C374C39C39C55C55BEADBEADNC9NC60.01uF0.01uF22uF22uFBYP0.1uF0.1uFU10LT1763CDEU10LT1763CDE78GNDSHDN102R47100K1%R47100K1%R460R460INOUT113INOUT512SENSENC1NC4C59C59C58C58C57C57NC9NC622uF22uF0.01uF0.01uF1uF1uFBYP78GNDSHDN 54 D C B A dc1730afa 9 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

DEMO MANUAL DC1370A DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC applica- tion engineer. Mailing Address: Linear Technology 1630 McCarthy Blvd. Milpitas, CA 95035 Copyright © 2004, Linear Technology Corporation dc1730afa 10 Linear Technology Corporation LT 0712 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2012