DAC8564 DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference CheckforSamples:DAC8564 FEATURES DESCRIPTION 1 • RelativeAccuracy:4LSB The DAC8564 is a low-power, voltage-output, 234 four-channel, 16-bit digital-to-analog converter (DAC). • GlitchEnergy:0.15nV-s The device includes a 2.5V, 2ppm/°C internal • InternalReference: reference (enabled by default), giving a full-scale – 2.5VReferenceVoltage(enabledbydefault) output voltage range of 2.5V. The internal reference has an initial accuracy of 0.004% and can source up – 0.004%InitialAccuracy(typ) to 20mA at the V H/V OUT pin. The device is REF REF – 2ppm/°CTemperatureDrift(typ) monotonic, provides very good linearity, and – 5ppm/°CTemperatureDrift(max) minimizes undesired code-to-code transient voltages (glitch). The DAC8564 uses a versatile 3-wire serial – 20mASink/SourceCapability interface that operates at clock rates up to 50MHz. • Power-OnResettoZero-Scale The interface is compatible with standard SPI™, • Ultra-LowPowerOperation:1mAat5V QSPI™, Microwire™, and digital signal processor (DSP)interfaces. • WidePowerSupplyRange:+2.7Vto+5.5V • 16-BitMonotonicOverTemperatureRange The DAC8564 incorporates a power-on-reset circuit that ensures the DAC output powers up at zero-scale • SettlingTime:10μsto±0.003%Full-Scale and remains there until a valid code is written to the Range(FSR) device. The device contains a power-down feature, • Low-PowerSerialInterfacewith accessed over the serial interface, that reduces the Schmitt-TriggeredInputs:Upto50MHz current consumption of the device to 1.3μA at 5V. • On-ChipOutputBufferAmplifierwith Power consumption is 2.9mW at 3V, reducing to 1.5μW in power-down mode. The low-power Rail-to-RailOperation consumption, internal reference, and small footprint • 1.8Vto5.5VLogicCompatibility make this device ideal for portable, battery-operated • TemperatureRange:–40°Cto+105°C equipment. The DAC8564 is drop-in and functionally compatible APPLICATIONS with the DAC7564 and DAC8164, and functionally • PortableInstrumentation compatible with the DAC7565, DAC8165, and DAC8565. All these devices are available in a • Closed-LoopServo-Control TSSOP-16package. • ProcessControl,PLCs • DataAcquisitionSystems IOVDD AVDD VREFL DAC8564 • ProgrammableAttenuation Data Buffer A DAC Register A 16-Bit DAC VOUTA • PCPeripherals Data Buffer B DAC Register B 16-Bit DAC VOUTB Data Buffer C DAC Register C 16-Bit DAC VOUTC RELATED DEVICES 16-BIT 14-BIT 12-BIT Pinand Data Buffer D DAC Register D 16-Bit DAC VOUTD Functionally DAC8564 DAC8164 DAC7564 SYNC Compatible SCLK 24-Bit Shift Register CBounffterorl RCeognistrtoelr 2.5V Power-Down Functionally DIN Control Logic Reference Control Logic DAC8565 DAC8165 DAC7565 Compatible GND A0 A1 LDAC ENABLE VREFH/VREFOUT 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. SPI,QSPIaretrademarksofMotorola,Inc. 2 MicrowireisatrademarkofNationalSemiconductor. 3 Allothertrademarksarethepropertyoftheirrespectiveowners. 4 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007–2011,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. PACKAGE/ORDERINGINFORMATION(1) RELATIVE DIFFERENTIAL REFERENCE SPECIFIED ACCURACY NONLINEARITY DRIFT PACKAGE- PACKAGE TEMPERATURE PACKAGE PRODUCT (LSB) (LSB) (ppm/°C) LEAD DESIGNATOR RANGE MARKING DAC8564A ±12 ±1 25 TSSOP-16 PW –40°Cto+105°C DAC8564 DAC8564B ±8 ±1 25 TSSOP-16 PW –40°Cto+105°C DAC8564B DAC8564C ±12 ±1 5 TSSOP-16 PW –40°Cto+105°C DAC8564 DAC8564D ±8 ±1 5 TSSOP-16 PW –40°Cto+105°C DAC8564D (1) ForthemostcurrentpackageandorderinginformationseethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS(1) Overoperatingfree-airtemperaturerange(unlessotherwisenoted). DAC8564 UNIT AV toGND –0.3to+6 V DD DigitalinputvoltagetoGND –0.3to+V +0.3 V DD V toGND –0.3to+V +0.3 V OUT DD V toGND –0.3to+V +0.3 V REF DD Operatingtemperaturerange –40to+125 °C Storagetemperaturerange –65to+150 °C Junctiontemperaturerange(T max) +150 °C J Powerdissipation (T max–T )/θ W J A JA Thermalimpedance,θ +118 °C/W JA Thermalimpedance,θ +29 °C/W JC Humanbodymodel(HBM) 4000 V ESDrating Chargeddevicemodel(CDM) 1500 V (1) StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Exposuretoabsolute maximumconditionsforextendedperiodsmayaffectdevicereliability. 2 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 ELECTRICAL CHARACTERISTICS AtAV =2.7Vto5.5Vand–40°Cto+105°Crange(unlessotherwisenoted). DD DAC8564 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT STATICPERFORMANCE(1) Resolution 16 Bits Measuredbytheline DAC8564A,DAC8564C ±4 ±12 LSB Relativeaccuracy passingthrough codes485and64714 DAC8564B,DAC8564D ±4 ±8 LSB Differentialnonlinearity 16-bitmonotonic ±0.5 ±1 LSB Offseterror ±5 ±8 mV Offseterrordrift Measuredbythelinepassingthroughcodes485and ±1 μV/°C Full-scaleerror 64714 ±0.2 ±0.5 %ofFSR Gainerror ±0.05 ±0.2 %ofFSR AVDD=5V ±1 ppmof Gaintemperaturecoefficient AVDD=2.7V ±2 FSR/°C PSRR Power-supplyrejectionratio Outputunloaded 1 mV/V OUTPUTCHARACTERISTICS(2) Outputvoltagerange 0 VREF V To±0.003%FSR,0200htoFD00h,RL=2kΩ, 8 10 Outputvoltagesettlingtime 0pF<CL<200pF μs RL=2kΩ,CL=500pF 12 Slewrate 2.2 V/μs RL=∞ 470 Capacitiveloadstability pF RL=2kΩ 1000 Codechangeglitchimpulse 1LSBchangearoundmajorcarry 0.15 nV-s Digitalfeedthrough SCLKtoggling,SYNChigh 0.15 nV-s Channel-to-channeldccrosstalk Full-scaleswingonadjacentchannel 0.25 LSB Channel-to-channelaccrosstalk 1kHzfull-scalesinewave,outputsunloaded –100 dB DCoutputimpedance Atmid-codeinput 1 Ω Short-circuitcurrent 50 mA Comingoutofpower-downmode,AVDD=5V 2.5 Power-uptime μs Comingoutofpower-downmode,AVDD=3V 5 ACPERFORMANCE(2) SNR 90 dB THD TA=+25°C,BW=20kHz,VDD=5V,fOUT=1kHz. –77 dB SFDR First19harmonicsremovedforSNRcalculation. 78 dB SINAD 77 dB DACoutputnoisedensity TA=+25°C,atmid-codeinput,fOUT=1kHz 120 nV/√Hz DACoutputnoise TA=+25°C,atmid-codeinput,0.1Hzto10Hz 6 μVPP REFERENCE AVDD=5.5V 360 μA Internalreferencecurrentconsumption AVDD=3.6V 348 μA Externalreferencecurrent ExternalVREF=2.5V,ifinternalreferenceisdisabled, 80 μA allfourchannelsactive ReferenceinputrangeVREFHvoltage VREFL<VREFH,AVDD–(VREFH+VREFL)/2>1.2V 0 AVDD V ReferenceinputrangeVREFLvoltage VREFL<VREFH,AVDD–(VREFH+VREFL)/2>1.2V 0 AVDD/2 V Referenceinputimpedance 31 kΩ (1) Linearitycalculatedusingareducedcoderangeof485to64714;outputunloaded. (2) Ensuredbydesignorcharacterization;notproductiontested. Copyright©2007–2011,TexasInstrumentsIncorporated 3

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AtAV =2.7Vto5.5Vand–40°Cto+105°Crange(unlessotherwisenoted). DD DAC8564 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT REFERENCEOUTPUT Outputvoltage TA=+25°C 2.4975 2.5 2.5025 V Initialaccuracy TA=+25°C –0.1 ±0.004 0.1 % DAC8564A,DAC8564B(3) 5 25 Outputvoltagetemperaturedrift ppm/°C DAC8564C,DAC8564D(4) 2 5 Outputvoltagenoise f=0.1Hzto10Hz 12 μVPP TA=+25°C,f=1MHz,CL=0μF 50 Outputvoltagenoisedensity (high-frequencynoise) TA=+25°C,f=1MHz,CL=1μF 20 nV/√Hz TA=+25°C,f=1MHz,CL=4μF 16 Loadregulation,sourcing(5) TA=+25°C 30 μV/mA Loadregulation,sinking(5) TA=+25°C 15 μV/mA Outputcurrentloadcapability(6) ±20 mA Lineregulation TA=+25°C 10 μV/V Long-termstability/drift(aging)(5) TA=+25°C,time=0to1900hours 50 ppm Firstcycle 100 Thermalhysteresis(5) ppm Additionalcycles 25 LOGICINPUTS(6) Inputcurrent ±1 μA 2.7V≤IOVDD≤5.5V 0.3×IOVDD VINL LogicinputLOWvoltage V 1.8V≤IOVDD≤2.7V 0.1×IOVDD 2.7V≤IOVDD≤5.5V 0.7×IOVDD VINH LogicinputHIGHvoltage V 1.8V≤IOVDD≤2.7V 0.95×IOVDD Pincapacitance 3 pF POWERREQUIREMENTS AVDD 2.7 5.5 V IOVDD 1.8 5.5 V IOIDD(6) 10 20 μA AVDD=IOVDD=3.6Vto5.5V 1 1.6 VINH=IOVDDandVINL=GND Normalmode mA AVDD=IOVDD=2.7Vto3.6V 0.95 1.5 IDD(7) VINH=IOVDDandVINL=GND AVDD=IOVDD=3.6Vto5.5V 1.3 3.5 VINH=IOVDDandVINL=GND Allpower-downmodes μA AVDD=IOVDD=2.7Vto3.6V 0.5 2.5 VINH=IOVDDandVINL=GND AVDD=IOVDD=3.6Vto5.5V 3.6 8.8 VINH=IOVDDandVINL=GND Normalmode mW AVDD=IOVDD=2.7Vto3.6V 2.6 5.4 Power VINH=IOVDDandVINL=GND Dissipation(7) AVDD=IOVDD=3.6Vto5.5V 4.7 19 VINH=IOVDDandVINL=GND Allpower-downmodes μW AVDD=IOVDD=2.7Vto3.6V 1.4 9 VINH=IOVDDandVINL=GND TEMPERATURERANGE Specifiedperformance –40 +105 °C (3) Referenceistrimmedandtestedatroomtemperature,andischaracterizedfrom–40°Cto+120°C. (4) Referenceistrimmedandtestedattwotemperatures(+25°Cand+105°C),andischaracterizedfrom–40°Cto+120°C. (5) ExplainedinmoredetailintheApplicationInformationsectionofthisdatasheet. (6) Ensuredbydesignorcharacterization;notproductiontested. (7) Inputcode=32768,referencecurrentincluded,noload. 4 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 PIN CONFIGURATIONS PWPACKAGE TSSOP-16 (TopView) VOUTA 1 16 LDAC VOUTB 2 15 ENABLE V H/V OUT 3 14 A1 REF REF AVDD 4 13 A0 DAC8564 VREFL 5 12 IOVDD GND 6 11 DIN VOUTC 7 10 SCLK VOUTD 8 9 SYNC PINDESCRIPTIONS PIN NAME DESCRIPTION 1 V A AnalogoutputvoltagefromDACA OUT 2 V B AnalogoutputvoltagefromDACB OUT V H/ 3 REF Positivereferenceinput/referenceoutput2.5Vifinternalreferenceused. V OUT REF 4 AV Power-supplyinput,2.7Vto5.5V DD 5 V L Negativereferenceinput REF 6 GND Groundreferencepointforallcircuitryonthepart 7 V C AnalogoutputvoltagefromDACC OUT 8 V D AnalogoutputvoltagefromDACD OUT Level-triggeredcontrolinput(activelow).Thisinputistheframesynchronizationsignalfortheinputdata.WhenSYNC goeslow,itenablestheinputshiftregister,anddataaresampledonsubsequentfallingclockedges.TheDACoutput 9 SYNC updatesfollowingthe24thclock.IfSYNCistakenhighbeforethe24thclockedge,therisingedgeofSYNCactsas aninterrupt,andthewritesequenceisignoredbytheDAC8564.Schmitt-Triggerlogicinput. 10 SCLK Serialclockinput.Datacanbetransferredatratesupto50MHz.Schmitt-Triggerlogicinput. Serialdatainput.Dataareclockedintothe24-bitinputshiftregisteroneachfallingedgeoftheserialclockinput. 11 D IN Schmitt-Triggerlogicinput. 12 IOV Digitalinput-outputpowersupply DD 13 A0 Address0—setsdeviceaddress;seeTable5. 14 A1 Address1—setsdeviceaddress;seeTable5. 15 ENABLE Theenablepin(activelow)connectstheSPIinterfacetotheserialport 16 LDAC LoadDACs;risingedgetriggered,loadsallDACregisters Copyright©2007–2011,TexasInstrumentsIncorporated 5

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com SERIAL WRITE OPERATION 3 2 B D t9 t15 t14 t12 t13 t7 B0 24 t10 D t2 t1 t3 t6 t5 3 t11 1 t4 DB2 t8 E K C N C NABL SCL SYN DI LDA E 6 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 TIMING REQUIREMENTS(1) (2) AtAV =IOV =2.7Vto5.5Vand–40°Cto+105°Crange(unlessotherwisenoted). DD DD DAC8564 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT IOV =AV =2.7Vto3.6V 40 t (3) SCLKcycletime DD DD ns 1 IOV =AV =3.6Vto5.5V 20 DD DD IOV =AV =2.7Vto3.6V 20 DD DD t SCLKHIGHtime ns 2 IOV =AV =3.6Vto5.5V 10 DD DD IOV =AV =2.7Vto3.6V 20 DD DD t SCLKLOWtime ns 3 IOV =AV =3.6Vto5.5V 10 DD DD IOV =AV =2.7Vto3.6V 0 DD DD t SYNCtoSCLKrisingedgesetuptime ns 4 IOV =AV =3.6Vto5.5V 0 DD DD IOV =AV =2.7Vto3.6V 5 DD DD t Datasetuptime ns 5 IOV =AV =3.6Vto5.5V 5 DD DD IOV =AV =2.7Vto3.6V 4.5 DD DD t Dataholdtime ns 6 IOV =AV =3.6Vto5.5V 4.5 DD DD IOV =AV =2.7Vto3.6V 0 DD DD t SCLKfallingedgetoSYNCrisingedge ns 7 IOV =AV =3.6Vto5.5V 0 DD DD IOV =AV =2.7Vto3.6V 40 DD DD t MinimumSYNCHIGHtime ns 8 IOV =AV =3.6Vto5.5V 20 DD DD IOV =AV =2.7Vto3.6V 130 DD DD t 24thSCLKfallingedgetoSYNCfallingedge ns 9 IOV =AV =3.6Vto5.5V 130 DD DD SYNCrisingedgeto24thSCLKfallingedge IOVDD=AVDD=2.7Vto3.6V 15 t ns 10 (forsuccessfulSYNCinterrupt) IOV =AV =3.6Vto5.5V 15 DD DD IOV =AV =2.7Vto3.6V 15 DD DD t ENABLEfallingedgetoSYNCfallingedge ns 11 IOV =AV =3.6Vto5.5V 15 DD DD IOV =AV =2.7Vto3.6V 10 DD DD t 24thSCLKfallingedgetoENABLErisingedge ns 12 IOV =AV =3.6Vto5.5V 10 DD DD IOV =AV =2.7Vto3.6V 50 DD DD t 24thSCLKfallingedgetoLDACrisingedge ns 13 IOV =AV =3.6Vto5.5V 50 DD DD IOV =AV =2.7Vto3.6V 10 DD DD t LDACrisingedgetoENABLErisingedge ns 14 IOV =AV =3.6Vto5.5V 10 DD DD IOV =AV =2.7Vto3.6V 10 DD DD t LDACHIGHtime ns 15 IOV =AV =3.6Vto5.5V 10 DD DD (1) Allinputsignalsarespecifiedwitht =t =3ns(10%to90%ofV )andtimedfromavoltagelevelof(V +V )/2. R F DD IL IH (2) SeetheSerialWriteOperationtimingdiagram. (3) MaximumSCLKfrequencyis50MHzatIOV =V =3.6Vto5.5Vand25MHzatIOV =AV =2.7Vto3.6V. DD DD DD DD Copyright©2007–2011,TexasInstrumentsIncorporated 7

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com TYPICAL CHARACTERISTICS: Internal Reference AtT =+25°C,unlessotherwisenoted. A INTERNALREFERENCEVOLTAGE INTERNALREFERENCEVOLTAGE vs vs TEMPERATURE(GradesCandD) TEMPERATURE(GradesAandB) 2.503 2.503 2.502 2.502 2.501 2.501 V) V) (REF 2.500 (REF 2.500 V V 2.499 2.499 2.498 2.498 10 Units Shown 13 Units Shown 2.497 2.497 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) Figure1. Figure2. REFERENCEOUTPUTTEMPERATUREDRIFT REFERENCEOUTPUTTEMPERATUREDRIFT (–40°Cto+120°C,GradesCandD) (–40°Cto+120°,GradesAandB) 40 30 Typ: 2ppm/°C Typ: 5ppm/°C Max: 5ppm/°C Max: 25ppm/°C 30 %) %) 20 n ( n ( atio 20 atio ul ul p p Po Po 10 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 3 5 7 9 11 13 15 17 19 Temperature Drift (ppm/°C) Temperature Drift (ppm/°C) Figure3. Figure4. REFERENCEOUTPUTTEMPERATUREDRIFT LONG-TERM (0°Cto+120°C,GradesCandD) STABILITY/DRIFT (1) 40 200 Typ: 1.2ppm/°C Max: 3ppm/°C 150 30 100 opulation (%) 20 Drift (ppm) -55000 P Average 10 -100 -150 20 Units Shown 0 -200 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 300 600 900 1200 1500 18000 9 Temperature Drift (ppm/°C) Time (Hours) 1 Figure5. Figure6. (1) ExplainedinmoredetailintheApplicationInformationsectionofthisdatasheet. 8 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 TYPICAL CHARACTERISTICS: Internal Reference (continued) AtT =+25°C,unlessotherwisenoted. A INTERNALREFERENCENOISEDENSITY vs INTERNALREFERENCENOISE FREQUENCY 0.1HzTO10Hz 300 250 12mV (peak-to-peak) Hz) 200 Reference Unbuffered V/div) ÖV/ 150 CREF= 0mF (5m n E ( S N OI V N 100 V 50 C = 4.8mF REF 0 10 100 1k 10k 100k 1M Time (2s/div) Frequency (Hz) Figure7. Figure8. INTERNALREFERENCEVOLTAGE INTERNALREFERENCEVOLTAGE vs vs LOADCURRENT(GradesCandD) LOADCURRENT(GradesAandB) 2.505 2.505 2.504 2.504 +120°C 2.503 2.503 2.502 2.502 +120°C V) 2.501 V) 2.501 +25°C ( ( EF 2.500 EF 2.500 R R V 2.499 V 2.499 +25°C 2.498 2.498 -40°C 2.497 2.497 -40°C 2.496 2.496 2.495 2.495 -25 -20 -15 -10 -5 0 5 10 15 20 25 -25 -20 -15 -10 -5 0 5 10 15 20 25 I (mA) I (mA) LOAD LOAD Figure9. Figure10. INTERNALREFERENCEVOLTAGE INTERNALREFERENCEVOLTAGE vs vs SUPPLYVOLTAGE(GradesCandD) SUPPLYVOLTAGE(GradesAandB) 2.503 2.503 +120°C 2.502 2.502 +120°C -40°C V) 2.501 V) 2.501 ( ( REF REF +25°C V 2.500 V 2.500 +25°C 2.499 2.499 -40°C 2.498 2.498 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 AV (V) AV (V) DD DD Figure11. Figure12. Copyright©2007–2011,TexasInstrumentsIncorporated 9

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AV = 5V DD AtT =+25°C,externalreferenceused,DACoutputnotloaded,andallDACcodesinstraightbinarydataformat,unless A otherwisenoted. LINEARITYERRORAND LINEARITYERRORAND DIFFERENTIALLINEARITYERROR DIFFERENTIALLINEARITYERROR vsDIGITALINPUTCODE(–40°C) vsDIGITALINPUTCODE(–40°C) 6 6 Channel A Channel B 4 4 AV = 5.0V, External V = 4.99V AV = 5.0V, External V = 4.99V B) 2 DD REF B) 2 DD REF S S L 0 L 0 E ( -2 E ( -2 L L -4 -4 -6 -6 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0 E (L 0 DL -0.5 DL -0.5 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Digital Input Code Figure13. Figure14. LINEARITYERRORAND LINEARITYERRORAND DIFFERENTIALLINEARITYERROR DIFFERENTIALLINEARITYERROR vsDIGITALINPUTCODE(–40°C) vsDIGITALINPUTCODE(–40°C) 6 6 Channel D 4 4 AV = 5.0V, External V = 4.99V B) 2 B) 2 DD REF S S L 0 L 0 E ( -2 E ( -2 L Channel C L -4 AV = 5.0V, External V = 4.99V -4 -6 DD REF -6 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0 E (L 0 DL -0.5 DL -0.5 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Digital Input Code Figure15. Figure16. 10 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 TYPICAL CHARACTERISTICS: DAC at AV = 5V (continued) DD AtT =+25°C,externalreferenceused,DACoutputnotloaded,andallDACcodesinstraightbinarydataformat,unless A otherwisenoted. LINEARITYERRORAND LINEARITYERRORAND DIFFERENTIALLINEARITYERROR DIFFERENTIALLINEARITYERROR vsDIGITALINPUTCODE(+25°C) vsDIGITALINPUTCODE(+25°C) 6 6 Channel A Channel B 4 4 AV = 5.0V, External V = 4.99V AV = 5.0V, External V = 4.99V B) 2 DD REF B) 2 DD REF S S L 0 L 0 E ( -2 E ( -2 L L -4 -4 -6 -6 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0 E (L 0 DL -0.5 DL -0.5 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Digital Input Code Figure17. Figure18. LINEARITYERRORAND LINEARITYERRORAND DIFFERENTIALLINEARITYERROR DIFFERENTIALLINEARITYERROR vsDIGITALINPUTCODE(+25°C) vsDIGITALINPUTCODE(+25°C) 6 6 Channel D 4 4 AV = 5.0V, External V = 4.99V B) 2 B) 2 DD REF S S L 0 L 0 E ( -2 E ( -2 L Channel C L -4 AV = 5.0V, External V = 4.99V -4 -6 DD REF -6 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0 E (L 0 DL -0.5 DL -0.5 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Digital Input Code Figure19. Figure20. Copyright©2007–2011,TexasInstrumentsIncorporated 11

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AV = 5V (continued) DD AtT =+25°C,externalreferenceused,DACoutputnotloaded,andallDACcodesinstraightbinarydataformat,unless A otherwisenoted. LINEARITYERRORAND LINEARITYERRORAND DIFFERENTIALLINEARITYERROR DIFFERENTIALLINEARITYERROR vsDIGITALINPUTCODE(+105°C) vsDIGITALINPUTCODE(+105°C) 6 6 Channel A Channel B 4 4 AV = 5.0V, External V = 4.99V AV = 5.0V, External V = 4.99V B) 2 DD REF B) 2 DD REF S S L 0 L 0 E ( -2 E ( -2 L L -4 -4 -6 -6 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0 E (L 0 DL -0.5 DL -0.5 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Digital Input Code Figure21. Figure22. LINEARITYERRORAND LINEARITYERRORAND DIFFERENTIALLINEARITYERROR DIFFERENTIALLINEARITYERROR vsDIGITALINPUTCODE(+105°C) vsDIGITALINPUTCODE(+105°C) 6 6 Channel D 4 4 AV = 5.0V, External V = 4.99V B) 2 B) 2 DD REF S S L 0 L 0 E ( -2 E ( -2 L Channel C L -4 AV = 5.0V, External V = 4.99V -4 -6 DD REF -6 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0 E (L 0 DL -0.5 DL -0.5 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Digital Input Code Figure23. Figure24. 12 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 TYPICAL CHARACTERISTICS: DAC at AV = 5V (continued) DD AtT =+25°C,externalreferenceused,DACoutputnotloaded,andallDACcodesinstraightbinarydataformat,unless A otherwisenoted. OFFSETERROR FULL-SCALEERROR vsTEMPERATURE vsTEMPERATURE 4 0.50 AV = 5V AV = 5V DD DD Internal VREFEnabled Ch C Internal VREFEnabled 3 Ch C V) mV) 0.25 Ch D Error (m 2 e Error ( 0 Offset 1 Ch A Ch D Full-Scal -0.25 Ch A Ch B 0 -1 Ch B -0.50 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) Figure25. Figure26. SOURCEANDSINK SOURCEANDSINK CURRENTCAPABILITY CURRENTCAPABILITY 5.5 5.5 DAC Loaded with FFFFh DAC Loaded with FFFFh 4.5 4.5 V) V) e ( e ( ag 3.5 ag 3.5 olt AVDD= 5V, Ch A olt AVDD= 5V, Ch B ut V 2.5 Internal Reference Disabled ut V 2.5 Internal Reference Disabled p p ut ut O O g 1.5 g 1.5 o o al al n n A A 0.5 0.5 DAC Loaded with 0000h DAC Loaded with 0000h -0.5 -0.5 0 5 10 15 20 0 5 10 15 20 I (mA) I (mA) SOURCE/SINK SOURCE/SINK Figure27. Figure28. SOURCEANDSINK SOURCEANDSINK CURRENTCAPABILITY CURRENTCAPABILITY 5.5 5.5 DAC Loaded with FFFFh DAC Loaded with FFFFh 4.5 4.5 V) V) e ( e ( ag 3.5 ag 3.5 olt AVDD= 5V, Ch C olt AVDD= 5V, Ch D ut V 2.5 Internal Reference Disabled ut V 2.5 Internal Reference Disabled p p ut ut O O g 1.5 g 1.5 o o al al n n A A 0.5 0.5 DAC Loaded with 0000h DAC Loaded with 0000h -0.5 -0.5 0 5 10 15 20 0 5 10 15 20 I (mA) I (mA) SOURCE/SINK SOURCE/SINK Figure29. Figure30. Copyright©2007–2011,TexasInstrumentsIncorporated 13

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AV = 5V (continued) DD AtT =+25°C,externalreferenceused,DACoutputnotloaded,andallDACcodesinstraightbinarydataformat,unless A otherwisenoted. POWER-SUPPLYCURRENT POWER-SUPPLYCURRENT vsDIGITALINPUTCODE vsTEMPERATURE 1300 1400 AVDD= 5.5V AVDD= 5.5V Internal V Included Internal V Included A) 1200 REF A) 1300 DAC LoadReEdF with 8000h m m urrent( 1100 urrent ( 1200 C C ply ply 1100 up 1000 up er-S er-S 1000 w w Po 900 Po 900 800 800 0 8192 16384 24576 32768 40960 49152 57344 65536 -40 -20 0 20 40 60 80 100 120 Digital Input Code Temperature (°C) Figure31. Figure32. POWER-SUPPLYCURRENT vs POWER-DOWNCURRENT POWER-SUPPLYVOLTAGE vsPOWER-SUPPLYVOLTAGE 1100 1.2 AV = 2.7V to 5.5V AV = 2.7V to 5.5V DD DD Internal V Included Internal V Included REF REF mCurrent (A) 11009800 DAC Loaded with 8000h Current (A)m 01..80 ply wn wer-Sup 1070 wer-Do 0.6 Po 1060 Po 0.4 1050 0.2 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 AV (V) AV (V) DD DD Figure33. Figure34. POWER-DOWNCURRENT POWER-SUPPLYCURRENT vsTEMPERATURE vsLOGICINPUTVOLTAGE 3.0 3200 AV = IOV = 5.5V, Internal V Included AV = 5.5V DD DD REF DD SYNCInput (all other digital inputs = GND) wer-Down Current (mA) 2211....5050 mwer-Supply Current (A) 2221840600000000 Sweep from S0Vw etoe p5 .f5roVm Po 0.5 Po 1200 5.5V to 0V 0 800 -40 -20 0 20 40 60 80 100 120 0 1 2 3 4 5 6 Temperature (°C) V (V) LOGIC Figure35. Figure36. 14 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 TYPICAL CHARACTERISTICS: DAC at AV = 5V (continued) DD AtT =+25°C,externalreferenceused,DACoutputnotloaded,andallDACcodesinstraightbinarydataformat,unless A otherwisenoted. TOTALHARMONICDISTORTION TOTALHARMONICDISTORTION vsOUTPUTFREQUENCY vsOUTPUTFREQUENCY -40 -40 AV = 5V, External V = 4.9V, Ch A AV = 5V, External V = 4.9V, Ch B DD REF DD REF -50 -1dB FSR Digital Input, fS= 225kSPS -50 -1dB FSR Digital Input, fS= 225kSPS Measurement Bandwidth = 20kHz Measurement Bandwidth = 20kHz -60 -60 B) B) THD d d D ( -70 D ( -70 H THD H T T 2nd Harmonic -80 -80 3rd Harmonic -90 -90 2nd Harmonic 3rd Harmonic -100 -100 0 1 2 3 4 5 0 1 2 3 4 5 f (kHz) f (kHz) OUT OUT Figure37. Figure38. TOTALHARMONICDISTORTION TOTALHARMONICDISTORTION vsOUTPUTFREQUENCY vsOUTPUTFREQUENCY -40 -40 AV = 5V, External V = 4.9V, Ch C AV = 5V, External V = 4.9V, Ch D DD REF DD REF -50 -1dB FSR Digital Input, fS= 225kSPS -50 -1dB FSR Digital Input, fS= 225kSPS Measurement Bandwidth = 20kHz Measurement Bandwidth = 20kHz -60 -60 B) B) -70 d d D ( -70 D ( THD 2nd Harmonic H THD H -80 T T -80 -90 3rd Harmonic 3rd Harmonic -90 -100 2nd Harmonic -100 -110 0 1 2 3 4 5 0 1 2 3 4 5 f (kHz) f (kHz) OUT OUT Figure39. Figure40. POWER-SUPPLYCURRENT HISTOGRAM 60 AV = 5.5V DD Internal V Included 50 REF %) 40 e ( c en 30 urr c Oc 20 10 0 950 1000 1050 1100 1150 1200 Power-Supply Current (mA) Figure41. Copyright©2007–2011,TexasInstrumentsIncorporated 15

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AV = 5V (continued) DD AtT =+25°C,externalreferenceused,DACoutputnotloaded,andallDACcodesinstraightbinarydataformat,unless A otherwisenoted. SIGNAL-TO-NOISERATIO vsOUTPUTFREQUENCY POWERSPECTRALDENSITY 94 0 AV = 5V, External V = 4.9V AV = 5V, External V = 4.9V DD REF DD REF -1dB FSR Digital Input, fS= 225kSPS -20 fOUT= 1kHz, fS= 225kSPS Measurement Bandwidth = 20kHz Measurement Bandwidth = 20kHz 92 Ch A Ch D -40 B) B) -60 d d R ( 90 n ( N ai -80 S Ch C G Ch B -100 88 -120 86 -140 0 1 2 3 4 5 0 5 10 15 20 f (kHz) Frequency (Hz) OUT Figure42. Figure43. FULL-SCALESETTLINGTIME: FULL-SCALESETTLINGTIME: 5VRISINGEDGE 5VFALLINGEDGE Trigger Pulse 5V/div Trigger Pulse 5V/div AV = 5V DD Ext V = 4.096V REF From Code: FFFFh AV = 5V DD To Code: 0000h Ext V = 4.096V REF From Code: 0000h To Code: FFFFh Rising Edge Falling 1V/div Zoomed Rising Edge Edge Zoomed Falling Edge 1mV/div 1V/div 1mV/div Time (2ms/div) Time (2ms/div) Figure44. Figure45. HALF-SCALESETTLINGTIME: HALF-SCALESETTLINGTIME: 5VRISINGEDGE 5VFALLINGEDGE Trigger Pulse 5V/div Trigger Pulse 5V/div AV = 5V DD Ext V = 4.096V REF From Code: C000h To Code: 4000h AV = 5V DD Ext V = 4.096V Rising From RCEoFde: 4000h Edge To Code: C000h Falling 1V/div Zoomed Rising Edge Edge Zoomed Falling Edge 1mV/div 1V/div 1mV/div Time (2ms/div) Time (2ms/div) Figure46. Figure47. 16 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 TYPICAL CHARACTERISTICS: DAC at AV = 5V (continued) DD AtT =+25°C,externalreferenceused,DACoutputnotloaded,andallDACcodesinstraightbinarydataformat,unless A otherwisenoted. GLITCHENERGY: GLITCHENERGY: 5V,1LSBSTEP,RISINGEDGE 5V,1LSBSTEP,FALLINGEDGE v) v) di di V/ V/ m m 0 0 0 0 5 5 ( ( VOUT AInVt DVDRE=F 5=V 2.5V VOUT AInVt DVDRE=F 5=V 2.5V From Code: 7FFFh From Code: 8000h To Code: 8000h To Code: 7FFFh Glitch: 0.08nV-s Glitch: 0.16nV-s Time (400ns/div) Time (400ns/div) Figure48. Figure49. GLITCHENERGY: GLITCHENERGY: 5V,16LSBSTEP,RISINGEDGE 5V,16LSBSTEP,FALLINGEDGE v) v) di di V/ V/ m m 0 0 0 0 5 5 ( ( VOUT AFInrVto DVmDR EC=F o5=dV e2:. 58V000h VOUT AFInrVto DVmDR EC=F o5=dV e2:. 58V010h To Code: 8010h To Code: 8000h Glitch: 0.04nV-s Glitch: 0.08nV-s Time (400ns/div) Time (400ns/div) Figure50. Figure51. GLITCHENERGY: GLITCHENERGY: 5V,256LSBSTEP,RISINGEDGE 5V,256LSBSTEP,FALLINGEDGE v) v) di di V/ V/ m m 5 5 ( ( UT UT O O V AVDD= 5V V AVDD= 5V Int V = 2.5V Int V = 2.5V REF REF From Code: 8000h From Code: 8100h To Code: 8100h To Code: 8000h Glitch: Not Detected Glitch: Not Detected Time (400ns/div) Time (400ns/div) Figure52. Figure53. Copyright©2007–2011,TexasInstrumentsIncorporated 17

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AV = 5V (continued) DD AtT =+25°C,externalreferenceused,DACoutputnotloaded,andallDACcodesinstraightbinarydataformat,unless A otherwisenoted. DACOUTPUTNOISEDENSITY DACOUTPUTNOISEDENSITY vs vs FREQUENCY(1) FREQUENCY (2) 1200 400 Internal Reference Enabled DAC = Full-Scale No Load at VREFH/VREFOUT Pin 350 Internal Reference Enabled 1000 4.8mF versus No Load at V H/V OUT Pin REF REF 300 )Hz 800 )Hz 250 Ö Ö V/ V/ n 600 n 200 se ( Mid-Scale se ( No Load on Reference oi oi 150 N 400 N Full Scale Zero Scale 100 200 4.8mF Capacitor 50 On Reference 0 0 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) Figure54. Figure55. DACOUTPUTNOISE 0.1HzTO10Hz 6mV (peak-to-peak) v) di V/ m 2 ( E S OI N V DAC = Mid-Scale Internal Reference Enabled Time (2s/div) Figure56. (1) ExplainedinmoredetailintheApplicationInformationsectionofthisdatasheet. (2) SeetheApplicationInformationsectionformoreinformation. 18 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 TYPICAL CHARACTERISTICS: DAC at AV = 3.6V DD AtT =+25°C,internalreferenceused,andDACoutputnotloaded,allDACcodesinstraightbinarydataformat,unless A otherwisenoted POWER-SUPPLYCURRENT POWER-SUPPLYCURRENT vs vs LOGICINPUTVOLTAGE TEMPERATURE 2400 1400 AVDD= IOVDD= 3.6V, Internal VREFIncluded AVDD= 3.6V SYNCInput (all other digital inputs = GND) 1300 Internal VREFIncluded A) A) DAC Loaded with 8000h mnt ( 2000 mnt ( 1200 e e urr urr C C pply 1600 Sweep from 0V to 3.6V pply 1100 u u er-S er-S 1000 w 1200 w o o P P 900 Sweep from 3.6V to 0V 800 800 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -40 -20 0 20 40 60 80 100 120 V (V) Temperature (°C) LOGIC Figure57. Figure58. POWER-SUPPLYCURRENT HISTOGRAM 80 AV = 3.6V DD Internal V Included REF 60 %) e ( c en 40 urr c c O 20 0 900 950 1000 1050 1100 1150 1200 Power-Supply Current (mA) Figure59. Copyright©2007–2011,TexasInstrumentsIncorporated 19

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AV = 2.7V DD AtT =+25°C,internalreferenceused,andDACoutputnotloaded,allDACcodesinstraightbinarydataformat,unless A otherwisenoted LINEARITYERRORAND LINEARITYERRORAND DIFFERENTIALLINEARITYERROR DIFFERENTIALLINEARITYERROR vsDIGITALINPUTCODE(–40°C) vsDIGITALINPUTCODE(–40°C) 6 6 Channel A Channel B 4 4 AV = 2.7V, Internal V = 2.5V AV = 2.7V, Internal V = 2.5V B) 2 DD REF B) 2 DD REF S S L 0 L 0 E ( -2 E ( -2 L L -4 -4 -6 -6 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0 E (L 0 DL -0.5 DL -0.5 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Digital Input Code Figure60. Figure61. LINEARITYERRORAND LINEARITYERRORAND DIFFERENTIALLINEARITYERROR DIFFERENTIALLINEARITYERROR vsDIGITALINPUTCODE(–40°C) vsDIGITALINPUTCODE(–40°C) 6 6 Channel D 4 4 AV = 2.7V, Internal V = 2.5V B) 2 B) 2 DD REF S S L 0 L 0 E ( -2 E ( -2 L Channel C L -4 AV = 2.7V, Internal V = 2.5V -4 -6 DD REF -6 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0 E (L 0 DL -0.5 DL -0.5 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Digital Input Code Figure62. Figure63. 20 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 TYPICAL CHARACTERISTICS: DAC at AV = 2.7V (continued) DD AtT =+25°C,internalreferenceused,andDACoutputnotloaded,allDACcodesinstraightbinarydataformat,unless A otherwisenoted LINEARITYERRORAND LINEARITYERRORAND DIFFERENTIALLINEARITYERROR DIFFERENTIALLINEARITYERROR vsDIGITALINPUTCODE(+25°C) vsDIGITALINPUTCODE(+25°C) 6 6 Channel A Channel B 4 4 AV = 2.7V, Internal V = 2.5V AV = 2.7V, Internal V = 2.5V B) 2 DD REF B) 2 DD REF S S L 0 L 0 E ( -2 E ( -2 L L -4 -4 -6 -6 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0 E (L 0 DL -0.5 DL -0.5 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Digital Input Code Figure64. Figure65. LINEARITYERRORAND LINEARITYERRORAND DIFFERENTIALLINEARITYERROR DIFFERENTIALLINEARITYERROR vsDIGITALINPUTCODE(+25°C) vsDIGITALINPUTCODE(+25°C) 6 6 Channel D 4 4 AV = 2.7V, Internal V = 2.5V B) 2 B) 2 DD REF S S L 0 L 0 E ( -2 E ( -2 L Channel C L -4 AV = 2.7V, Internal V = 2.5V -4 -6 DD REF -6 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0 E (L 0 DL -0.5 DL -0.5 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Digital Input Code Figure66. Figure67. Copyright©2007–2011,TexasInstrumentsIncorporated 21

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AV = 2.7V (continued) DD AtT =+25°C,internalreferenceused,andDACoutputnotloaded,allDACcodesinstraightbinarydataformat,unless A otherwisenoted LINEARITYERRORAND LINEARITYERRORAND DIFFERENTIALLINEARITYERROR DIFFERENTIALLINEARITYERROR vsDIGITALINPUTCODE(+105°C) vsDIGITALINPUTCODE(+105°C) 6 6 Channel A Channel B 4 4 AV = 2.7V, Internal V = 2.5V AV = 2.7V, Internal V = 2.5V B) 2 DD REF B) 2 DD REF S S L 0 L 0 E ( -2 E ( -2 L L -4 -4 -6 -6 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0 E (L 0 DL -0.5 DL -0.5 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Digital Input Code Figure68. Figure69. LINEARITYERRORAND LINEARITYERRORAND DIFFERENTIALLINEARITYERROR DIFFERENTIALLINEARITYERROR vsDIGITALINPUTCODE(+105°C) vsDIGITALINPUTCODE(+105°C) 6 6 Channel C Channel D B) 42 AVDD= 2.7V, Internal VREF= 2.5V B) 42 AVDD= 2.7V, Internal VREF= 2.5V S S L 0 L 0 E ( -2 E ( -2 L L -4 -4 -6 -6 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0 E (L 0 DL -0.5 DL -0.5 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Digital Input Code Figure70. Figure71. 22 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 TYPICAL CHARACTERISTICS: DAC at AV = 2.7V (continued) DD AtT =+25°C,internalreferenceused,andDACoutputnotloaded,allDACcodesinstraightbinarydataformat,unless A otherwisenoted OFFSETERROR FULL-SCALEERROR vsTEMPERATURE vsTEMPERATURE 4 0.50 AVDD= 2.7V AVDD= 2.7V Internal VREFEnabled Ch C Internal VREFEnabled 3 Ch C V) mV) 0.25 Ch D Error (m 2 e Error ( 0 Offset 1 Ch D Ch B Full-Scal -0.25 Ch A Ch B 0 -1 Ch A -0.50 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) Figure72. Figure73. SOURCEANDSINK SOURCEANDSINK CURRENTCAPABILITY CURRENTCAPABILITY 3.0 3.0 DAC Loaded with FFFFh DAC Loaded with FFFFh 2.5 2.5 V) V) e( e ( ag 2.0 ag 2.0 olt AVDD= 2.7V, Ch A olt AVDD= 2.7V, Ch B ut V 1.5 Internal Reference Enabled ut V 1.5 Internal Reference Enabled p p ut ut O O g 1.0 g 1.0 o o al al n n A A 0.5 0.5 DAC Loaded with 0000h DAC Loaded with 0000h 0 0 0 5 10 15 20 0 5 10 15 20 I (mA) I (mA) SOURCE/SINK SOURCE/SINK Figure74. Figure75. SOURCEANDSINK SOURCEANDSINK CURRENTCAPABILITY CURRENTCAPABILITY 3.0 3.0 DAC Loaded with FFFFh DAC Loaded with FFFFh 2.5 2.5 V) V) e ( e ( ag 2.0 ag 2.0 olt AVDD= 2.7V, Ch C olt AVDD= 2.7V, Ch D ut V 1.5 Internal Reference Enabled ut V 1.5 Internal Reference Enabled p p ut ut O O g 1.0 g 1.0 o o al al n n A A 0.5 0.5 DAC Loaded with 0000h DAC Loaded with 0000h 0 0 0 5 10 15 20 0 5 10 15 20 I (mA) I (mA) SOURCE/SINK SOURCE/SINK Figure76. Figure77. Copyright©2007–2011,TexasInstrumentsIncorporated 23

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AV = 2.7V (continued) DD AtT =+25°C,internalreferenceused,andDACoutputnotloaded,allDACcodesinstraightbinarydataformat,unless A otherwisenoted POWER-SUPPLYCURRENT POWER-SUPPLYCURRENT vsDIGITALINPUTCODE vsLOGICINPUTVOLTAGE 1300 1600 AV = 2.7V AV = 2.7V, Internal V Included DD DD REF Internal V Included SYNCInput (all other digital inputs = GND) REF A) 1200 A) m m 1400 nt( nt ( e e urr 1100 urr C C y y 1200 Suppl 1000 Suppl S2w.7eVe pto f r0oVm Sweep from 0V to 2.7V er- er- w w 1000 Po 900 Po 800 800 0 8192 16384 24576 32768 40960 49152 57344 65536 0 0.5 1.0 1.5 2.0 2.5 3.0 Digital Input Code V (V) LOGIC Figure78. Figure79. FULL-SCALESETTLINGTIME: FULL-SCALESETTLINGTIME: 2.7VRISINGEDGE 2.7VFALLINGEDGE Trigger Pulse 2.7V/div Trigger Pulse 2.7V/div AV = 2.7V DD Int V = 2.5V Rising REF From Code: FFFFh Edge To Code: 0000h 0.5V/div AV = 2.7V DD Int V = 2.5V REF From Code: 0000h To Code: FFFFh Zoomed Falling Edge Falling 1mV/div Zoomed Rising Edge Edge 1mV/div 0.5V/div Time (2ms/div) Time (2ms/div) Figure80. Figure81. HALF-SCALESETTLINGTIME: HALF-SCALESETTLINGTIME: 2.7VRISINGEDGE 2.7VFALLINGEDGE Trigger Pulse 2.7V/div Trigger Pulse 2.7V/div AV = 2.7V DD Int V = 2.5V REF From Code: C000h To Code: 4000h AV = 2.7V DD Int V = 2.5V REF From Code: 4000h To Code: C000h Rising Falling Edge Zoomed Rising Edge Edge Zoomed Falling Edge 0.5V/div 1mV/div 0.5V/div 1mV/div Time (2ms/div) Time (2ms/div) Figure82. Figure83. 24 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 TYPICAL CHARACTERISTICS: DAC at AV = 2.7V (continued) DD AtT =+25°C,internalreferenceused,andDACoutputnotloaded,allDACcodesinstraightbinarydataformat,unless A otherwisenoted GLITCHENERGY: GLITCHENERGY: 2.7V,1LSBSTEP,RISINGEDGE 2.7V,1LSBSTEP,FALLINGEDGE v) v) di di V/ V/ m m 0 0 0 0 2 2 ( ( UT UT VO AVDD= 2.7V VO AVDD= 2.7V Int VREF= 2.5V Int VREF= 2.5V From Code: 7FFFh From Code: 8000h To Code: 8000h To Code: 7FFFh Glitch: 0.08nV-s Glitch: 0.16nV-s Time (400ns/div) Time (400ns/div) Figure84. Figure85. GLITCHENERGY: GLITCHENERGY: 2.7V,16LSBSTEP,RISINGEDGE 2.7V,16LSBSTEP,FALLINGEDGE v) v) di di V/ V/ m m 0 0 0 0 2 2 ( ( VOUT AIFnrVto DVmDR EC=F o2=d.7 e2V:. 58V000h VOUT AIFnrVto DVmDR EC=F o2=d.7 e2V:. 58V010h To Code: 8010h To Code: 8000h Glitch: 0.04nV-s Glitch: 0.12nV-s Time (400ns/div) Time (400ns/div) Figure86. Figure87. GLITCHENERGY: GLITCHENERGY: 2.7V,256LSBSTEP,RISINGEDGE 2.7V,256LSBSTEP,FALLINGEDGE v) v) di di V/ V/ m m 5 5 ( ( UT UT VO AVDD= 2.7V VO AVDD= 2.7V Int V = 2.5V Int V = 2.5V REF REF From Code: 8000h From Code: 8100h To Code: 8100h To Code: 8000h Glitch: Not Detected Glitch: Not Detected Time (400ns/div) Time (400ns/div) Figure88. Figure89. Copyright©2007–2011,TexasInstrumentsIncorporated 25

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AV = 2.7V (continued) DD AtT =+25°C,internalreferenceused,andDACoutputnotloaded,allDACcodesinstraightbinarydataformat,unless A otherwisenoted POWER-SUPPLYCURRENT POWER-DOWNCURRENT vsTEMPERATURE vsTEMPERATURE 1400 2.0 AV = 2.7V AV = 2.7V DD DD Internal V Included mwer-Supply Current (A) 1111321000000000 DAC LoadReEdF with 8000h wer-Down Current (mA) 110...505 Po 900 Po 800 0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) Figure90. Figure91. 26 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER (DAC) V REF The DAC8564 architecture consists of a string DAC followed by an output buffer amplifier. Figure 92 R showsablockdiagramoftheDACarchitecture. DIVIDER V REF VREFH 50kW 50kW 2 R 62kW DAC REF(+) VOUTX Resistor String Register REF(-) To Output Amplifier R (2x Gain) V L REF Figure92. DAC8564Architecture The input coding to the DAC8564 is straight binary, sotheidealoutputvoltageisgivenbyEquation1. D V X(cid:4)2(cid:1)V L(cid:2)(V H(cid:3)V L)(cid:1) IN OUT REF REF REF 65536 (1) R where D = decimal equivalent of the binary code IN that is loaded to the DAC register; it can range from 0 to65535.XrepresentschannelA,B,C,orD. R RESISTOR STRING The resistor string section is shown in Figure 93. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to Figure93. ResistorString be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. It is monotonicbecauseitisastringofresistors. OUTPUT AMPLIFIER The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0V to AV . It is capable of driving a load of DD 2kΩ in parallel with 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the Typical Characteristics. The slew rate is 2.2V/μs, with a full-scale settling time of 8μs with the output unloaded. Copyright©2007–2011,TexasInstrumentsIncorporated 27

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com INTERNAL REFERENCE V REF The DAC8564 includes a 2.5V internal reference that is enabled by default. The internal reference is externally available at the V H/V OUT pin. A REF REF minimum 100nF capacitor is recommended between thereferenceoutputandGNDfornoisefiltering. Reference The internal reference of the DAC8564 is a bipolar Disable transistor-based, precision bandgap voltage reference. Figure 94 shows the basic bandgap Q 1 N Q 1 2 topology. Transistors Q and Q are biased such that 1 2 the current density of Q is greater than that of Q . 1 2 R The difference of the two base-emitter voltages 1 (V – V ) has a positive temperature coefficient BE1 BE2 and is forced across resistor R . This voltage is 1 R gained up and added to the base-emitter voltage of 2 Q ,whichhasanegativetemperaturecoefficient.The 2 resulting output voltage is virtually independent of temperature. The short-circuit current is limited by Figure94. SimplifiedSchematicoftheBandgap designtoapproximately100mA. Reference Enable/DisableInternalReference To then enable the internal reference, either perform a power-cycle to reset the device, or write the 24-bit The internal reference in the DAC8564 is enabled by serial command shown in Table 2. These actions put defaultandoperatesinautomaticmode;however,the the internal reference back into the default mode. In reference can be disabled for debugging, evaluation the default mode, the internal reference powers down purposes, or when using an external reference. A automatically when all DACs power down in any of serial command that requires a 24-bit write sequence the power-down modes (see the Power-Down Modes (see the Serial Interface section) must be used to section); the internal reference powers up disable the internal reference, as shown in Table 1. automaticallywhenanyDACispoweredup. During the time that the internal reference is disabled, the DAC functions normally using an external The DAC8564 also provides the option of keeping the reference. At this point, the internal reference is internal reference powered on all the time, regardless disconnected from the VREFH/VREFOUT pin (3-state of the DAC(s) state (powered up or down). To keep output). Do not attempt to drive the VREFH/VREFOUT the internal reference powered on, regardless of the pin externally and internally at the same time DAC(s) state, write the 24-bit serial command shown indefinitely. inTable3. Table1.WriteSequenceforDisablingInternalReference (internalreferencealwayspowereddown—012000h) DB23 DB16 DB13 DB0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 |—————————————————–DataBits––—————————————————| Table2.WriteSequenceforEnablingInternalReference (internalreferencepowereduptodefaultmode—010000h) DB23 DB16 DB0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |—————————————————–DataBits––—————————————————| Table3.WriteSequenceforEnablingInternalReference (internalreferencealwayspoweredup—011000h) DB23 DB16 DB12 DB0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 |—————————————————–DataBits––—————————————————| 28 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 SERIAL INTERFACE begin the next cycle. To assure the lowest power consumption of the device, care should be taken that The DAC8564 has a 3-wire serial interface (SYNC, the levels are as close to each rail as possible. Refer SCLK, and D ) compatible with SPI, QSPI, and IN to the Typical Characteristics section for Figure 36, Microwire interface standards, as well as most DSPs. Figure 57, and Figure 79 (Supply Current vs Logic See the Serial Write Operation timing diagram for an InputVoltage). exampleofatypicalwritesequence. The DAC8564 input shift register is 24 bits wide, IOV AND VOLTAGE TRANSLATORS DD consistingofeightcontrolbits(DB23toDB16)and16 The IOV pin powers the digital input structures of data bits (DB15 to DB0). All 24 bits of data are DD the DAC8564. For single-supply operation, it can be loaded into the DAC under the control of the serial tiedtoAV .Fordual-supplyoperation,theIOV pin clock input, SCLK. DB23 (MSB) is the first bit that is DD DD provides interface flexibility with various CMOS logic loaded into the DAC shift register, and is followed by families and should be connected to the logic supply the rest of the 24-bit word pattern, left-aligned. This of the system. Analog circuits and internal logic of the configuration means that the first 24 bits of data are DAC8564 use AV as the supply voltage. The latched into the shift register and any further clocking DD external logic high inputs translate to AV by level of data is ignored. The DAC8564 receives all 24 bits DD shifters.TheselevelshiftersusetheIOV voltageas of data and decodes the first eight bits to determine DD a reference to shift the incoming logic HIGH levels to the DAC operating/control mode. The 16 bits of data AV . IOV is ensured to operate from 2.7V to 5.5V that follow are decoded by the DAC to determine the DD DD regardless of the AV voltage, assuring compatibility equivalent analog output. The data format is straight DD withvariouslogicfamilies.Althoughspecifieddownto binary with all '0's corresponding to 0V output and all 2.7V, IOV operates at as low as 1.8V with '1's corresponding to full-scale output (that is, V – DD REF degraded timing and temperature performance. For 1LSB). lowest power consumption, logic V levels should be IH The write sequence begins by bringing the SYNC line as close as possible to IOV , and logic V levels DD IL low. Data from the D line are clocked into the 24-bit shouldbeascloseaspossibletoGNDvoltages. IN shift register on each falling edge of SCLK. The serial clock frequency can be as high as 50MHz, making INPUT SHIFT REGISTER the DAC8564 compatible with high-speed DSPs. On The input shift register (SR) of the DAC8564 is 24 the 24th falling edge of the serial clock, the last data bits wide, as shown in Table 4, and consists of eight bit is clocked into the shift register and the shift control bits (DB23 and DB16) and 16 data bits (DB15 register locks. Further clocking does not change the to DB0). The first two control bits (DB23 and DB22) shift register data. Once 24 bits are locked into the are the address match bits. The DAC8564 offers shift register, the eight MSBs are used as control bits hardware-enabled addressing capability, allowing a andthe16LSBsareusedasdata.Afterreceivingthe single host to talk to up to four DAC8564s through a 24th falling clock edge, the DAC8564 decodes the single SPI bus without any glue logic, enabling up to eight control bits and 16 data bits to perform the 16-channel operation. The state of DB23 should required function, without waiting for a SYNC rising match the state of pin A1; similarly, the state of DB22 edge. A new write sequence starts at the next falling should match the state of pin A0. If there is no match, edge of SYNC. A rising edge of SYNC before the the control command and the data (DB21...DB0) are 24-bit sequence is complete resets the SPI interface; ignored by the DAC8564. That is, if there is no no data transfer occurs. After the 24th falling edge of match, the DAC8564 is not addressed. Address SCLK is received, the SYNC line may be kept LOW matchingcanbeoverriddenbythebroadcastupdate. or brought HIGH. In either case, the minimum delay time from the 24th falling SCLK edge to the next falling SYNC edge must be met in order to properly Table4.DataInputRegisterFormat DB23 DB12 A1 A0 LD1 LD0 0 DACSelect1 DACSelect0 PD0 D15 D14 D13 D12 DB11 DB0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Copyright©2007–2011,TexasInstrumentsIncorporated 29

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com LD1 (DB21) and LD0 (DB20) control the loading of DB21 = 0 and DB20 = 1: Single-channel update. each analog output with the specified 16-bit data The data buffer and DAC register corresponding to a value or power-down command. Bit DB19 must DAC selected by DB18 and DB17 update with the always be '0'. The DAC channel select bits (DB18, contentsofSRdata(orpower-down). DB17) control the destination of the data (or DB21 = 1 and DB20 = 0: Simultaneous update. A power-down command) from DAC A through DAC D. channel selected by DB18 and DB17 updates with The final control bit, PD0 (DB16), selects the the SR data; simultaneously, all the other channels power-down mode of the DAC8564 channels as well update with previously stored data (or power-down) asthepower-downmodeoftheinternalreference. fromdatabuffers. The DAC8564 supports a number of different load DB21 = 1 and DB20 = 1: Broadcast update. All the commands. The load commands include broadcast DAC8564s on the SPI bus respond, regardless of commands to address all the DAC8564s on an SPI address matching. If DB18 = 0, SR data are ignored bus.Theloadcommandsaresummarizedasfollows: and any channels from all DAC8564s update with previously stored data (or power-down). If DB18 = 1, DB21 = 0 and DB20 = 0: Single-channel store. The SR data (or power-down) update any channels of all data buffer corresponding to a DAC selected by DAC8564s in the system. This broadcast update DB18 and DB17 updates with the contents of SR feature allows the simultaneous update of up to 16 data(orpower-down). channels. RefertoTable5formoreinformation. Table5.ControlMatrixfortheDAC8564 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13-DB0 A1 A0 LD1 LD0 0 DACSel1 DACSel0 PD0 MSB MSB-1 MSB-2...LSB (AddressSelect) DESCRIPTION Thisaddressselectsoneoffourpossibledevicesona 0/1 0/1 SeeBelow singleSPIdatabusbasedontheaddresspin(s)state ofeachdevice. 0 0 0 0 0 0 Data WritetobufferAwithdata 0 0 0 0 1 0 Data WritetobufferBwithdata 0 0 0 1 0 0 Data WritetobufferCwithdata 0 0 0 1 1 0 Data WritetobufferDwithdata Writetobuffer(selectedbyDB17andDB18)with 0 0 0 (00,01,10,or11) 1 SeeTable6 0 power-downcommand A0andA1should correspondtothe WritetobufferwithdataandloadDAC(selectedby packageaddress 0 1 0 (00,01,10,or11) 0 Data DB17andDB18) setviapins13 and14 0 1 0 (00,01,10,or11) 1 SeeTable6 0 Writetobufferwithpower-downcommandandload DAC(selectedbyDB17andDB18) Writetobufferwithdata(selectedbyDB17andDB18) 1 0 0 (00,01,10,or11) 0 Data andthenloadallDACssimultaneouslyfromtheir correspondingbuffers Writetobufferwithpower-downcommand(selectedby 1 0 0 (00,01,10,or11) 1 SeeTable6 0 DB17andDB18)andthenloadallDACs simultaneouslyfromtheircorrespondingbuffers BroadcastModes SimultaneouslyupdateallchannelsofallDAC8564 X X 1 1 0 0 X X X devicesinthesystemwithdatastoredineach channelsdatabuffer X X 1 1 0 1 X 0 Data WritetoalldevicesandloadallDACswithSRdata WritetoalldevicesandloadallDACswithpower-down X X 1 1 0 1 X 1 SeeTable6 0 commandinSR 30 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 SYNC INTERRUPT LDAC FUNCTIONALITY In a normal write sequence, the SYNC line stays low The DAC8564 offers both a software and hardware for at least 24 falling edges of SCLK and the simultaneous update function. The DAC addressed DAC register updates on the 24th falling double-buffered architecture has been designed so edge. However, if SYNC is brought high before the that new data can be entered for each DAC without 24th falling edge, it acts as an interrupt to the write disturbingtheanalogoutputs. sequence; the shift register resets and the write DAC8564 data updates are synchronized with the sequence is discarded. Neither an update of the data falling edge of the 24th SCLK cycle, which follows a buffer contents, DAC register contents, nor a change fallingedgeofSYNC.Forsuchsynchronousupdates, in the operating mode occurs (as shown in the LDAC pin is not required and it must be Figure95). connected to GND permanently. The LDAC pin is used as a positive edge triggered timing signal for POWER-ON RESET TO ZERO-SCALE asynchronous DAC updates. To do an LDAC The DAC8564 contains a power-on reset circuit that operation, single-channel store(s) should be done controls the output voltage during power-up. On (loading DAC buffers) by setting LD0 and LD1 to '0'. power-up, the DAC registers are filled with zeros and Multiple single-channel updates can be done in order the output voltages are set to zero-scale; they remain to set different channel buffers to desired values and that way until a valid write sequence and load then make a rising edge on LDAC. Data buffers of all command are made to the respective DAC channel. channels must be loaded with desired data before an The power-on reset is useful in applications where it LDAC rising edge. After a low-to-high LDAC is important to know the state of the output of each transition, all DACs are simultaneously updated with DAC while the device is in the process of powering the contents of the corresponding data buffers. If the up. contents of a data buffer are not changed by the serial interface, the corresponding DAC output No device pin should be brought high before power is remainsunchangedaftertheLDACtrigger. applied to the device. The internal reference is powered on by default and remains that way until a ENABLE PIN validreference-changecommandisexecuted. For normal operation, the enable pin must be driven to a logic low. If the enable pin is driven high, the DAC8564 stops listening to the serial port. However, SCLK, SYNC, and D must not be kept floating, but IN must be at some logic level. This feature can be usefulforapplicationsthatsharethesameserialport. 24th Falling Edge 24th Falling Edge CLK SYNC DIN DB23 DB0 DB23 DB0 Invalid/Interrupted Write Sequence: Valid Write Sequence: Output/Mode Does Not Updateon the 24th Falling Edge Output/Mode Updateson the 24th Falling Edge Figure95. SYNCInterruptFacility Copyright©2007–2011,TexasInstrumentsIncorporated 31

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com POWER-DOWN MODES DACs. However, for the three power-down modes, the supply current falls to 1.3μA at 5.5V (0.5μA at The DAC8564 has two separate sets of power-down 3.6V). Not only does the supply current fall, but the commands. One set is for the DAC channels and the output stage also switches internally from the output other set is for the internal reference. For more oftheamplifiertoaresistornetworkofknownvalues. information on powering down the reference, see the Enable/DisableInternalReferencesection. The advantage of this switching is that the output impedance of the device is known while it is in DACPower-DownCommands power-downmode.AsdescribedinTable6,thereare three different power-down options. V can be The DAC8564 uses four modes of operation. These OUT connectedinternallytoGNDthrougha1kΩ resistor,a modes are accessed by setting three bits (PD2, PD1, 100kΩ resistor, or open circuited (High-Z). The output and PD0) in the shift register. Table 6 shows how to stage is shown in Figure 96. In other words, DB16, control the operating mode with data bits PD0 DB15, and DB14 = '111' represent a power-down (DB16),PD1(DB15),andPD2(DB14). condition with Hi-Z output impedance for a selected channel. '101' represents a power-down condition Table6.DACOperatingModes with 1kΩ output impedance, and '110' represents a PD0 PD1 PD2 power-downconditionwith100kΩ outputimpedance. (DB16) (DB15) (DB14) DACOPERATINGMODES 0 X X Normaloperation 1 0 1 Outputtypically1kΩtoGND Resistor 1 1 0 Outputtypically100kΩtoGND String Amplifier VOUTX DAC 1 1 1 Outputhigh-impedance The DAC8564 treats the power-down condition as data; all the operational modes are still valid for Power-Down Resistor power-down.Itispossibletobroadcastapower-down Circuitry Network condition to all the DAC8564s in a system; it is also possible to simultaneously power-down a channel whileupdatingdataonotherchannels. Figure96. OutputStageDuringPower-Down When the PD0 bit is set to '0', the device works normally with its typical current consumption of 1mA All analog channel circuitries are shut down when the at 5.5V with an input code = 32768. The reference power-down mode is exercised. However, the current is included with the operation of all four contents of the DAC register are unaffected when in power down. The time required to exit power-down is typically 2.5μs for V = 5V, and 5μs for V = 3V. DD DD SeetheTypicalCharacteristicsformoreinformation. 32 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 OPERATING EXAMPLES: DAC8564 For the following examples, ensure that DAC pins A0 and A1 are both connected to ground. Pins A0 and A1 must always match data bits DB22 and DB23 within the SPI write sequence/protocol. X = don't care. Value can beeither'0'or'1'. Example1:WritetoDataBufferAThroughBufferD;LoadDACAThroughDACDSimultaneously • 1st:WritetodatabufferA: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11–D0 • 2nd:WritetodatabufferB: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 0 0 0 1 0 D15 D14 D13 D12 D11–D0 • 3rd:WritetodatabufferC: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 0 0 1 0 0 D15 D14 D13 D12 D11–D0 • 4th:WritetodatabufferDandsimultaneouslyupdateallDACs: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 1 0 0 1 1 0 D15 D14 D13 D12 D11–D0 The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon completionofthe4thwritesequence.(TheDACvoltagesupdatesimultaneouslyafterthe24thSCLKfallingedge ofthefourthwritecycle). Example2:LoadNewDatatoDACAThroughDACDSequentially • 1st:WritetodatabufferAandloadDACA:DACAoutputsettlestospecifiedvalueuponcompletion: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 1 0 0 0 0 D15 D14 D13 D12 D11–D0 • 2nd:WritetodatabufferBandloadDACB:DACBoutputsettlestospecifiedvalueuponcompletion: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 1 0 0 1 0 D15 D14 D13 D12 D11–D0 • 3rd:WritetodatabufferCandloadDACC:DACCoutputsettlestospecifiedvalueuponcompletion: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 1 0 1 0 0 D15 D14 D13 D12 D11–D0 • 4th:WritetodatabufferDandloadDACD:DACDoutputsettlestospecifiedvalueuponcompletion: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 1 0 1 1 0 D15 D14 D13 D12 D11–D0 Aftercompletionofeachwritecycle,DACanalogoutputsettlestothevoltagespecified. Copyright©2007–2011,TexasInstrumentsIncorporated 33

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com Example 3: Power-Down DAC A and DAC B to 1kΩ and Power-Down DAC C and DAC D to 100kΩ Simultaneously • 1st:Writepower-downcommandtodatabufferA:DACAto1kΩ. DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 0 0 0 0 1 0 1 X X X • 2nd:Writepower-downcommandtodatabufferB:DACBto1kΩ. DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 0 0 0 1 1 0 1 X X X • 3rd:Writepower-downcommandtodatabufferC:DACCto100kΩ. DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 0 0 1 0 1 1 0 X X X • 4th:Writepower-downcommandtodatabufferD:DACDto100kΩ andsimultaneouslyupdateallDACs. DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 1 0 0 1 1 1 1 0 X X X TheDACA,DACB,DACC,andDACDanalogoutputssimultaneouslypower-downtoeachrespectivespecified modeuponcompletionofthefourthwritesequence. Example4:Power-DownDACAThroughDACDtoHigh-ImpedanceSequentially • 1st:Writepower-downcommandtodatabufferAandloadDACA:DACAoutput=Hi-Z: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 1 0 0 0 1 1 1 X X X • 2nd:Writepower-downcommandtodatabufferBandloadDACB:DACBoutput=Hi-Z: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 1 0 0 1 1 1 1 X X X • 3rd:Writepower-downcommandtodatabufferCandloadDACC:DACCoutput=Hi-Z: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 1 0 1 0 1 1 1 X X X • 4th:Writepower-downcommandtodatabufferDandloadDACD:DACDoutput=Hi-Z: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 1 0 1 1 1 1 1 X X X The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon completionofthefirst,second,third,andfourthwritesequences,respectively. 34 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 Example5:Power-DownAllChannelsSimultaneouslywhileReferenceisAlwaysPoweredUp • 1st:WritesequenceforenablingtheDAC8564internalreferenceallthetime: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 0 0 0 0 1 0 0 0 1 X • 2nd:Writesequencetopower-downallDACstohigh-impedance: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 1 1 0 1 0 1 1 1 X X X The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon completionofthefirstandsecondwritesequences,respectively. Example6:WriteaSpecificValuetoAllDACswhileReferenceisAlwaysPoweredDown • 1st: Write sequence for disabling the DAC8564 internal reference all the time (after this sequence, the DAC8564requiresanexternalreferencesourcetofunction): DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 0 0 0 0 1 0 0 1 0 X • 2nd:WritesequencetowritespecifieddatatoallDACs: DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 1 1 0 1 0 0 D15 D14 D13 D12 D11–D0 The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon completion of the fourth write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling edgeofthefourthwritecycle).Referenceisalwayspowered-down. Example 7: Write a Specific Value to DAC A, while Reference is Placed in Default Mode and All Other DACsarePoweredDowntoHigh-Impedance • 1st: Write sequence for placing the DAC8564 internal reference into default mode. Alternately, this step can bereplacedbyperformingapower-onreset(seethePower-OnResetsection): DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 0 0 0 0 1 0 0 0 0 X • 2nd: Write sequence to power-down all DACs to high-impedance (after this sequence, the DAC8564 internal referencepowersdownautomatically): DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 1 1 0 1 0 1 1 1 X X X • 3rd: Write sequence to power-up DAC A to a specified value (after this sequence, the DAC8564 internal referencepowersupautomatically): DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11–DB0 (A1) (A0) (LD1) (LD0) (DACSel1) (DACSel0) (PD0) 0 0 0 1 0 0 0 0 D15 D14 D13 D12 D11–D0 The DAC B, DAC C, and DAC D analog outputs simultaneously power-down to high-impedance, and DAC A settlestothespecifiedvalueuponcompletion. Copyright©2007–2011,TexasInstrumentsIncorporated 35

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com APPLICATION INFORMATION INTERNAL REFERENCE TemperatureDrift The internal reference of the DAC8564 does not require an external load capacitor for stability The internal reference is designed to exhibit minimal because it is stable with any capacitive load. drift error, defined as the change in reference output However, for improved noise performance, an voltage over varying temperature. The drift is external load capacitor of 150nF or larger connected calculated using the box method described by to the V H/V OUT output is recommended. Equation2: REF REF Figure 97 shows the typical connections required for V -V operation of the DAC8564 internal reference. A Drift Error = REF_MAX REF_MIN ´106(ppm/°C) supply bypass capacitor at the AV input is also V ´T DD REF RANGE recommended. (2) Where: DAC8564 V = maximum reference voltage observed REF_MAX withintemperaturerangeT . RANGE 1 V A LDAC 16 OUT V = minimum reference voltage observed REF_MIN 150nF 2 VOUTB ENABLE 15 withintemperaturerangeTRANGE. 3 VREFH/VREFOUT A1 14 VREF = 2.5V, target value for reference output voltage. AV 4 AV A0 13 DD DD 1mF The internal reference (grades C and D) features an 5 V L IOV 12 REF DD exceptional typical drift coefficient of 2ppm/°C 6 GND D 11 from–40°Cto+120°C.Characterizingalargenumber IN of units, a maximum drift coefficient of 5ppm/°C 7 V C SCLK 10 OUT (grades C and D) is observed. Temperature drift 8 V D SYNC 9 resultsaresummarizedintheTypicalCharacteristics. OUT NoisePerformance Figure97. TypicalConnectionsforOperatingthe Typical 0.1Hz to 10Hz voltage noise can be seen in DAC8564InternalReference Figure 8, Internal Reference Noise. Additional filtering can be used to improve output noise levels, although SupplyVoltage care should be taken to ensure the output impedance does not degrade the ac performance. The output The internal reference features an extremely low noise spectrum at V H/V OUT without any dropout voltage. It can be operated with a supply of REF REF external components is depicted in Figure 7, Internal only 5mV above the reference output voltage in an Reference Noise Density vs Frequency. Another unloaded condition. For loaded conditions, refer to noise density spectrum is also shown in Figure 7. the Load Regulation section. The stability of the This spectrum was obtained using a 4.8μF load internal reference with variations in supply voltage capacitor at V H/V OUT for noise filtering. (line regulation, dc PSRR) is also exceptional. Within REF REF Internal reference noise impacts the DAC output the specified supply voltage range of 2.7V to 5.5V, noise; see the DAC Noise Performance section for the variation at V H/V OUT is less than 10μV/V; REF REF moredetails. seetheTypicalCharacteristics. 36 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 LoadRegulation ThermalHysteresis Load regulation is defined as the change in reference Thermal hysteresis for a reference is defined as the output voltage as a result of changes in load current. change in output voltage after operating the device at The load regulation of the internal reference is +25°C, cycling the device through the operating measured using force and sense contacts as shown temperature range, and returning to +25°C. in Figure 98. The force and sense lines reduce the HysteresisisexpressedbyEquation3: impact of contact and trace resistance, resulting in |V -V | accurate measurement of the load regulation REF_PRE REF_POST V = ´106(ppm/°C) contributed solely by the internal reference. HYST V REF_NOM Measurement results are summarized in the Typical (3) Characteristics. Force and sense lines should be Where: used for applications that require improved load regulation. VHYST=thermalhysteresis. V = output voltage measured at +25°C REF_PRE pre-temperaturecycling. Output Pin Contact and V = output voltage measured after the Trace Resistance REF_POST device cycles through the temperature range of–40°Cto+120°C,andreturnsto+25°C. V OUT Force Line I DAC NOISE PERFORMANCE L Sense Line Typical noise performance for the DAC8564 with the Load Meter internal reference enabled is shown in Figure 54 to Figure 56. Output noise spectral density at the V OUT pin versus frequency is depicted in Figure 54 for full-scale, midscale, and zero-scale input codes. The Figure98. AccurateLoadRegulationofthe typical noise density for midscale code is 120nV/√Hz DAC8564InternalReference at 1kHz and 100nV/√Hz at 1MHz. High-frequency noise can be improved by filtering the reference noise Long-TermStability as shown in Figure 55, where a 4.8μF load capacitor is connected to the V H/V OUT pin and REF REF Long-term stability/aging refers to the change of the compared to the no-load condition. Integrated output output voltage of a reference over a period of months noise between 0.1Hz and 10Hz is close to 6μV PP or years. This effect lessens as time progresses (see (midscale),asshowninFigure56. Figure 6, the typical long-term stability curve). The typical drift value for the internal reference is 50ppm from 0 hours to 1900 hours. This parameter is characterized by powering-up and measuring 20 units atregularintervalsforaperiodof1900hours. Copyright©2007–2011,TexasInstrumentsIncorporated 37

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com BIPOLAR OPERATION USING THE DAC8564 R 2 V H AV 10kW The DAC8564 is designed for single-supply REF DD operation, but a bipolar output range is also possible R +6V 1 using the circuit in either Figure 99 or Figure 100. 10kW The circuit shown gives an output voltage range of OPA703 ±5V ±VREF. Rail-to-rail operation at the amplifier output is AVDD VOUT achievableusinganOPA703astheoutputamplifier. VREFH DAC8564 The output voltage for any input code can be 10mF 0.1mF VREFL GND -6V calculatedwithEquation4: D R + R R 3-Wire V = V ´ ´ 1 2 -V ´ 2 Serial Interface O REF 65536 R REF R 1 1 Figure99. BipolarOutputRangeUsingExternal Referenceat5V (4) where D represents the input code in decimal (0–65535). R 2 AV 10kW WithV H=5V,R =R =10kΩ. DD REF 1 2 10´D R +6V V = -5V 1 O 65536 10kW (5) OPA703 ±2.5V This result has an output voltage range of ±5V with AVDD VOUT 0000h corresponding to a –5V output and FFFFh VREFH DAC8564 corresponding to a +5V output, as shown in -6V Figure 99. Similarly, using the internal reference, a 150nF VREFL GND ±2.5V output voltage range can be achieved, as Figure100shows. 3-Wire Serial Interface Figure100. BipolarOutputRangeUsingInternal Reference 38 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 MICROPROCESSOR INTERFACING DAC8564toMicrowireInterface Figure 102 shows an interface between the DAC8564 DACSPIInterfacing and any Microwire-compatible device. Serial data are Care must be taken with the digital control signals shifted out on the falling edge of the serial clock and that are applied directly to the DAC, especially with are clocked into the DAC8564 on the rising edge of the SYNC pin. The SYNC pin must not be toggled theSKsignal. without having a full SCLK pulse in between. If this condition is violated, the SPI interface locks up in an erroneous state, causing the DAC to behave Microwire(1) DAC8564(1) incorrectly and have errors. The DAC can be CS SYNC recovered from this faulty state by writing a valid SPI SK SCLK command or using the SYNC pin correctly; communication will then be restored. Avoid glitches SO DIN and transients on the SYNC line to ensure proper NOTE: (1) Additional pins omitted for clarity. operation. Figure102. DAC8564toMicrowireInterface DAC8564toan8051Interface Figure 101 shows a serial interface between the DAC8564to68HC11Interface DAC8564 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the Figure 103 shows a serial interface between the 8051 drives SCLK of the DAC8564, while RXD drives DAC8564 and the 68HC11 microcontroller. SCK of the serial data line of the device. The SYNC signal is the 68HC11 drives the SCLK of the DAC8564, while derived from a bit-programmable pin on the port of the MOSI output drives the serial data line of the the 8051; in this case, port line P3.3 is used. When DAC. The SYNC signal derives from a port line data are to be transmitted to the DAC8564, P3.3 is (PC7),similartothe8051diagram. taken low. The 8051 transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left 68HC11(1) DAC8564(1) low after the first eight bits are transmitted; then, a PC7 SYNC second write cycle is initiated to transmit the second SCK SCLK byte of data. P3.3 is taken high following the completion of the third write cycle. The 8051 outputs MOSI D IN the serial data in a format that has the LSB first. The DAC8564 requires its data with the MSB as the first NOTE: (1) Additional pins omitted for clarity. bitreceived.The8051transmitroutinemusttherefore take this requirement into account, and mirror the Figure103. DAC8564to68HC11Interface dataasneeded. The 68HC11 should be configured so that its CPOL bit is '0' and its CPHA bit is '1'. This configuration 80C51/80L51(1) DAC8564(1) causes data appearing on the MOSI output to be P3.3 SYNC valid on the falling edge of SCK. When data are being transmitted to the DAC, the SYNC line is held TXD SCLK low (PC7). Serial data from the 68HC11 are RXD DIN transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. (Data are NOTE: (1) Additional pins omitted for clarity. transmitted MSB first.) In order to load data to the DAC8564, PC7 is left low after the first eight bits are Figure101. DAC8564to80C51/80L51Interface transferred; then, a second and third serial write operation are performed to the DAC. PC7 is taken highattheendofthisprocedure. Copyright©2007–2011,TexasInstrumentsIncorporated 39

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com LAYOUT Aprecisionanalogcomponentrequirescarefullayout, The power applied to V should be well-regulated DD adequate bypassing, and clean, well-regulated power and low noise. Switching power supplies and dc/dc supplies. converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital The DAC8564 offers single-supply operation, and is components can create similar high-frequency spikes often used in close proximity with digital logic, as their internal logic switches states. This noise can microcontrollers, microprocessors, and digital signal easily couple into the DAC output voltage through processors. The more digital logic present in the various paths between the power connections and design and the higher the switching speed, the more analogoutput. difficult it is to keep digital noise from appearing at theoutput. As with the GND connection, V should be DD connected to a power-supply plane or trace that is As a result of the single ground pin of the DAC8564, separate from the connection for digital logic until all return currents (including digital and analog return they are connected at the power-entry point. In currents for the DAC) must flow through a single addition, a 1μF to 10μF capacitor and 0.1μF bypass point. Ideally, GND would be connected directly to an capacitor are strongly recommended. In some analog ground plane. This plane would be separate situations, additional bypassing may be required, from the ground connection for the digital such as a 100μF electrolytic capacitor or even a Pi components until they were connected at the filter made up of inductors and capacitors—all power-entrypointofthesystem. designed to essentially low-pass filter the supply and removethehigh-frequencynoise. 40 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 PARAMETER DEFINITIONS With the increased complexity of many different specifications listed in product data sheets, this Full-ScaleError section summarizes selected specifications related to Full-scale error is defined as the deviation of the real digital-to-analogconverters. full-scale output voltage from the ideal output voltage while the DAC register is loaded with the full-scale STATIC PERFORMANCE code (0xFFFF). Ideally, the output should be V – 1 DD LSB. The full-scale error is expressed in percent of Static performance parameters are specifications full-scalerange(%FSR). such as differential nonlinearity (DNL) or integral nonlinearity (INL). These are dc specifications and OffsetError provideinformationontheaccuracyoftheDAC.They are most important in applications where the signal The offset error is defined as the difference between changesslowlyandaccuracyisrequired. actual output voltage and the ideal output voltage in the linear region of the transfer function. This Resolution difference is calculated by using a straight line defined by two codes (code 485 and 64714). Since Generally, the DAC resolution can be expressed in the offset error is defined by a straight line, it can different forms. Specifications such as IEC 60748-4 have a negative or positive value. Offset error is recognize the numerical, analog, and relative measuredinmV. resolution. The numerical resolution is defined as the number of digits in the chosen numbering system Zero-CodeError necessary to express the total number of steps of the transfer characteristic, where a step represents both The zero-code error is defined as the DAC output a digital input code and the corresponding discrete voltage, when all '0's are loaded into the DAC analogue output value. The most commonly-used register. Zero-scale error is a measure of the definition of resolution provided in data sheets is the difference between actual output voltage and ideal numericalresolutionexpressedinbits. output voltage (0V). It is expressed in mV. It is primarilycausedbyoffsetsintheoutputamplifier. LeastSignificantBit(LSB) GainError The least significant bit (LSB) is defined as the smallestvalueinabinarycodedsystem.Thevalueof Gain error is defined as the deviation in the slope of the LSB can be calculated by dividing the full-scale the real DAC transfer characteristic from the ideal output voltage by 2n, where n is the resolution of the transfer function. Gain error is expressed as a converter. percentageoffull-scalerange(%FSR). MostSignificantBit(MSB) Full-ScaleErrorDrift The most significant bit (MSB) is defined as the Full-scale error drift is defined as the change in largest value in a binary coded system. The value of full-scale error with a change in temperature. the MSB can be calculated by dividing the full-scale Full-scale error drift is expressed in units outputvoltageby2.Itsvalueisone-halfoffull-scale. of%FSR/°C. RelativeAccuracyorIntegralNonlinearity(INL) OffsetErrorDrift Relative accuracy or integral nonlinearity (INL) is Offset error drift is defined as the change in offset defined as the maximum deviation between the real error with a change in temperature. Offset error drift transfer function and a straight line passing through isexpressedinμV/°C. the endpoints of the ideal DAC transfer function. DNL ismeasuredinLSBs. Zero-CodeErrorDrift DifferentialNonlinearity(DNL) Zero-code error drift is defined as the change in zero-code error with a change in temperature. Differential nonlinearity (DNL) is defined as the Zero-codeerrordriftisexpressedinμV/°C. maximum deviation of the real LSB step from the ideal 1LSB step. Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one LSB apart. If the DNL is less than 1LSB, theDACissaidtobemonotonic. Copyright©2007–2011,TexasInstrumentsIncorporated 41

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com GainTemperatureCoefficient DigitalFeedthrough The gain temperature coefficient is defined as the Digital feedthrough is defined as impulse seen at the change in gain error with changes in temperature. output of the DAC from the digital inputs of the DAC. The gain temperature coefficient is expressed in ppm ItismeasuredwhentheDACoutputisnotupdated.It ofFSR/°C. is specified in nV-s, and measured with a full-scale code change on the data bus; that is, from all '0's to Power-SupplyRejectionRatio(PSRR) all'1'sandviceversa. Power-supply rejection ratio (PSRR) is defined as the Channel-to-ChannelDCCrosstalk ratio of change in output voltage to a change in supply voltage for a full-scale output of the DAC. The Channel-to-channel dc crosstalk is defined as the dc PSRR of a device indicates how the output of the change in the output level of one DAC channel in DAC is affected by changes in the supply voltage. response to a change in the output of another DAC PSRRismeasuredindecibels(dB). channel. It is measured with a full-scale output change on one DAC channel while monitoring Monotonicity another DAC channel remains at midscale. It is expressedinLSB. Monotonicity is defined as a slope whose sign does not change. If a DAC is monotonic, the output Channel-to-ChannelACCrosstalk changes in the same direction or remains at least constant for each step increase (or decrease) in the AC crosstalk in a multi-channel DAC is defined as the inputcode. amount of ac interference experienced on the output of a channel at a frequency (f) (and its harmonics), DYNAMIC PERFORMANCE when the output of an adjacent channel changes its value at the rate of frequency (f). It is measured with Dynamic performance parameters are specifications one channel output oscillating with a sine wave of suchassettlingtimeorslewrate,whichareimportant 1kHz frequency, while monitoring the amplitude of in applications where the signal rapidly changes 1kHz harmonics on an adjacent DAC channel output and/orhighfrequencysignalsarepresent. (keptatzeroscale).ItisexpressedindB. SlewRate Signal-to-NoiseRatio(SNR) The output slew rate (SR) of an amplifier or other Signal-to-noise ratio (SNR) is defined as the ratio of electronic circuit is defined as the maximum rate of the root mean-squared (RMS) value of the output change of the output voltage for all possible input signal divided by the RMS values of the sum of all signals. other spectral components below one-half the output SR = max DVOUT(t) frequency, not including harmonics or dc. SNR is measuredindB. Dt Where ΔV (t) is the output produced by the TotalHarmonicDistortion(THD) OUT amplifierasafunctionoftimet. Total harmonic distortion + noise is defined as the ratio of the RMS values of the harmonics and noise OutputVoltageSettlingTime to the value of the fundamental frequency. It is Settling time is the total time (including slew time) for expressed in a percentage of the fundamental the DAC output to settle within an error band around frequencyamplitudeatsamplingratefS. its final value after a change in input. Settling times are specified to within ±0.003% (or whatever value is Spurious-FreeDynamicRange(SFDR) specified)offull-scalerange(FSR). Spurious-free dynamic range (SFDR) is the usable dynamic range of a DAC before spurious noise CodeChange/Digital-to-AnalogGlitchEnergy interferes or distorts the fundamental signal. SFDR is Digital-to-analog glitch impulse is the impulse injected the measure of the difference in amplitude between into the analog output when the input code in the the fundamental and the largest harmonically or DAC register changes state. It is normally specified non-harmonically related spur from dc to the full as the area of the glitch in nanovolts-second (nV-s), Nyquist bandwidth (half the DAC sampling rate, or and is measured when the digital input code is fS/2). A spur is any frequency bin on a spectrum changedby1LSBatthemajorcarrytransition. analyzer, or from a Fourier transform, of the analog output of the DAC. SFDR is specified in decibels relativetothecarrier(dBc). 42 Copyright©2007–2011,TexasInstrumentsIncorporated

DAC8564 www.ti.com SBAS403D–JUNE2007–REVISEDMAY2011 Signal-to-NoiseplusDistortion(SINAD) DACOutputNoise SINAD includes all the harmonic and outstanding DAC output noise is defined as any voltage deviation spurious components in the definition of output noise of DAC output from the desired value (within a power in addition to quantizing any internal random particular frequency band). It is measured with a DAC noise power. SINAD is expressed in dB at a specified channel kept at midscale while filtering the output inputfrequencyandsamplingrate,f . voltage within a band of 0.1Hz to 10Hz and S measuring its amplitude peaks. It is expressed in DACOutputNoiseDensity termsofpeak-to-peakvoltage(V ). pp Output noise density is defined as Full-ScaleRange(FSR) internally-generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is Full-scale range (FSR) is the difference between the measured by loading the DAC to midscale and maximum and minimum analog output values that the measuringnoiseattheoutput. DAC is specified to provide; typically, the maximum and minimum values are also specified. For an n-bit DAC, these values are usually given as the values matchingwithcode0and2n. Copyright©2007–2011,TexasInstrumentsIncorporated 43

DAC8564 SBAS403D–JUNE2007–REVISEDMAY2011 www.ti.com REVISION HISTORY NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(September2010)toRevisionD Page • ChangedOutputVoltageparametermin/maxvaluesfrom2.4995and2.5005to2.4975and2.5025,respectively ........... 4 • ChangedInitialAccuracyparametermin/maxvaluesfrom–0.02and0.02to–0.1and0.1,respectively........................... 4 ChangesfromRevisionB(March2008)toRevisionC Page • Changedt minimumvaluesintheTimingRequirementstable ........................................................................................... 7 2 • AddedDACSPIInterfacingsubsectiontoMicroprocessorInterfacingsection .................................................................. 39 44 Copyright©2007–2011,TexasInstrumentsIncorporated

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) DAC8564IAPW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 DAC & no Sb/Br) 8564 DAC8564IAPWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 DAC & no Sb/Br) 8564 DAC8564IBPW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 DAC & no Sb/Br) 8564 B DAC8564ICPW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 DAC & no Sb/Br) 8564 DAC8564ICPWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 DAC & no Sb/Br) 8564 DAC8564IDPW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 DAC & no Sb/Br) 8564 D DAC8564IDPWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 DAC & no Sb/Br) 8564 D (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) DAC8564IAPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 DAC8564ICPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 DAC8564IDPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) DAC8564IAPWR TSSOP PW 16 2000 350.0 350.0 43.0 DAC8564ICPWR TSSOP PW 16 2000 350.0 350.0 43.0 DAC8564IDPWR TSSOP PW 16 2000 350.0 350.0 43.0 PackMaterials-Page2

PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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