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DAC8551IDGKT产品简介:
ICGOO电子元器件商城为您提供DAC8551IDGKT由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 DAC8551IDGKT价格参考。Texas InstrumentsDAC8551IDGKT封装/规格:数据采集 - 数模转换器, 16 位 数模转换器 1 8-VSSOP。您可以下载DAC8551IDGKT参考资料、Datasheet数据手册功能说明书,资料中有DAC8551IDGKT 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | 集成电路 (IC)半导体 |
描述 | IC DAC 16BIT SNGL W/SPI 8VSSOP数模转换器- DAC 16-Bit UltrLo Glitch Vltg Output |
产品分类 | |
品牌 | Texas Instruments |
产品手册 | http://www.ti.com/litv/slas429b |
产品图片 | |
rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | 数据转换器IC,数模转换器- DAC,Texas Instruments DAC8551IDGKT- |
数据手册 | |
产品型号 | DAC8551IDGKT |
PCN封装 | |
产品培训模块 | http://www.digikey.cn/PTM/IndividualPTM.page?site=cn&lang=zhs&ptm=13240 |
产品目录页面 | |
产品种类 | 数模转换器- DAC |
位数 | 16 |
供应商器件封装 | 8-VSSOP |
其它名称 | 296-18290-6 |
分辨率 | 16 bit |
制造商产品页 | http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&orderablePartNumber=DAC8551IDGKT |
包装 | Digi-Reel® |
单位重量 | 19 mg |
商标 | Texas Instruments |
安装类型 | 表面贴装 |
安装风格 | SMD/SMT |
封装 | Reel |
封装/外壳 | 8-TSSOP,8-MSOP(0.118",3.00mm 宽) |
封装/箱体 | VSSOP-8 |
工作温度 | -40°C ~ 105°C |
工厂包装数量 | 250 |
建立时间 | 8µs |
接口类型 | QSPI, SPI, Serial (3-Wire, Microwire) |
数据接口 | SPI |
最大工作温度 | + 105 C |
最小工作温度 | - 40 C |
标准包装 | 1 |
电压参考 | External |
电压源 | 单电源 |
电源电压-最大 | 5.5 V |
电源电压-最小 | 2.7 V |
积分非线性 | +/- 8 LSB |
稳定时间 | 12 us |
系列 | DAC8551 |
结构 | Resistor-String |
转换器数 | 1 |
转换器数量 | 1 |
输出数和类型 | 1 电压,单极1 电压,双极 |
输出类型 | Voltage |
配用 | /product-detail/zh/DAC8551EVM/296-20838-ND/1216443 |
采样比 | 200 kSPs |
采样率(每秒) | 200k |
Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design DAC8551 SLAS429E–APRIL2005–REVISEDJUNE2017 DAC8551 16-Bit, Ultralow-Glitch, Voltage-Output Digital‑‑to‑‑Analog Converter 1 Features 3 Description • RelativeAccuracy:8LSB The DAC8551 is a small, low-power, voltage output, 1 16-bit digital-to-analog converter (DAC). It is • GlitchEnergy:0.1nV-s monotonic, provides good linearity, and minimizes • MicroPowerOperation:140μAat2.7V undesired code-to-code transient voltages. The • Power-OnResettoZero DAC8551 uses a versatile 3-wire serial interface that operates at clock rates to 30 MHz and is compatible • PowerSupply:2.7Vto5.5V with standard SPI™, QSPI™, Microwire™, and digital • 16-BitMonotonic signalprocessor(DSP)interfaces. • SettlingTime:10μsto±0.003%FSR The DAC8551 requires an external reference voltage • Low-PowerSerialInterfacewith to set its output range. The DAC8551 incorporates a Schmitt-TriggeredInputs power-on-reset circuit that ensures the DAC output • On-ChipOutputBufferAmplifierwith powers up at 0 V and remains there until a valid write Rail-to-RailOperation takes place to the device. The DAC8551 contains a power-down feature, accessed over the serial • Power-DownCapability interface, that reduces the current consumption of the • BinaryInput deviceto200nAat5V. • SYNCInterruptFacility The low-power consumption of this device in normal • Drop-InCompatibleWithDAC85x1 operation makes it ideally suited for portable, battery- andDAC8550(2'sComplementInput) operated equipment. The power consumption is 0.38 mW at 2.7 V, reducing to less than 1 μW in 2 Applications power‑downmode. • ProcessControl For additional flexibilty, see the DAC8550 (SLAS476), a2'scomplement-inputcounterparttotheDAC8551. • DataAcquisitionSystems • Closed-LoopServo-Control DeviceInformation(1) • PCPeripherals PARTNUMBER PACKAGE BODYSIZE(NOM) • PortableInstrumentation DAC8551 VSSOP(8) 3.00mm×3.00mm • ProgrammableAttenuation (1) For all available packages, see the orderable addendum at theendofthedatasheet. FunctionalBlockDiagram VDD VFB VREF Ref (+) VOUT 16-Bit DAC 16 DAC Register 16 SYNC SCLK Shift Register PWD Control RNeestwisotorkr DIN GND Copyright © 2016,Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
DAC8551 SLAS429E–APRIL2005–REVISEDJUNE2017 www.ti.com Table of Contents 1 Features.................................................................. 1 7.5 Programming...........................................................18 2 Applications........................................................... 1 8 ApplicationandImplementation........................ 20 3 Description............................................................. 1 8.1 ApplicationInformation............................................20 4 RevisionHistory..................................................... 2 8.2 TypicalApplication..................................................21 8.3 SystemExamples...................................................23 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 24 6 Specifications......................................................... 4 10 Layout................................................................... 24 6.1 AbsoluteMaximumRatings......................................4 6.2 ESDRatings..............................................................4 10.1 LayoutGuidelines.................................................24 6.3 RecommendedOperatingConditions.......................4 10.2 LayoutExample....................................................24 6.4 ThermalInformation..................................................4 11 DeviceandDocumentationSupport................. 25 6.5 ElectricalCharacteristics...........................................5 11.1 DocumentationSupport........................................25 6.6 TimingCharacteristics...............................................7 11.2 ReceivingNotificationofDocumentationUpdates25 6.7 TypicalCharacteristics..............................................8 11.3 CommunityResources..........................................25 7 DetailedDescription............................................ 16 11.4 Trademarks...........................................................25 7.1 Overview.................................................................16 11.5 ElectrostaticDischargeCaution............................25 7.2 FunctionalBlockDiagram.......................................16 11.6 Glossary................................................................25 7.3 FeatureDescription.................................................16 12 Mechanical,Packaging,andOrderable Information........................................................... 25 7.4 DeviceFunctionalModes........................................18 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionD(February2017)toRevisionE Page • ChangedtheV TestConditionsFrom:V =5VTo:3V≤V ≤5.5VandFrom:V =3VTo:2.7V≤V <3V IL DD DD DD DD intheElectricalCharacteristics.............................................................................................................................................. 6 • ChangedtheV TestConditionsFrom:V =5VTo:3V≤V ≤5.5VandFrom:V =3VTo:2.7V≤V <3V IH DD DD DD DD intheElectricalCharacteristics.............................................................................................................................................. 6 ChangesfromRevisionC(March2016)toRevisionD Page • RelativeaccuracyDAC8551,DeletedtheTYPvalueof±3,ChangedtheMAXvalueFrom:±8To:±12inthe ElectricalCharacteristics ....................................................................................................................................................... 5 • RelativeaccuracyDAC8551A,DeletedtheTYPvalueof±3,ChangedtheMAXvalueFrom:±8To:±16inthe ElectricalCharacteristics ....................................................................................................................................................... 5 • ChangedDifferentialnonlinearityTestConditionsFrom:16-bitmonotonicTo:threeseparateentriesintheElectrical Characteristics ....................................................................................................................................................................... 5 • ChangedInputLOWvoltage5VMAXvalueFrom:0.8To:0.3XV intheElectricalCharacteristics .............................. 6 DD • ChangedInputLOWvoltage3VMAXvalueFrom:0.6To:0.1XV intheElectricalCharacteristics .............................. 6 DD • ChangedInputHIGHvoltage5VMINvalueFrom:2.4To:0.7XV intheElectricalCharacteristics ................................ 6 DD • ChangedInputHIGHvoltage3VMINvalueFrom:2.1To:0.9XV intheElectricalCharacteristics ................................ 6 DD ChangesfromRevisionB(October2006)toRevisionC Page • RemovedPackaging/OrderingInformationtable.................................................................................................................... 1 • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 2 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:DAC8551
DAC8551 www.ti.com SLAS429E–APRIL2005–REVISEDJUNE2017 5 Pin Configuration and Functions DGKPackage 8-PinVSSOP TopView VDD 1 8 GND VREF 2 7 DIN DAC8551 VFB 3 6 SCLK VOUT 4 5 SYNC PinFunctions PIN TYPE DESCRIPTION NAME NO. Serialdatainput.Dataisclockedintothe24-bitinputshiftregisteroneachfallingedgeoftheserialclock D 7 I IN input.Schmitt-Triggerlogicinput. GND 8 GND Groundreferencepointforallcircuitryonthepart SCLK 6 I Serialclockinput.Datacanbetransferredatratesupto30-MHzSchmitt-Triggerlogicinput. Level-triggeredcontrolinput(activeLOW).Thisistheframesynchronizationsignalfortheinputdata. WhenSYNCgoesLOW,itenablestheinputshiftregisteranddataistransferredinonthefallingedges SYNC 5 I ofthefollowingclocks.TheDACisupdatedfollowingthe24thclock(unlessSYNCistakenHIGHbefore thisedge,inwhichcasetherisingedgeofSYNCactsasaninterruptandthewritesequenceisignored bytheDAC8551).Schmitt-Triggerlogicinput. V 1 PWR Powersupplyinput,2.7Vto5.5V DD V 3 I Feedbackconnectionfortheoutputamplifier.Forvoltageoutputoperation,tietoV externally. FB OUT V 4 O AnalogoutputvoltagefromDAC.Theoutputamplifierhasrail-to-railoperation. OUT V 2 I Referencevoltageinput REF Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DAC8551
DAC8551 SLAS429E–APRIL2005–REVISEDJUNE2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings(1) MIN MAX UNIT Inputvoltage GND –0.3 6 V Digitalinputvoltage GND –0.3 V +0.3 V DD Outputvoltage GND –0.3 V +0.3 V DD Operatingtemperature –40 105°C °C Junctiontemperature,T 150°C °C J Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Supplyvoltage(V toGND) 2.7 5.5 V DD Digitalinputvoltage(D ,SCLK,andSYNC) 0 V V IN DD V Referenceinputvoltage 0 V V REF DD V Outputamplifierfeedbackinput V V FB OUT T Operatingambienttemperature –40 105 °C A 6.4 Thermal Information DAC8551 THERMALMETRIC(1) DGK(VSSOP) UNIT 8PINS R Junction-to-ambientthermalresistance 206 °C/W θJA R Junction-to-case(top)thermalresistance 44 °C/W θJC(top) R Junction-to-boardthermalresistance 94.2 °C/W θJB ψ Junction-to-topcharacterizationparameter 10.2 °C/W JT ψ Junction-to-boardcharacterizationparameter 92.7 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 4 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:DAC8551
DAC8551 www.ti.com SLAS429E–APRIL2005–REVISEDJUNE2017 6.5 Electrical Characteristics V =2.7Vto5.5Vand–40°Cto105°C(unlessotherwisenoted) DD PARAMETER TESTCONDITIONS MIN TYP MAX UNIT STATICPERFORMANCE(1) Resolution 16 Bits Measuredbylinepassingthrough DAC8551 ±12 LSB Relativeaccuracy codes485and64741atVREF=5 V,codes970and63947at DAC8551A ±16 LSB VREF=2.5V 2.5V≤VREF≤5.5V,0°C≤TA≤105°C ±1 LSB Differentialnonlinearity 4.2V<VREF≤5.5V,-40°C≤TA≤105°C ±1 LSB 2.5V≤VREF≤4.2V,-40°C≤TA≤0°C ±2 LSB Zero-codeerror ±2 ±12 mV Measuredbylinepassingthroughcodes485and64741 Full-scaleerror ±0.05% ±0.5% FSR Measuredbylinepassingthrough DAC8551 ±0.02% ±0.15% FSR Gainerror codes485and64741 DAC8551A ±0.02% ±0.2% FSR Zero-codeerrordrift ±5 μV/°C ppmof Gaintemperaturecoefficient ±1 FSR/°C PSRR Power-supplyrejectionratio RL=2kΩ,CL=200pF 0.75 mV/V OUTPUTCHARACTERISTICS(2) Outputvoltagerange 0 VREF V To±0.003%FSR,0200htoFD00h,RL=2kΩ, 8 10 μs Outputvoltagesettlingtime 0pF<CL<200pF RL=2kΩ,CL=50pF 12 μs Slewrate 1.8 V/μs RL=∞ 470 pF Capacitiveloadstability RL=2kΩ 1000 pF Codechangeglitchimpulse 1LSBchangearoundmajorcarry 0.1 nV-s Digitalfeedthrough 50kΩseriesresistanceondigitallines 0.1 DCoutputimpedance Atmid-codeinput 1 Ω VDD=5V 50 Short-circuitcurrent mA VDD=3V 20 Comingoutofpower-downmode,VDD=5V 2.5 Power-uptime μs Comingoutofpower-downmode,VDD=3V 5 ACPERFORMANCE SNR Signal-to-noiseratio BW=20kHz,VDD=5V,fOUT=1kHz, 95 dB 1st19harmonicsremovedforSNRcalculation THD Totalharmonicdistortion BW=20kHz,VDD=5V,fOUT=1kHz, –85 dB 1st19harmonicsremovedforSNRcalculation SFDR Spurious-freedynamicrange BW=20kHz,VDD=5V,fOUT=1kHz, 87 dB 1st19harmonicsremovedforSNRcalculation SINAD Signaltonoiseanddistortion BW=20kHz,VDD=5V,fOUT=1kHz, 84 dB 1st19harmonicsremovedforSNRcalculation REFERENCEINPUT VREF=VDD=5V 40 75 μA Referencecurrent VREF=VDD=3.6V 30 45 μA Referenceinputrange 0 VDD V Referenceinputimpedance 125 kΩ (1) Linearitycalculatedusingareducedcodesrangeof485and64741atV =5V,codes970and63947atV =2.5V;output REF REF unloaded,100mVheadroombetweenreferenceandsupply (2) Specifiedbydesignandcharacterization;notproductiontested. Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DAC8551
DAC8551 SLAS429E–APRIL2005–REVISEDJUNE2017 www.ti.com Electrical Characteristics (continued) V =2.7Vto5.5Vand–40°Cto105°C(unlessotherwisenoted) DD PARAMETER TESTCONDITIONS MIN TYP MAX UNIT LOGICINPUTS(2) Inputcurrent ±1 μA 3V≤VDD≤5.5V 0.3XVDD VIL InputLOWvoltage V 2.7V≤VDD<3V 0.1XVDD 3V≤VDD≤5.5V 0.7XVDD VIH InputHIGHvoltage V 2.7V≤VDD<3V 0.9XVDD Pincapacitance 3 pF POWERREQUIREMENTS VDD Supplyvoltage 2.7 5.5 V VDD=3.6Vto5.5V, VIH=VDDand 160 250 Normalmode,inputcode=32768, VIL=GND noload,doesnotinclude μA referencecurrent VDD=2.7Vto3.6V, IDD Supplycurrent VIH=VDDand 140 240 VIL=GND Allpower-downmodes, VDD=3.6Vto5.5V 0.2 2 μA VIH=VDDandVIL=GND VDD=2.7Vto3.6V 0.05 2 IOUT/IDD Powerefficiency ILOAD=2mA,VDD=5V 89% Specifiedperformance –40 105 °C temperature 6 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:DAC8551
DAC8551 www.ti.com SLAS429E–APRIL2005–REVISEDJUNE2017 6.6 Timing Characteristics V =2.7Vto5.5V,allspecifications–40°Cto105°C(unlessotherwisenoted)(1)(2) DD PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V =2.7Vto3.6V 50 t (3) SCLKcycletime DD ns 1 V =3.6Vto5.5V 33 DD V =2.7Vto3.6V 13 DD t SCLKHIGHtime ns 2 V =3.6Vto5.5V 13 DD V =2.7Vto3.6V 22.5 DD t SCLKLOWtime ns 3 V =3.6Vto5.5V 13 DD V =2.7Vto3.6V 0 DD t SYNCtoSCLKrisingedgesetuptime ns 4 V =3.6Vto5.5V 0 DD V =2.7Vto3.6V 5 DD t Datasetuptime ns 5 V =3.6Vto5.5V 5 DD V =2.7Vto3.6V 4.5 DD t Dataholdtime ns 6 V =3.6Vto5.5V 4.5 DD V =2.7Vto3.6V 0 DD t 24thSCLKfallingedgetoSYNCrisingedge ns 7 V =3.6Vto5.5V 0 DD V =2.7Vto3.6V 50 DD t MinimumSYNCHIGHtime ns 8 V =3.6Vto5.5V 33 DD t 24thSCLKfallingedgetoSYNCfallingedge V =2.7Vto5.5V 100 ns 9 DD (1) Allinputsignalsarespecifiedwitht =t =5ns(10%to90%ofV )andtimedfromavoltagelevelof(V +V )/2. R F DD IL IH (2) SeeFigure1. (3) MaximumSCLKfrequencyis30MHzatV =3.6Vto5.5Vand20MHzatV =2.7Vto3.6V. DD DD t t 1 9 SCLK 1 24 t8 t t3 t2 t7 4 SYNC t 6 t 5 D DB23 DB0 DB23 IN Figure1. SerialWriteOperation Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DAC8551
DAC8551 SLAS429E–APRIL2005–REVISEDJUNE2017 www.ti.com 6.7 Typical Characteristics 6.7.1 V =5V DD AtT =25°C(unlessotherwisenoted) A 6 6 4 VDD= 5V, VREF= 4.99V 4 VDD= 5V, VREF= 4.99V B) 2 B) 2 S S L 0 L 0 E ( -2 E ( -2 L L -4 -4 -6 -6 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0 E (L 0 DL-0.5 DL-0.5 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Digital Input Code Figure2.LinearityErrorandDifferentialLinearityErrorvs Figure3.LinearityErrorandDifferentialLinearityErrorvs DigitalInputCode(–40°C) DigitalInputCode 6 10 4 VDD= 5V, VREF= 4.99V VDD= 5V B) 2 VREF= 4.99V S L 0 E ( -2 L 5 -4 V) -6 m 1.0 Error ( B) 0.5 0 S E (L 0 DL-0.5 -1.0 -5 0 8192 16384 24576 32768 40960 49152 57344 65536 -40 0 40 80 120 Digital Input Code Temperature (°C) Figure4.LinearityErrorandDifferentialLinearityErrorvs Figure5.Zero-ScaleErrorvsTemperature DigitalInputCode(105°C) 0 6 V = 5V DD V = 4.99V REF 5 DAC Loaded with FFFFh 4 V) V) m m Error ( -5 V(OUT 3 VVDD== 5 V.5V-10mV 2 REF DD 1 DAC Loaded with 0000h -10 0 -40 0 40 80 120 0 2 4 6 8 10 Temperature (°C) I (mA) (SOURCE/SINK) Figure6.Full-ScaleErrorvsTemperature Figure7.SourceandSinkCurrentCapability 8 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:DAC8551
DAC8551 www.ti.com SLAS429E–APRIL2005–REVISEDJUNE2017 V = 5 V (continued) DD AtT =25°C(unlessotherwisenoted) A 300 250 V = V = 5V V = V = 5V REF DD DD REF 250 200 200 150 A) Reference Current Included A) m( 150 (m IDD IDD100 100 50 50 0 0 0 8192 16384 24576 32768 40960 49152 57344 65536 -40 -10 20 50 80 110 Digital Input Code Temperature (°C) Figure8.SupplyCurrentvsDigitalInputCode Figure9.Power-SupplyCurrentvsTemperature 300 1.0 280 VREF= VDD VREF= VDD Reference Current Included, No Load 260 A) 0.8 m 240 nt ( e (A)m 222000 n Curr 0.6 D w ID 180 Do 0.4 160 er- w o 140 P 0.2 120 100 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.7 3.1 3.5 4.3 4.7 5.1 5.5 V (V) V (V) DD DD Figure10.SupplyCurrentvsSupplyVoltage Figure11.Power-DownCurrentvsSupplyVoltage 1800 1600 VTA= =2 5V°C, S=C 5L.5 IVnput (all other inputs = GND) Trigger Pulse 5V/div DD REF 1400 1200 A) 1000 m ( IDD 800 VDD= 5V V = 4.096V 600 REF From Code: D000 400 To Code: FFFF Rising Edge 200 1V/div Zoomed Rising Edge 1mV/div 0 0 1 2 3 4 5 Time (2ms/div) V (V) LOGIC Figure13.Full-ScaleSettlingTime,5-VRisingEdge Figure12.SupplyCurrentvsLogicInputVoltage Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DAC8551
DAC8551 SLAS429E–APRIL2005–REVISEDJUNE2017 www.ti.com V = 5 V (continued) DD AtT =25°C(unlessotherwisenoted) A Trigger Pulse 5V/div Trigger Pulse 5V/div V = 5V DD V = 4.096V REF From Code: FFFF V = 5V To Code: 0000 DD V = 4.096V REF Rising From Code: 4000 Edge To Code: CFFF Falling 1V/div Edge Zoomed Falling Edge Zoomed Rising Edge 1V/div 1mV/div 1mV/div Time (2ms/div) Time (2ms/div) Figure14.Full-ScaleSettlingTime,5-VFallingEdge Figure15.Half-ScaleSettlingTime,5-VRisingEdge Trigger Pulse 5V/div V = 5V DD V = 4.096V FrRoEmF Code: CFFF div) To Code: 4000 V/ m 0 0 5 ( T VOU VDD= 5V V = 4.096V REF Falling From Code: 7FFF Edge To Code: 8000 Zoomed Falling Edge 1V/div Glitch: 0.08nV-s 1mV/div Time (2ms/div) Time (400ns/div) Figure16.Half-ScaleSettlingTime,5-VFallingEdge Figure17.GlitchEnergy:5-V,1-LSBStep,RisingEdge v) v) di di V/ V/ m m 0 0 0 0 5 5 ( ( VOUT VVFrDRoDEmF= = C5 4oV.d0e9:6 8V000 VOUT VVDRDEF== 5 4V.096V To Code: 7FFF From Code: 8000 Glitch: 0.16nV-s To Code: 8010 Measured Worst Case Glitch: 0.04nV-s Time (400ns/div) Time (400ns/div) Figure18.GlitchEnergy:5-V,1-LSBStep,FallingEdge Figure19.GlitchEnergy:5-V,16-LSBStep,RisingEdge 10 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:DAC8551
DAC8551 www.ti.com SLAS429E–APRIL2005–REVISEDJUNE2017 V = 5 V (continued) DD AtT =25°C(unlessotherwisenoted) A V = 5V DD V = 4.096V REF V/div)m FTGorloi tCmcho :Cd 0eo.:d0 8e80:n 08V00-s10 V/div) 0 m 0 5 5 ( ( T V = 5V T U DD VOU VO VFrRoEmF =C 4o.d0e9:6 8V000 To Code: 80FF Glitch: Not Detected Theoretical Worst Case Time (400ns/div) Time (400ns/div) Figure20.GlitchEnergy:5-V,16-LSBStep,FallingEdge Figure21.GlitchEnergy:5-V,256-LSBStep,RisingEdge -40 V = 5V V = 5V DD DD V = 4.9V V = 4.096V -50 REF REF -1dB FSR Digital Input From Code: 80FF f = 1MSPS mV/div) TGTohli etCcohor:de Netic:o a8t l0D W0e0otersctt eCdase (dB) --6700 MSeasurement Bandwidth = 20kHz (5 HD THD OUT T -80 V -90 2nd Harmonic 3rd Harmonic -100 0 1 2 3 4 5 Time (400ns/div) f (kHz) OUT Figure22.GlitchEnergy:5-V,256-LSBStep,FallingEdge Figure23.TotalHarmonicDistortionvsOutputFrequency 98 VREF= VDD= 5V -10 VDD= 5V 96 -1dB FSR Digital Input VREF= 4.096V fS= 1MSPS -30 fOUT= 1kHz 94 Measurement Bandwidth = 20kHz f = 1MSPS CLK -50 dB) 92 dB) SNR ( 90 Gain ( -70 -90 88 86 -110 84 -130 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.5 0 5 10 15 20 f (kHz) Frequency (kHz) OUT Figure24.Signal-to-NoiseRatiovsOutputFrequency Figure25.PowerSpectralDensity Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DAC8551
DAC8551 SLAS429E–APRIL2005–REVISEDJUNE2017 www.ti.com V = 5 V (continued) DD AtT =25°C(unlessotherwisenoted) A 350 V = 5V DD V = 4.99V REF 300 Code = 7FFFh )z No Load H Ö V/ 250 n e ( s Noi 200 e g a Volt 150 100 100 1k 10k 100k Frequency (Hz) Figure26.OutputNoiseDensity 6.7.2 V =2.7V DD AtT =25°C(unlessotherwisenoted) A 6 6 4 VDD= 2.7V, VREF= 2.69V 4 VDD= 2.7V, VREF= 2.69V B) 2 B) 2 S S L 0 L 0 E ( -2 E ( -2 L L -4 -4 -6 -6 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0 E (L 0 DL-0.5 DL-0.5 -1.0 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Digital Input Code Figure27.LinearityErrorandDifferentialLinearityError Figure28.LinearityErroranddifferentialLinearityErrorvs vsDigitalInputCode(–40°C) DigitalInputCode 6 10 4 VDD= 2.7V, VREF= 2.69V VDD= 2.7V B) 2 VREF= 2.69V S L 0 E ( -2 L 5 --46 mV) 1.0 Error ( B) 0.5 0 S E (L 0 DL-0.5 -1.0 -5 0 8192 16384 24576 32768 40960 49152 57344 65536 -40 0 40 80 120 Digital Input Code Temperature (°C) Figure29.LinearityErrorandDifferentialLinearityError Figure30.Zero-ScaleErrorvsTemperature vsDigitalInputCode(105°C) 12 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:DAC8551
DAC8551 www.ti.com SLAS429E–APRIL2005–REVISEDJUNE2017 V = 2.7 V (continued) DD AtT =25°C(unlessotherwisenoted) A 5 3.0 V = 2.7V DD V = 2.69V REF 2.5 DAC Loaded with FFFFh 0 2.0 V) V) m m Error ( V(OUT 1.5 VVDD== 2 V.7V-10mV -5 1.0 REF DD 0.5 DAC Loaded with 0000h -10 0 -40 0 40 80 120 0 2 4 6 8 10 Temperature (°C) I(SOURCE/SINK)(mA) Figure31.Full-ScaleErrorvsTemperature Figure32.SourceandSinkCurrentCapability 180 250 160 VDD= VREF= 2.7V VREF= VDD= 2.7V 140 200 Reference Current Included 120 150 A) 100 A) m m ( ( D 80 D ID ID100 60 40 50 20 0 0 0 8192 16384 24576 32768 40960 49152 57344 65536 -40 -10 20 50 80 110 Digital Input Code Temperature (°C) Figure33.SupplyCurrentvsDigitalInputCode Figure34.Power-SupplyCurrentvsTemperature 800 TA= 25°C, SCL Input (all other inputs = GND) Trigger Pulse 2.7V/div 700 V = V = 2.7V DD REF 600 Rising 500 Edge A) 0.5V/div (m 400 IDD 300 VVDD== 2 2.7.5VV REF From Code: 0000 200 To Code: FFFF 100 Zoomed Rising Edge 0 1mV/div 0 0.5 1.0 1.5 2.0 2.5 2.7 Time (2ms/div) V (V) LOGIC Figure35.SupplyCurrentvsLogicInputVoltage Figure36.Full-ScaleSettlingTime:2.7-VRisingEdge Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DAC8551
DAC8551 SLAS429E–APRIL2005–REVISEDJUNE2017 www.ti.com V = 2.7 V (continued) DD AtT =25°C(unlessotherwisenoted) A Trigger Pulse 2.7V/div Trigger Pulse 2.7V/div V = 2.7V DD V = 2.5V REF From Code: FFFF To Code: 0000 V = 2.7V DD V = 2.5V REF From Code: 4000 Zoomed Falling Edge To Code: CFFF Falling 1mV/div Rising Edge Edge Zoomed Rising Edge 0.5V/div 0.5V/div 1mV/div Time (2ms/div) Time (2ms/div) Figure37.Full-ScaleSettlingTime:2.7-VFallingEdge Figure38.Half-ScaleSettlingTime:2.7-VRisingEdge Trigger Pulse 2.7V/div V = 2.7V DD VREF= 2.5V v) From Code: CFFF di V/ To Code: 4000 m 0 0 2 ( T U O V = 2.7V V DD V = 2.5V REF Falling From Code: 7FFF Edge Zoomed Falling Edge To Code: 8000 0.5V/div 1mV/div Glitch: 0.08nV-s Time (2ms/div) Time (400ns/div) Figure39.Half-ScaleSettlingTime:2.7-VFallingEdge Figure40.GlitchEnergy:2.7-V,1-LSBStep,RisingEdge v) v) di di V/ V/ m m 0 0 0 0 2 2 ( ( VOUT VVFrDRoDEmF= = C2 2o.7.d5VeV: 8000 VOUT VVDRDEF== 2 2.7.5VV To Code: 7FFF From Code: 8000 Glitch: 0.16nV-s To Code: 8010 Measured Worst Case Glitch: 0.04nV-s Time (400ns/div) Time (400ns/div) Figure41.GlitchEnergy:2.7-V,1-LSBStep,FallingEdge Figure42.GlitchEnergy:2.7-V,16-LSBStep,RisingEdge 14 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:DAC8551
DAC8551 www.ti.com SLAS429E–APRIL2005–REVISEDJUNE2017 V = 2.7 V (continued) DD AtT =25°C(unlessotherwisenoted) A V = 2.7V DD V = 2.5V REF V/div)m FTGorloi tCmcho :Cd 0eo.:d1 8e20:n 08V00-s10 V/div) 0 m 0 5 2 ( ( T V = 2.7V T U DD VOU VO VFrRoEmF =C 2o.d5eV: 8000 To Code: 80FF Glitch: Not Detected Theoretical Worst Case Time (400ns/div) Time (400ns/div) Figure43.GlitchEnergy:2.7-V,16-LSBStep,FallingEdge Figure44.GlitchEnergy:2.7-V,256-LSBStep,RisingEdge V = 2.7V DD V = 2.5V REF From Code: 80FF To Code: 8000 div) Glitch: Not Detected V/ Theoretical Worst Case m 5 ( T U O V Time (400ns/div) Figure45.GlitchEnergy:2.7-V,256-LSBStep,FallingEdge Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DAC8551
DAC8551 SLAS429E–APRIL2005–REVISEDJUNE2017 www.ti.com 7 Detailed Description 7.1 Overview The DAC8551 is a small, low-power, voltage output, single-channel, 16-bit, DAC. The device is monotonic by design, provides excellent linearity, and minimizes undesired code-to-code transient voltages. The DAC8551 uses a versatile, three-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with standardSPI,QSPI,Microwire,anddigitalsignalprocessor(DSP)interfaces. 7.2 Functional Block Diagram V DD V FB VREF Ref (+) VOUT 16-Bit DAC 16 DAC Register 16 SYNC Resistor SCLK Shift Register PWD Control Network D IN GND Copyright © 2016,Texas Instruments Incorporated 7.3 Feature Description 7.3.1 DACSection The DAC8551 architecture consists of a string DAC followed by an output buffer amplifier. Figure 46 shows a blockdiagramoftheDACarchitecture. VREF 50kW 50kW V FB 62kW REF (+) V DAC OUT Register String Register REF (-) GND Copyright © 2016,Texas Instruments Incorporated Figure46. DAC8551Architecture TheinputcodingtotheDAC8551isstraightbinary,sotheidealoutputvoltageisgivenby: D V = IN ´V O 65536 REF where • D =decimalequivalentofthebinarycodethatisloadedtotheDACregister;itcanrangefrom0to65535 (1) IN 16 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:DAC8551
DAC8551 www.ti.com SLAS429E–APRIL2005–REVISEDJUNE2017 Feature Description (continued) 7.3.1.1 ResistorString The resistor string section is shown in Figure 47. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. Monotonicity is ensured becauseofthestringresistorarchitecture. 7.3.1.2 OutputAmplifier The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 V to V . It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink DD capabilities of the output amplifier can be seen in the Typical Characteristics section V = 5 V. The slew rate is DD 1.8V/μswithafull-scalesettingtimeof8 μswiththeoutputunloaded. The inverting input of the output amplifier is brought out to the V pin. This configuration allows for better FB accuracy in critical applications by tying the V point and the amplifier output together directly at the load. Other FB signalconditioningcircuitrymayalsobeconnectedbetweenthesepointsforspecificapplications. V REF R DIVIDER V REF 2 R To Output Amplifier R (2x Gain) R R Figure47. ResistorString 7.3.2 Power-OnReset The DAC8551 contains a power-on-reset circuit that controls the output voltage during power up. On power up, the DAC registers are filled with zeros and the output voltages are 0 V; they remain that way until a valid write sequence is made to the DAC. The power-on reset is useful in applications where it is important to know the stateoftheoutputoftheDACwhileitisintheprocessofpoweringup. Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DAC8551
DAC8551 SLAS429E–APRIL2005–REVISEDJUNE2017 www.ti.com 7.4 Device Functional Modes 7.4.1 Power-DownModes The DAC8551 supports four separate modes of operation. These modes are programmable by setting two bits (PD1 and PD0) in the control register. Table 1 shows how the state of the bits corresponds to the mode of operationofthedevice. Table1.OperatingModes PD1(DB17) PD0(DB16) OPERATINGMODE 0 0 Normaloperation Power-downmodes 0 1 Outputtypically1kΩtoGND 1 0 Outputtypically100kΩtoGND 1 1 High-Z When both bits are set to '0', the device works normally with its typical current consumption of 200 μA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This configuration has the advantage that the output impedance of the device is known while it is in power-down mode. There are three different options. The output is connected internally to GNDthrougha1-kΩ resistor,a100-kΩ resistor,oritisleftopen-circuited(High-Z).Theoutputstageisillustrated inFigure48. V FB Resistor Amplifier VOUT String DAC Power-Down Resistor Circuitry Network Copyright © 2016,Texas Instruments Incorporated Figure48. OutputStageDuringPower-Down All analog circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 2.5 μs for V = 5 V, and 5 DD μsforV =3V.SeeTypicalCharacteristics formoreinformation. DD 7.5 Programming 7.5.1 SerialInterface The DAC8551 has a 3-wire serial interface (SYNC, SCLK, and D ), which is compatible with SPI, QSPI, and IN Microwireinterfacestandards,aswellasmostDSPs.SeeFigure1 foranexampleofatypicalwritesequence. The write sequence begins by bringing the SYNC line LOW. Data from the D line are clocked into the 24-bit IN shift register on each falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the DAC8551 compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed (that is, a change in DAC register contents and/or a change inthemodeofoperation). At this point, the SYNC line may be kept LOW or brought HIGH. In either case, it must be brought HIGH for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence.Aspreviouslymentioned,itmustbebroughtHIGHagainjustbeforethenextwritesequence. 18 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:DAC8551
DAC8551 www.ti.com SLAS429E–APRIL2005–REVISEDJUNE2017 Programming (continued) 7.5.2 InputShiftRegister The input shift register is 24 bits wide, as shown in Figure 49. The first six bits are unused bits. The next two bits (PD1 and PD0) are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). A more complete description of the various modes is located in Power-Down Modes. The next 16 bits are the data bits. These bits are transferred to the DAC register on the 24th falling edge of SCLK. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused PD1 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure49. DAC8551DataInputRegisterFormat 7.5.3 SYNCInterrupt In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the DAC is updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an updateoftheDACregistercontentsnorachangeintheoperatingmodeoccurs,asshowninFigure50. 24th Falling Edge 24th Falling Edge CLK SYNC DIN DB23 DB80 DB23 DB80 Valid Write Sequence: Output Updates on the 24th Falling Edge Figure50. SYNCInterruptFacility Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DAC8551
DAC8551 SLAS429E–APRIL2005–REVISEDJUNE2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The low-power consumption of the DAC8551 lends itself to applications such as loop-powered control where the currentdissipationofeachdeviceiscritical.ThelowpowerconsumptionalsoallowstheDAC8551tobepowered using only a precision reference for increased accuracy. The low-power operation coupled with the ultra-low powerpower-downmodesalsomaketheDAC8551agreatchoiceforbatteryandportableapplications. 8.1.1 BipolarOperationUsingtheDAC8551 The DAC8551 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 51. The circuit shown gives an output voltage range of ±V . Rail-to-rail operation at the REF amplifier output is achievable using an OPA703 as the operational amplifier. See CMOS, Rail-to-Rail, I/O OperationalAmplifiers(SBOS180)formoreinformation. V R REF 2 10kW R +6V 1 10kW OPA703 5V V FB V DAC8551 V REF OUT –6V 10mF 0.1mF Three-Wire Serial Interface Copyright © 2016,Texas Instruments Incorporated Figure51. BipolarOutputRange Theoutputvoltageforanyinputcodecanbecalculatedasfollows: é æ D ö æR +R ö æR öù VO = êêëVREF´çè65536÷ø´çè 1R1 2÷ø-VREF´èçR21÷øûúú where • Distheinputcodeindecimal(0–65535) (2) WithV =5V,R =R =10kΩ. REF 1 2 æ10´D ö VO =çè65536÷ø-5 V (3) Using this example, an output voltage range of ±5 V—with 0000h corresponding to a –5-V output and FFFFh corresponding to a 5-V output—can be achieved. Similarly, using V = 2.5 V, a ±2.5-V output voltage range REF canbeachieved. 20 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:DAC8551
DAC8551 www.ti.com SLAS429E–APRIL2005–REVISEDJUNE2017 8.2 Typical Application 8.2.1 Loop-Powered,2-Wire,4-mAto20-mATransmitterWithXTR116 V XTR116 V+ REG V+ Regulator C || C 2 3 0.1001µF V ref Reference C U1 1 R 2.2µF 1 V+ Vref 102.4 kΩ R V+ 2 49.9W I DAC8551 VOUT IN + B R3 U2 Q1 25.6kΩ Q1 R I LIM E RET 2475Ω 25Ω Return I O Copyright © 2016,Texas Instruments Incorporated Figure52. Loop-PoweredTransmitter 8.2.1.1 DesignRequirements This design is commonly referred to as a loop-powered, or 2-wire, 4-mA to 20-mA transmitter. The transmitter has only two external input terminals: a supply connection and an output, or return, connection. The transmitter communicates back to its host, typically a PLC analog input module, by precisely controlling the magnitude of its return current. In order to conform to the 4-mA to 20-mA communication standard, the complete transmitter must consume less than 4 mA of current. The DAC8551 enables the accurate control of the loop current from 4 mA to 20mAin16-bitsteps. 8.2.1.2 DetailedDesignProcedure Although it is possible to recreate the loop-powered circuit using discrete components, the XTR116 provides simplicity and improved performance due to the matched internal resistors. The output current can be modified if necessarybylookingusingEquation4. æ ö I (Code)=çVref ´Code + VREG ÷´æç1+ 2475Wö÷ OUT ç 2N´R R ÷ è 25W ø è 3 1 ø (4) See 2-wire, 4-mA to 20-mA Transmitter, EMC/EMI Tested Reference Design (TIDUAO7) for more information. It coversindetailthedesignofthiscircuitaswellashowtoprotectitfromEMC/EMItests. 8.2.1.3 ApplicationCurves Total unadjusted error (TUE) is a good estimate for the performance of the output as shown in Figure 53. The linearityoftheoutputorINLisinFigure54. Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:DAC8551
DAC8551 SLAS429E–APRIL2005–REVISEDJUNE2017 www.ti.com Typical Application (continued) 0.1 10 8 SR) s) 6 F 0.05 B % S 4 Error ( arity (L 2 d 0 ne 0 Unadjuste gral Nonli --42 otal -0.05 Inte -6 T -8 -0.1 -10 0 10k 20k 30k 40k 50k 60k 65535 0 10k 20k 30k 40k 50k 60k 65535 Code Code D001 D002 Figure53.TotalUnadjustedError Figure54.IntegralNonlineareity 8.2.2 UsingtheREF02asaPowerSupplyfortheDAC8551 +15V +5V REF02 285mA SYNC Three-Wire V = 0V to 5V Serial SCLK DAC8551 OUT Interface D IN Copyright © 2016,Texas Instruments Incorporated Figure55. REF02asaPowerSupplytotheDAC8551 8.2.2.1 DesignRequirements Due to the extremely low supply current required by the DAC8551, an alternative option is to use the REF02 to supply the required voltage to the device, as illustrated in Figure 55. See +5V Precision Voltage Reference (SBVS003)formoreinforation. 8.2.2.2 DetailedDesignProcedure This configuration is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V. The REF02 outputs a steady supply voltage for the DAC8551. If the REF02 is used, the current it needs to supply to the DAC8551 is 200 μA. This configuration is with no load on the output of the DAC.WhenaDACoutputisloaded,theREF02alsoneedstosupplythecurrenttotheload. Thetotaltypicalcurrentrequired(witha5-kΩ loadontheDACoutput)is: 5 V 200µA+ =1.2mA 5kW (5) The load regulation of the REF02 is typically 0.005%/mA, resulting in an error of 299 μV for the 1.2-mA current drawnfromit.Thisvaluecorrespondstoa3.9-LSBerror. 22 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:DAC8551
DAC8551 www.ti.com SLAS429E–APRIL2005–REVISEDJUNE2017 8.3 System Examples 8.3.1 MicroprocessorInterfacing 8.3.1.1 DAC8551to8051Interface Figure56showsaserialinterfacebetweentheDAC8551andatypical8051-typemicrocontroller. The interface is setup with the TXD of the 8051 drives SCLK of the DAC8551, while RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port line P3.3 is used. When data are to be transmitted to the DAC8551, P3.3 is taken LOW. The 8051 transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left LOW after the first eight bits are transmitted, then a second write cycle is initiated to transmit the second byte of data. P3.3 is taken HIGH following the completion of the third write cycle. The 8051 outputs the serial data in a format that has the LSB first. The DAC8551 requires data with the MSB as the first bit received. The 8051transmitroutinemustthereforetakethisintoaccount,and mirrorthedataasneeded. 80C51/80L51(1) DAC8554(1) P3.3 SYNC TXD SCLK RXD D IN NOTE: (1) Additional pins omitted for clarity. Figure56. DAC8551to80C51or80L51Interface 8.3.1.2 DAC8551toMicrowireInterface Figure 57 shows an interface between the DAC8551 and any Microwire-compatible device. Serial data are shifted out on the falling edge of the serial clock and is clocked into the DAC8551 on the rising edge of the SK signal. MicrowireTM DAC8554(1) CS SYNC SK SCLK SO D IN NOTE: (1) Additional pins omitted for clarity. Figure57. DAC8551toMicrowireInterface 8.3.1.3 DAC8551to68HC11Interface Figure 58 shows a serial interface between the DAC8551 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8551, while the MOSI output drives the serial data line of the DAC. The SYNC signal isderivedfromaportline(PC7),similartothe8051diagram. 68HC11(1) DAC8551(1) PC7 SYNC SCK SCLK MOSI D IN NOTE: (1) Additional pins omitted for clarity. Figure58. DAC8551to68HC11Interface Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:DAC8551
DAC8551 SLAS429E–APRIL2005–REVISEDJUNE2017 www.ti.com System Examples (continued) The 68HC11 should be configured so that its CPOL bit is '0' and its CPHA bit is '1'. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to the DAC, the SYNC line is held LOW (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. (Data are transmitted MSB first.) In order to load data to the DAC8551, PC7 is left LOW after the first eight bits are transferred, then a second and third serial write operationareperformedtotheDAC.PC7istakenHIGHattheendofthisprocedure. 9 Power Supply Recommendations The DAC8551 can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to V DD should be well-regulated and low-noise. Switching power supplies and DCDC converters often have high- frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high- frequency spikes. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. TI recommends including a 1-µF to 10-µF capacitor and 0.1-µF bypass capacitor in order to further minimize noise from the power supply. The current consumption on the V pin, the DD short-circuit current limit, and the load current for the device is listed in Electrical Characteristics. The power supplymustmeettheaforementionedcurrentrequirements. 10 Layout 10.1 Layout Guidelines A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC8551 offers single-supply operation, and it often is used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and thehighertheswitchingspeed,themoredifficultitistokeepdigitalnoisefromappearingattheoutput. Due to the single ground pin of the DAC8551, all return currents, including digital and analog return currents for the DAC, must flow through a single point. Ideally, GND would be connected directly to an analog ground plane. Thisplanewouldbeseparatefromthegroundconnectionforthedigitalcomponentsuntiltheywereconnectedat thepower-entrypointofthesystem. As with the GND connection, V should be connected to a 5-V power-supply plane or trace that is separate DD from the connection for digital logic until they are connected at the power-entry point. TI recommends an additional 1-μF to 10-μF capacitor and 0.1-μF bypass capacitor. In some situations, additional bypassing may be required, such as a 100-μF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designedtoessentiallylow-passfilterthe5-Vsupply,removingthehigh-frequencynoise. 10.2 Layout Example 1 8 2 7 3 6 4 5 Figure59. LayoutDiagram 24 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:DAC8551
DAC8551 www.ti.com SLAS429E–APRIL2005–REVISEDJUNE2017 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • 2-wire,4-mAto20-mATransmitter,EMC/EMITestedReferenceDesign,TIDUAO7 • +5VPrecisionVoltageReference,SBVS003 • CMOS,Rail-to-Rail,I/OOperationalAmplifiers,SBOS180 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.4 Trademarks E2EisatrademarkofTexasInstruments. SPI,QSPIaretrademarksofMotorola,Inc. MicrowireisatrademarkofNationalSemiconductor. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:DAC8551
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) DAC8551IADGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 105 D81 & no Sb/Br) DAC8551IADGKT ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 105 D81 & no Sb/Br) DAC8551IADGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 105 D81 & no Sb/Br) DAC8551IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 105 D81 & no Sb/Br) DAC8551IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 105 D81 & no Sb/Br) DAC8551IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 105 D81 & no Sb/Br) DAC8551IDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 105 D81 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DAC8551 : •Automotive: DAC8551-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) DAC8551IADGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC8551IADGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC8551IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC8551IDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PackMaterials-Page1
PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) DAC8551IADGKR VSSOP DGK 8 2500 350.0 350.0 43.0 DAC8551IADGKT VSSOP DGK 8 250 210.0 185.0 35.0 DAC8551IDGKR VSSOP DGK 8 2500 350.0 350.0 43.0 DAC8551IDGKT VSSOP DGK 8 250 210.0 185.0 35.0 PackMaterials-Page2
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