® DAC7615 DAC7615 DAC7615 Quad, Serial Input, 12-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES APPLICATIONS l LOW POWER: 20mW l PROCESS CONTROL l UNIPOLAR OR BIPOLAR OPERATION l ATE PIN ELECTRONICS l SETTLING TIME: 10m s to 0.012% l CLOSED-LOOP SERVO-CONTROL l 12-BIT LINEARITY AND MONOTONICITY: l MOTOR CONTROL (cid:176) (cid:176) –40 C to +85 C l DATA ACQUISITION SYSTEMS l DOUBLE-BUFFERED DATA INPUTS l DAC-PER-PIN PROGRAMMERS l SMALL 20-LEAD SSOP PACKAGE DESCRIPTION for simultaneous update of all DAC outputs. The device can be powered from a single +5V supply or The DAC7615 is a quad, serial input, 12-bit, voltage from dual +5V and –5V supplies. output digital-to-analog converter (DAC) with guar- Low power and small size makes the DAC7615 ideal anteed 12-bit monotonic performance over the –40(cid:176) C for automatic test equipment, DAC-per-pin program- to +85(cid:176) C temperature range. An asynchronous reset mers, data acquisition systems, and closed-loop servo- clears all registers to either mid-scale (800 ) or zero- H control. The device is available in 16-pin plastic DIP, scale (000 ), selectable via the RESETSEL pin. The H 16-lead SOIC, and 20-lead SSOP packages and is individual DAC inputs are double buffered to allow guaranteed over the –40(cid:176) C to +85(cid:176) C temperature range. GND VDD VREFH Input DAC DAC A Register A Register A VOUTA SDI Input DAC DAC B Register B Register B Serial-to- VOUTB Parallel 12 Shift Register Input DAC DAC C Register C Register C VOUTC CLK CS DAC Input DAC Select DAC D Register D Register D VOUTD LOADREG RESETSEL RESET LOADDACS VREFL VSS International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation PDS-1443C Printed in U.S.A. November, 1998 SBAS091

SPECIFICATIONS At T = –40(cid:176)C to +85(cid:176)C, V = +5V, V = –5V, V = +2.5V, and V = –2.5V, unless otherwise noted. A DD SS REFH REFL DAC7615E, P, U DAC7615EB, PB, UB PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ACCURACY Linearity Error(1) V = 0V or –5V – 2 – 1 LSB(2) SS Linearity Matching(3) V = 0V or –5V – 2 – 1 LSB SS Differential Linearity Error V = 0V or –5V – 1 – 1 LSB SS Monotonicity 12 [ Bits Zero-Scale Error Code = 000 – 4 [ LSB H Zero-Scale Drift 2 5 [ [ ppm/(cid:176)C Zero-Scale Matching(3) – 2 – 1 LSB Full-Scale Error Code = FFF – 4 [ LSB H Full-Scale Matching(3) – 2 – 1 LSB Zero-Scale Error Code = 00A , V = 0V – 8 [ LSB H SS Zero-Scale Drift V = 0V 5 10 [ [ ppm/(cid:176)C SS Zero-Scale Matching(3) V = 0V – 4 – 2 LSB SS Full-Scale Error Code = FFF , V = 0V – 8 [ LSB H SS Full-Scale Matching(3) V = 0V – 4 – 2 LSB SS Power Supply Rejection 30 [ ppm/V ANALOG OUTPUT Voltage Output(4) V = 0V or –5V V V [ [ V SS REFL REFH Output Current –1.25 +1.25 [ [ mA Load Capacitance No Oscillation 100 [ pF Short-Circuit Current +5, –15 [ mA Short-Circuit Duration Indefinite [ REFERENCE INPUT V Input Range V = 0V or –5V V +1.25 +2.5 [ [ V REFH SS REFL V Input Range V = 0V 0 V –1.25 [ [ V REFL SS REFH V Input Range V = –5V –2.5 V –1.25 [ [ V REFL SS REFH DYNAMIC PERFORMANCE Settling Time(5) To – 0.012% 5 10 [ [ m s Channel-to-Channel Crosstalk Full-Scale Step 0.1 [ LSB On Any Other DAC, R = 2kW L Output Noise Voltage Bandwidth: 0Hz to 1MHz 40 [ nV/(cid:214) Hz DIGITAL INPUT/OUTPUT Logic Family TTL-Compatible CMOS [ Logic Levels V | I | £ 10m A 2.4 V +0.3 [ [ V IH IH DD V | I | £ 10m A –0.3 0.8 [ [ V IL IL Data Format Straight Binary [ POWER SUPPLY REQUIREMENTS V 4.75 5.25 [ [ V DD V If V „ 0V –5.25 –4.75 [ [ V SS SS I 1.5 1.9 [ [ mA DD I –2.1 –1.6 [ [ mA SS Power Dissipation V = –5V 15 20 [ [ mW SS V = 0V 7.5 10 [ [ mW SS TEMPERATURE RANGE Specified Performance –40 +85 [ [ (cid:176)C [ Specification same as grade to the left. NOTES: (1) If V = 0V, specification applies at code 00A and above. (2) LSB means Least Significant Bit, with V equal to +2.5V and V equal to –2.5V, SS H REFH REFL one LSB is 1.22mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage, does not take into account zero or full-scale error. (5) If V = –5V, full-scale step from code 000 to FFF or vice-versa. If V = 0V, full-scale positive step from code 000 to FFF and negative step from code SS H H SS H H FFF to 00A . H H The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC7615 2

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC V to V ...........................................................................–0.3V to +11V DISCHARGE SENSITIVITY DD SS V to GND........................................................................–0.3V to +5.5V DD VREFL to VSS...............................................................–0.3V to (VDD – VSS) This integrated circuit can be damaged by ESD. Burr-Brown V to V ..............................................................–0.3V to (V – V ) DD REFH DD SS recommends that all integrated circuits be handled with V to V ............................................................–0.3V to (V – V ) REFH REFL DD SS appropriate precautions. Failure to observe proper handling Digital Input Voltage to GND......................................–0.3V to V + 0.3V DD Maximum Junction Temperature...................................................+150(cid:176)C and installation procedures can cause damage. Operating Temperature Range.........................................–40(cid:176)C to +85(cid:176)C ESD damage can range from subtle performance degradation Storage Temperature Range..........................................–65(cid:176)C to +150(cid:176)C Lead Temperature (soldering, 10s)...............................................+300(cid:176)C to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may changes could cause the device not to meet its published cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. specifications. PACKAGE/ORDERING INFORMATION MAXIMUM MAXIMUM LINEARITY DIFFERENTIAL PACKAGE SPECIFICATION ERROR LINEARITY DRAWING TEMPERATURE ORDERING TRANSPORT PRODUCT (LSB) (LSB) PACKAGE NUMBER(1) RANGE NUMBER(2) MEDIA DAC7615P – 2 – 1 16-Pin DIP 180 –40(cid:176)C to +85(cid:176)C DAC7615P Rails DAC7615PB " " " " " DAC7615PB Rails DAC7615U – 2 – 1 16-Lead SOIC 211 –40(cid:176)C to +85(cid:176)C DAC7615U Rails " " " " " " DAC7615U/1K Tape and Reel DAC7615UB – 1 – 1 16-Lead SOIC 211 –40(cid:176)C to +85(cid:176)C DAC7615UB Rails " " " " " " DAC7615UB/1K Tape and Reel DAC7615E – 2 – 1 20-Lead SSOP 334 –40(cid:176)C to +85(cid:176)C DAC7615E Rails " " " " " " DAC7615E/1K Tape and Reel DAC7615EB – 1 – 1 20-Lead SSOP 334 –40(cid:176)C to +85(cid:176)C DAC7615EB Rails " " " " " " DAC7615EB/1K Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7615EB/1K” will get a single 1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. ® 3 DAC7615

PIN CONFIGURATION—P, U Packages PIN CONFIGURATION—E Package Top View PDIP, SOIC Top View SSOP V 1 16 RESETSEL V 1 20 RESETSEL DD DD V 2 15 RESET V 2 19 RESET OUTD OUTD V 3 14 LOADREG V 3 18 LOADREG OUTC OUTC V 4 13 LOADDACS V 4 17 LOADDACS REFL REFL DAC7615P, U V 5 12 CS NIC 5 16 NIC REFH DAC7615E V 6 11 CLK NIC 6 15 NIC OUTB V 7 10 SDI V 7 14 CS OUTA REFH V 8 9 GND V 8 13 CLK SS OUTB V 9 12 SDI OUTA V 10 11 GND SS PIN DESCRIPTIONS—P, U Packages PIN DESCRIPTIONS—E Package PIN LABEL DESCRIPTION PIN LABEL DESCRIPTION 1 VDD Positive Analog Supply Voltage, +5V nominal. 1 VDD Positive Analog Supply Voltage, +5V nominal. 2 VOUTD DAC D Voltage Output 2 VOUTD DAC D Voltage Output 3 VOUTC DAC C Voltage Output 3 VOUTC DAC C Voltage Output 4 VREFL Rpuetf evroelntacgee I nfopru at lVl DolAtaCgse. Low. Sets minimum out- 4 VREFL Rpuetf evroelntacgee I nfopru at lVl DolAtaCgse. Low. Sets minimum out- 5 V Reference Input Voltage High. Sets maximum out- REFH 5 NIC Not Internally Connected. put voltage for all DACs. 6 NIC Not Internally Connected. 6 V DAC B Voltage Output OUTB 7 V Reference Input Voltage High. Sets maximum out- 7 V DAC A Voltage Output REFH OUTA put voltage for all DACs. 8 V Negative Analog Supply Voltage, 0V or –5V nomi- SS nal. 8 VOUTB DAC B Voltage Output 9 GND Ground 9 VOUTA DAC A Voltage Output 10 SDI Serial Data Input 10 V Negative Analog Supply Voltage, 0V or –5V nomi- SS nal. 11 CLK Serial Data Clock 12 CS Chip Select Input 11 GND Ground 13 LOADDACS All DAC registers become transparent when 12 SDI Serial Data Input LOADDACS is LOW. They are in the latched state 13 CLK Serial Data Clock when LOADDACS is HIGH. 14 CS Chip Select Input 14 LOADREG The selected input register becomes transparent when LOADREG is LOW. It is in the latched state 15 NIC Not Internally Connected. when LOADREG is HIGH. 16 NIC Not Internally Connected. 15 RESET Asynchronous Reset Input. Sets DAC and input 17 LOADDACS All DAC registers becomes transparent when registers to either zero-scale (000 ) or mid-scale H LOADDACS is LOW. They are in the latched state (800 ) when LOW. RESETSEL determines which H when LOADDACS is HIGH. code is active. 18 LOADREG The selected input register becomes transparent 16 RESETSEL When LOW, a LOW on RESET will cause the DAC when LOADREG is LOW. It is in the latched state and input registers to be set to code 000 . When H when LOADREG is HIGH. RESETSEL is HIGH, a LOW on RESET will set the registers to code 800 . 19 RESET Asynchronous Reset Input. Sets all DAC registers H to either zero-scale (000 ) or mid-scale (800 ) H H when LOW. RESETSEL determines which code is active. 20 RESETSEL When LOW, a LOW on RESET will cause all DAC registers to be set to code 000 . When RESETSEL H is HIGH, a LOW on RESET will set the registers to code 800 . H ® DAC7615 4

TYPICAL PERFORMANCE CURVES: V = 0V SS At T = +25(cid:176)C, V = +5V, V = 0V, V = +2.5V, and V = 0V, representative unit, unless otherwise specified. A DD SS REFH REFL LINEARITY ERROR and LINEARITY ERROR and DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A) (DAC B) 0.50 0.50 B) 0.25 B) 0.25 E (LS 0.00 E (LS 0.00 L –0.25 L –0.25 –0.50 –0.50 0.50 0.50 B) 0.25 B) 0.25 S S E (L 0.00 E (L 0.00 DL –0.25 DL –0.25 –0.50 –0.50 000H 200H 400H 600H 800H A00H C00H E00H FFFH 000H 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code Digital Input Code LINEARITY ERROR and LINEARITY ERROR and DIFFERENTIAL DIFFERENTIAL LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE (DAC C) (DAC D) 0.50 0.50 B) 0.25 B) 0.25 S S L 0.00 L 0.00 E ( E ( L –0.25 L –0.25 –0.50 –0.50 0.50 0.50 B) 0.25 B) 0.25 S S E (L 0.00 E (L 0.00 DL –0.25 DL –0.25 –0.50 –0.50 000H 200H 400H 600H 800H A00H C00H E00H FFFH 000H 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code Digital Input Code LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE (DAC A, –40°C and +85°C) (DAC B, –40°C and +85°C) 0.50 0.50 +85°C +85°C B) 0.25 B) 0.25 S S L 0.00 L 0.00 E ( E ( L –0.25 L –0.25 –0.50 –0.50 0.50 0.50 –40°C –40°C B) 0.25 B) 0.25 S S L 0.00 L 0.00 E ( E ( L –0.25 L –0.25 –0.50 –0.50 000 200 400 600 800 A00 C00 E00 FFF 000 200 400 600 800 A00 C00 E00 FFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code ® 5 DAC7615

TYPICAL PERFORMANCE CURVES: V = 0V (CONT) SS At T = +25(cid:176)C, V = +5V, V = 0V, V = +2.5V, and V = 0V, representative unit, unless otherwise specified. A DD SS REFH REFL LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE (DAC C, –40°C and +85°C) (DAC D, –40°C and +85°C) 0.50 0.50 +85°C +85°C 0.25 0.25 B) B) S S L 0.00 L 0.00 E ( E ( L –0.25 L –0.25 –0.50 –0.50 0.50 0.50 –40°C –40°C 0.25 0.25 B) B) S S L 0.00 L 0.00 E ( E ( L –0.25 L –0.25 –0.50 –0.50 000 200 400 600 800 A00 C00 E00 FFF 000 200 400 600 800 A00 C00 E00 FFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code 2.75 POSITIVE SLEW RATE and SETTLING TIME 9 LSB) 2.75 NEGATIVE SLEW RATE and SETTLING TIME 9 (LSB)H 2.25 5V 6 2.5V ( 2.25 6 e 00A A: Output Voltage (V) 1100....72725555 LOADDAC0SV A B 30––36 ut Voltage, Deviation from + A: Output Voltage (V) 1100....72725555 LOADDA05CVVS A B 30––36 Voltage, Deviation from Cod –0.25–2 –1 0 1 2 3 4 5 6 7 8 –9 B: Outp –0.25–2 –1 0 1 2 3 4 5 6 7 8 –9 Output Time (µs) Time (µs) B: ® DAC7615 6

TYPICAL PERFORMANCE CURVES: V = –5V SS At T = +25(cid:176)C, V = +5V, V = –5V, V = +2.5V, and V = –2.5V, representative unit, unless otherwise specified. A DD SS REFH REFL LINEARITY ERROR and LINEARITY ERROR and DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A) (DAC B) 0.50 0.50 B) 0.25 B) 0.25 S S L 0.00 L 0.00 E ( E ( L –0.25 L –0.25 –0.50 –0.50 0.50 0.50 B) 0.25 B) 0.25 S S E (L 0.00 E (L 0.00 DL –0.25 DL –0.25 –0.50 –0.50 000 200 400 600 800 A00 C00 E00 FFF 000 200 400 600 800 A00 C00 E00 FFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code LINEARITY ERROR and LINEARITY ERROR and DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C) (DAC D) 0.50 0.50 B) 0.25 B) 0.25 E (LS 0.00 E (LS 0.00 L –0.25 L –0.25 –0.50 –0.50 0.50 0.50 B) 0.25 B) 0.25 S S E (L 0.00 E (L 0.00 DL –0.25 DL –0.25 –0.50 –0.50 000H 200H 400H 600H 800H A00H C00H E00H FFFH 000H 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code Digital Input Code LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE (DAC A, –40°C and +85°C) (DAC B, –40°C and +85°C) 0.50 0.50 +85°C +85°C B) 0.25 B) 0.25 S S L 0.00 L 0.00 E ( E ( L –0.25 L –0.25 –0.50 –0.50 0.50 0.50 –40°C –40°C B) 0.25 B) 0.25 S S L 0.00 L 0.00 E ( E ( L –0.25 L –0.25 –0.50 –0.50 000 200 400 600 800 A00 C00 E00 FFF 000 200 400 600 800 A00 C00 E00 FFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code ® 7 DAC7615

TYPICAL PERFORMANCE CURVES: V = –5V (CONT) SS At T = +25(cid:176)C, V = +5V, V = –5V, V = +2.5V, and V = –2.5V, representative unit, unless otherwise specified. A DD SS REFH REFL LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE (DAC C, –40°C and +85°C) (DAC D, –40˚C and +85˚C) 0.50 0.50 +85°C +85˚C B) 0.25 B) 0.25 S S L 0.00 L 0.00 E ( E ( L –0.25 L –0.25 –0.50 –0.50 0.50 0.50 –40°C –40˚C B) 0.25 B) 0.25 S S L 0.00 L 0.00 E ( E ( L –0.25 L –0.25 –0.50 –0.50 000 200 400 600 800 A00 C00 E00 FFF 000 200 400 600 800 A00 C00 E00 FFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code 3 POSITIVE SLEW RATE and SETTLING TIME 6 SB) 3 NEGATIVE SLEW RATE and SETTLING TIME 6 SB) A: Output Voltage (V) –––321012 LOADDAC05SVV A B –420––624 Output Voltage, Deviation from +2.5V (L A: Output Voltage (V) –––321012 LOADDAC05VVS A B –420––624 Output Voltage, Deviation from –2.5V (L –2 –1 0 1 2 3 4 5 6 7 8 B: –2 –1 0 1 2 3 4 5 6 7 8 B: Time (µs) Time (µs) V CURRENT vs CODE V CURRENT vs CODE REFH REFL (All DACs Set to Indicated Code) (All DACs Set to Indicated Code) 600 0 500 –100 A) 400 A) –200 µ µ nt ( nt ( urre 300 urre –300 C C REH 200 REL –400 V V 100 –500 0 –600 000 400 800 C00 FFF 000 400 800 C00 FFF H H H H H H H H H H Digital Input Code Digital Input Code ® DAC7615 8

THEORY OF OPERATION ANALOG OUTPUTS When V = –5V (dual supply operation), the output The DAC7615 is a quad, serial input, 12-bit, voltage output SS amplifier can swing to within 2.25V of the supply rails, DAC. The architecture is a classic R-2R ladder configuration over the –40(cid:176) C to +85(cid:176) C temperature range. With V = 0V followed by an operational amplifier that serves as a buffer. SS (single-supply operation), the output can swing to ground. Each DAC has its own R-2R ladder network and output op Note that the settling time of the output op amp will be amp, but all share the reference voltage inputs. The minimum longer with voltages very near ground. Also, care must be voltage output (“zero-scale”) and maximum voltage output taken when measuring the zero-scale error when V = 0V. (“full-scale”) are set by external voltage references (V SS REFL If the output amplifier has a negative offset, the output and V , respectively). The digital input is a 16-bit serial REFH voltage may not change for the first few digital input codes word that contains the 12-bit DAC code and a 2-bit address (000 , 001 , 002 , etc.) since the output voltage cannot code that selects one of the four DACs (the two remaining H H H swing below ground. bits are unused). The converter can be powered from a single +5V supply or a dual – 5V supply. Each device offers a reset The behavior of the output amplifier can be critical in some function which immediately sets all DAC output voltages and applications. Under short-circuit conditions (DAC output internal registers to either zero-scale (code 000 ) or mid-scale shorted to ground), the output amplifier can sink a great deal H (code 800 ). The reset code is selected by the state of the more current than it can source. See the Specifications table H RESETSEL pin (LOW = 000 , HIGH = 800 ). See Figures for more details concerning short circuit current. H H 1 and 2 for the basic operation of the DAC7615. +5V DAC7615(1) + 1µF to 10µF 0.1µF 1 V RESETSEL 16 DD 2 V RESET 15 Reset DACs(2) 0V to +2.5V OUTD 3 V LOADREG 14 Update Selected Register 0V to +2.5V OUTC 4 V LOADDACS 13 Update All DAC Registers +2.500V REFL 0.1µF 5 V CS 12 Chip Select REFH 6 V CLK 11 Clock OUTB 0V to +2.5V 7 V SDI 10 Serial Data In OUTA 0V to +2.5V 8 V GND 9 SS NOTE: (1) P and U package pin configurations shown. (2) As configured, RESET LOW sets all internal registers to code 000 (0V). If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800 (1.25V). H H FIGURE 1. Basic Single-Supply Operation of the DAC7615. DAC7615(1) +5V + 1µF to 10µF 0.1µF 1 V RESETSEL 16 +5V DD –2.5V to +2.5V 2 VOUTD RESET 15 Reset DACs(2) –2.5V to +2.5V 3 V LOADREG 14 Update Selected Register OUTC –2.500V 4 V LOADDACS 13 Update All DAC Registers 0.1µF REFL 5 V CS 12 Chip Select REFH +2.500V 0.1µF 6 VOUTB CLK 11 Clock 7 V SDI 10 Serial Data In –2.5V to +2.5V OUTA –2.5V to +2.5V 8 V GND 9 SS –5V 1µF to 10µF 0.1µF + NOTE: (1) P and U package pin configurations shown. (2) As configured, RESET LOW sets all internal registers to code 800 (0V). If RESETSEL is LOW, RESET LOW sets all internal registers to code 000 (–2.5V). H H FIGURE 2. Basic Dual-Supply Operation of the DAC7615. ® 9 DAC7615

REFERENCE INPUTS SYMBOL DESCRIPTION MIN TYP MAX UNITS The reference inputs, V and V , can be any voltage REFL REFH tDS Data Valid to CLK Rising 25 ns between V + 2.25V and V – 2.25V provided that V SS DD REFH tDH Data Held Valid after CLK Rises 20 ns is at least 1.25V greater than V . The minimum output REFL tCH CLK HIGH 30 ns of each DAC is equal to V – 1LSB plus a small offset REFL tCL CLK LOW 50 ns voltage (essentially, the offset of the output op amp). The t CS LOW to CLK Rising 55 ns CSS maximum output is equal to V plus a similar offset REFH tCSH CLK HIGH to CS Rising 15 ns voltage. Note that V (the negative power supply) must SS tLD1 LOADREG HIGH to CLK Rising 40 ns either be connected to ground or must be in the range of – t CLK Rising to LOADREG LOW 15 ns LD2 4.75V to –5.25V. The voltage on V sets several bias SS tLDRW LOADREG LOW Time 45 ns points within the converter. If V is not in one of these two SS tLDDW LOADDACS LOW Time 45 ns configurations, the bias values may be in error and proper t RESETSEL Valid to RESET LOW 25 ns RSSH operation of the device is not guaranteed. t RESET LOW Time 70 ns RSTW The current into the reference inputs depends on the DAC tS Settling Time 10 m s output voltages and can vary from a few microamps to TABLE I. Timing Specifications (T = –40(cid:176) C to +85(cid:176) C). A approximately 0.6 milliamp. Bypassing the reference volt- age or voltages with a 0.1m F capacitor placed as close as possible to the DAC7615 package is strongly recommended. chronous reset input (RESET) is provided to simplify start- up conditions, periodic resets, or emergency resets to a DIGITAL INTERFACE known state. Figure 3 and Table I provide the basic timing for the The DAC code and address are provided via a 16-bit serial DAC7615. The interface consists of a serial clock (CLK), interface as shown in Figure 3. The first two bits select the serial data (SDI), a load register signal (LOADREG), and a input register that will be updated when LOADREG goes “load all DAC registers” signal (LOADDACS). In addition, LOW (see Table II). The next two bits are not used. The last a chip select (CS) input is available to enable serial commu- 12 bits are the DAC code which is provided, most significant nication when there are multiple serial devices. An asyn- bit first. (MSB) (LSB) SDI A1 A0 X X D11 D10 D9 D3 D2 D1 D0 CLK tcss tCSH CS tLD1 tLD2 LOADREG t LDRW t t DS DH SDI t t CL CH CLK t LDDW LOADDACS tS tS 1 LSB 1 LSB V OUT ERROR BAND ERROR BAND t RSTW RESET t RSSH RESETSEL FIGURE 3. DAC7615 Timing. ® DAC7615 10

STATE OF SELECTED SELECTED STATE OF INPUT INPUT ALL DAC A1 A0 LOADREG LOADDACS RESET REGISTER REGISTER REGISTERS L(1) L L H(2) H A Transparent Latched L H L H H B Transparent Latched H L L H H C Transparent Latched H H L H H D Transparent Latched X(3) X H L H NONE (All Latched) Transparent X X H H H NONE (All Latched) Latched X X X X L ALL Reset(4) Reset(4) NOTES: (1) L = Logic LOW. (2) H = Logic HIGH. (3) X = Don’t Care. (4) Resets to either 000H or 800 , per the RESETSEL state (LOW = 000 , HIGH = 800 ). H H H When RESET rises, all registers that are in their latched state retain the reset value. TABLE II. Control Logic Truth Table. If both CS and CLK are used, then CS should rise only when CS(1) CLK(1) LOADREG RESET SERIAL SHIFT REGISTER CLK is HIGH. If not, then either CS or CLK can be used to H(2) X(3) H H No Change operate the shift register. See Table III for more information. L(4) L H H No Change The digital data into the DAC7615 is double-buffered. This L › (5) H H Advanced One Bit allows new data to be entered for each DAC without disturb- › L H H Advanced One Bit ing the analog outputs. When the new settings have been H(6) X L(7) H No Change entered into the device, all of the DAC outputs can be H(6) X H L(8) No Change updated simultaneously. The transfer from the input regis- NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X = ters to the DAC registers is accomplished with a HIGH to Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH LOW transition on the LOADDACS input. value is suggested in order to avoid a “false clock” from advancing the shift register and changing the shift register. (7) If data is clocked into the serial Because the DAC registers become transparent when register while LOADREG is LOW, the selected input register will change as the shift register bits “flow” through A1 and A0. This will corrupt the data in each LOADDACS is LOW, it is possible to keep this pin LOW input register that has been erroneously selected. (8) RESET LOW causes no and update each DAC via LOADREG. However, as each change in the contents of the serial shift register. new data word is entered into the device, the corresponding TABLE III. Serial Shift Register Truth Table. output will update immediately when LOADREG is taken LOW. Note that CS and CLK are combined with an OR gate and the output controls the serial-to-parallel shift register inter- Digital Input Coding nal to the DAC7615 (see the block diagram on the front of The DAC7615 input data is in Straight Binary format. The this data sheet). These two inputs are completely inter- output voltage is given by the following equation: changeable. In addition, care must be taken with the state of CLK when CS rises at the end of a serial transfer. If CLK is LOW when CS rises, the OR gate will provide a rising edge (VREFH – VREFL) • N V = V + to the shift register, shifting the internal data one additional OUT REFL 4096 bit. The result will be incorrect data and possible selection of the wrong input register. where N is the digital input code (in decimal). This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. ® 11 DAC7615

LAYOUT The power applied to V (as well as V , if not grounded) DD SS should be well regulated and low noise. Switching power A precision analog component requires careful layout, ad- supplies and DC/DC converters will often have high-fre- equate bypassing, and clean, well-regulated power supplies. quency glitches or spikes riding on the output voltage. In As the DAC7615 offers single-supply operation, it will often addition, digital components can create similar high-fre- be used in close proximity with digital logic, microcontrollers, quency spikes as their internal logic switches states. This microprocessors, and digital signal processors. The more noise can easily couple into the DAC output voltage through digital logic present in the design and the higher the switch- various paths between the power connections and analog ing speed, the more difficult it will be to achieve good output. performance from the converter. As with the GND connection, V should be connected to DD Because the DAC7615 has a single ground pin, all return a +5V power supply plane or trace that is separate from the currents, including digital and analog return currents, must connection for digital logic until they are connected at the flow through the GND pin. Ideally, GND would be con- power entry point. In addition, the 1m F to 10m F and 0.1m F nected directly to an analog ground plane. This plane would capacitors shown in Figure 4 are strongly recommended. In be separate from the ground connection for the digital some situations, additional bypassing may be required, such components until they were connected at the power entry as a 100m F electrolytic capacitor or even a “Pi” filter made point of the system (see Figure 4). up of inductors and capacitors—all designed to essentially lowpass filter the +5V supply, removing the high frequency noise (see Figure 4). Digital Circuits +5V +5V Power Supply Ground +5V DAC7615 Ground V DD 100µF + + 1µF to 0.1µF 10µF GND Optional Other Analog Components FIGURE 4. Suggested Power and Ground Connections for a DAC7615 Sharing a +5V Supply with a Digital System. ® DAC7615 12

PACKAGE OPTION ADDENDUM www.ti.com 3-Jul-2009 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty DAC7615E ACTIVE SSOP DB 20 70 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615E/1K ACTIVE SSOP DB 20 1000 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615E/1KG4 ACTIVE SSOP DB 20 1000 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615EB ACTIVE SSOP DB 20 70 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615EB/1K ACTIVE SSOP DB 20 1000 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615EB/1KG4 ACTIVE SSOP DB 20 1000 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615EBG4 ACTIVE SSOP DB 20 70 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615EG4 ACTIVE SSOP DB 20 70 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615P NRND PDIP N 16 25 Green(RoHS& CUNIPDAU N/AforPkgType noSb/Br) DAC7615PB NRND PDIP N 16 25 Green(RoHS& CUNIPDAU N/AforPkgType noSb/Br) DAC7615PBG4 NRND PDIP N 16 25 Green(RoHS& CUNIPDAU N/AforPkgType noSb/Br) DAC7615PG4 NRND PDIP N 16 25 Green(RoHS& CUNIPDAU N/AforPkgType noSb/Br) DAC7615U ACTIVE SOIC DW 16 40 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615U/1K ACTIVE SOIC DW 16 1000 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615U/1KG4 ACTIVE SOIC DW 16 1000 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615UB ACTIVE SOIC DW 16 40 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615UB/1K ACTIVE SOIC DW 16 1000 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615UB/1KG4 ACTIVE SOIC DW 16 1000 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615UBG4 ACTIVE SOIC DW 16 40 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7615UG4 ACTIVE SOIC DW 16 40 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. Addendum-Page1

PACKAGE OPTION ADDENDUM www.ti.com 3-Jul-2009 TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 30-Jan-2009 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) DAC7615E/1K SSOP DB 20 1000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 DAC7615EB/1K SSOP DB 20 1000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 DAC7615U/1K SOIC DW 16 1000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1 DAC7615UB/1K SOIC DW 16 1000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 30-Jan-2009 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) DAC7615E/1K SSOP DB 20 1000 346.0 346.0 33.0 DAC7615EB/1K SSOP DB 20 1000 346.0 346.0 33.0 DAC7615U/1K SOIC DW 16 1000 346.0 346.0 33.0 DAC7615UB/1K SOIC DW 16 1000 346.0 346.0 33.0 PackMaterials-Page2

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