® DAC7612 DAC7612 Dual, 12-Bit Serial Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION l LOW POWER: 3.7mW The DAC7612 is a dual, 12-bit digital-to-analog con- l FAST SETTLING: 7m s to 1 LSB verter (DAC) with guaranteed 12-bit monotonicity performance over the industrial temperature range. It l 1mV LSB WITH 4.095V FULL-SCALE requires a single +5V supply and contains an input RANGE shift register, latch, 2.435V reference, a dual DAC, and l COMPLETE WITH REFERENCE high speed rail-to-rail output amplifiers. For a full- l 12-BIT LINEARITY AND MONOTONICITY scale step, each output will settle to 1 LSB within 7m s OVER INDUSTRIAL TEMP RANGE while only consuming 3.7mW. l 3-WIRE INTERFACE: Up to 20MHz Clock The synchronous serial interface is compatible with a l SMALL PACKAGE: 8-Lead SOIC wide variety of DSPs and microcontrollers. Clock (CLK), Serial Data In (SDI), Chip Select (CS) and APPLICATIONS Load DACs (LOADDACS) comprise the serial inter- face. l PROCESS CONTROL The DAC7612 is available in an 8-lead SOIC package l DATA ACQUISITION SYSTEMS and is fully specified over the industrial temperature l CLOSED-LOOP SERVO-CONTROL range of –40(cid:176) C to +85(cid:176) C. l PC PERIPHERALS l PORTABLE INSTRUMENTATION VDD 12-Bit DAC A VOUTA 12 LOADDACS DAC Register A 12 CS CLK 14-Bit Serial Shift Register SDI 12 Ref DAC Register B 12 12-Bit DAC B VOUTB DAC7612 GND International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1999 Burr-Brown Corporation PDS-1501A Printed in U.S.A. June, 1999 SBAS106

SPECIFICATIONS At T = –40(cid:176)C to +85(cid:176)C, and V = +5V, unless otherwise noted. A DD DAC7612U DAC7612UB PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 12 [ Bits ACCURACY Relative Accuracy(1) –2 – 1/2 +2 –1 – 1/4 +1 LSB Differential Nonlinearity Guaranteed Monotonic –1 – 1/2 +1 –1 – 1/4 +1 LSB Zero-Scale Error Code 000 –1 +1 +3 [ [ [ LSB H Zero Scale Match Code 000 1/2 1/2 2 LSB H Full-Scale Voltage Code FFF 4.079 4.095 4.111 4.087 4.095 4.103 V H Full-Scale Match Code FFF 1/2 1/2 2 LSB H ANALOG OUTPUT Output Current Code 800 – 5 – 7 [ [ mA H Load Regulation R ‡ 402W , Code 800 1 3 [ [ LSB LOAD H Capacitive Load No Oscillation 500 [ pF Short-Circuit Current – 15 [ mA Short-Circuit Duration GND or V Indefinite [ DD DIGITAL INPUT Data Format Serial [ Data Coding Straight Binary [ Logic Family CMOS [ Logic Levels V 0.7 • V [ V IH DD V 0.3 • V [ V IL DD I – 10 [ m A IH I – 10 [ m A IL DYNAMIC PERFORMANCE Settling Time(2) (t ) To – 1 LSB of Final Value 7 [ m s S DAC Glitch 2.5 [ nV-s Digital Feedthrough 0.5 [ nV-s POWER SUPPLY V +4.75 +5.0 +5.25 [ [ [ V DD I V = 5V, V = 0V, No Load, at Code 000 0.75 1.5 [ [ mA DD IH IL H Power Dissipation V = 5V, V = 0V, No Load 3.5 7.5 [ [ mW IH IL Power Supply Sensitivity D V = – 5% 0.0025 0.002 [ [ %/% DD TEMPERATURE RANGE Specified Performance –40 +85 [ [ (cid:176)C [ Same specification as for DAC7612U. NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC7612 2

PIN CONFIGURATION PIN DESCRIPTIONS Top View SO-8 PIN LABEL DESCRIPTION 1 SDI Serial Data Input. Data is clocked into the internal serial register on the rising edge of CLK. 2 CLK Synchronous Clock for the Serial Data Input. SDI 1 8 VOUTA 3 LOADDACS aLroea dtrsa tnhsep ainrteenrtn alal tDchAeCs raengdis taerres . tAralln DspAaCre rnetg wishteerns CLK 2 7 VDD LOADDACS is LOW (regardless of the state of CS DAC7612U or CLK). LOADDACS 3 6 GND 4 CS Chip Select. Active LOW. CS 4 5 VOUTB 5 VOUTB DAC B Output Voltage 6 GND Ground 7 V Positive Power Supply DD 8 V DAC A Output Voltage OUTA ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC V to GND..........................................................................–0.3V to 6V DISCHARGE SENSITIVITY DD Digital Inputs to GND..............................................–0.3V to V + 0.3V DD VOUT to GND ...........................................................–0.3V to VDD + 0.3V This integrated circuit can be damaged by ESD. Burr-Brown Power Dissipation........................................................................325mW Thermal Resistance, q ...........................................................150(cid:176)C/W recommends that all integrated circuits be handled with JA Maximum Junction Temperature..................................................+150(cid:176)C appropriate precautions. Failure to observe proper handling Operating Temperature Range......................................–40(cid:176)C to +85(cid:176)C and installation procedures can cause damage. Storage Temperature Range.......................................–65(cid:176)C to +150(cid:176)C Lead Temperature (soldering, 10s)..............................................+300(cid:176)C ESD damage can range from subtle performance degrada- NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” tion to complete device failure. Precision integrated circuits may cause permanent damage to the device. Exposure to absolute maximum may be more susceptible to damage because very small conditions for extended periods may affect device reliability. parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION MINIMUM RELATIVE DIFFERENTIAL SPECIFICATION PACKAGE ACCURACY NONLINEARITY TEMPERATURE DRAWING ORDERING TRANSPORT PRODUCT (LSB) (LSB) RANGE PACKAGE NUMBER(1) NUMBER(2) MEDIA DAC7612U – 2 – 1 –40(cid:176)C to +85(cid:176)C SO-8 182 DAC7612U Rails " " " " " " DAC7612U/2K5 Tape and Reel DAC7612UB – 1 – 1 –40(cid:176)C to +85(cid:176)C SO-8 182 DAC7612UB Rails " " " " " " DAC7612UB/2K5 Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC7612U/2K5” will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. ® 3 DAC7612

EQUIVALENT INPUT LOGIC ESD protection DAC Switches diodes to V DD and GND 12 LOADDACS DAC B Register 12 SDI Data Serial Shift Register CS 12 CLK DAC A Register 12 DAC Switches ® DAC7612 4

TIMING DIAGRAMS (MSB) (LSB) SDI A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK tCSS tCSH CS t t LD1 LD2 LOADDACS t t DS DH SDI t t CL CH CLK t LDW LOADDACS t FS S – 1 LSB V OUT Error Band ZS LOGIC TRUTH TABLE TIMING SPECIFICATIONS SERIAL SHIFT DAC DAC TA = –40(cid:176)C to +85(cid:176)C and VDD = +5V. A1 A0 CLK CS LOADDACS REGISTER REGISTER A REGISTER B SYMBOL DESCRIPTION MIN TYP MAX UNITS X X X H H No Change No Change No Change t Clock Width HIGH 30 ns X X › L H Shifts One Bit No Change No Change CH t Clock Width LOW 30 ns L X X H(1) L No Change Loads Serial Loads Serial CL Data Word Data Word tLDW Load Pulse Width 20 ns H L X H L No Change Loads Serial No Change t Data Setup 15 ns DS Data Word t Data Hold 15 ns DH H H X H L No Change No Change Loads Serial t Load Setup 15 ns Data Word LD1 › Positive Logic Transition; X = Don’t Care. tLD2 Load Hold 10 ns t Select 30 ns CSS NOTE: (1) A HIGH value is suggested in order to avoid to “false clock” from t Deselect 20 ns advancing the shift register and changing the DAC voltage. CSH NOTE: All input control signals are specified with t = t = 5ns (10% to 90% R F of +5V) and timed from a voltage level of 2.5V. These parameters are DATA INPUT TABLE guaranteed by design and are not subject to production testing. B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ® 5 DAC7612

TYPICAL PERFORMANCE CURVES At T = +25(cid:176), and V = 5V, unless otherwise specified. A DD OUTPUT SWING vs LOAD PULL-DOWN VOLTAGE vs OUTPUT SINK CURRENT 5 1k 4 100 +85°C e (V) RDL atitead = t oF FGFNHD mV) Voltag 3 V (OUT 10 +25°C utput 2 Delta 1 –40°C O 1 R tied to V 0.1 L DD Data = 000 H Data = 000 H 0 0.01 10 100 1k 10k 100k 0.001 0.01 0.1 1 10 100 Load Resistance (W ) Current (mA) BROADBAND NOISE SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 4.0 3.5 v) V/di mA) 3.0 mge (500 Current ( 22..50 Volta pply 1.5 oise Su 1.0 N 0.5 0 Time (2ms/div) 0 1 2 3 4 5 Code = FFFH, BW = 1MHz Logic Voltage (V) POWER SUPPLY REJECTION vs FREQUENCY MINIMUM SUPPLY VOLTAGE vs LOAD 70 5.0 Data = FFF H 60 V = 5V – 2D0D0mV AC 4.8 50 V) R (dB) 40 nimum ( 4.6 PS 30 MiD 4.4 D V 20 4.2 10 0 4.0 10 100 1k 10k 100k 1M 0.01 0.1 1 10 Frequency (Hz) Output Load Current (mA) ® DAC7612 6

TYPICAL PERFORMANCE CURVES (CONT) At T = +25(cid:176), and V = 5V, unless otherwise specified. A DD SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE SUPPLY CURRENT vs TEMPERATURE 20 2.0 V = 3.5V V = 5.0V 15 PCousrriteivnet 11..86 DNLaoOt aLG oIC=a dFFFH VDD = 5.25V DD mA) 10 Limit Data = 800 mA) 1.4 put Current ( –505 Output tied to ISHOURCE ply Current ( 110...208 VDD = 4.75V Out –10 Sup 0.6 Negative 0.4 –15 Current 0.2 At worst-case digital inputs. Limit –20 0 0 1 2 3 4 5 6 –50 –30 –10 10 30 50 70 90 110 130 Output Voltage (V) Temperature (°C) MIDSCALE GLITCH PERFORMANCE MIDSCALE GLITCH PERFORMANCE LOADDACS LOADDACS div) div) V/ V/ m m 5 5 (OUT (OUT V V 7FFH to 800H 800H to 7FFH Time (500ns/div) Time (500ns/div) LARGE-SIGNAL SETTLING TIME RISE TIME DETAIL C = 100pF LOADDACS L R = No Load L C = 100pF L R = No Load L V/div) mV/div) V (1OUT V (1OUT LOADDACS Time (20µs/div) Time (10µs/div) ® 7 DAC7612

TYPICAL PERFORMANCE CURVES (CONT) At T = +25(cid:176), and V = 5V, unless otherwise specified. A DD FALL TIME DETAIL OUTPUT VOLTAGE NOISE vs FREQUENCY 10.000 CL = 100pF Data = FFFH R = No Load L div) Hz) 1.000 mV/ µ(cid:214)V/ (1OUT oise ( V N 0.100 LOADDACS 0.010 Time (10µs/div) 10 100 1k 10k 100k Frequency (Hz) LONG-TERM DRIFT ACCELERATED BY BURN-IN TOTAL UNADJUSTED ERROR HISTOGRAM 5 35 V) 4 T.U.E = S (INL + ZSE + FSE) m 30 Sample Size = 200 Units S ( 3 Max T = +25°C e at F 2 nits 25 A ge Chang –101 Avg mber of U 2105 olta –2 Min Nu 10 V ut –3 Outp –4 5 –5 0 0 168 336 504 672 840 1008 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 Hours of Operation at +150°C FULL-SCALE VOLTAGE vs TEMPERATURE ZERO-SCALE VOLTAGE vs TEMPERATURE 4.111 3 Avg + 3s Avg + 3s V) 4.103 mV) 2 ull-Scale Output ( 4.095 Avg o-Scale Output ( 1 Avg Avg – 3s F 4.087 Zer 0 Avg – 3s 4.079 –1 –40 –15 10 35 60 85 –40 –15 10 35 60 85 Temperature (°C) Temperature (°C) ® DAC7612 8

TYPICAL PERFORMANCE CURVES (CONT) At T = +25(cid:176), and V = 5V, unless otherwise specified. A DD LINEARITY ERROR vs DIGITAL CODE LINEARITY ERROR vs DIGITAL CODE (DAC A at +85°C) (DAC B at +85°C) 2.0 2.0 1.5 1.5 s) 1.0 s) 1.0 B B S S L 0.5 L 0.5 or ( or ( Err 0 Err 0 y y arit–0.5 arit–0.5 e e n n Li–1.0 Li–1.0 –1.5 –1.5 –2.0 –2.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 Code Code LINEARITY ERROR vs DIGITAL CODE LINEARITY ERROR vs DIGITAL CODE (DAC A at +25°C) (DAC B at +25°C) 2.0 2.0 1.5 1.5 s) 1.0 s) 1.0 B B S S L 0.5 L 0.5 or ( or ( Err 0 Err 0 y y arit–0.5 arit–0.5 e e n n Li–1.0 Li–1.0 –1.5 –1.5 –2.0 –2.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 Code Code LINEARITY ERROR vs DIGITAL CODE LINEARITY ERROR vs DIGITAL CODE (DAC A at –40°C) (DAC B at –40°C) 2.0 2.0 1.5 1.5 s) 1.0 s) 1.0 B B S S L 0.5 L 0.5 or ( or ( Err 0 Err 0 y y arit–0.5 arit–0.5 e e n n Li–1.0 Li–1.0 –1.5 –1.5 –2.0 –2.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 Code Code ® 9 DAC7612

OPERATION next 12 bits are the code (MSB-first) sent to the DAC. The data format is Straight Binary and is loaded MSB-first into The DAC7612 is a dual, 12-bit digital-to-analog converter the shift registers after loading the address bits. Table I shows (DAC) complete with a serial-to-parallel shift register, DAC the relationship between input code and output voltage. registers, laser-trimmed 12-bit DACs, on-board reference, The digital data into the DAC7612 is double-buffered. This and rail-to-rail output amplifiers. Figure 1 shows the basic means that new data can be entered into the chosen DAC operation of the DAC7612. without disturbing the old data and the analog output of the converter. At some point after the data has been entered into INTERFACE the serial shift register, this data can be transferred into the Figure 1 shows the basic connection between a DAC registers. This transfer is accomplished with a HIGH microcontroller and the DAC7612. The interface consists of to LOW transition of the LOADDACS pin. The LOADDACS a Serial Clock (CLK), Serial Data (SDI), and a Load DAC pin makes the DAC registers transparent. If new data is signal (LOADDACS). In addition, a chip select (CS) input is shifted into the shift register while LOADDACS is LOW, available to enable serial communication when there are the DAC output voltages will change as each new bit is multiple serial devices. Loading either DAC A or DAC B is entered. To prevent this, LOADDACS must be returned done by shifting 14 serial bits in via the SDI input. The first HIGH prior to shifting in new serial data. 2 bits represent the address of the DAC to be updated and the DIGITAL-TO-ANALOG CONVERTER The internal DAC section is a 12-bit voltage output DAC7612 Full-Scale Range = 4.095V device that swings between ground and the internal ref- Least Significant Bit = 1mV erence voltage. The DAC is realized by a laser-trimmed DIGITAL INPUT CODE ANALOG OUTPUT R-2R ladder network which is switched by N-channel STRAIGHT OFFSETBINARY (V) DESCRIPTION MOSFETs. Each DAC output is internally connected to a FFFH +4.095 Full Scale rail-to-rail output operational amplifier. 801 +2.049 Midscale + 1 LSB H 800 +2.048 Midscale H OUTPUT AMPLIFIER 7FF +2.047 Midscale – 1 LSB H 000 0 Zero Scale A precision, low-power amplifier buffers the output of each H DAC section and provides additional gain to achieve a 0V to TABLE I. Digital Input Code and Corresponding Ideal 4.095V range. Each amplifier has low offset voltage, low Analog Output. DAC7612U Serial Data 1 SDI V 8 0V to +4.095V OUTA Serial Clock 2 CLK VDD 7 + 0.1µF 10µF Load DACs 3 LOADDACS GND 6 Chip Select 4 CS VOUTB 5 0V to +4.095V FIGURE 1. Basic Operation of the DAC7612. ® DAC7612 10

noise, and a set gain of 1.682V/V (4.095/2.435). See Figure If power consumption is critical, it is important to keep the 2 for an equivalent circuit schematic of the analog portion of logic levels on the digital inputs (SDI, CLK, CS, the DAC7612. LOADDACS) as close as possible to either V or ground. DD The output amplifier has a 7m s typical settling time to – 1 This will keep the CMOS inputs (see “Supply Current vs Logic Input Voltages” in the Typical Performance Curves) LSB of the final value. Note that there are differences in the from shunting current between V and ground. settling time for negative-going signals versus positive- DD going signals. The DAC7612 power supply should be bypassed as shown The rail-to-rail output stage of the amplifier provides the full- in Figure 1. The bypass capacitors should be placed as close scale range of 0V to 4.095V while operating on a supply voltage to the device as possible, with the 0.1m F capacitor taking as low as 4.75V. In addition to its ability to drive resistive loads, priority in this regard. The “Power Supply Rejection vs the amplifier will remain stable while driving capacitive loads Frequency” graph in the Typical Performance Curves sec- of up to 500pF. See Figure 3 for an equivalent circuit schematic tion shows the PSRR performance of the DAC7612. This of the amplifier’s output driver and the Typical Performance should be taken into account when using switching power Curves section for more information regarding settling time, supplies or DC/DC converters. load driving capability, and output noise. In addition to offering guaranteed performance with V in DD the 4.75V to 5.25V range, the DAC7612 will operate with reduced performance down to 4.5V. Operation between POWER SUPPLY 4.5V and 4.75V will result in longer settling time, reduced A BiCMOS process and careful design of the bipolar and performance, and current sourcing capability. Consult the CMOS sections of the DAC7612 result in a very low power “V vs Load Current” graph in the Typical Performance device. Bipolar transistors are used where tight matching DD Curves section for more information. and low noise are needed to achieve analog accuracy, and CMOS transistors are used for logic, switching functions and for other low power stages. R-2R DAC 2R Output Amplifier R Buffer 2R R 2 Bandgap 2.435V Reference R R 2R 1 R 2R Typical of DAC A or DAC B 2R FIGURE 2. Simplified Schematic of Analog Portion. V DD P-Channel V OUT N-Channel GND FIGURE 3. Simplified Driver Section of Output Amplifier. ® 11 DAC7612

APPLICATIONS reference point for the internal bandgap reference. Ideally, GND would be connected directly to an analog ground POWER AND GROUNDING plane. This plane would be separate from the ground con- The DAC7612 can be used in a wide variety of situations— nection for the digital components until they are connected from low power, battery operated systems to large-scale at the power entry point of the system (see Figure 4). industrial process control systems. In addition, some appli- The power applied to V should be well regulated and low- DD cations require better performance than others, or are par- noise. Switching power supplies and DC/DC converters will ticularly sensitive to one or two specific parameters. This often have high-frequency glitches or spikes riding on the diversity makes it difficult to define definite rules to follow output voltage. In addition, digital components can create concerning the power supply, bypassing, and grounding. similar high frequency spikes as their internal logic switches The following discussion must be considered in relation to states. This noise can easily couple into the DAC output the desired performance and needs of the particular system. voltage through various paths between V and V . DD OUT A precision analog component requires careful layout, ad- As with the GND connection, V should be connected to DD equate bypassing, and a clean, well-regulated power supply. a +5V power supply plane or trace that is separate from the As the DAC7612 is a single-supply, +5V component, it will connection for digital logic until they are connected at the often be used in conjunction with digital logic, power entry point. In addition, the 10m F and 0.1m F capaci- microcontrollers, microprocessors, and digital signal proces- tors shown in Figure 4 are strongly recommended and sors. The more digital logic present in the design and the should be installed as close to V and ground as possible. DD higher the switching speed, the more difficult it will be to In some situations, additional bypassing may be required achieve good performance. such as a 100m F electrolytic capacitor or even a “Pi” filter Because the DAC7612 has a single ground pin, all return made up of inductors and capacitors—all designed to essen- currents, including digital and analog return currents, must tially lowpass filter the +5V supply, removing the high flow through this pin. The GND pin is also the ground frequency noise (see Figure 4). Digital Circuits +5V Power +5V Supply +5V GND DAC7612 GND VDD + + 100µF 10µF 0.1µF GND Optional Other Analog Components FIGURE 4. Suggested Power and Ground Connections for a DAC7612 Sharing a +5V Supply with a Digital System. ® DAC7612 12

PACKAGE OPTION ADDENDUM www.ti.com 16-Feb-2009 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty DAC7612U ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7612U/2K5 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7612U/2K5G4 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7612UB ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7612UB/2K5 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7612UB/2K5G4 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7612UBG4 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7612UG4 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) DAC7612U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 DAC7612UB/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) DAC7612U/2K5 SOIC D 8 2500 346.0 346.0 29.0 DAC7612UB/2K5 SOIC D 8 2500 346.0 346.0 29.0 PackMaterials-Page2

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