® DAC7611 DAC7611 DAC7611 12-Bit Serial Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION l LOW POWER: 2.5mW The DAC7611 is a 12-bit digital-to-analog converter l FAST SETTLING: 7m s to 1 LSB (DAC) with guaranteed 12-bit monotonicity perfor- mance over the industrial temperature range. It re- l 1mV LSB WITH 4.095V FULL-SCALE quires a single +5V supply and contains an input shift RANGE register, latch, 2.435V reference, DAC, and high speed l COMPLETE WITH REFERENCE rail-to-rail output amplifier. For a full-scale step, the l 12-BIT LINEARITY AND MONOTONICITY output will settle to 1 LSB within 7m s. The device OVER INDUSTRIAL TEMP RANGE consumes 2.5mW (0.5mA at 5V). l ASYNCHRONOUS RESET TO 0V The synchronous serial interface is compatible with a l 3-WIRE INTERFACE: Up to 20MHz Clock wide variety of DSPs and microcontrollers. Clock (CLK), serial data in (SDI), and load strobe (LD) l ALTERNATE SOURCE TO DAC8512 comprise the serial interface. In addition, two control pins provide a chip select (CS) function and an asyn- chronous clear (CLR) input. The CLR input can be APPLICATIONS used to ensure that the DAC7611 output is 0V on power-up or as required by the application. l PROCESS CONTROL The DAC7611 is available in an 8-lead SOIC or 8-pin l DATA ACQUISITION SYSTEMS plastic DIP package and is fully specified over the l CLOSED-LOOP SERVO-CONTROL industrial temperature range of –40(cid:176) C to +85(cid:176) C. l PC PERIPHERALS l PORTABLE INSTRUMENTATION V DD DAC7611 Ref 12-Bit DAC V OUT 12 CLR DAC Register LD 12 CS CLK Serial Shift Register SDI GND International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1997 Burr-Brown Corporation PDS-11402A DAPrCinte7d 6in 1U.1S.A. April, 1998 SBAS075

SPECIFICATIONS ELECTRICAL At T = –40(cid:176)C to +85(cid:176)C, and V = +5V, unless otherwise noted. A DD DAC7611P, U DAC7611PB, UB PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ACCURACY Resolution 12 [ Bits Relative Accuracy(1) –2 – 1/2 +2 –1 – 1/4 +1 LSB Differential Nonlinearity Guaranteed Monotonic –1 – 1/2 +1 –1 – 1/4 +1 LSB Zero-Scale Error Code 000H –1 +1 +3 [ [ [ LSB Full Scale Voltage Code FFFH 4.079 4.095 4.111 4.087 4.095 4.103 V ANALOG OUTPUT Output Current Code 800H – 5 – 7 [ [ mA Load Regulation R ‡ 402W , Code 800 1 3 [ [ LSB LOAD H Capacitive Load No Oscillation 500 [ pF Short Circuit Current – 70 [ mA Short Circuit Duration GND or V Indefinite [ DD DIGITAL INPUT Data Format Serial [ Data Coding Straight Binary [ Logic Family TTL [ Logic Levels VIH 2.4 [ V V 0.8 [ V IL IIH – 10 [ m A IIL – 10 [ m A DYNAMIC PERFORMANCE Settling Time(2) (tS) To – 1 LSB of Final Value 7 [ m s DAC Glitch 15 [ nV-s Digital Feedthrough 2 [ nV-s POWER SUPPLY VDD +4.75 +5.0 +5.25 [ [ [ V IDD VIH = 5V, VIL = 0V, No Load, at Code 000H 0.5 1 [ [ mA Power Dissipation V = 5V, V = 0V, No Load 2.5 5 [ [ mW IH IL Power Supply Sensitivity D VDD = – 5% 0.001 0.004 [ [ %/% TEMPERATURE RANGE Specified Performance –40 +85 [ [ (cid:176)C [ Same specification as for DAC7611P, U. NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC7611 2

PIN CONFIGURATION PIN DESCRIPTION Top View DIP PIN LABEL DESCRIPTION 1 V Power Supply DD 2 CS Chip Select (active LOW). VDD 1 8 VOUT 3 CLK Synchronous Clock for the Serial Data Input. CS 2 7 GND 4 SDI Serial Data Input. Data is clocked into the internal CLK 3 DAC7611 6 CLR serial register on the rising edge of CLK. 5 LD Loads the Internal DAC Register. NOTE: The DAC SDI 4 5 LD register is a transparent latch and is transparent when LD is LOW (regardless of the state of CS or CLK). 6 CLR Asynchronous Input to Clear the DAC Register. PIN CONFIGURATION When CLR is strobbed LOW, the DAC register is set to 000 and the output voltage to 0V. H Top View SOIC 7 GND Ground 8 V Voltage Output. Fixed output voltage range of ap- OUT proximately 0V to 4.095V (1mV/LSB). The internal VDD 1 8 VOUT reference maintains this output range over time, temperature, and power supply variations (within CS 2 7 GND the values defined in the specifications section). DAC7611 CLK 3 6 CLR SDI 4 5 LD ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with VDD to GND..........................................................................–0.3V to 6V appropriate precautions. Failure to observe proper handling Digital Inputs to GND.............................................–0.3V to VDD + 0.3V and installation procedures can cause damage. V to GND...........................................................–0.3V to V + 0.3V OUT DD Power Dissipation........................................................................325mW ESD damage can range from subtle performance degrada- TMhaexrimmaulm R Jeusniscttaionnc eT, eqmJAp.e..r.a..t.u..r..e..................................................................................................15+01(cid:176)5C0/(cid:176)WC tion to complete device failure. Precision integrated circuits Operating Temperature Range......................................–40(cid:176)C to +85(cid:176)C may be more susceptible to damage because very small Storage Temperature Range........................................–65(cid:176)C to +150(cid:176)C parametric changes could cause the device not to meet its Lead Temperature (soldering, 10s).............................................+300(cid:176)C published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION MINIMUM RELATIVE DIFFERENTIAL SPECIFICATION PACKAGE ACCURACY NONLINEARITY TEMPERATURE DRAWING ORDERING TRANSPORT PRODUCT (LSB) (LSB) RANGE PACKAGE NUMBER(1) NUMBER(2) MEDIA DAC7611P – 2 – 1 –40(cid:176)C to +85(cid:176)C 8-Pin DIP 006 DAC7611P Rails DAC7611U – 2 – 1 –40(cid:176)C to +85(cid:176)C 8-Lead SOIC 182 DAC7611U Rails " " " " " " DAC7611U/2K5 Tape and Reel DAC7611PB – 1 – 1 –40(cid:176)C to +85(cid:176)C 8-Pin DIP 006 DAC7611PB Rails DAC7611UB – 1 – 1 –40(cid:176)C to +85(cid:176)C 8-Lead SOIC 182 DAC7611UB Rails " " " " " " DAC7611UB/2K5 Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC7611/2K5” will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. ® 3 DAC7611

EQUIVALENT INPUT LOGIC ESD protection DAC diodes to V DD Switches and GND 12 CLR Force to 000 H DAC Register LD Latched Transparent 12 SDI Data Serial Shift Register CS CLK ® DAC7611 4

TIMING DIAGRAMS (MSB) (LSB) SDI D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK t t CSS CSH CS t t LD1 LD2 LD t t DS DH SDI t t CL CH CLK t LDW LD t CLRW CLR t t FS S – 1 LSB S V OUT Error Band ZS LOGIC TRUTH TABLE TIMING SPECIFICATIONS SERIAL SHIFT TA = –40(cid:176)C to +85(cid:176)C and VDD = +5V. CS(1) CLK(1) CLR LD REGISTER DAC REGISTER SYMBOL DESCRIPTION MIN TYP MAX UNITS H X H H No Change No Change t Clock Width HIGH 30 ns L L H H No Change No Change CH L H H H No Change No Change tCL Clock Width LOW 30 ns L › H H Advanced One Bit No Change tLDW Load Pulse Width 20 ns › L H H Advanced One Bit No Change tDS Data Setup 15 ns H(2) X H fl No Change Changes to Value of tDH Data Hold 15 ns Serial Shift Register tCLRW Clear Pulse Width 30 ns H(2) X H L(3) No Change Transparent t Load Setup 15 ns LD1 H X L X No Change Loaded with 000H tLD2 Load Hold 10 ns H X › H No Change Latched with 000H t Select 30 ns CSS › Positive Logic Transition; fl Negative Logic Transition; X = Don’t Care. tCSH Deselect 20 ns NOTES: (1) CS and CLK are interchangeable. (2) A HIGH value is suggested NOTE: All input control signals are specified with t = t = 5ns (10% to 90% R F in order to avoid to “false clock” from advancing the shift register and changing of +5V) and timed from a voltage level of 1.6V. These parameters are the DAC voltage. (3) If data is clocked into the serial register while LD is LOW, guaranteed by design and are not subject to production testing. the DAC output voltage will change, reflecting the current value of the serial shift register. ® 5 DAC7611

TYPICAL PERFORMANCE CURVES At TA = +25(cid:176), and VDD = 5V, unless otherwise specified. OUTPUT SWING vs LOAD PULL-DOWN VOLTAGE vs OUTPUT SINK CURRENT 5 1k 4 100 85°C (mV) oltage (V) 3 RLD taietad =to F AFGFNHD (mV)OUT 10 25°C V V utput 2 Delta 1 O R tied to +5V –40°C 1 DLata = 000 0.1 H Data = 000 H 0 0.01 10 100 1k 10k 100k 0.001 0.01 0.1 1 10 100 Load Resistance (W ) Current (mA) BROADBAND NOISE SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 4.0 No Load v) 3.2 V/di mA) m00 nt ( 2.4 5 e e ( urr g C olta ply 1.6 V p se Code = FFFH Su Noi BW = 2MHz 0.8 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Time (2ms/div) Logic Voltage (V) POWER SUPPLY REJECTION vs FREQUENCY MINIMUM SUPPLY VOLTAGE vs LOAD 70 5.0 D V = 1 LSB Data = FFF FS 60 V = 5V H Data = FFFH DD±200mV AC 4.8 50 V) R (dB) 40 nimum ( 4.6 PS 30 MiD4.4 D V 20 4.2 10 0 4.0 10 100 1k 10k 100k 1M 0.010 0.100 1.000 10.000 Frequency (Hz) Output Load Current (mA) ® DAC7611 6

TYPICAL PERFORMANCE CURVES (CONT) At TA = +25(cid:176), and VDD = 5V, unless otherwise specified. SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE SUPPLY CURRENT vs TEMPERATURE 80 4.0 V = 2.4V Positive LOGIC 60 3.5 Data = FFF Current H No Load A) 40 Limit A) 3.0 m Data = 800 m put Current ( –22000 Output tied to ISHOURCE ply Current ( 221...505 VDD = 5.0V VDD = 5.25V Out –40 Sup 1.0 Negative –60 Current 0.5 V = 4.75V Limit DD –80 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –50 –25 0 25 50 75 100 125 Output Voltage (V) Temperature (°C) MIDSCALE GLITCH PERFORMANCE MIDSCALE GLITCH PERFORMANCE LD LD mV/div) VOUT mV/div) VOUT V (10OUT V (10OUT 800 to 7FF 7FF to 800 H H H H Time (500ns/div) Time (500ns/div) LARGE-SIGNAL SETTLING TIME RISE TIME DETAIL CL = 110pF LD R = No Load L v) di V/ m V/div age (1 VOUT 1 olt V VOUT put ut O LD Time (20µs/div) Time (10µs/div) ® 7 DAC7611

TYPICAL PERFORMANCE CURVES (CONT) At TA = +25(cid:176), and VDD = 5V, unless otherwise specified. FALL TIME DETAIL OUTPUT VOLTAGE NOISE vs FREQUENCY 10.000 Data = FFF H v) di mV/ z) 1.000 1 H e ( VOUT (cid:214)V/ ut Voltag Noise (µ 0.100 p LD ut O 0.010 Time (10µs/div) 10 100 1k 10k 100k Frequency (Hz) LONG-TERM DRIFT ACCELERATED BY BURN-IN TOTAL UNADJUSTED ERROR HISTOGRAM 5 60 120 Units T.U.E = S INL = Z + FS 4 S mV) 3 50 SampleT S =iz e+ 2=5 3°C00 Units hange ( 21 min Units 40 A ge C 0 avg er of 30 a b ut Volt ––12 max Num 20 p ut –3 O 10 –4 –5 0 0 200 400 600 800 1000 1200 –12 –8 –4 0 4 8 12 Hours of Operation at +150°C FULL-SCALE VOLTAGE vs TEMPERATURE ZERO-SCALE VOLTAGE vs TEMPERATURE 4.115 3 4.110 Avg + 3s Samp Nleo S Lizoea d= 300 V) 4.105 2 put ( 4.100 mV) e Out 4.095 cale ( 1 ull-Scal 4.090 Avg Zero-S F 4.085 0 4.080 Avg – 3s 4.075 –1 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) ® DAC7611 8

TYPICAL PERFORMANCE CURVES (CONT) At TA = +25(cid:176), and VDD = 5V, unless otherwise specified. LINEARITY ERROR vs DIGITAL CODE LINEARITY ERROR vs DIGITAL CODE (at +85°C) (at +25°C) 2.0 2.0 1.5 1.5 s) 1.0 s) 1.0 B B S S L 0.5 L 0.5 or ( or ( Err 0 Err 0 y y arit –0.5 arit –0.5 e e n n Li –1.0 Li –1.0 –1.5 –1.5 –2.0 –2.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 Code Code LINEARITY ERROR vs DIGITAL CODE (at –40°C) 2.0 1.5 s) 1.0 B S L 0.5 or ( Err 0 y arit –0.5 e n Li –1.0 –1.5 –2.0 0 512 1024 1536 2048 2560 3072 3584 4096 Code ® 9 DAC7611

OPERATION clear input (CLR) is provided to simplify start-up or periodic resets. Table I shows the relationship between input code The DAC7611 is a 12-bit digital-to-analog converter (DAC) and output voltage. complete with a serial-to-parallel shift register, DAC regis- The digital data into the DAC7611 is double-buffered. This ter, laser-trimmed 12-bit DAC, on-board reference, and a means that new data can be entered into the DAC without rail-to-rail output amplifier. Figure 1 shows the basic opera- disturbing the old data and the analog output of the con- tion of the DAC7611. verter. At some point after the data has been entered into the serial shift register, this data can be transferred into the DAC INTERFACE register. This transfer is accomplished with a HIGH to LOW Figure 1 shows the basic connection between a transition of the LD pin. However, the LD pin makes the microcontroller and the DAC7611. The interface consists of DAC register transparent. If new data is shifted into the shift a serial clock (CLK), serial data (SDI), and a load strobe register while LD is LOW, the DAC output voltage will signal (LD). In addition, a chip select (CS) input is available change as each new bit is entered. To prevent this, LD must to enable serial communication when there are multiple be returned HIGH prior to shifting in new serial data. serial devices. The data format is Straight Binary and is At any time, the contents of the DAC register can be set to loaded MSB-first into the shift registers. An asynchronous 000 (analog output equals 0V) by taking the CLR input H LOW. The DAC register will remain at this value until CLR is returned HIGH and LD is taken LOW to allow the DAC7611 Full-Scale Range = 4.095V contents of the shift register to be transferred to the DAC Least Significant Bit = 1mV register. If LD is LOW when CLR is taken LOW, the DAC DIGITAL INPUT CODE ANALOG OUTPUT register will be set to 000 and the analog output driven to H STRAIGHT BINARY (V) DESCRIPTION 0V. When CLR is returned HIGH, the DAC register will be FFF +4.095 Full Scale set to the current value in the serial shift register and the H 801H +2.049 Midscale + 1 LSB analog output will respond accordingly. 800H +2.048 Midscale 7FF +2.047 Midscale – 1 LSB H 000H 0 Zero Scale DIGITAL-TO-ANALOG CONVERTER TABLE I. Digital Input Code and Corresponding Ideal The internal DAC section is a 12-bit voltage output Analog Output. device that swings between ground and the internal ref- erence voltage. The DAC is realized by a laser-trimmed +5V R-2R ladder network which is switched by N-channel MOSFETs. The DAC output is internally connected to the rail-to-rail output operational amplifier. DAC7611 0V to 10µF+ 0.1µF 1 VDD VOUT 8 +4.095V OUTPUT AMPLIFIER 2 CS GND 7 A precision, low-power amplifier buffers the output of the Serial Clock 3 CLK CLR 6 DAC section and provides additional gain to achieve a 0 to From Serial Data 4 SDI LD 5 4.095V range. The amplifier has low offset voltage, low µC noise, and a set gain of 1.682V/V (4.095/2.435). See Figure Load Strobe 2 for an equivalent circuit schematic of the analog portion of FIGURE 1. Basic Operation of the DAC7611. the DAC7611. R-2R DAC 2R Output Amplifier R Buffer 2R R2 Bandgap 2.435V Reference R R1 2R R 2R 2R FIGURE 2. Simplified Schematic of Analog Portion. ® DAC7611 10

The output amplifier has a 7m s typical settling time to – 1 The DAC7611 power supply should be bypassed as shown LSB of the final value. Note that there are differences in the in Figure 1. The bypass capacitors should be placed as close settling time for negative-going signals versus positive- to the device as possible, with the 0.1uF capacitor taking going signals. priority in this regard. The Power Supply Rejection vs The rail-to-rail output stage of the amplifier provides the Frequency graph in the Typical Performance Curves section full-scale range of 0V to 4.095V while operating on a supply shows the PSRR performance of the DAC7611. This should voltage as low as 4.75V. In addition to its ability to drive be taken into account when using switching power supplies resistive loads, the amplifier will remain stable while driving or DC/DC converters. capacitive loads of up to 500pF. See Figure 3 for an equiva- In addition to offering guaranteed performance with V in DD lent circuit schematic of the amplifier’s output driver and the the 4.75V to 5.25V range, the DAC7611 will operate with Typical Performance Curves section for more information reduced performance down to 4.5V. Operation between regarding settling time, load driving capability, and output 4.5V and 4.75V will result in longer settling time, reduced noise. performance, and current sourcing capability. Consult the V vs Load Current graph in the Typical Performance DD Curves section for more information. APPLICATIONS V DD P-Channel POWER AND GROUNDING The DAC7611 can be used in a wide variety of situations— from low power, battery operated systems to large-scale V industrial process control systems. In addition, some appli- OUT cations require better performance than others, or are par- N-Channel ticularly sensitive to one or two specific parameters. This diversity makes it difficult to define definite rules to follow concerning the power supply, bypassing, and grounding. The following discussion must be considered in relation to the desired performance and needs of the particular system. AGND A precision analog component requires careful layout, ad- equate bypassing, and a clean, well-regulated power supply. As the DAC7611 is a single-supply, +5V component, it will FIGURE 3. Simplified Driver Section of Output Amplifier. often be used in conjunction with digital logic, microcontrollers, microprocessors, and digital signal proces- sors. The more digital logic present in the design and the POWER SUPPLY higher the switching speed, the more difficult it will be to A BiCMOS process and careful design of the bipolar and achieve good performance. CMOS sections of the DAC7611 result in a very low power Because the DAC7611 has a single ground pin, all return device. Bipolar transistors are used where tight matching currents, including digital and analog return currents, must and low noise are needed to achieve analog accuracy, and flow through this pin. The GND pin is also the ground CMOS transistors are used for logic, switching functions reference point for the internal bandgap reference. Ideally, and for other low power stages. GND would be connected directly to an analog ground If power consumption is critical, it is important to keep the plane. This plane would be separate from the ground con- logic levels on the digital inputs (SDI, CLK, CS, LD, CLR) nection for the digital components until they are connected as close as possible to either V or ground. This will keep at the power entry point of the system (see Figure 4). DD the CMOS inputs (see “Supply Current vs Logic Input The power applied to V should be well regulated and low- DD Voltages” in the Typical Performance Curves) from shunt- noise. Switching power supplies and DC/DC converters will ing current between V and ground. Thus, CMOS logic often have high-frequency glitches or spikes riding on the DD levels rather than TTL logic levels, are strongly recom- output voltage. In addition, digital components can create mended for driving the DAC7611. similar high frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between V and V . DD OUT ® 11 DAC7611

As with the GND connection, V should be connected to OFFSET ERROR MEASUREMENT DD a +5V power supply plane or trace that is separate from the As with most DACs, the DAC7611 can have an offset error connection for digital logic until they are connected at the (or zero scale error) which is either negative or positive. If power entry point. In addition, the 10m F and 0.1m F capaci- the error is positive, the output voltage for an input code of tors shown in Figure 4 are strongly recommended and 000 will be greater than 0V. If the error is negative, the H should be installed as close to V and ground as possible. DD output voltage is below 0V. However, since the DAC7611 is In some situations, additional bypassing may be required a single-supply device and cannot swing below ground, the such as a 100m F electrolytic capacitor or even a “Pi” filter output voltage will be 0V, giving the impression that the made up of inductors and capacitors—all designed to essen- offset error is zero. tially lowpass filter the +5V supply, removing the high Since measuring the offset error on a DAC is such a frequency noise (see Figure 4). common task, a method is needed to reliably measure the offset error of the DAC7611. This can easily be done as shown in Figure 5. The resistor between V and a nega- OUT tive voltage provides the output amplifier some ability to swing below ground. Digital Circuits +5V Power +5V Supply +5V GND DAC7611 GND VDD + + 100µF 10µF 0.1µF GND Optional Other Analog Components FIGURE 4. Suggested Power and Ground Connections for a DAC7611 Sharing a +5V Supply with a Digital System. +5V DAC7611 + 1 VDD VOUT 8 10µF 0.1µF 2 CS GND 7 3 CLK CLR 6 R i £ 200µA 4 SDI LD 5 –V FIGURE 5. Offset Error Measurement Circuit. ® DAC7611 12

PACKAGE OPTION ADDENDUM www.ti.com 3-Jul-2009 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty DAC7611P NRND PDIP P 8 50 Green(RoHS& CUNIPDAU N/AforPkgType noSb/Br) DAC7611PB NRND PDIP P 8 50 Green(RoHS& CUNIPDAU N/AforPkgType noSb/Br) DAC7611PBG4 NRND PDIP P 8 50 Green(RoHS& CUNIPDAU N/AforPkgType noSb/Br) DAC7611PG4 NRND PDIP P 8 50 Green(RoHS& CUNIPDAU N/AforPkgType noSb/Br) DAC7611U ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7611U/2K5 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7611U/2K5G4 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7611UB ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7611UB/2K5 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7611UB/2K5G4 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7611UBG4 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) DAC7611UG4 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-3-260C-168HR noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. Addendum-Page1

PACKAGE OPTION ADDENDUM www.ti.com 3-Jul-2009 InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) DAC7611U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 DAC7611UB/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) DAC7611U/2K5 SOIC D 8 2500 346.0 346.0 29.0 DAC7611UB/2K5 SOIC D 8 2500 346.0 346.0 29.0 PackMaterials-Page2

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