DAC7512 DAC7512 DAC7512 SBAS156B – JULY 2002 Low-Power, Rail-to-Rail Output, 12-Bit Serial Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION (cid:1) microPOWER OPERATION: 135µA at 5V The DAC7512 is a low-power, single, 12-bit buffered voltage (cid:1) POWER-DOWN: 200nA at 5V, 50nA at 3V output Digital-to-Analog Converter (DAC). Its on-chip preci- (cid:1) POWER SUPPLY: +2.7V to +5.5V sion output amplifier allows rail-to-rail output swing to be achieved. The DAC7512 uses a versatile three-wire serial (cid:1) TESTED MONOTONIC BY DESIGN interface that operates at clock rates up to 30MHz and is (cid:1) POWER-ON RESET TO 0V compatible with standard SPI™, QSPI™, Microwire™, and (cid:1) THREE POWER-DOWN FUNCTIONS DSP interfaces. (cid:1) LOW POWER SERIAL INTERFACE WITH The reference for the DAC7512 is derived from the power SCHMITT-TRIGGERED INPUTS supply, resulting in the widest dynamic output range possible. (cid:1) ON-CHIP OUTPUT BUFFER AMPLIFIER, The DAC7512 incorporates a power-on reset circuit that RAIL-TO-RAIL OPERATION ensures that the DAC output powers up at 0V and remains (cid:1) SYNC INTERRUPT FACILITY there until a valid write takes place in the device. The (cid:1) SOT23-6 AND MSOP-8 PACKAGES DAC7512 contains a power-down feature, accessed over the serial interface, that can reduce the current consumption of APPLICATIONS the device to 50nA at 5V. The low power consumption of this part in normal operation (cid:1) (cid:1)PORTABLE BATTERY-POWERED makes it ideally suited to portable battery-operated equip- INSTRUMENTS ment. The power consumption is 0.7mW at 5V reducing to (cid:1) (cid:1)DIGITAL GAIN AND OFFSET 1µW in power-down mode. ADJUSTMENT The DAC7512 is available in a SOT23-6 package and an (cid:1) (cid:1)PROGRAMMABLE VOLTAGE AND MSOP-8 package. CURRENT SOURCES SPI and QSPI are registered trademarks of Motorola. Microwire is a registered trademark of National Semiconductor. VDD GND Power-On Reset RDegAiCst er REF1 (2+)- RBEitF (–) OBuutfpfeurt VOUT DAC Input Control Power-Down Resistor Logic Control Logic Network SYNCSCLK DIN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3)(cid:9)(cid:10)(cid:4)(cid:11)(cid:7)(cid:11)(cid:10)(cid:12)(cid:13)(cid:14)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:12)(cid:15)(cid:13)(cid:10)(cid:12)(cid:20)(cid:10)(cid:21)(cid:22)(cid:16)(cid:16)(cid:23)(cid:13)(cid:19)(cid:10)(cid:18)(cid:20)(cid:10)(cid:15)(cid:14)(cid:10)(cid:24)(cid:22)(cid:25)(cid:26)(cid:12)(cid:21)(cid:18)(cid:19)(cid:12)(cid:15)(cid:13)(cid:10)(cid:27)(cid:18)(cid:19)(cid:23)(cid:28) Copyright © 2002, Texas Instruments Incorporated (cid:1)(cid:16)(cid:15)(cid:27)(cid:22)(cid:21)(cid:19)(cid:20)(cid:10)(cid:21)(cid:15)(cid:13)(cid:14)(cid:15)(cid:16)(cid:17)(cid:10)(cid:19)(cid:15)(cid:10)(cid:20)(cid:24)(cid:23)(cid:21)(cid:12)(cid:14)(cid:12)(cid:21)(cid:18)(cid:19)(cid:12)(cid:15)(cid:13)(cid:20)(cid:10)(cid:24)(cid:23)(cid:16)(cid:10)(cid:19)(cid:29)(cid:23)(cid:10)(cid:19)(cid:23)(cid:16)(cid:17)(cid:20)(cid:10)(cid:15)(cid:14)(cid:10)(cid:7)(cid:23)(cid:30)(cid:18)(cid:20)(cid:10)(cid:8)(cid:13)(cid:20)(cid:19)(cid:16)(cid:22)(cid:17)(cid:23)(cid:13)(cid:19)(cid:20) (cid:20)(cid:19)(cid:18)(cid:13)(cid:27)(cid:18)(cid:16)(cid:27)(cid:10)(cid:31)(cid:18)(cid:16)(cid:16)(cid:18)(cid:13)(cid:19) (cid:28)(cid:10)(cid:1)(cid:16)(cid:15)(cid:27)(cid:22)(cid:21)(cid:19)(cid:12)(cid:15)(cid:13)(cid:10)(cid:24)(cid:16)(cid:15)(cid:21)(cid:23)(cid:20)(cid:20)(cid:12)(cid:13)!(cid:10)(cid:27)(cid:15)(cid:23)(cid:20)(cid:10)(cid:13)(cid:15)(cid:19)(cid:10)(cid:13)(cid:23)(cid:21)(cid:23)(cid:20)(cid:20)(cid:18)(cid:16)(cid:12)(cid:26) (cid:10)(cid:12)(cid:13)(cid:21)(cid:26)(cid:22)(cid:27)(cid:23) (cid:19)(cid:23)(cid:20)(cid:19)(cid:12)(cid:13)!(cid:10)(cid:15)(cid:14)(cid:10)(cid:18)(cid:26)(cid:26)(cid:10)(cid:24)(cid:18)(cid:16)(cid:18)(cid:17)(cid:23)(cid:19)(cid:23)(cid:16)(cid:20)(cid:28) www.ti.com

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC VDD to GND...........................................................................–0.3V to +6V DISCHARGE SENSITIVITY Digital Input Voltage to GND..................................–0.3V to +V + 0.3V DD V to GND...........................................................–0.3V to +V + 0.3V OUT DD Operating Temperature Range.....................................–40°C to +105°C This integrated circuit can be damaged by ESD. Texas Instru- Storage Temperature Range.........................................–65°C to +150°C ments recommends that all integrated circuits be handled with Junction Temperature Range (T max).........................................+150°C J appropriate precautions. Failure to observe proper handling SOT23 Package: Power Dissipation..................................................(T max — T )/(cid:1) and installation procedures can cause damage. J A JA (cid:1) Thermal Impedance.........................................................240°C/W JA ESD damage can range from subtle performance degradation Lead Temperature, Soldering: Vapor Phase (60s)...............................................................+215°C to complete device failure. Precision integrated circuits may be Infrared (15s)........................................................................+220°C more susceptible to damage because very small parametric MSOP Package: Power Dissipation........................................................(T max — T )/(cid:1) changes could cause the device not to meet its published J A JA (cid:1) Thermal Impedance.........................................................206°C/W specifications. JA (cid:1) Thermal Impedance...........................................................44°C/W JC Lead Temperature, Soldering: Vapor Phase (60s)...............................................................+215°C Infrared (15s)........................................................................+220°C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION MINIMUM RELATIVE DIFFERENTIAL SPECIFIED ACCURACY NONLINEARITY PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT (LSB) (LSB) PACKAGE-LEAD DESIGNATOR(1) RANGE MARKING NUMBER(1) MEDIA, QUANTITY DAC7512E ±8 ±1 MSOP-8 DGK –40°C to +105°C D12E DAC7512E/250 Tape and Reel, 250 " " " " " " " DAC7512E/2K5 Tape and Reel, 2500 DAC7512N ±8 ±1 SOT23-6 DBV –40°C to +105°C D12N DAC7512N/250 Tape and Reel, 250 " " " " " " " DAC7512N/3K Tape and Reel, 3000 NOTES: (1) For the most current specifications and package information, refer to our web site at www.ti.com. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC7512E/2K5” will get a single 2500-piece Tape and Reel. PIN CONFIGURATIONS PIN DESCRIPTION (SOT23-6) Top View SOT23-6 PIN NAME DESCRIPTION 1 V Analog output voltage from DAC. The output ampli- OUT VOUT 1 6 SYNC fier has rail-to-rail operation. GND 2 DAC7512 5 SCLK 2 GND Ground reference point for all circuitry on the part. 3 V Power Supply Input, +2.7V to 5.5V. V 3 4 D DD DD IN 4 D Serial Data Input. Data is clocked into the 16-bit IN input shift register on the falling edge of the serial clock input. MSOP-8 5 SCLK Serial Clock Input. Data can be transferred at rates up to 30MHz. VDD 1 8 GND 6 SYNC Level triggered control input (active LOW). This is the frame sychronization signal for the input data. NC 2 7 D IN When SYNC goes LOW, it enables the input shift DAC7512 NC 3 6 SCLK register and data is transferred in on the falling edges of the following clocks. The DAC is updated V 4 5 SYNC following the 16th clock cycle unless SYNC is taken OUT HIGH before this edge, in which case the rising edge of SYNC acts as an interrupt and the write NC = No Internal Connection sequence is ignored by the DAC7512. DAC7512N LOT TRACE LOCATION Top View Bottom View Pin 1 D12N YMLL Lot Trace Code Pin 1 DAC7512 2 www.ti.com SBAS156B

ELECTRICAL CHARACTERISTICS V = +2.7V to +5.5V; R = 2ký to GND; C = 200pF to GND. DD L L DAC7512E, N PARAMETER CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 12 Bits Relative Accuracy ±8 LSB Differential Nonlinearity Tested Monotonic by Design ±1 LSB Zero Code Error All Zeroes Loaded to DAC Register +5 +20 mV Full-Scale Error All Ones Loaded to DAC Register –0.15 –1.25 % of FSR Gain Error ±1.25 % of FSR Zero Code Error Drift –20 µV/°C Gain Temperature Coefficient –5 ppm of FSR/°C OUTPUT CHARACTERISTICS (2) Output Voltage Range 0 V V DD Output Voltage Settling Time 1/4 Scale to 3/4 Scale Change (400 to C00 ) 8 10 µs H H R = 2kΩ; 0pF < C < 200pF L L R = 2kΩ; C = 500pF 12 µs L L Slew Rate 1 V/µs Capacitive Load Stability R = × 470 pF L R = 2kΩ 1000 pF L Code Change Glitch Impulse 1LSB Change Around Major Carry 20 nV-s Digital Feedthrough 0.5 nV-s DC Output Impedance 1 Ω Short-Circuit Current V = +5V 50 mA DD V = +3V 20 mA DD Power-Up Time Coming Out of Power-Down Mode V = +5V 2.5 µs DD Coming Out of Power-Down Mode V = +3V 5 µs DD LOGIC INPUTS (2) Input Current ±1 µA V L, Input Low Voltage V = +5V 0.8 V IN DD V L, Input Low Voltage V = +3V 0.6 V IN DD V H, Input High Voltage V = +5V 2.4 V IN DD V H, Input High Voltage V = +3V 2.1 V IN DD Pin Capacitance 3 pF POWER REQUIREMENTS V 2.7 5.5 V DD I (normal mode) DAC Active and Excluding Load Current DD V = +3.6V to +5.5V V = V and V = GND 135 200 µA DD IH DD IL V = +2.7V to +3.6V V = V and V = GND 115 160 µA DD IH DD IL I (all power-down modes) DD V = +3.6V to +5.5V V = V and V = GND 0.2 1 µA DD IH DD IL V = +2.7V to +3.6V V = V and V = GND 0.05 1 µA DD IH DD IL POWER EFFICIENCY I /I I = 2mA. V = +5V 93 % OUT DD LOAD DD TEMPERATURE RANGE Specified Performance –40 +105 °C NOTES: (1) Linearity calculated using a reduced code range of 48 to 4047; output unloaded. (2) Guaranteed by design and characterization, not production tested. DAC7512 3 SBAS156B www.ti.com

TIMING CHARACTERISTICS(1, 2) V = +2.7V to +5.5V; all specifications –40°C to +105°C, unless otherwise noted. DD DAC7512E, N PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNITS t(3) SCLK Cycle Time 1 V = 2.7V to 3.6V 50 ns DD V = 3.6V to 5.5V 33 ns DD t SCLK HIGH Time 2 V = 2.7V to 3.6V 13 ns DD V = 3.6V to 5.5V 13 ns DD t SCLK LOW Time 3 V = 2.7V to 3.6V 22.5 ns DD V = 3.6V to 5.5V 13 ns DD t SYNC to SCLK Rising 4 Edge Setup Time V = 2.7V to 3.6V 0 ns DD V = 3.6V to 5.5V 0 ns DD t Data Setup Time 5 V = 2.7V to 3.6V 5 ns DD V = 3.6V to 5.5V 5 ns DD t Data Hold Time 6 V = 2.7V to 3.6V 4.5 ns DD V = 3.6V to 5.5V 4.5 ns DD t SCLK Falling Edge to 7 SYNC Rising Edge V = 2.7V to 3.6V 0 ns DD V = 3.6V to 5.5V 0 ns DD t Minimum SYNC HIGH Time 8 V = 2.7V to 3.6V 50 ns DD V = 3.6V to 5.5V 33 ns DD NOTES: (1) All input signals are specified with t = t = 5ns (10% to 90% of V ) and timed from a voltage level of (V + V )/2. (2) See Serial Write Operation timing R F DD IL IH diagram, below. (3) Maximum SCLK frequency is 30MHz at V = +3.6V to +5.5V and 20MHz at V = +2.7V to +3.6V. DD DD SERIAL WRITE OPERATION t 1 SCLK t t 8 t t3 2 t7 4 SYNC t 6 t 5 D DB15 DB0 IN DAC7512 4 www.ti.com SBAS156B

TYPICAL CHARACTERISTICS: V = +5V DD At T = +25°C, +V = +5V, unless otherwise noted. A DD LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) (+25°C) 16.0 16.0 12.0 12.0 8.0 8.0 B) 4.0 B) 4.0 S S L 0.0 L 0.0 E ( –4.0 E ( –4.0 L –8.0 L –8.0 –12.0 –12.0 –16.0 –16.0 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0.0 E (L 0.0 L L D –0.5 D –0.5 –1.0 –1.0 0 200 400 600 800 A00 C00 E00 FFF 0 200 400 600 800 A00 C00 E00 FFF H H H H H H H H H H H H H H H H CODE CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+105°C) TYPICAL TOTAL UNADJUSTED ERROR 16.0 16 12.0 8.0 B) 4.0 S E (L –04..00 8 L –8.0 –12.0 s) –16.0 B LS 0 1.0 E ( U B) 0.5 T S –8 E (L 0.0 L D –0.5 –1.0 –16 0 200H 400H 600H 800H A00H C00H E00H FFFH 0 200H 400H 600H 800H A00H C00H E00H FFFH CODE CODE ZERO-SCALE ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 30 30 20 20 10 10 V) V) m m or ( 0 or ( 0 Err Err –10 –10 –20 –20 –30 –30 –40 0 40 80 120 –40 0 40 80 120 Temperature (°C) Temperature (°C) DAC7512 5 SBAS156B www.ti.com

TYPICAL CHARACTERISTICS: V = +5V (Cont.) DD At T = +25°C, +V = +5V, unless otherwise noted. A DD I HISTOGRAM SOURCE AND SINK CURRENT CAPABILITY DD 3000 5 2500 DAC Loaded with FFFH 4 2000 y 3 nc V) ue 1500 (T q U Fre VO 2 1000 1 500 DAC Loaded with 000 H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 10 15 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 I (µA) ISOURCE/SINK (mA) DD SUPPLY CURRENT vs CODE SUPPLY CURRENT vs TEMPERATURE 500 300 250 400 200 300 A) A) µI (DD 200 µI(DD 150 100 100 50 0 0 0 200 400 600 800 A00 C00 E00 FFF –40 0 40 80 120 H H H H H H H H CODE Temperature (°C) SUPPLY CURRENT vs SUPPLY VOLTAGE POWER-DOWN CURRENT vs SUPPLY VOLTAGE 300 100 90 250 80 70 200 60 +105°C µ(A)DD 150 (nA)DD 5400 –40°C I I 100 30 20 50 10 +25°C 0 0 2.7 3.2 3.7 4.2 4.7 5.2 5.7 2.7 3.2 3.7 4.2 4.7 5.2 5.7 VDD (V) VDD (V) DAC7512 6 www.ti.com SBAS156B

TYPICAL CHARACTERISTICS: V = +5V (Cont.) DD At T = +25°C, +V = +5V, unless otherwise noted. A DD SUPPLY CURRENT vs LOGIC INPUT VOLTAGE FULL-SCALE SETTLING TIME 2500 CLK (5V/div) 2000 1500 A) VOUT (1V/div) µ (D D 1000 I Full-Scale Code Change 500 000H to FFFH Output Loaded with 2kΩ and 200pF to GND 0 0 1 2 3 4 5 Time (1µs/div) V (V) LOGIC FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME CLK (5V/div) CLK (5V/div) V (1V/div) OUT Full-Scale Code Change Half-Scale Code Change FFFH to 000H 400H to C00H Output Loaded with Output Loaded with 2kΩ and 200pF to GND V (1V/div) 2kΩ and 200pF to GND OUT Time (1µs/div) Time (1µs/div) HALF-SCALE SETTLING TIME POWER-ON RESET TO 0V CLK (5V/div) Half-Scale Code Change Loaded with 2kΩ to VDD. C00 to 400 H H Output Loaded with 2kΩ and 200pF to GND V (1V/div) DD V (1V/div) OUT V (1V/div) OUT Time (1µs/div) Time (20µs/div) DAC7512 7 SBAS156B www.ti.com

TYPICAL CHARACTERISTICS: V = +5V (Cont.) DD At T = +25°C, +V = +5V, unless otherwise noted. A DD EXITING POWER-DOWN (800H Loaded) CODE CHANGE GLITCH CLK (5V/div) Loaded with 2kΩ and 200pF to GND. Code Change: 800 to 7FF . H H v) di V/ m 0 2 (T U O V V (1V/div) OUT Time (5µs/div) Time (0.5µs/div) TYPICAL CHARACTERISTICS: V = +2.7V DD At T = +25°C, +V = +2.7V, unless otherwise noted. A DD LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) (+25°C) 16.0 16.0 12.0 12.0 8.0 8.0 E (LSB) –404...000 E (LSB) –404...000 L –8.0 L –8.0 –12.0 –12.0 –16.0 –16.0 1.0 1.0 B) 0.5 B) 0.5 S S E (L 0.0 E (L 0.0 DL –0.5 DL –0.5 –1.0 –1.0 0 200H 400H 600H 800H A00H C00H E00H FFFH 0 200H 400H 600H 800H A00H C00H E00H FFFH CODE CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+105°C) TYPICAL TOTAL UNADJUSTED ERROR 16 16 12 8 B) 4 S L 0 8 E ( –4 L –8 –12 s) –16 LSB 0 1.0 E ( U T B) 0.5 S –8 E (L 0 L D –0.5 –1.0 –16 000H 200H 400H 600H 800H A00H C00H E00H FFFH 0 200H 400H 600H 800H A00H C00H E00H FFFH CODE CODE DAC7512 8 www.ti.com SBAS156B

TYPICAL CHARACTERISTICS: V = +2.7V (Cont.) DD At T = +25°C, +V = +2.7V, unless otherwise noted. A DD ZERO-SCALE ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 30 30 20 20 10 10 V) V) m m or ( 0 or ( 0 Err Err –10 –10 –20 –20 –30 –30 –40 0 40 80 120 –40 0 40 80 120 Temperature (°C) Temperature (°C) I HISTOGRAM SOURCE AND SINK CURRENT CAPABILITY DD 3000 3 V tied to V . V = +3V REF DD DD 2500 DAC Loaded with FFF H 2000 2 y nc V) que 1500 (UT e O Fr V 1000 1 DAC Loaded with 000 500 H 0 0 50 60 70 80 90 00 10 20 30 40 50 60 70 80 90 0 5 10 15 1 1 1 1 1 1 1 1 1 1 I (µA) ISOURCE/SINK (mA) DD SUPPLY CURRENT vs CODE SUPPLY CURRENT vs TEMPERATURE 500 300 250 400 200 300 A) A) µI (DD 200 µI(DD 150 100 100 50 0 0 0 200 400 600 800 A00 C00 E00 FFF –40 0 40 80 120 H H H H H H H H CODE Temperature (°C) DAC7512 9 SBAS156B www.ti.com

TYPICAL CHARACTERISTICS: V = +2.7V (Cont.) DD At T = +25°C, +V = +2.7V, unless otherwise noted. A DD SUPPLY CURRENT vs LOGIC INPUT VOLTAGE FULL-SCALE SETTLING TIME 2500 CLK (2.7V/div) 2000 1500 A) µ (D D 1000 I Full-Scale Code Change 500 000 to FFF H H Output Loaded with V (1V/div) 2kΩ and 200pF to GND 0 OUT 0 1 2 3 4 5 Time (1µs/div) V (V) LOGIC FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME CLK (2.7V/div) CLK (2.7V/div) Full-Scale Code Change V (1V/div) OUT FFF to 000 H H Output Loaded with Half-Scale Code Change 2kΩ and 200pF to GND 400H to C00H Output Loaded with V (1V/div) OUT 2kΩ and 200pF to GND Time (1µs/div) Time (1µs/div) HALF-SCALE SETTLING TIME POWER-ON RESET to 0V CLK (2.7V/div) Half-Scale Code Change C00 to 400 H H Output Loaded with 2kΩ and 200pF to GND V (1V/div) OUT Time (1µs/div) Time (20µs/div) DAC7512 10 www.ti.com SBAS156B

TYPICAL CHARACTERISTICS: V = +2.7V (Cont.) DD At T = +25°C, +V = +2.7V, unless otherwise noted. A DD EXITING POWER-DOWN (800 Loaded) CODE CHANGE GLITCH H Loaded with 2kΩ CLK (2.7V/div) and 200pF to GND. Code Change: 800 to 7FF . H H v) di V/ m 0 2 (T U VOUT (1V/div) VO Time (5µs/div) Time (0.5µs/div) THEORY OF OPERATION DAC SECTION R The DAC7512 is fabricated using a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Since there is no reference input pin, the power supply (V ) acts as the reference. Figure 1 shows a R DD block diagram of the DAC architecture. VDD R To Output Amplifier REF (+) DAC Register RSetsriisntgor VOUT REF(–) Output Amplifier GND FIGURE 1. DAC7512 Architecture. R The input coding to the DAC7512 is straight binary, so the ideal output voltage is given by: V = V • D R OUT DD 4096 where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 4095. FIGURE 2. Resistor String. RESISTOR STRING OUTPUT AMPLIFIER The resistor string section is shown in Figure 2. It is simply a string of resistors, each of value R. The code loaded into The output buffer amplifier is capable of generating rail-to- the DAC register determines at which node on the string the rail voltages on its output which gives an output range of voltage is tapped off to be fed into the output amplifier by 0V to V . It is capable of driving a load of 2kΩ in parallel DD closing one of the switches connecting the string to the with 1000pF to GND. The source and sink capabilities of the amplifier. It is tested monotonic because it is a string of output amplifier can be seen in the typical characteristics. resistors. The slew rate is 1V/µs with a half-scale settling time of 8µs with the output unloaded. DAC7512 11 SBAS156B www.ti.com

SERIAL INTERFACE write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC The DAC7512 has a three-wire serial interface (SYNC, register contents or a change in the operating mode occurs, SCLK, and DIN), which is compatible with SPI, QSPI, and as shown in Figure 4. Microwire interface standards as well as most Digital Signal Processors (DSPs). See the Serial Write Operation timing POWER-ON RESET diagram for an example of a typical write sequence. The DAC7512 contains a power-on reset circuit that controls The write sequence begins by bringing the SYNC line LOW. the output voltage during power-up. On power-up, the DAC Data from the D line is clocked into the 16-bit shift register IN register is filled with zeros and the output voltage is 0V; it on the falling edge of SCLK. The serial clock frequency can remains there until a valid write sequence is made to the be as high as 30MHz, making the DAC7512 compatible with DAC. This is useful in applications where it is important to high-speed DSPs. On the 16th falling edge of the serial know the state of the output of the DAC while it is in the clock, the last data bit is clocked in and the programmed process of powering up. function is executed (i.e., a change in DAC register contents and/or a change in the mode of operation). POWER-DOWN MODES At this point, the SYNC line may be kept LOW or brought HIGH. In either case, it must be brought HIGH for a minimum The DAC7512 contains four separate modes of operation. of 33ns before the next write sequence so that a falling edge These modes are programmable by setting two bits (PD1 of SYNC can initiate the next write sequence. Since the and PD0) in the control register. Table I shows how the state SYNC buffer draws more current when the SYNC signal is of the bits corresponds to the mode of operation of the HIGH than it does when it is LOW, SYNC should be idled device. LOW between write sequences for lowest power operation of the part. As mentioned above, however, it must be brought DB13 DB12 OPERATING MODE HIGH again just before the next write sequence. 0 0 Normal Operation Power-Down Modes: INPUT SHIFT REGISTER 0 1 Output 1kΩ to GND 1 0 Output 100kΩ to GND The input shift register is 16 bits wide, as shown in Figure 3. 1 1 High-Z The first two bits are “don’t cares”. The next two bits (PD1 and PD0) are control bits that control which mode of opera- TABLE I. Modes of Operation for the DAC7512. tion the part is in (normal mode or one of three power-down modes). There is a more complete description of the various When both bits are set to 0, the part works normally with its modes in the Power-Down Modes section. The next 12 bits normal power consumption of 135µA at 5V. However, for the are the data bits. These are transferred to the DAC register three power-down modes, the supply current falls to 200nA on the 16th falling edge of SCLK. at 5V (50nA at 3V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has SYNC INTERRUPT the advantage that the output impedance of the part is known In a normal write sequence, the SYNC line is kept LOW for while the part is in power-down mode. There are three at least 16 falling edges of SCLK and the DAC is updated on different options. The output is connected internally to GND the 16th falling edge. However, if SYNC is brought HIGH through a 1kΩ resistor, a 100kΩ resistor, or it is left open- before the 16th falling edge, this acts as an interrupt to the circuited (High-Z). See Figure 5 for the output stage. DB15 DB0 X X PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FIGURE 3. Data Input Register. CLK SYNC DIN DB15 DB0 DB15 DB0 Invalid Write Sequence: Valid Write Sequence: Output Updates SYNC HIGH before 16th Falling Edge on the 16th Falling Edge FIGURE 4. SYNC Interrupt Facility. DAC7512 12 www.ti.com SBAS156B

Amplifier MicrowireTM DAC7513(1) Resistor CS SYNC V String DAC OUT SK SCLK SO D IN NOTE: (1) Additional pins omitted for clarity. Power-down Resistor Microwire is a registered trademark of National Semiconductor. Circuitry Network FIGURE 7. DAC7512 to Microwire Interface. DAC7512 TO 68HC11 INTERFACE FIGURE 5. Output Stage During Power-Down. Figure 8 shows a serial interface between the DAC7512 and the 68HC11 microcontroller. SCK of the 68HC11 drives the All linear circuitry is shut down when the power-down mode SCLK of the DAC7512, while the MOSI output drives the is activated. However, the contents of the DAC register are serial data line of the DAC. The SYNC signal is derived from unaffected when in power-down. The time to exit power- a port line (PC7), similar to what was done for the 8051. down is typically 2.5µs for V = 5V and 5µs for V = 3V. DD DD See the Typical Characteristics for more information. MICROPROCESSOR 68HC11(1) DAC7513(1) INTERFACING PC7 SYNC DAC7512 TO 8051 INTERFACE SCK SCLK Figure 6 shows a serial interface between the DAC7512 and MOSI DIN a typical 8051-type microcontroller. The setup for the inter- NOTE: (1) Additional pins omitted for clarity. face is as follows: TXD of the 8051 drives SCLK of the DAC7512, while RXD drives the serial data line of the part. The SYNC signal is derived from a bit programmable pin on FIGURE 8. DAC7512 to 68HC11 Interface. the port. In this case, port line P3.3 is used. When data is to be transmitted to the DAC7512, P3.3 is taken LOW. The The 68HC11 should be configured so that its CPOL bit is a 8051 transmits data only in 8-bit bytes; thus only eight falling 0 and its CPHA bit is a 1. This configuration causes data clock edges occur in the transmit cycle. To load data to the appearing on the MOSI output is valid on the falling edge of DAC, P3.3 is left LOW after the first eight bits are transmitted, SCK. When data is being transmitted to the DAC, the SYNC and a second write cycle is initiated to transmit the second line is taken LOW (PC7). Serial data from the 68HC11 is byte of data. P3.3 is taken HIGH following the completion of transmitted in 8-bit bytes with only eight falling clock edges this cycle. The 8051 outputs the serial data in a format which occurring in the transmit cycle. Data is transmitted MSB first. has the LSB first. The DAC7512 requires its data with the In order to load data to the DAC7512, PC7 is left LOW after MSB as the first bit received. The 8051 transmit routine must the first eight bits are transferred, and a second serial write therefore take this into account, and “mirror” the data as operation is performed to the DAC and PC7 is taken HIGH needed. at the end of this procedure. APPLICATIONS 80C51/80L51(1) DAC7512(1) P3.3 SYNC USING REF02 AS A POWER TXD SCLK SUPPLY FOR THE DAC7512 RXD DIN Due to the extremely low supply current required by the DAC7512, an alternative option is to use a REF02 +5V NOTE: (1) Additional pins omitted for clarity. precision voltage reference to supply the required voltage to the part, see Figure 9. This is especially useful if the power FIGURE 6. DAC7512 to 80C51/80L51 Interface. supply is too noisy or if the system supply voltages are at DAC7512 TO MICROWIRE™ INTERFACE some value other than 5V. The REF02 will output a steady supply voltage for the DAC7512. If the REF02 is used, the Figure 7 shows an interface between the DAC7512 and any current it needs to supply to the DAC7512 is 135µA. This is Microwire compatible device. Serial data is shifted out on the with no load on the output of the DAC. When the DAC output falling edge of the serial clock and is clocked into the DAC7512 on the rising edge of the SK signal. DAC7512 13 SBAS156B www.ti.com

This is an output voltage range of ±5V with 000 correspond- +15 H ing to a –5V output and FFF corresponding to a +5V output. H +5V LAYOUT REF02 135µA A precision analog component requires careful layout, ad- equate bypassing, and clean, well-regulated power supplies. As the DAC7512 offers single-supply operation, it will often SYNC be used in close proximity with digital logic, microcontrollers, Three-Wire V = 0V to 5V Serial SCLK DAC7512 OUT microprocessors, and digital signal processors. The more Interface digital logic present in the design and the higher the switch- D IN ing speed, the more difficult it will be to achieve good performance from the converter. Due to the single ground pin of the DAC7512, all return FIGURE 9. REF02 as Power Supply to DAC7512. currents, including digital and analog return currents, must flow through the GND pin. Ideally, GND would be connected is loaded, the REF02 also needs to supply the current to the directly to an analog ground plane. This plane would be load. The total current required (with a 5kΩ load on the DAC separate from the ground connection for the digital compo- output) is: nents until they were connected at the power entry point of 135µA + (5V/5kΩ) = 1.14mA the system. The load regulation of the REF02 is typically 0.005%/mA, The power applied to V should be well regulated and low DD which results in an error of 285µV for the 1.14mA current noise. Switching power supplies and DC/DC converters will drawn from it. This corresponds to a 0.2LSB error. often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create BIPOLAR OPERATION USING THE DAC7512 similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output The DAC7512 has been designed for single-supply operation voltage through various paths between the power connec- but a bipolar output range is also possible using the circuit in tions and analog output. This is particularly true for the Figure 10. The circuit shown will give an output voltage range DAC7512, as the power supply is also the reference voltage of ±5V. Rail-to-rail operation at the amplifier output is achiev- for the DAC. able using an OPA340 as the output amplifier. As with the GND connection, V should be connected to a The output voltage for any input code can be calculated as DD +5V power supply plane or trace that is separate from the follows: connection for digital logic until they are connected at the VO = V • 40D96 • R1R+R2 –VDD• RR2  pbyopwaesrs ecnatrpya cpitooinrst. aIrne asdtrdointiognly, rtehceo m1µmFe ntod e1d0.µ IFn saonmd e0 .s1iµtuF- 1 1 ations, additional bypassing may be required, such as a where D represents the input code in decimal (0 - 4095). 100µF electrolytic capacitor or even a “Pi” filter made up of With V = 5V, R = R = 10kΩ: inductors and capacitors—all designed to essentially low- DD 1 2 pass filter the +5V supply, removing the high-frequency noise.  10•D V = –5V O  4096 R 2 5V 10kΩ +5V R 1 10kΩ OPA703 –5V VDD DAC7512 VOUT 10F 0.1F —5V Three-Wire Serial Interface FIGURE 10. Bipolar Operation with the DAC7512. DAC7512 14 www.ti.com SBAS156B

PACKAGE DRAWINGS MPDS028B – JUNE 1997 – REVISED SEPTEMBER 2001 DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,65 0,08 M 0,25 8 5 0,15 NOM 3,05 4,98 2,95 4,78 Gage Plane 0,25 1 4 0°–6° 0,69 3,05 0,41 2,95 Seating Plane 0,15 1,07 MAX 0,10 0,05 4073329/C 08/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. Falls within JEDEC MO-187 DAC7512 15 SBAS156B www.ti.com

PACKAGE DRAWINGS (Cont.) MPDS026D FEBRUARY 1997 REVISED FEBRUARY 2002 DBV (R-PDSO-G6) PLASTIC SMALL-OUTLINE 0,50 0,95 6X 0,20 M 0,25 6 4 0,15 NOM 1,70 3,00 1,50 2,60 1 3 Gage Plane 3,00 2,80 0,25 0°8° 0,55 0,35 Seating Plane 1,45 0,05 MIN 0,10 0,95 4073253-5/G 01/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation. DAC7512 16 www.ti.com SBAS156B

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) DAC7512E/250 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 105 D12E & no Sb/Br) DAC7512E/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 105 D12E & no Sb/Br) DAC7512E/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 105 D12E & no Sb/Br) DAC7512N/250 ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 D12N & no Sb/Br) DAC7512N/250G4 ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 D12N & no Sb/Br) DAC7512N/3K ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 D12N & no Sb/Br) DAC7512N/3KG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 D12N & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) DAC7512E/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC7512E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC7512N/250 SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 DAC7512N/3K SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) DAC7512E/250 VSSOP DGK 8 250 210.0 185.0 35.0 DAC7512E/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 DAC7512N/250 SOT-23 DBV 6 250 180.0 180.0 18.0 DAC7512N/3K SOT-23 DBV 6 3000 180.0 180.0 18.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0006A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 B A 1.45 MAX PIN 1 INDEX AREA 1 6 2X 0.95 3.05 2.75 1.9 5 2 4 3 0.50 6X 0.25 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214840/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178. www.ti.com

EXAMPLE BOARD LAYOUT DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214840/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214840/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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