DAC5574 www.ti.com SLAS407–DECEMBER2003 QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, 2 I C INTERFACE DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • MicropowerOperation:500µAat3VV DD The DAC5574 is a low-power, quad channel, 8-bit • FastUpdateRate:188kSPS buffered voltage output DAC. Its on-chip precision • Per-channelPower-downCapability output amplifier allows rail-to-rail output swing to be achieved. The DAC5574 utilizes an I2C compatible • Power-OnResettoZero two wire serial interface supporting high-speed • 2.7-Vto5.5-VAnalogPowerSupply interface mode with address support of up to four • 8-bitMonotonic DAC5574sforatotalof16channelsonthebus. • I2C™InterfaceUpto3.4Mbps The DAC5574 uses V and GND to set the output DD • DataTransmitCapability range of the DAC. The DAC5574 incorporates a • On-ChipOutputBufferAmplifier,Rail-to-Rail power-on-reset circuit that ensures that the DAC Operation outputpowersupatzerovoltsandremainsthere until • Double-BufferedInputRegister a valid write takes place to the device. The DAC5574 contains a per-channel power-down feature, ac- • AddressSupportforuptoFourDAC5574s cessed via the internal control register, reducing the • SynchronousUpdateSupportforupto16 currentconsumptionofthedeviceto200nAat5V. Channels The low power consumption of this part in normal • OperationFrom–40(cid:176) Cto105(cid:176) C operation makes it ideally suited to portable battery • Small10LeadMSOPPackage operated equipment. The power consumption is less than 3mW at V = 5 V reducing to 1 µW in DD APPLICATIONS power-downmode. • ProcessControl TI offers a variety of data converters with I2C • DataAcquisitionSystems interface. See DACx57x family of 16/12/10/8 bit, • Closed-LoopServoControl single and quad channel DACs. Also see ADS7823 • PCPeripherals and ADS1100, 12-bit octal channel and 16-bit single channelADCs. • PortableInstrumentation VDD Data DAC DAC A VOUTA Buffer A Register A VOUTB VOUTC Data DAC Buffer D Register D DAC D VOUTD 14 SCL I2C Power-Down Block Buffer Register Control Logic Control Control SDA Resistor 8 Network A0 A1 GND Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. I2CisatrademarkofPhilipsCorporation. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2003,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

DAC5574 www.ti.com SLAS407–DECEMBER2003 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedurescancausedamage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could causethedevicenottomeetitspublishedspecifications. PACKAGE/ORDERINGINFORMATION(1) PRODUCT PACKAGE PACKAGE SPECIFICATION PACKAGE ORDERING TRANSPORTMEDIA DRAWING TEMPERATURE MARKING NUMBER NUMBER RANGE DAC5574 10-MSOP DGS –40(cid:176)C TO+105(cid:176)C D574 DAC5574IDGS 80PieceTube DAC5574IDGSR 2500PieceTapeandReel (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. DGSPACKAGE PINDESCRIPTIONS (TOPVIEW) PIN NAME DESCRIPTION VOUTA 1 10 A1 1 VOUTA AnalogoutputvoltagefromDACA V B 2 9 A0 2 VOUTB AnalogoutputvoltagefromDACB OUT Groundreferencepointforallcircuitryonthe GND 3 DAC5574 8 VDD 3 GND part VOUTC 4 7 SDA 4 VOUTC AnalogoutputvoltagefromDACC VOUTD 5 6 SCL 5 VOUTD AnalogoutputvoltagefromDACD 6 SCL Serialclockinput 7 SDA Serialdatainputandoutput 8 V Analogvoltagesupplyinput DD 9 A0 Deviceaddressselect-I2C 10 A1 Deviceaddressselect-I2C . ABSOLUTE MAXIMUM RATINGS(1) V toGND –0.3Vto+6V DD DigitalinputvoltagetoGND –0.3VtoV +0.3V DD V toGND –0.3VtoV +0.3V OUT DD Operatingtemperaturerange –40(cid:176)C to+105(cid:176)C Storagetemperaturerange –65(cid:176)C to+150(cid:176)C Junctiontemperaturerange(T max) +150(cid:176)C J Powerdissipation: Thermalimpedance(QJA) 270(cid:176)C/W Thermalimpedance(QJC) 77(cid:176)C/W Leadtemperature,soldering: Vaporphase(60s) 215(cid:176)C Infrared(15s) 220(cid:176)C (1) StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Exposuretoabsolute maximumconditionsforextendedperiodsmayaffectdevicereliability. 2

DAC5574 www.ti.com SLAS407–DECEMBER2003 ELECTRICAL CHARACTERISTICS V =2.7Vto5.5V,R =2kW toGND;C =200pFtoGND;allspecifications–40(cid:176) Cto+105(cid:176) C,unlessotherwisespecified. DD L L PARAMETER TESTCONDITIONS MIN TYP MAX UNITS STATICPERFORMANCE(1) Resolution 8 Bits Relativeaccuracy – 0.15 – 0.5 LSB Differentialnonlinearity Specifiedmonotonicbydesign – 0.02 – 0.25 LSB Zero-scaleerror 5 20 mV Full-scaleerror -0.15 – 1.0 %ofFSR Gainerror – 1.0 %ofFSR Zerocodeerrordrift – 7 µV/(cid:176)C Gaintemperaturecoefficient – 3 ppmof FSR/(cid:176)C OUTPUTCHARACTERISTICS(2) Outputvoltagerange 0 V V DD Outputvoltagesettlingtime(fullscale) R =¥ ;0pF<C <200pF 6 8 µs L L R =¥ ;C =500pF 12 µs L L Slewrate 1 V/µs dccrosstalk(channel-to-channel) 0.0025 LSB accrosstalk(channel-to-channel) 1kHzSineWave -100 dB Capacitiveloadstability R =¥ 470 pF L R =2kW 1000 pF L Digital-to-analogglitchimpulse 1LSBchangearoundmajorcarry 12 nV-s Digitalfeedthrough 0.3 nV-s dcoutputimpedance 1 W Short-circuitcurrent V =5V 50 mA DD V =3V 20 mA DD Power-uptime Comingoutofpower-downmode, 2.5 µs V =+5V DD Comingoutofpower-downmode, 5 µs V =+3V DD LOGICINPUTS (2) Inputcurrent – 1 µA V ,Inputlowvoltage 0.3xV V IN_L DD V ,Inputhighvoltage V =3V 0.7xV V IN_H DD DD PinCapacitance 3 pF POWERREQUIREMENTS V 2.7 5.5 V DD I (normaloperation),includingreferencecurrent Excludingloadcurrent DD I @V =+3.6Vto+5.5V V =V andV =GND 600 900 µA DD DD IH DD IL I @V =+2.7Vto+3.6V V =V andV =GND 500 750 µA DD DD IH DD IL I (allpower-downmodes) DD I @V =+3.6Vto+5.5V V =V andV =GND 0.2 1 µA DD DD IH DD IL I @V =+2.7Vto+3.6V V =V andV =GND 0.05 1 µA DD DD IH DD IL POWEREFFICIENCY I /I I =2mA,V =+5V 93% OUT DD LOAD DD TEMPERATURERANGE Specifiedperformance -40 +105 (cid:176)C (1) Linearitytestedusingareducedcoderangeof48to4047;outputunloaded. (2) Specifiedbydesignandcharacterization,notproductiontested. 3

DAC5574 www.ti.com SLAS407–DECEMBER2003 TIMING CHARACTERISTICS V =2.7Vto5.5V,R =2kW toGND;allspecifications–40(cid:176) Cto+105(cid:176) C,unlessotherwisespecified. DD L SYMBOL PARAMETER TESTCONDITIONS MIN TYP MAX UNITS Standardmode 100 kHz Fastmode 400 kHz f SCLclockfrequency SCL High-SpeedMode,C =100pFmax 3.4 MHz B High-speedmode,C =400pFmax 1.7 MHz B Busfreetimebetweena Standardmode 4.7 µs t BUF STOPandSTARTcondition Fastmode 1.3 µs Standardmode 4.0 µs Holdtime(repeated)START t ;t Fastmode 600 ns HD STA condition High-speedmode 160 ns Standardmode 4.7 µs Fastmode 1.3 µs t LOWperiodoftheSCLclock LOW High-speedmode,C =100pFmax 160 ns B High-speedmode,C =400pFmax 320 ns B Standardmode 4.0 µs Fastmode 600 ns t HIGHperiodoftheSCLclock HIGH High-SpeedMode,C =100pFmax 60 ns B High-speedmode,C =400pFmax 120 ns B Standardmode 4.7 µs Setuptimeforarepeated t ;t Fastmode 600 ns SU STA STARTcondition High-speedmode 160 ns Standardmode 250 ns t ;t Datasetuptime Fastmode 100 ns SU DAT High-speedmode 10 ns Standardmode 0 3.45 µs Fastmode 0 0.9 µs t ;t Dataholdtime HD DAT High-speedmode,C =100pFmax 0 70 ns B High-speedmode,C =400pFmax 0 150 ns B Standardmode 1000 ns Fastmode 20+0.1C 300 ns B t RisetimeofSCLsignal RCL High-speedmode,C =100pFmax 10 40 ns B High-speedmode,C =400pFmax 20 80 ns B Standardmode 1000 ns RisetimeofSCLsignalafter arepeatedSTARTcondition Fastmode 20+0.1CB 300 ns t RCL1 andafteranacknowledge High-speedmode,C =100pFmax 10 80 ns B BIT High-speedmode,C =400pFmax 20 160 ns B Standardmode 300 ns Fastmode 20+0.1C 300 ns B t FalltimeofSCLsignal FCL High-speedmode,C =100pFmax 10 40 ns B High-speedmode,C =400pFmax 20 80 ns B Standardmode 1000 ns Fastmode 20+0.1C 300 ns B t RisetimeofSDAsignal RDA High-speedmode,C =100pFmax 10 80 ns B High-speedmode,C =400pFmax 20 160 ns B 4

DAC5574 www.ti.com SLAS407–DECEMBER2003 TIMING CHARACTERISTICS (continued) V =2.7Vto5.5V,R =2kW toGND;allspecifications–40(cid:176) Cto+105(cid:176) C,unlessotherwisespecified. DD L SYMBOL PARAMETER TESTCONDITIONS MIN TYP MAX UNITS Standardmode 300 ns Fastmode 20+0.1C 300 ns B t FalltimeofSDAsignal FDA High-speedmode,C =100pFmax 10 80 ns B High-speedmode,C =400pFmax 20 160 ns B Standardmode 4.0 µs SetuptimeforSTOPcon- t ;t Fastmode 600 ns SU STO dition High-speedmode 160 ns CapacitiveloadforSDAand C 400 pF B SCL Pulsewidthofspikesup- Fastmode 50 ns t SP pressed High-speedmode 10 ns Standardmode NoisemarginattheHIGH V levelforeachconnectedde- Fastmode 0.2V V NH DD vice(includinghysteresis) High-speedmode Standardmode NoisemarginattheLOW V levelforeachconnectedde- Fastmode 0.1V V NL DD vice(includinghysteresis) High-speedmode TYPICAL CHARACTERISTICS AtT =+25(cid:176) C,unlessotherwisenoted. A LINEARITYERRORANDDIFFERENTIAL LINEARITYERRORANDDIFFERENTIAL LINEARITYERRORvsDIGITALINPUTCODE LINEARITYERRORvsDIGITALINPUTCODE 1 1 CChhaannnneell AA VDD = 5 V Channel B VDD = 5 V LE − LSB −00..505 LE − LSB −00..505 −1 −1 0.5 0.5 B 0.25 B 0.25 S S L L E − 0 E − 0 L L D−0.25 D−0.25 −0.5 −0.5 0 32 64 96 128 160 192 224 255 0 32 64 96 128 160 192 224 255 Digital Input Code Digital Input Code Figure1. Figure2. 5

DAC5574 www.ti.com SLAS407–DECEMBER2003 TYPICAL CHARACTERISTICS (continued) AtT =+25(cid:176) C,unlessotherwisenoted. A LINEARITYERRORANDDIFFERENTIAL LINEARITYERRORANDDIFFERENTIAL LINEARITYERRORvsDIGITALINPUTCODE LINEARITYERRORvsDIGITALINPUTCODE 1 1 Channel C VDD = 5 V Channel D VDD = 5 V 0.5 0.5 B B S S L 0 L 0 − − LE −0.5 LE −0.5 −1 −1 0.5 0.5 B 0.25 B 0.25 DLE − LS−0.205 DLE − LS−0.205 −0.5 −0.5 0 32 64 96 128 160 192 224 255 0 32 64 96 128 160 192 224 255 Digital Input Code Digital Input Code Figure3. Figure4. LINEARITYERRORANDDIFFERENTIAL LINEARITYERRORANDDIFFERENTIAL LINEARITYERRORvsDIGITALINPUTCODE LINEARITYERRORvsDIGITALINPUTCODE 1 1 0.5 Channel A VDD = 2.7 V 0.5 Channel B VDD = 2.7 V LE − LSB −0.05 LE − LSB −0.05 −1 −1 0.5 0.5 B 0.25 B 0.25 S S E − L 0 E − L 0 DL−0.25 DL−0.25 −0.5 −0.5 0 32 64 96 128 160 192 224 255 0 32 64 96 128 160 192 224 255 Digital Input Code Digital Input Code Figure5. Figure6. LINEARITYERRORANDDIFFERENTIAL LINEARITYERRORANDDIFFERENTIAL LINEARITYERRORvsDIGITALINPUTCODE LINEARITYERRORvsDIGITALINPUTCODE 1 1 0.5 Channel C VDD = 2.7 V 0.5 Channel D VDD = 2.7 V B B S S E − L 0 E − L 0 L −0.5 L −0.5 −1 −1 0.5 0.5 B 0.25 B 0.25 S S E − L 0 E − L 0 DL −0.25 DL−0.25 −0.5 −0.5 0 32 64 96 128 160 192 224 255 0 32 64 96 128 160 192 224 255 Digital Input Code Digital Input Code Figure7. Figure8. 6

DAC5574 www.ti.com SLAS407–DECEMBER2003 TYPICAL CHARACTERISTICS (continued) AtT =+25(cid:176) C,unlessotherwisenoted. A ZERO-SCALEERROR ZERO-SCALEERROR vsTEMPERATURE vsTEMPERATURE 20 15 VDD = 5 V VDD = 2.7 V V V m m or − 15 CH A or − 10 CH A Err CH C Err CH C e e Scal CH D Scal CH D ero- 10 CH B ero- 5 CH B Z Z 5 0 −40 −10 20 50 80 −40 −10 20 50 80 TA − Free−Air Temperature − °C TA − Free−Air Temperature − °C Figure9. Figure10. FULL-SCALEERROR FULL-SCALEERROR vsTEMPERATURE vsTEMPERATURE 30 20 VDD = 5 V VDD = 2.7 V 25 CH C mV CH A mV 15 CH C − 20 − e Error 15 CH D e Error 10 CH A CH D al al Sc Sc Full- 10 CH B Full- 5 5 CH B 0 0 −40 −10 20 50 80 −40 −10 20 50 80 TA − Free−Air Temperature − °C TA − Free−Air Temperature − °C Figure11. Figure12. SINKCURRENTCAPABILITY SOURCECURRENTCAPABILITY ATNEGATIVERAIL ATPOSITIVERAIL 0.150 5.50 Typical For All Channels Typical For All Channels V 0.125 V e − e − 5.45 oltag 0.100 VDD = 2.7 V oltag ut V 0.075 VDD = 5.5 V ut V 5.40 p p ut ut O O − 0.050 − UT UT 5.35 O O V 0.025 V DAC Loaded With FFH DAC Loaded With 00H VDD = 5.5 V 0.000 5.30 0 1 2 3 4 5 0 1 2 3 4 5 ISINK − Sink Current − mA ISOURCE − Source Current − mA Figure13. Figure14. 7

DAC5574 www.ti.com SLAS407–DECEMBER2003 TYPICAL CHARACTERISTICS (continued) AtT =+25(cid:176) C,unlessotherwisenoted. A SOURCECURRENTCAPABILITY SUPPLYCURRENT ATPOSITIVERAIL vsDIGITALINPUTCODE 2.7 800 Typical For All Channels 700 e − V 2.6 m− A 600 VDD = 5.5 V ag nt Volt urre 500 − Output 2.5 Supply C 340000 VDD = 2.7 V V OUT 2.4 DAC Loaded With FFH I − DD 120000 VDD = 2.7 V All Channels Powered, No Load 2.3 0 0 1 2 3 4 5 0 32 64 96 128 160 192 224 255 ISOURCE − Source Current − mA Digital Input Code Figure15. Figure16. SUPPLYCURRENT SUPPLYCURRENT vsTEMPERATURE vsSUPPLYVOLTAGE 700 700 650 600 A VDD = 5.5 V A 600 mnt − 500 mnt − 550 y Curre 400 VDD = 2.7 V y Curre 455000 ppl 300 ppl 400 u u − S 200 − S 350 DD DD 300 I 100 I 250 All Channels Powered, No Load All DACs Powered, No Load 0 200 −40 −10 20 50 80 110 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 TA − Free−Air Temperature − °C VDD − Supply Voltage − V Figure17. Figure18. SUPPLYCURRENT HISTOGRAM vsLOGICINPUTVOLTAGE OFCURRENTCONSUMPTION 1200 2000 TA = 25°C A0 Input (All Other Inputs = GND) VDD = 5 V A 1000 m− 1500 nt upply Curre 680000 VDD = 5.5 V Frequency 1000 S − DD 400 500 I VDD = 2.7 V 200 0 0 1 2 3 4 5 500520540560580600620640660680700720740 VLogic − Logic Input Voltage − V IDD − Current Consumption − m A Figure19. Figure20. 8

DAC5574 www.ti.com SLAS407–DECEMBER2003 TYPICAL CHARACTERISTICS (continued) AtT =+25(cid:176) C,unlessotherwisenoted. A HISTOGRAM EXITING OFCURRENTCONSUMPTION POWER-DOWNMODE 2000 6 VDD = 2.7 V V 5 VPDowD e=r u5p V to Code 250 1500 e − 4 g a ncy Volt 3 ue 1000 ut q p Fre Out 2 − 500 UT 1 O V 0 0 −1 400 420440 460480 500520 540560580 600620 IDD − Current Consumption − m A Time (2 m s/div) Figure21. Figure22. LARGESIGNAL LARGESIGNAL SETTLINGTIME SETTLINGTIME 5 3.0 − V 4 − V 2.5 Voltage 3 Ou2t0p0Vu tDp LDFo =tao d5 Ge VdN wDith Voltage 2.0 OutpVuDtD L =oa 2d.7e dV with put 10% to 90% FSR put 1.5 200 pF to GND Out 2 Out 10% to 90% FSR − − 1.0 T T U U O 1 O V V 0.5 0 0.0 Time (25 m s/div) Time (25 m s/div) Figure23. Figure24. ABSOLUTEERROR† ABSOLUTEERROR† 24 18 VDD = 5 V, TA = 25°C VDD = 2.7 V, TA = 25°C 20 14 Channel A Output Channel D Output V) 16 V) 10 Channel A Output m m Error ( 12 Error ( 6 ut ut Outp 8 Channel B Output Channel C Output Outp 2 Channel B Output 4 Channel D Output −2 Channel C Output 0 −6 0 32 64 96 128 160 192 224 255 0 32 64 96 128 160 192 224 255 Digital Input Code Digital Input Code Figure25. Figure26. †Absolute error is the deviation from ideal DAC characteristics. It includes affects of offset, gain, and integral linearity. 9

DAC5574 www.ti.com SLAS407–DECEMBER2003 THEORY OF OPERATION D/A SECTION The architecture of the DAC5574 consists of a string DAC followed by an output buffer amplifier. Figure 27 showsageneralizedblockdiagramoftheDACarchitecture. VDD 50 k(cid:1) 50 k(cid:1) 70 k(cid:1) _ Ref+ VOUT DAC Register Resistor String + Ref- GND Figure27.R-StringDACArchitecture TheinputcodingtotheDAC5574isunsignedbinary,whichgivestheidealoutputvoltageas: V (cid:2)V (cid:1) D OUT DD 256 WhereD=decimalequivalentofthebinarycodethatisloadedtotheDACregister;itcanrangefrom0to255. RESISTOR STRING The resistor string section is shown in Figure 28. It is basically a divide-by-2 resistor, followed by a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier.Becausethearchitectureconsistsofastringofresistors,itisspecifiedmonotonic. VDD To Output Amplifier GND R R R R Figure28.TypicalResistorString Output Amplifier The output buffer is a gain-of-2 noninverting amplifiers, capable of generating rail-to-rail voltages on its output, which gives an output range of 0V to V . It is capable of driving a load of 2 kW in parallel with 1000 pF to GND. DD The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/µs withahalf-scalesettlingtimeof6µswiththeoutputunloaded. I2C Interface I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January2000).Thebusconsistsofadataline(SDA)andaclockline(SCL)with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controlsthebus.ThemasterisresponsibleforgeneratingtheSCLsignalanddeviceaddresses.Themasteralso generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmitsdataonthebusundercontrolofthemasterdevice. 10

DAC5574 www.ti.com SLAS407–DECEMBER2003 THEORY OF OPERATION (continued) The DAC5574 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as H/S-mode. The DAC5574 supports 7-bit addressing; 10-bit addressing and general call address are not supported. F/S-Mode Protocol • The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transitionoccursontheSDAlinewhileSCLishigh,asshowninFigure29.AllI2C-compatibledevices should recognizeastartcondition. • The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requirestheSDAlinetobestableduring the entire high period of the clock pulse (see Figure 30). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 31) by pulling the SDA line low during the entire high period of the 9th SCL cycle. Upon detecting this acknowledge, the master knows that communicationlinkwithaslavehasbeenestablished. • The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. • Tosignaltheendofthedatatransfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 29). This releases the bus and stops the communication link withtheaddressedslave.AllI2Ccompatibledevicesmust recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matchingaddress. H/S-Mode Protocol • Whenthebusisidle,bothSDAandSCLlinesarepulledhighbythepullupdevices. • The master generates a start condition followed by a valid serial byte containing H/S master code 00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the H/S master code, but all devices must recognize it and switch their internal setting to support3.4Mbpsoperation. • The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the H/S-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated startconditionsshouldbeusedtosecurethebusinH/S-mode. SDA SDA SCL SCL S P Start Stop Condition Condition Figure29.STARTandSTOPConditions 11

DAC5574 www.ti.com SLAS407–DECEMBER2003 THEORY OF OPERATION (continued) SDA SCL Data Line Stable; Change of Data Allowed Data Valid Figure30.BitTransferontheI2CBus Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From 1 2 8 9 Master S Clock Pulse for START Acknowledgement Condition Figure31.AcknowledgeontheI2CBus Recognize START or Recognize STOP or REPEATED START REPEATED START Condition Condition Generate ACKNOWLEDGE Signal P SDA MSB Acknowledgement Sr Signal From Slave Address R/W SCL 1 2 7 8 9 1 2 3 - 8 9 S Sr ACK ACK or or Sr P Clock Line Held Low While Interrupts are Serviced START or STOP or Repeated START Repeated START Condition Condition Figure32.BusProtocol 12

DAC5574 www.ti.com SLAS407–DECEMBER2003 DAC5574 I2C Update Sequence The DAC5574 requires a start condition, a valid I2C address, a control byte, an MSB byte, and an LSB byte for a single update. After the receipt of each byte, DAC5574 acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the DAC5574. The control byte sets the operational modeoftheselectedDAC5574.Oncetheoperationalmodeisselectedbythe control byte, DAC5574 expects an MSB byte followed by an LSB byte for data update to occur. DAC5574 performs an update on the falling edge of theacknowledgesignalthatfollowstheLSBbyte. Control byte needs not to be resent until a change in operational mode is required. The bits of the control byte continuously determine the type of update performed. Thus, for the first update, DAC5574 requires a start condition, a valid I2C address, a control byte, an MSB byte and an LSB byte. For all consecutive updates, DAC5574needsanMSBbyteandanLSBbyteaslongasthecontrolcommandremainsthesame. Using the I2C high-speed mode (f = 3.4 MHz), the clock running at 3.4 MHz, each 8-bit DAC update other than scl the first update can be done within 18 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge signal), at 188.88 KSPS. Using the fast mode (f = 400 kHz), clock running at 400 kHz, maximum DAC update scl rateislimitedto22.22KSPS.OnceastopconditionisreceivedDAC5574releasestheI2Cbus and awaits a new startcondition. AddressByte MSB LSB 1 0 0 1 1 A1 A0 R/W The address byte is the first byte received following the START condition from the master device. The first five bits (MSBs) of the address are factory preset to 10011. The next two bits of the address are the device select bits A1 and A0. The A1, A0 address inputs can be connected to V or digital GND, or can be actively driven by DD TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of theDAC5574.Upto4devices(DAC5574)canstillbeconnectedtothesameI2C-Bus. BroadcastAddressByte MSB LSB 1 0 0 1 0 0 0 0 Broadcast addressing is also supported by DAC5574. Broadcast addressing can be used for synchronously updating or powering down multiple DAC5574 devices. DAC5574 is designed to work with other members of the DAC857x and DAC757x families to support multichannel synchronous update. Using the broadcast address, DAC5574 responds regardless of the states of the address pins. Broadcast is supported only in write mode (MasterwritestoDAC5574). 13

DAC5574 www.ti.com SLAS407–DECEMBER2003 ControlByte MSB LSB 0 0 L1 L0 X Sel1 Sel0 PD0 Table1.ControlRegisterBitDescriptions BitName BitNumber/Description L1 Load1(ModeSelect)Bit Areusedforselectingtheupdatemode. L2 Load0(ModeSelect)Bit 00 StoreI2Cdata.ThecontentsofMS-BYTEandLS-BYTE(orpowerdowninformation)arestoredinthe temporaryregisterofaselectedchannel.ThismodedoesnotchangetheDACoutputoftheselected channel. 01 UpdateselectedDACwithI2Cdata.Mostcommonlyutilizedmode.ThecontentsofMS-BYTEand LS-BYTE(orpowerdowninformation)arestoredinthetemporaryregisterandintheDACregisterof theselectedchannel.ThismodechangestheDACoutputoftheselectedchannelwiththenewdata. 10 4-Channelsynchronousupdate.ThecontentsofMS-BYTEandLS-BYTE(orpowerdowninformation) arestoredinthetemporaryregisterandintheDACregisteroftheselectedchannel.Simultaneously, theotherthreechannelsgetupdatedwithpreviouslystoreddatafromthetemporaryregister.This modeupdatesallfourchannelstogether. 11 Broadcastupdatemode.Thismodehastwofunctions.Inbroadcastmode,DAC5574responds regardlessoflocaladdressmatching,andchannelselectionbecomesirrelevantasallchannelsupdate. Thismodeisintendedtoenableupto16channelssimultaneousupdate,ifusedwiththeI2Cbroadcast address(10010000). IfSel1=0 Allfourchannelsareupdatedwiththecontentsoftheirtemporaryregister data. IfSel1=1 AllfourchannelsareupdatedwiththeMS-BYTEandLS-BYTEdataor powerdown. Sel1 BuffSel1Bit ChannelSelectBits Sel0 BuffSel0Bit 00 ChannelA 01 ChannelB 10 ChannelC 11 ChannelD PD0 PowerDownFlag 0 Normaloperation 1 Power-downflag(MSB7andMSB6indicateapower-downoperation,asshowninTable2). 14

DAC5574 www.ti.com SLAS407–DECEMBER2003 Table2.ControlByte C7 C6 C5 C4 C3 C2 C1 C0 MSB7 MSB6 MSB5... Don't MSB MSB-1 MSB-2 0 0 Load1 Load0 ChSel1 ChSel0 PD0 Care (PD1) (PD2) ...LSB DESCRIPTION (Address Select) Writetotemporary 0 0 X 0 0 0 Data registerA(TRA)with data Writetotemporary 0 0 X 0 1 0 Data registerB(TRB)with data Writetotemporary 0 0 X 1 0 0 Data registerC(TRC)with data Writetotemporary 0 0 X 1 1 0 Data registerD(TRD)with data (00,01,10,or11) WritetoTRx(selected byC2&C1 0 0 X 1 seeTable8 0 w/PowerdownCom- mand (00,01,10,or11) WritetoTRx(selected 0 1 X 0 Data byC2&C1andload DACxw/data (00,01,10,or11) Power-downDACx 0 1 X 1 seeTable8 0 (selectedbyC2and C1) (00,01,10,or11) WritetoTRx(selected 1 0 X 0 Data byC2&C1w/dataand loadallDACs (00,01,10,or11) Power-downDACx 1 0 X 1 seeTable8 0 (selectedbyC2and C1)&loadallDACs BroadcastModes(controlsupto4devicesonasingleserialbus) UpdateallDACs,all X X 1 1 X 0 X X X deviceswithpreviously storedTRxdata UpdateallDACs,all X X 1 1 X 1 X 0 Data deviceswithMSB[7:0] andLSB[7:0]data Power-downallDACs, X X 1 1 X 1 X 1 seeTable8 0 alldevices Most Significant Byte Most significant byte MSB[7:0] consists of eight most significant bits of 8-bit unsigned binary D/A conversion data.IfC0=1,MSB[7],MSB[6]indicateapowerdownoperationasshowninTable8. Least Significant Byte Least significant byte LSB[7:0] consists of 8 don't care bits. DAC5574 updates at the falling edge of the acknowledgesignalthatfollowstheLSB[0]bit.Therefore,LSB[7:0]isneededfortheupdatetooccur. Default Readback Condition If the user initiates a readback of a specified channel without first writing data to that specified channel, the defaultreadbackisallzeros,sincethereadbackregisterisinitializedto0duringthepoweronresetphase. 15

DAC5574 www.ti.com SLAS407–DECEMBER2003 DAC5574 Registers Table3.DAC5574ArchitectureRegisterDescriptions REGISTER DESCRIPTION CTRL[7:0] Stores8-bitwidecontrolbytesentbythemaster MSB[7:0] Storesthe8mostsignificantbitsofunsignedbinarydatasentbythemaster.Canalsostore2-bitpower-downdata. TRA[9:0],TRB[9:0], 10-bittemporarystorageregistersassignedtoeachchannel.TwoMSBsstorepower-downinformation,8LSBs TRC[9:0],TRD[9:0] storedata. DRA[9:0],DRB[9:0], 10-bitDACregistersforeachchannel.TwoMSBsstorepower-downinformation,8LSBsstoreDACdata.An DRC[9:0],DRD[9:0] updateofthisregistermeansaDACupdatewithdataorpowerdown. DAC5574 as a Slave Receiver - Standard and Fast Mode Figure 33 shows the standard and fast mode master transmitter addressing a DAC5574 Slave Receiver with a 7-bitaddress. S SLAVE ADDRESS R/W A Ctrl-Byte A MS-Byte A LS-Byte A/A P 0 (write) Data Transferred (n* Words + Acknowledge) Word = 16 Bit From Master to DAC5574 DAC5574 I2C-SLAVE ADDRESS: From DAC5574 to Master MSB LSB A = Acknowledge (SDA LOW) 1 0 0 1 1 A1 A0 R/W A = Not Acknowledge (SDA HIGH) 0 = Write to DAC5574 S = START Condition Factory Preset 1 = Read from DAC5574 Sr= Repeated START Condition A0 = I2C Address Pin P = STOP Condition A1 = I2C Address Pin Figure33.StandardandFastMode:SlaveReceiver 16

DAC5574 www.ti.com SLAS407–DECEMBER2003 DAC5574 as a Slave Receiver - High-Speed Mode Figure 34 shows the high-speed mode master transmitter addressing a DAC5574 Slave Receiver with a 7-bit address. F/S-Mode HS-Mode F/S-Mode S HS-Master Code A Sr Slave Address R/W A Ctrl-Byte A MS-Byte A LS-Byte A/A P 0 (write) Data Transferred HS-Mode Continues (n* Words + Acknowledge) Word = 16 Bit HS-Mode Master Code: Sr Slave Address MSB LSB 0 0 0 0 1 X X R/W Control Byte: MSB LSB A3 A2 L1 L0 X Sel1 Sel2 PD0 MS-Byte: A3 = Extended Address Bit MSB LSB A2 = Extended Address Bit D7 D6 D5 D4 D3 D2 D1 D0 L1 = Load1 (Mode Select) Bit L0 = Load0 (Mode Select) Bit LS-Byte: Sel1 = Buff Sel1 (Channel) Select Bit MSB LSB Sel0 = Buff Sel0 (Channel) Select Bit X X X X X X X X PD0 = Power Down Flag D11 − D0 = Data Bits X = Don’t Care Figure34.High-SpeedMode:SlaveReceiver 17

DAC5574 www.ti.com SLAS407–DECEMBER2003 Master Transmitter Writing to a Slave Receiver (DAC5574) in Standard/Fast Modes All write access sequences begin with the device address (with R/W = 0) followed by the control byte. This control byte specifies the operation mode of DAC5574 and determines which channel of DAC5574 is being accessed in the subsequent read/write operation. The LSB of the control byte (PD0-Bit) determines if the followingdataispower-downdataorregulardata. With (PD0-Bit = 0) the DAC5574 expects to receive data in the following sequence HIGH-BYTE –LOW-BYTE – HIGH-BYTE – LOW-BYTE..., until a STOP Condition or REPEATED START Condition on the I2C-Bus is recognized(refertotheDATAINPUTMODEsectionofTable4). With (PD0-Bit = 1) the DAC5574 expects to receive 2 Bytes of power-down data (refer to the POWER DOWN MODEsectionofTable4). Table4. WriteSequenceinF/SMode DATAINPUTMODE Transmitter MSB 6 5 4 3 2 1 LSB Comment Master Start Beginsequence Master 1 0 0 1 1 A1 A0 R/W Writeaddressing(R/W=0) DAC5574 DAC5574Acknowledges Master 0 0 Load1 Load0 x BuffSel1 BuffSel0 PD0 Controlbyte(PD0=0) DAC5574 DAC5574Acknowledges Master D7 D6 D5 D4 D3 D2 D1 D0 Writingdataword,highbyte DAC5574 DAC5574Acknowledges Master x x x x x x x x Writingdataword,lowbyte DAC5574 DAC5574Acknowledges Master DataorStoporRepeatedStart(1) Dataordone(2) POWERDOWNMODE Transmitter MSB 6 5 4 3 2 1 LSB Comment Master Start Beginsequence Master 1 0 0 1 1 A1 A0 R/W Writeaddressing(R/W=0) DAC5574 DAC5574Acknowledges Master 0 0 Load1 Load0 x BuffSel1 BuffSel0 PD0 Controlbyte(PD0=1) DAC5574 DAC5574Acknowledges Master PD1 PD2 0 0 0 0 0 0 Writingdataword,highbyte DAC5574 DAC5574Acknowledges Master x x x x x x x x Writingdataword,lowbyte DAC5574 DAC5574Acknowledges Master StoporRepeatedStart(1) Done (1) UserepeatedSTARTtosecurebusoperationandloopbacktothestageofwriteaddressingfornextWrite. (2) OnceDAC5574isproperlyaddressedandcontrolbyteissent,HIGH–BYTE–LOW–BYTEsequencescanrepeatuntilaSTOPcondition orrepeatedSTARTconditionisreceived. 18

DAC5574 www.ti.com SLAS407–DECEMBER2003 Master Transmitter Writing to a Slave Receiver (DAC5574) in HS Mode When writing data to the DAC5574 in HS-mode, the master begins to transmit what is called the HS-Master Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master CodeisfollowedbyaNOTacknowledge. The master then switches to HS-mode and issues a repeated start condition, followed by the address byte (with R/W = 0) after which the DAC5574 acknowledges by pulling SDA low. This address byte is usually followed by the control byte, which is also acknowledged by the DAC5574. The LSB of the control byte (PD0-Bit) determines ifthefollowingdataispower-downdataorregulardata. With (PD0-Bit = 0) the DAC5574 expects to receive data in the following sequence HIGH-BYTE – LOW-BYTE – HIGH-BYTE – LOW-BYTE...., until a STOP condition or repeated start condition on the I2C-Bus is recognized (refertoTable5HS-MODEWRITESEQUENCE-DATA). With (PD0-Bit = 1) the DAC5574 expects to receive 2 bytes of power-down data (refer to Table 5 HS-MODE WRITESEQUENCE-POWERDOWN). Table5. MasterTransmitterWritestoSlaveReceiver(DAC5574)inHS-Mode HSMODEWRITESEQUENCE-DATA Transmitter MSB 6 5 4 3 2 1 LSB Comment Master Start Beginsequence Master 0 0 0 0 1 X X X HSModeMasterCode NodevicemayacknowledgeHSmas- NONE NotAcknowledge tercode Master RepeatedStart Master 1 0 0 1 1 A1 A0 R/W Writeaddressing(R/W=0) DAC5574 DAC5574Acknowledges Master 0 0 Load1 Load0 0 BuffSel1 BuffSel0 PD0 Controlbyte(PD0=0) DAC5574 DAC5574Acknowledges Master D7 D6 D5 D4 D3 D2 D1 D0 Writingdataword,MSB DAC5574 DAC5574Acknowledges Master x x x x x x x x Writingdataword,LSB DAC5574 DAC5574Acknowledges Master DataorStoporRepeatedStart(1) Dataordone (2) HSMODEWRITESEQUENCE-POWERDOWN Transmitter MSB 6 5 4 3 2 1 LSB Comment Master Start Beginsequence Master 0 0 0 0 1 X X X HSModeMasterCode NodevicemayacknowledgeHSmas- NONE NotAcknowledge tercode Master RepeatedStart Master 1 0 0 1 1 A1 A0 R/W Writeaddressing(R/W=0) DAC5574 DAC5574Acknowledges Master 0 0 Load1 Load2 0 BuffSel1 BuffSel0 PD0 ControlByte(PD0=1) DAC5574 DAC5574Acknowledges Master PD1 PD2 0 0 0 0 0 0 Writingdataword,highbyte DAC5574 DAC5574Acknowledges Master x x x x x x x x Writingdataword,lowbyte DAC5574 DAC5574Acknowledges Master Stoporrepeatedstart(1) Done (1) UserepeatedstarttosecurebusoperationandloopbacktothestageofwriteaddressingfornextWrite. (2) OnceDAC5574isproperlyaddressedandcontrolbyteissent,high-byte-low-bytesequencescanrepeatuntilastoporrepeatedstart conditionisreceived. 19

DAC5574 www.ti.com SLAS407–DECEMBER2003 DAC5574 as a Slave Transmitter - Standard and Fast Mode Figure 35 shows the standard and fast mode master transmitter addressing a DAC5574 Slave Transmitter with a 7-bitaddress. (DAC5574) (DAC5574) (DAC5574) (MASTER) (MASTER) S SLAVE ADDRESS R/W A Ctrl <7:1> PD0 A Sr Slave Address R/W A MS-Byte A LS-Byte A P 0 (write) 1 (read) Data Transferred (2 Bytes + Acknowledge) 0 = (Normal Mode) (DAC5574) (MASTER) (MASTER) (MASTER) PD0 A Sr Slave Address R/W A PDN-Byte A MS-Byte A LS-Byte A P 1 = (Power Down Flag) 1 (read) Data Transferred PDN-Byte: (3 Bytes + Acknowledge) MSB LSB PD1 PD2 1 1 1 1 1 1 PD1 = Power−Down Bit PD2 = Power−Down Bit Figure35. StandardandFastMode:SlaveTransmitter DAC5574 as a Slave Transmitter - High-Speed Mode Figure 36 shows an I2C-Master addressing DAC5574 in high-speed mode (with a 7-bit address), as a Slave Transmitter. F/S-Mode S HS-Master Code A HS-Mode (DAC5574) (DAC5574) (DAC5574) (MASTER) (MASTER) Sr Slave Address R/W A Ctrl <7:1> PD0 A Sr Slave Address R/W A MS-Byte A LS-Byte A P 0 (write) 1 (read) Data Transferred (2 Bytes + Acknowledge) 0 = (Normal Mode) (DAC5574) (MASTER) (MASTER) (MASTER) PD0 A Sr Slave Address R/W A PDN-Byte A MS-Byte A LS-Byte A P 1 = (Power −Down Flag) 1 (read) Data Transferred (3 Bytes + Acknowledge) Figure36. High-SpeedMode:SlaveTransmitter 20

DAC5574 www.ti.com SLAS407–DECEMBER2003 Master Receiver Reading From a Slave Transmitter (DAC5574) in Standard/Fast Modes When reading data back from the DAC5574, the user begins with an address byte (with R/W = 0) after which the DAC5574 will acknowledge by pulling SDA low. This address byte is usually followed by the Control Byte, which isalsoacknowledgedbytheDAC5574.Following this there is a REPEATED START condition by the Master and the address is resent with (R/W = 1). This is acknowledged by the DAC5574, indicating that it is prepared to transmit data. Two or three bytes of data are then read back from the DAC5574, depending on the (PD0-Bit). ThevalueofBuff-Sel1andBuff-Sel0determines,whichchanneldataisreadback.ASTOPConditionfollows. With the (PD0-Bit = 0) the DAC5574 transmits 2 bytes of data, HIGH-BYTE followed by the LOW-BYTE (refer to Table2.DataReadbackMode-2bytes). With the (PD0-Bit = 1) the DAC5574 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the HIGH-BYTEfollowedbytheLOW-BYTE(refertoTable2.DataReadbackMode-3bytes). Table6. ReadSequenceinF/SMode DATAREADBACKMODE-2BYTES Transmitter MSB 6 5 4 3 2 1 LSB Comment Master Start Beginsequence Master 1 0 0 1 1 A1 A0 R/W Writeaddressing(R/W=0) DAC5574 DAC5574Acknowledges Master 0 0 Load1 Load0 x BuffSel1 BuffSel0 PD0 Controlbyte(PD0=0) DAC5574 DAC5574Acknowledges Master RepeatedStart Master 1 0 0 1 1 A1 A0 R/W Readaddressing(R/W=1) DAC5574 DAC5574Acknowledges DAC5574 D7 D6 D5 D4 D3 D2 D1 D0 Readingdataword,highbyte Master MasterAcknowledges DAC5574 x x x x x x x x Readingdataword,lowbyte Master MasterNotAcknowledges Mastersignalendofread Master StoporRepeatedStart(1) Done DATAREADBACKMODE-3BYTES Transmitter MSB 6 5 4 3 2 1 LSB Comment Master Start Beginsequence Master 1 0 0 1 1 A1 A0 R/W Writeaddressing(R/W=0) DAC5574 DAC5574Acknowledges Master 0 0 Load1 Load0 x BuffSel1 BuffSel0 PD0 Controlbyte(PD0=1) DAC5574 DAC5574Acknowledges Master RepeatedStart Master 1 0 0 1 1 A1 A0 R/W Readaddressing(R/W=1) DAC5574 DAC5574Acknowledges DAC5574 PD1 PD2 1 1 1 1 1 1 Readpowerdownbyte Master MasterAcknowledges DAC5574 D7 D6 D5 D4 D3 D2 D1 D0 Readingdataword,highbyte Master MasterAcknowledges DAC5574 x x x x x x x x Readingdataword,lowbyte Master MasterNotAcknowledges Mastersignalendofread Master StoporRepeatedStart(1) Done (1) UserepeatedstarttosecurebusoperationandloopbacktothestageofwriteaddressingfornextWrite. 21

DAC5574 www.ti.com SLAS407–DECEMBER2003 Master Receiver Reading From a Slave Transmitter (DAC5574) in HS-Mode When reading data to the DAC5574 in HS-MODE, the master begins to transmit, what is called the HS-Master Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master CodeisfollowedbyaNOTacknowledge. The Master then switches to HS-mode and issues a REPEATED START condition, followed by the address byte (with R/W = 0) after which the DAC5574 acknowledges by pulling SDA low. This address byte is usually followed bythecontrolbyte,whichisalsoacknowledgedbytheDAC5574. Then there is a REPEATED START condition initiated by the master and the address is resent with (R/W = 1). This is acknowledged by the DAC5574, indicating that it is prepared to transmit data. Two or Three bytes of data are then read back from the DAC5574, depending on the (PD0-Bit). The value of Buff-Sel1 and Buff-Sel0 determines,whichchanneldataisreadback.ASTOPconditionfollows. With the (PD0-Bit = 0) the DAC5574 transmits 2 bytes of data, HIGH-BYTE followed by LOW-BYTE (refer to Table7HS-ModeReadbackSequence). With the (PD0-Bit = 1) the DAC5574 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the HIGH-BYTEfollowedbytheLOW-BYTE(refertoTable7HS-ModeReadbackSequence). Table7.MasterReceiverReadingSlaveTransmitter(DAC5574)inHS-Mode HSMODEREADBACKSEQUENCE Transmitter MSB 6 5 4 3 2 1 LSB Comment Master Start Beginsequence Master 0 0 0 0 1 X X X HSModeMasterCode NodevicemayacknowledgeHS NONE NotAcknowledge mastercode Master RepeatedStart Master 1 0 0 1 1 A1 A0 R/W Writeaddressing(R/W=0) DAC5574 DAC5574Acknowledges Master 0 0 Load1 Load0 X BuffSel1 BuffSel0 PD0 Controlbyte(PD0=1) DAC5574 DAC5574Acknowledges Master RepeatedStart Master 1 0 0 1 1 A1 A0 R/W Readaddressing(R/W=1) DAC5574 DAC5574Acknowledges DAC5574 PD1 PD2 1 1 1 1 1 1 Power-downbyte Master MasterAcknowledges DAC5574 D7 D6 D5 D4 D3 D2 D1 D0 Readingdataword,highbyte Master MasterAcknowledges DAC5574 x x x x x x x x Readingdataword,lowbyte Master MasterNotAcknowledges Mastersignalendofread Master StoporRepeatedStart Done Power-On Reset The DAC5574 contains a power-on-reset circuit that controls the output voltage during power up. On power up, the DAC register is filled with zeros and the output voltage is 0 V; it remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC whileitisintheprocessofpoweringup.Nodevicepinshouldbebroughthighbeforesupplyisapplied. Power-Down Modes The DAC5574 contains four separate power-down modes of operation. The modes are programmable via two most significant bits of the MSB byte, while (CTRL[0] = PD0 = 1). Table 8 shows how the state of these bits correspondtothemodeofoperationofthedevice. 22

DAC5574 www.ti.com SLAS407–DECEMBER2003 Table8.Power-DownModesofOperationfortheDAC5574 CTRL[0] MSB[7] MSB[6] OPERATINGMODE 1 0 0 HighImpedanceOutput 1 0 1 1kW toGND 1 1 0 100kW toGND 1 1 1 HighImpedance When (CTRL[0] = PD0 = 0), the device works normally with its normal power consumption of 150 µA at 5 V per channel. However, for the power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall but also the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while in power-down mode. There are three different options: The output is connected internally to GND through a 1-kW resistor, a 100-kW resistor or left open-circuit (high impedance). The output stage is illustrated in Figure37. Amplifier Resistor String DAC VOUT Powerdown Circuitry Resistor Network Figure37.OutputStageDuringPowerDown All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power down is typically 2.5 µs for V = 5 V and 5 DD µsforV =3V.(SeetheTypicalCurvessectionforadditionalinformation.) DD The DAC5574 offers a flexible power-down interface based on channel register operation. A channel consists of asingle8-bitDACwithpower-downcircuitry,atemporarystorageregister(TR)andaDAC register (DR). TR and DR are both 10 bits wide. Two MSBs represent the power-down condition and the 8 LSBs represent data for TR and DR. By using bits 9 and 8 of TR and DR, a power-down condition can be temporarily stored and used just like data. Internal circuits ensure that MSB[7] and MSB[6] get transferred to TR[9] and TR[8] (DR[9] and DR[8]) when the power-down flag (CTRL[0] = PD0) is set. Therefore, DAC5574 treats power-down conditions like data andall the operational modes are still valid for power down. It is possible to broadcast a power-down condition to all the DAC5574s in the system, or it is possible to simultaneously power down a channel while updating data on otherchannels. CURRENT CONSUMPTION TheDAC5574typicallyconsumes150µAatV =5V and 125µA at V = 3 V for each active channel, including DD DD reference current consumption. Additional current consumption can occur at the digital inputs if V << V . For IH DD most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In power-downmode,typicalcurrentconsumptionis200nA. DRIVING RESISTIVE AND CAPACITIVE LOADS The DAC5574 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset and gain error margins, the DAC5574 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2 kW can be driven by the DAC5574 while achieving a good load regulation. When the outputs of the DAC are driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output stage can enter into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the DAC. This only occurs within approximately the top 20 mV of the DAC's digital input-to-voltage output transfer characteristic. 23

DAC5574 www.ti.com SLAS407–DECEMBER2003 CROSSTALK The DAC5574 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel istypicallylessthan0.0025LSBs.Theaccrosstalkmeasured (for a full-scale, 1 kHz sine wave output generated atonechannel,andmeasuredattheremainingoutputchannel)istypicallyunder–100dB. OUTPUT VOLTAGE STABILITY The DAC5574 exhibits excellent temperature stability of –3 ppm/(cid:176)C typical output voltage drift over the specified temperaturerangeofthedevice.Thisenablestheoutputvoltageofeachchanneltostay within a –25 µV window for a –1 (cid:176)C ambient temperature change. Combined with good dc noise performance and true 8-bit differential linearity,theDAC5574becomesaperfectchoiceforclosed-loopcontrolapplications. SETTLING TIME AND OUTPUT GLITCH PERFORMANCE Settling time to within the 8-bit accurate range of the DAC5574 is achievable within 6 µs for a full-scale code changeattheinput.Worstcasesettling times between consecutive code changes is typically less than 2 µs. The high-speed serial interface of the DAC5574 is designed in order to support up to 188 kSPS update rate. For full-scale output swings, the output stage of each DAC5574 channel typically exhibits less than 100 mV of overshoot and undershoot when driving a 200 pF capacitive load. Code-to-code change glitches are extremely low (~10 µV) given that the code-to-code transition does not cross an Nx16 code boundary. Due to internal segmentation of the DAC5574, code-to-code glitches occur at each crossing of an Nx16 code boundary. These glitches can approach 100 mVs for N = 15, but settle out within ~2 µs. Sufficient bypass capacitance is required to ensure 10 µs settling under capacitive loading. To observe the settling performance under resistive load conditions,thepowersupply(henceDAC5574referencesupply)mustsettlequickerthantheDAC5574. 24

DAC5574 www.ti.com SLAS407–DECEMBER2003 APPLICATION INFORMATION The following sections give example circuits and tips for using the DAC5574 in various applications. For more information,contactyourlocalTIrepresentative,orvisittheTexasInstrumentswebsiteathttp://www.ti.com. BASIC CONNNECTIONS For many applications, connecting the DAC5574 is extremely simple. A basic connection diagram for the DAC5574 is shown in Figure 38. The 0.1 µF bypass capacitors help provide the momentary bursts of extra currentneededfromthesupplies. DAC5574 1 VOUTA A1 10 2 VOUTB A0 9 3 GND VDD 8 I2C Pullup Resistors VDD 4 VOUTC SDA 7 1 kW to 10 kW (typical) 5 VOUTD SCL 6 Microcontroller or Microprocessor With I2C Port SCL SDA NOTE: DAC5574 power and input/output connections are omitted for clarity, except I(cid:1)C Inputs. Figure38.TypicalDAC5574Connections The DAC5574 interfaces directly to standard mode, fast mode and high-speed mode I2C controllers. Any microcontroller's I2C peripheral, including master-only and non-multiple-master I2C peripherals, work with the DAC5574. The DAC5574 does not perform clock-stretching (i.e., it never pulls the clock line low), so it is not necessarytoprovideforthisunlessotherdevicesareonthesameI2Cbus. Pullup resistors are necessary on both the SDA and SCL lines because I2C bus drivers are open-drain. The size of the these resistors depend on the bus operating speed and capacitance on the bus lines. Higher-value resistors consume less power, but increase the transition times on the bus, limiting the bus speed. Lower-value resistors allow higher speed at the expense of higher power consumption. Long bus lines have higher capacitance and require smaller pullup resistors to compensate. If the pullup resistors are too small the bus driversmaynotbeabletopullthebuslinelow. USING GPIO PORTS FOR I2C Most microcontrollers have programmable input/output pins that can be set in software to act as inputs or outputs. If an I2C controller is not available, the DAC5574 can be connected to GPIO pins, and the I2C bus protocolsimulated,orbit-banged,insoftware.AnexampleofthisforasingleDAC5574isshowninFigure39. 25

DAC5574 www.ti.com SLAS407–DECEMBER2003 APPLICATION INFORMATION (continued) DAC5574 1 VOUTA A1 10 2 VOUTB A0 9 3 GND VDD 8 VDD 4 VOUTC SDA 7 5 VOUTD SCL 6 Microcontroller or Microprocessor GPIO-1 GPIO-2 NOTE: DAC5574 power and input/output connections are omitted for clarity, except I(cid:1)C Inputs. Figure39.UsingGPIOWithaSingleDAC5574 Bit-banging I2C with GPIO pins can be done by setting the GPIO line to zero and toggling it between input and output modes to apply the proper bus states. To drive the line low, the pin is set to output a zero; to let the line go high, the pin is set to input. When the pin is set to input, the state of the pin can be read; if another device is pullingthelinelow,thisreadsasazerointheport'sinputregister. Note that no pullup resistor is shown on the SCL line. In this simple case the resistor is not needed. The microcontroller can simply leave the line on output, and set it to one or zero as appropriate. It can do this because the DAC5574 never drives its clock line low. This technique can also be used with multiple devices, and hastheadvantageoflowercurrentconsumptionduetotheabsenceofaresistivepullup. If there are any devices on the bus that may drive their clock lines low, the above method should not be used. The SCL line should be high-Z or zero, and a pullup resistor provided as usual. Note also that this cannot be done on the SDA line in any case, because the DAC5574 drives the SDA line low from time to time, as all I2C devicesdo. Some microcontrollers have selectable strong pullup circuits built in to their GPIO ports. In some cases, these can be switched on and used in place of an external pullup resistor. Weak pullups are also provided on some microcontrollers, but usually these are too weak for I2C communication. Test any circuit before committing it to production. POWER SUPPLY REJECTION The positive reference voltage input of DAC5574 is internally tied to the power supply pin of the device. This increases I2C system flexibility, creating room for an extra I2C address pin in a low pin-count package. To eliminate the supply noise appearing at the DAC output, the user must pay close attention to how DAC5574 is powered. The supply to DAC5574 must be clean and well regulated. For best performance, use of a precision voltage reference is recommended to supply power to DAC5574. This is equivalent to providing a precision 26

DAC5574 www.ti.com SLAS407–DECEMBER2003 APPLICATION INFORMATION (continued) external reference to the device. Due to low power consumption of DAC5574, load regulation errors are negligible. In order to avoid excess power consumption at the Schmitt-triggered inputs of DAC5574, the precision reference voltage should be close to the I2C bus pullup voltage. For 3-V, 3.3-V and 5-V I2C bus pullup voltages, REF2930, REF2933 and REF02 precision voltage references are recommended respectively. These precision voltagereferencescanbeusedtosupplypowerformultipledevicesonasystem. USING REF02 AS A POWER SUPPLY FOR DAC5574 Due to the extremely low supply current required by the DAC5574, a possible configuration is to use a REF02 +5 V precision voltage reference to supply the required voltage to the DAC5574's supply input as well as the referenceinput,asshowninFigure40.This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V. The REF02 outputs a steady supply voltage for the DAC5574. If the REF02 is used, the current it needs to supply to the DAC5574 is 600 µA typical and 900 µA max for V = 5 V. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The total DD typicalcurrentrequired(witha5-kW loadonasingleDACoutput)is: 600µA+(5V/5kW) =1.6mA TheloadregulationoftheREF02istypically0.005%/mA,whichresultsinanerrorof 400µV for 1.6-mA of current drawnfromit.Thiscorrespondstoa0.02LSBerrorfora0Vto5Voutputrange. 15 V 5 V REF02 1.6 mA I2C SCL VDD VOUT = 0 V to 5 V Interface SDA DAC5574 Figure40.REF02PowerSupply LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The power applied to V should be well-regulated and low noise. Switching power supplies and dc/dc DD converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily coupleintotheDACoutputvoltagethroughvariouspathsbetweenthepowerconnectionsandanalogoutput. As with the GND connection, V should be connected to a positive power-supply plane or trace that is separate DD from the connection for digital logic until they are connected at the power-entry point. In addition, a 1-µF to 10-µF capacitor in parallel with a 0.1-µF bypass capacitor is strongly recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—alldesignedtoessentiallylow-passfilterthe–5Vsupply,removingthehigh-frequencynoise. 27

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) DAC5574IDGS ACTIVE VSSOP DGS 10 80 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 105 D574 & no Sb/Br) DAC5574IDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 105 D574 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) DAC5574IDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) DAC5574IDGSR VSSOP DGS 10 2500 350.0 350.0 43.0 PackMaterials-Page2

PACKAGE OUTLINE DGS0010A VSSOP - 1.1 mm max height SCALE 3.200 SMALL OUTLINE PACKAGE C 5.05 4.75 TYP SEATING PLANE A PIN 1 ID 0.1 C AREA 8X 0.5 10 1 3.1 2X 2.9 NOTE 3 2 5 6 0.27 10X 0.17 B 3.1 0.1 C A B 1.1 MAX 2.9 NOTE 4 0.23 TYP SEE DETAIL A 0.13 0.25 GAGE PLANE 0.15 0.7 0 - 8 0.05 0.4 DETAIL A TYPICAL 4221984/A 05/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA. www.ti.com

EXAMPLE BOARD LAYOUT DGS0010A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 10X (1.45) 10X (0.3) SYMM (R0.05) TYP 1 10 SYMM 8X (0.5) 5 6 (4.4) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221984/A 05/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DGS0010A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 10X (1.45) SYMM (R0.05) TYP 10X (0.3) 1 10 SYMM 8X (0.5) 5 6 (4.4) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221984/A 05/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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