CYUSB301X/CYUSB201X ® EZ-USB FX3: SuperSpeed USB Controller EZ-USB® FX3: SuperSpeed USB Controller Features ❐Firmware examples covering all I/O modules ❐Visual Studio host examples using C++ and C# ■Universal serial bus (USB) integration ■SuperSpeed Explorer Board available for rapid prototyping ❐USB 3.1, Gen 1 and USB 2.0 peripherals compliant with USB ❐Several accessory boards also available: 3.1 Specification Revision 1.0 (TID # 340800007) • Adapter boards for Xilinx/Altera FPGA development ❐5-Gbps SuperSpeed PHY compliant with USB 3.1 Gen 1 ❐High-speed On-The-Go (HS-OTG) host and peripheral • Adapter board for Video development compliant with OTG Supplement Version 2.0 • CPLD board for concept testing and initial development ❐Thirty-two physical endpoints Applications ■General Programmable Interface (GPIF™ II) ■Digital video camcorders ❐Programmable 100-MHz GPIF II enables connectivity to a wide range of external devices ■Digital still cameras ❐8-, 16-, 24-, and 32-bit data bus ❐Up to16 configurable control signals ■Printers ■Fully accessible 32-bit CPU ■Scanners ❐ARM926EJ core with 200-MHz operation ■Video capture cards ❐512-KB or 256-KB embedded SRAM ■Test and measurement equipment ■Additional connectivity to the following peripherals ■Surveillance cameras ❐SPI master at up to 33 MHz ❐UART support of up to 4 Mbps ■Personal navigation devices ❐I2C master controller at 1 MHz ❐I2S master (transmitter only) at sampling frequencies of ■Medical imaging devices 8kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz and 192 kHz ■Video IP phones ■Selectable clock input frequencies ■Portable media players ❐19.2, 26, 38.4, and 52 MHz ■Industrial cameras ❐19.2-MHz crystal input support ■Ultra low-power in core power-down mode ■Data loggers ❐Less than 60 µA with VBATT on and 20 µA with VBATT off ■Data acquisition ■Independent power domains for core and I/O ■High-performance Human Interface Devices (gesture ❐Core operation at 1.2 V recognition) ❐I2S, UART, and SPI operation at 1.8 to 3.3 V ❐I2C operation at 1.2 V to 3.3 V Functional Description ■Package options For a complete list of related documentation, click here. ❐121-ball, 10- × 10-mm, 0.8-mm pitch Pb-free ball grid array (BGA) ❐See Table24 for details on the seven FX3 variants ■EZ-USB® Software Development Kit (SDK) for code devel- opment of firmware and PC Applications ❐Includes RTOS Framework (using ThreadX Version 5) CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 •408-943-2600 Document Number: 001-52136 Rev. *X Revised December 17, 2018

CYUSB301X/CYUSB201X Logic Block Diagram Document Number: 001-52136 Rev. *X Page 2 of 58

CYUSB301X/CYUSB201X More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right <product> device for your design, and to help you to quickly and effectively integrate the device into your design. ■Overview: USB Portfolio, USB Roadmap ❐AN73609 - EZ-USB FX2LP/ FX3 Developing Bulk-Loop Ex- ample on Linux ■USB 3.0 Product Selectors: FX3, FX3S, CX3, GX3, HX3 ❐AN77960 - Introduction to EZ-USB FX3 High-Speed USB ■Application notes: Cypress offers a large number of USB appli- Host Controller cation notes covering a broad range of topics, from basic to ❐AN76348 - Differences in Implementation of EZ-USB FX2LP advanced level. Recommended application notes for getting and EZ-USB FX3 Applications started with FX3 are: ❐AN89661 - USB RAID 1 Disk Design Using EZ-USB FX3S ❐AN75705 - Getting Started with EZ-USB FX3 ■Code Examples: ❐AN76405 - EZ-USB FX3 Boot Options ❐AN70707 - EZ-USB FX3/FX3S Hardware Design Guidelines ❐USB Hi-Speed and Schematic Checklist ❐USB Full-Speed ❐AN65974 - Designing with the EZ-USB FX3 Slave FIFO In- ❐USB SuperSpeed terface ■Technical Reference Manual (TRM): ❐AN75779 - How to Implement an Image Sensor Interface with EZ-USB FX3 in a USB Video Class (UVC) Framework ❐EZ-USB FX3 Technical Reference Manual ❐AN86947 - Optimizing USB 3.0 Throughput with EZ-USB ■Development Kits: FX3 ❐CYUSB3KIT-003, EZ-USB FX3 SuperSpeed Explorer Kit ❐AN84868 - Configuring an FPGA over USB Using Cypress ❐CYUSB3KIT-001, EZ-USB FX3 Development Kit EZ-USB FX3 ❐AN68829 - Slave FIFO Interface for EZ-USB FX3: 5-Bit Ad- ■Models: IBIS dress Mode EZ-USB FX3 Software Development Kit Cypress delivers the complete software and firmware stack for FX3, in order to easily integrate SuperSpeed USB into any embedded application. The Software Development Kit (SDK) comes with tools, drivers and application examples, which help accelerate appli- cation development. GPIF™ II Designer The GPIF II Designer is a graphical software that allows designers to configure the GPIF II interface of the EZ-USB FX3 USB 3.0 Device Controller. The tool allows users the ability to select from one of five Cypress supplied interfaces, or choose to create their own GPIF II interface from scratch. Cypress has supplied industry standard interfaces such as Asynchronous and Synchronous Slave FIFO, Asynchronous and Synchronous SRAM, and Asynchronous SRAM. Designers who already have one of these pre-defined interfaces in their system can simply select the interface of choice, choose from a set of standard parameters such as bus width (x8, 16, x32) endianess, clock settings, and compile the interface. The tool has a streamlined three step GPIF interface development process for users who need a customized interface. Users are able to first select their pin configuration and standard parameters. Secondly, they can design a virtual state machine using configurable actions. Finally, users can view output timing to verify that it matches the expected timing. Once the three step process is complete, the interface can be compiled and integrated with FX3. Document Number: 001-52136 Rev. *X Page 3 of 58

CYUSB301X/CYUSB201X Contents Functional Overview ..........................................................5 Electrical Specifications ..................................................19 Application Examples ....................................................5 Absolute Maximum Ratings .........................................19 USB Interface ......................................................................6 Operating Conditions ...................................................19 OTG ...............................................................................6 DC Specifications ........................................................19 ReNumeration ...............................................................7 Thermal Characteristics ...................................................21 VBUS Overvoltage Protection .......................................7 AC Timing Parameters .....................................................21 Carkit UART Mode ........................................................7 GPIF II lines AC characteristics at 100 MHz ...............21 GPIF II ..................................................................................8 GPIF II PCLK Jitter characteristics ..............................21 CPU ......................................................................................8 GPIF II Timing .............................................................22 Slave FIFO Interface ...................................................25 JTAG Interface ....................................................................8 Host Processor Interface (P-Port) Timing ...................31 Other Interfaces ..................................................................8 Serial Peripherals Timing ............................................38 SPI Interface ..................................................................8 Reset Sequence ..........................................................43 UART Interface ..............................................................9 Package Diagram ..............................................................44 I2C Interface ..................................................................9 I2S Interface ..................................................................9 Ordering Information ........................................................45 Ordering Code Definitions ...........................................45 Boot Options .......................................................................9 Acronyms ..........................................................................46 Reset ....................................................................................9 Hard Reset ....................................................................9 Document Conventions ...................................................46 Soft Reset ......................................................................9 Units of Measure .........................................................46 Clocking ............................................................................10 Errata .................................................................................47 32-kHz Watchdog Timer Clock Input ...........................10 Qualification Status .....................................................47 Errata Summary ..........................................................47 Power .................................................................................11 Power Modes ..............................................................11 Document History Page ...................................................53 Digital I/Os .........................................................................13 Sales, Solutions, and Legal Information ........................58 Worldwide Sales and Design Support .........................58 GPIOs .................................................................................13 Products ......................................................................58 System-level ESD .............................................................13 PSoC® Solutions ........................................................58 Pin Configurations ...........................................................14 Cypress Developer Community ...................................58 Pin Description .................................................................15 Technical Support .......................................................58 Document Number: 001-52136 Rev. *X Page 4 of 58

CYUSB301X/CYUSB201X Functional Overview FX3 contains 512KB or 256KB of on-chip SRAM (see Ordering Information on page 45) for code and data. EZ-USB FX3 also Cypress’s EZ-USB FX3 is a SuperSpeed peripheral controller, provides interfaces to connect to serial peripherals such as providing integrated and flexible features. UART, SPI, I2C, and I2S. FX3 has a fully configurable, parallel, general programmable FX3 comes with application development tools. The software interface called GPIF II, which can connect to any processor, development kit comes with firmware and host application ASIC, or FPGA. GPIF II is an enhanced version of the GPIF in examples for accelerating time to market. FX2LP, Cypress’s flagship USB2.0 product. It provides easy and FX3 complies with the USB3.1, Gen 1.0 specification and is also glueless connectivity to popular interfaces, such as backward compatible with USB2.0. It also complies with asynchronous SRAM, asynchronous and synchronous address USB2.0 OTG Specification v2.0. data multiplexed interfaces, and parallel ATA. Application Examples FX3 has integrated the USB3.1 Gen 1 and USB2.0 physical layers (PHYs) along with a 32-bit ARM926EJ-S microprocessor In a typical application (see Figure 1), the FX3 functions as the for powerful data processing and for building custom main processor running the application software that connects applications. It implements an architecture that enables external hardware to the SuperSpeed USB connection. 375-MBps data transfer from GPIF II to the USB interface. Additionally, FX3 can function as a coprocessor connecting via An integrated USB2.0 OTG controller enables applications in the GPIF II interface to an application processor (see Figure 2) which FX3 may serve dual roles; for example, EZ-USB FX3 may and operates as a subsystem providing SuperSpeed USB function as an OTG Host to MSC as well as HID-class devices. connectivity to the application processor. Figure 1. EZ-USB FX3 as Main Processor Crystal* Clock External Slave USB Device USB Ez-USB FX3 GPIF II Host (e.g. Image Sensor) I2C * A clock input may be provided on the EEPROM CLKIN pin instead of a crystal input Document Number: 001-52136 Rev. *X Page 5 of 58

CYUSB301X/CYUSB201X Figure 2. EZ-USB FX3 as a Coprocessor Crystal* Clock External Master USB USB Ez-USB FX3 GPIF II (e.g. MCU/CPU/ Host FPGA/ASIC) I2C * A clock input may be provided on the EEPROM CLKIN pin instead of a crystal input USB Interface OTG FX3 is compliant with the OTG Specification Revision 2.0. In FX3 complies with the following specifications and supports the OTG mode, FX3 supports both A and B device modes and following features: supports Control, Interrupt, Bulk, and Isochronous data ■Supports USB peripheral functionality compliant with USB 3.1 transfers. Specification Revision 1.0 and is also backward compatible FX3 requires an external charge pump (either standalone or with the USB 2.0 Specification. integrated into a PMIC) to power VBUS in the OTG A-device mode. ■FX3 Hi-Speed parts (CYUSB201X) only support USB 2.0. The Target Peripheral List for OTG host implementation consists ■Complies with OTG Supplement Revision 2.0. It supports of MSC- and HID-class devices. High-Speed, Full-Speed, and Low-Speed OTG dual-role device capability. As a peripheral, FX3 is capable of SuperSpeed, FX3 does not support Attach Detection Protocol (ADP). High-Speed, and Full-Speed. As a host, it is capable of OTG Connectivity High-Speed, Full-Speed, and Low-Speed. In OTG mode, FX3 can be configured to be an A, B, or dual-role ■Supports Carkit Pass-Through UART functionality on USB device. It can connect to the following: D+/D– lines based on the CEA-936A specification. ■ACA device ■Supports 16 IN and 16 OUT endpoints. ■Targeted USB peripheral ■Supports the USB3.0 Streams feature. It also supports USB Attached SCSI (UAS) device-class to optimize mass-storage ■SRP-capable USB peripheral access performance. ■HNP-capable USB peripheral ■As a USB peripheral, application examples show that the FX3 ■OTG host supports UAS, USB Video Class (UVC), and Mass Storage Class (MSC) USB peripheral classes. All other device classes ■HNP-capable host can be supported by customer firmware; a template example is provided as a starting point. ■OTG device ■As an OTG host, application examples show that FX3 supports MSC and HID device classes. Note When the USB port is not in use, disable the PHY and transceiver to save power. Document Number: 001-52136 Rev. *X Page 6 of 58

CYUSB301X/CYUSB201X ReNumeration Carkit UART Mode Because of FX3's soft configuration, one chip can take on the The USB interface supports the Carkit UART mode (UART over identities of multiple distinct USB devices. D+/D–) for non-USB serial data transfer. This mode is based on the CEA-936A specification. When first plugged into USB, FX3 enumerates automatically with the Cypress Vendor ID (0x04B4) and downloads firmware and In the Carkit UART mode, the output signaling voltage is 3.3V. USB descriptors over the USB interface. The downloaded When configured for the Carkit UART mode, TXD of UART firmware executes an electrical disconnect and connect. FX3 (output) is mapped to the D– line, and RXD of UART (input) is enumerates again, this time as a device defined by the mapped to the D+ line. downloaded information. This patented two-step process, called In the Carkit UART mode, FX3 disables the USB transceiver and ReNumeration, happens instantly when the device is plugged in. D+ and D– pins serve as pass-through pins to connect to the UART of the host processor. The Carkit UART signals may be VBUS Overvoltage Protection routed to the GPIF II interface or to GPIO[48] and GPIO[49], as The maximum input voltage on FX3’s VBUS pin is 6V. A charger shown in Figure4. can supply up to 9V on VBUS. In this case, an external In this mode, FX3 supports a rate of up to 9600 bps. overvoltage protection (OVP) device is required to protect FX3 from damage on VBUS. Figure3 shows the system application diagram with an OVP device connected on VBUS. Refer to Table 8 on page 19 for the operating range of VBUS and VBATT. Figure 3. System Diagram with OVP Device For VBUS POWER SUBSYSTEM Q Q XVDD XVDD VIO1 VIO2 VIO3 VIO4 VDDQ VIO5 AVDDVDD R T C U3 U3 EZ-USB FX3 1 OVP device VBUS OTG_ID 2 Connector 345 SSSSSSSSRRTTXXXX+-+- B-Port B 6 S S D- U U 7 D+ 8 GND 9 Figure 4. Carkit UART Pass-through Block Diagram Carkit UART Pass-through Ctrl Carkit UART Pass-th(ro)ugh UART_TXD TXD RXD( DP) Interface on GPIF II UART_RXD RXD ort P DP B- GPIO[48] USB PHY DM MUX US TXD( DM) (UART_TX) Carkit UART Pass-through Interface on GPIOs GPIO[49] (UART_RX) Document Number: 001-52136 Rev. *X Page 7 of 58

CYUSB301X/CYUSB201X GPIF II CPU The high-performance GPIF II interface enables functionality FX3 has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU. similar to, but more advanced than, FX2LP’s GPIF and Slave The core has direct access to 16KB of Instruction Tightly FIFO interfaces. Coupled Memory (TCM) and 8KB of Data TCM. The ARM926EJ-S core provides a JTAG interface for firmware The GPIF II is a programmable state machine that enables a debugging. flexible interface that may function either as a master or slave in industry-standard or proprietary interfaces. Both parallel and FX3 offers the following advantages: serial interfaces may be implemented with GPIF II. ■Integrates 256/512 KB of embedded SRAM for code and data Here is a list of GPIF II features: and 8KB of Instruction cache and Data cache. ■Functions as master or slave ■Implements efficient and flexible DMA connectivity between the various peripherals (such as, USB, GPIF II, I2S, SPI, UART, ■Provides 256 firmware programmable states I2C), requiring firmware only to configure data accesses ■Supports 8-bit, 16-bit, 24-bit, and 32-bit parallel data bus between peripherals, which are then managed by the DMA fabric. ■Enables interface frequencies up to 100 MHz ■Allows easy application development using industry-standard ■Supports 14 configurable control pins when a 32- bit data bus development tools for ARM926EJ-S. is used. All control pins can be either input/output or bidirec- tional. Examples of the FX3 firmware are available with the Cypress EZ-USB FX3 Development Kit. ■Supports 16 configurable control pins when a 16/8 data bus is used. All control pins can be either input/output or bi-directional. JTAG Interface GPIFII state transitions are based on control input signals. The control output signals are driven as a result of the GPIFII state FX3’s JTAG interface has a standard five-pin interface to connect transitions. The INT# output signal can be controlled by GPIFII. to a JTAG debugger in order to debug firmware through the Refer to the GPIFII Designer tool. The GPIFII state machine’s CPU-core’s on-chip-debug circuitry. behavior is defined by a GPIFII descriptor. The GPIFII Industry-standard debugging tools for the ARM926EJ-S core descriptor is designed such that the required interface specifica- can be used for the FX3 application development. tions are met. 8KB of memory (separate from the 256/512 KB of For ARM JTAG access, TCK frequency should not be more than embedded SRAM) is dedicated to the GPIF II waveform where 1/6 of the CPU clock frequency. the GPIFII descriptor is stored in a specific format. Cypress’s GPIFII Designer Tool enables fast development of Other Interfaces GPIFII descriptors and includes examples for common interfaces. FX3 supports the following serial peripherals: Example implementations of GPIFII are the asynchronous slave ■SPI FIFO and synchronous slave FIFO interfaces. ■UART Slave FIFO interface ■I2C The Slave FIFO interface signals are shown in Figure 5. This interface allows an external processor to directly access up to ■I2S four buffers internal to FX3. Further details of the Slave FIFO The SPI, UART, and I2S interfaces are multiplexed on the serial interface are described on page25. peripheral port. Note Access to all 32 buffers is also supported over the slave The CYUSB3012 and CYUSB3014 Pin List on page 15 shows FIFO interface. For details, contact Cypress Applications details of how these interfaces are multiplexed. Note that when Support. GPIF II is configured for a 32-bit data bus width (CYUSB3012 and CYUSB3014), then the SPI interface is not available. Figure 5. Slave FIFO Interface SLCS# SPI Interface PKTEND FX3 supports an SPI Master interface on the Serial Peripherals FLAGB port. The maximum operation frequency is 33MHz. FLAGA External Master The SPI controller supports four modes of SPI communication A[1:0] (For example, (see SPI Timing Specification on page 41 for details on the MCU/CPU/ D[31:0] EZ-USB FX3 modes) with the Start-Stop clock. This controller is a FPGA/ASIC) SLWR# single-master controller with a single automated SSN control. It supports transaction sizes ranging from four bits to 32 bits. SLRD# SLOE# Note: Multiple Flags may be configured. Document Number: 001-52136 Rev. *X Page 8 of 58

CYUSB301X/CYUSB201X UART Interface Boot Options The UART interface of FX3 supports full-duplex communication. FX3 can load boot images from various sources, selected by the It includes the signals noted in Table1. configuration of the PMODE pins. Following are the FX3 boot Table 1. UART Interface Signals options: Signal Description ■Boot from USB TX Output signal ■Boot from I2C RX Input signal ■Boot from SPI CTS Flow control ❐Cypress SPI Flash parts supported are RTS Flow control S25FS064S (64-Mbit), S25FS128S (128-Mbit) and S25LFL064L (64-Mbit). The UART is capable of generating a range of baud rates, from ❐W25Q32FW (32-Mbit) is also supported. 300bps to 4608 Kbps, selectable by the firmware. If flow control ■Boot from GPIF II ASync ADMux mode is enabled, then FX3's UART only transmits data when the CTS input is asserted. In addition to this, FX3’s UART asserts the RTS ■Boot from GPIF II Sync ADMux mode output signal, when it is ready to receive data. ■Boot from GPIF II ASync SRAM mode I2C Interface Table 2. FX3 Booting Options FX3’s I2C interface is compatible with the I2C Bus Specification Revision 3. This I2C interface is capable of operating only as I2C PMODE[2:0][1] Boot From master; therefore, it may be used to communicate with other I2C F00 Sync ADMux (16-bit) slave devices. For example, FX3 may boot from an EEPROM connected to the I2C interface, as a selectable boot option. F01 Async ADMux (16-bit) FX3’s I2C Master Controller also supports multi-master mode F11 USB boot functionality. F0F Async SRAM (16-bit) The power supply for the I2C interface is VIO5, which is a F1F I2C, On Failure, USB Boot is Enabled separate power domain from the other serial peripherals. This 1FF I2C only gives the I2C interface the flexibility to operate at a different voltage than the other serial interfaces. 0F1 SPI, On Failure, USB Boot is Enabled The I2C controller supports bus frequencies of 100kHz, Reset 400kHz, and 1MHz. When VIO5 is 1.2V, the maximum operating frequency supported is 100kHz. When VIO5 is 1.8V, Hard Reset 2.5V, or 3.3 V, the operating frequencies supported are 400 kHz and 1 MHz. The I2C controller supports clock-stretching to A hard reset is initiated by asserting the Reset# pin on FX3. The enable slower devices to exercise flow control. specific reset sequence and timing requirements are detailed in The I2C interface’s SCL and SDA signals require external pull-up Figure 29 on page 43 and Table 23 on page 43. All I/Os are resistors. The pull-up resistors must be connected to VIO5. tristated during a hard reset. Note however, that the on-chip bootloader has control after a hard reset and it will configure I/O I2S Interface signals depending on the selected boot mode; see AN76405 - FX3 has an I2S port to support external audio codec devices. EZ-USB® FX3™ Boot Options for more details. FX3 functions as I2S Master as transmitter only. The I2S interface Soft Reset consists of four signals: clock line (I2S_CLK), serial data line (I2S_SD), word select line (I2S_WS), and master system clock In a soft reset, the processor sets the appropriate bits in the (I2S_MCLK). FX3 can generate the system clock as an output PP_INIT control register. There are two types of Soft Reset: on I2S_MCLK or accept an external system clock input on ■CPU Reset – The CPU Program Counter is reset. Firmware I2S_MCLK. does not need to be reloaded following a CPU Reset. The sampling frequencies supported by the I2S interface are ■Whole Device Reset – This reset is identical to Hard Reset. 8kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz and 192 kHz. ■The firmware must be reloaded following a Whole Device Reset. Note 1. F indicates Floating. Document Number: 001-52136 Rev. *X Page 9 of 58

CYUSB301X/CYUSB201X Clocking Clock inputs to FX3 must meet the phase noise and jitter require- ments specified in Table4. FX3 allows either a crystal to be connected between the XTALIN The input clock frequency is independent of the clock and data and XTALOUT pins or an external clock to be connected at the rate of the FX3 core or any of the device interfaces. The internal CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins PLL applies the appropriate clock multiply option depending on can be left unconnected if they are not used. the input frequency. Crystal frequency supported is 19.2 MHz, while the external Table 3. Crystal/Clock Frequency Selection clock frequencies supported are 19.2, 26, 38.4, and 52 MHz. Crystal/Clock FX3 has an on-chip oscillator circuit that uses an external FSLC[2] FSLC[1] FSLC[0] Frequency 19.2-MHz (±100 ppm) crystal (when the crystal option is used). An appropriate load capacitance is required with a crystal. Refer 0 0 0 19.2-MHz crystal to the specification of the crystal used to determine the appro- 1 0 0 19.2-MHz input CLK priate load capacitance. The FSLC[2:0] pins must be configured 1 0 1 26-MHz input CLK appropriately to select the crystal- or clock-frequency option. The 1 1 0 38.4-MHz input CLK configuration options are shown in Table3. 1 1 1 52-MHz input CLK Table 4. FX3 Input Clock Specifications Specification Parameter Description Units Min Max 100-Hz offset – –75 1-kHz offset – –104 Phase noise 10-kHz offset – –120 dB 100-kHz offset – –128 1-MHz offset – –130 Maximum frequency deviation – – 150 ppm Duty cycle – 30 70 Overshoot – – 3 % Undershoot – – –3 Rise time/fall time – – 3 ns 32-kHz Watchdog Timer Clock Input FX3 includes a watchdog timer. The watchdog timer can be used to interrupt the ARM926EJ-S core, automatically wake up the FX3 in Standby mode, and reset the ARM926EJ-S core. The watchdog timer runs a 32-kHz clock, which may be optionally supplied from an external source on a dedicated FX3 pin. The firmware can disable the watchdog timer. Requirements for the optional 32-kHz clock input are listed in Table5. Table 5. 32-kHz Clock Input Requirements Parameter Min Max Units Duty cycle 40 60 % Frequency deviation – ±200 ppm Rise time/fall time – 200 ns Document Number: 001-52136 Rev. *X Page 10 of 58

CYUSB301X/CYUSB201X Power USB transceiver through FX3’s internal voltage regulator. VBATT is internally regulated to 3.3V. FX3 has the following power supply domains: Note: ■IO_VDDQ: This is a group of independent supply domains for No specific power-up sequence for FX3 power domains. digital I/Os. The voltage level on these supplies is 1.8V to 3.3V. Minimum power on reset time of 1 ms should be met and the FX3 provides six independent supply domains for digital I/Os power domains must be stable for FX3 operation. listed as follows (see Table 7 on page 15 for details on each of the power domain signals): Power Modes ❐VIO1: GPIF II I/O FX3 supports the following power modes: ❐VIO2: IO2 ■Normal mode: This is the full-functional operating mode. The ❐VIO3: IO3 ❐VIO4: UART-/SPI/I2S internal CPU clock and the internal PLLs are enabled in this mode. ❐VIO5: I2C and JTAG (supports 1.2V to 3.3V) ❐Normal operating power consumption does not exceed the ❐CVDDQ: This is the supply voltage for clock and reset I/O. It sum of I Core max and I USB max (see Table 8 on page should be either 1.8 V or 3.3 V based on the voltage level of CC CC 19 for current consumption specifications). the CLKIN signal. ❐The I/O power supplies VIO2, VIO3, VIO4, and VIO5 can be ❐V : This is the supply voltage for the logic core. The nominal DD turned off when the corresponding interface is not in use. supply-voltage level is 1.2 V. This supplies the core logic VIO1 cannot be turned off at any time if the GPIFII interface circuits. The same supply must also be used for the following: is used in the application. • AVDD: This is the 1.2-V supply for the PLL, crystal oscilla- tor, and other core analog circuits ■Low-power modes (see Table6): • U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt- ❐Suspend mode with USB 3.0 PHY enabled (L1) ages for the USB 3.0 interface. ❐Suspend mode with USB 3.0 PHY disabled (L2) ❐Standby mode (L3) ■VBATT/VBUS: This is the 3.2-V to 6-V battery power supply ❐Core power-down mode (L4) for the USB I/O and analog circuits. This supply powers the Table 6. Entry and Exit Methods for Low-Power Modes Low-Power Mode Characteristics Methods of Entry Methods of Exit Suspend Mode with ■The power consumption in this mode does ■Firmware executing on ■D+ transitioning to low USB 3.0 PHY not exceed ISB ARM926EJ-S core can put FX3 into or high 1 Enabled (L1) suspend mode. For example, on ■USB 3.0 PHY is enabled and is in U3 mode ■D- transitioning to low USB suspend condition, firmware (one of the suspend modes defined by the or high may decide to put FX3 into suspend USB3.0 specification). This one block mode ■Impedance change on alone is operational with its internal clock OTG_ID pin while all other clocks are shut down ■External Processor, through the use of mailbox registers, can put FX3 into ■Resume condition on ■All I/Os maintain their previous state suspend mode SSRX± ■Power supply for the wakeup source and ■Detection of VBUS core power must be retained. All other power domains can be turned on/off ■Level detect on individually UART_CTS (programmable ■The states of the configuration registers, polarity) buffer memory, and all internal RAM are maintained ■GPIF II interface assertion of CTL[0] ■All transactions must be completed before FX3 enters Suspend mode (state of ■Assertion of RESET# outstanding transactions are not preserved) ■The firmware resumes operation from where it was suspended (except when woken up by RESET# assertion) because the program counter does not reset Document Number: 001-52136 Rev. *X Page 11 of 58

CYUSB301X/CYUSB201X Table 6. Entry and Exit Methods for Low-Power Modes (continued) Low-Power Mode Characteristics Methods of Entry Methods of Exit Suspend Mode with ■The power consumption in this mode does ■Firmware executing on ■D+ transitioning to low USB 3.0 PHY not exceed ISB ARM926EJ-S core can put FX3 into or high 2 Disabled (L2) suspend mode. For example, on ■USB 3.0 PHY is disabled and the USB ■D- transitioning to low USB suspend condition, firmware interface is in suspend mode or high may decide to put FX3 into suspend ■The clocks are shut off. The PLLs are mode ■Impedance change on disabled OTG_ID pin ■External Processor, through the use ■All I/Os maintain their previous state of mailbox registers can put FX3 into ■Detection of VBUS suspend mode ■USB interface maintains the previous ■Level detect on state UART_CTS (programmable ■Power supply for the wakeup source and polarity) core power must be retained. All other power domains can be turned on/off ■GPIF II interface individually assertion of CTL[0] ■The states of the configuration registers, ■Assertion of RESET# buffer memory and all internal RAM are maintained ■All transactions must be completed before FX3 enters Suspend mode (state of outstanding transactions are not preserved) ■The firmware resumes operation from where it was suspended (except when woken up by RESET# assertion) because the program counter does not reset Standby Mode (L3) ■The power consumption in this mode does ■Firmware executing on ■Detection of VBUS not exceed ISB3 ARM926EJ-S core or external ■Level detect on processor configures the appropriate ■All configuration register settings and UART_CTS register program/data RAM contents are (Programmable preserved. However, data in the buffers or Polarity) other parts of the data path, if any, is not ■GPIF II interface guaranteed. Therefore, the external assertion of CTL[0] processor should take care that the data needed is read before putting FX3 into this ■Assertion of RESET# Standby Mode ■The program counter is reset after waking up from Standby ■GPIO pins maintain their configuration ■Crystal oscillator is turned off ■Internal PLL is turned off ■USB transceiver is turned off ■ARM926EJ-S core is powered down. Upon wakeup, the core re-starts and runs the program stored in the program/data RAM ■Power supply for the wakeup source and core power must be retained. All other power domains can be turned on/off individually Document Number: 001-52136 Rev. *X Page 12 of 58

CYUSB301X/CYUSB201X Table 6. Entry and Exit Methods for Low-Power Modes (continued) Low-Power Mode Characteristics Methods of Entry Methods of Exit Core Power Down ■The power consumption in this mode does ■Turn off V ■Reapply VDD DD Mode (L4) not exceed ISB 4 ■Assertion of RESET# ■Core power is turned off ■All buffer memory, configuration registers, and the program RAM do not maintain state. After exiting this mode, reload the firmware ■In this mode, all other power domains can be turned on/off individually Note: The power consumption depends on how the FX3 IOs are utilized in the application. Refer to KBA85505 to estimate the current consumption by different power domains (VIO1–VIO5). Digital I/Os EMI FX3 meets EMI requirements outlined by FCC 15B (USA) and FX3 has internal firmware-controlled pull-up or pull-down EN55022 (Europe) for consumer electronics. FX3 can tolerate resistors on all digital I/O pins. An internal 50-kresistor pulls EMI, conducted by the aggressor, outlined by these specifica- the pins high, while an internal 10-k resistor pulls the pins low tions and continue to function as expected. to prevent them from floating. The I/O pins may have the following states: System-level ESD ■Tristated (High-Z) FX3 has built-in ESD protection on the D+, D–, and GND pins on ■Weak pull-up (via internal 50 k) the USB interface. The ESD protection levels provided on these ■Pull-down (via internal 10 k) ports are: ■Hold (I/O hold its value) when in low-power modes ■±2.2-kV human body model (HBM) based on JESD22-A114 ■The JTAG TDI, TMS, and TRST# signals have fixed 50-k Specification internal pull-ups, and the TCK signal has a fixed 10-k ■±6-kV contact discharge and ±8-kV air gap discharge based pull-down resistor. on IEC61000-4-2 level 3A All unused I/Os should be pulled high by using the internal ■± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based pull-up resistors. All unused outputs should be left floating. All on IEC61000-4-2 level 4C. I/Os can be driven at full-strength, three-quarter strength, This protection ensures the device continues to function after half-strength, or quarter-strength. These drive strengths are ESD events up to the levels stated in this section. configured separately for each interface. The SSRX+, SSRX–, SSTX+, and SSTX– pins only have up to GPIOs ±2.2-kV HBM internal ESD protection. EZ-USB enables a flexible pin configuration both on the GPIF II and the serial peripheral interfaces. Any unused control pins (except CTL[15]) on the GPIF II interface can be used as GPIOs. Similarly, any unused pins on the serial peripheral interfaces may be configured as GPIOs. See Pin Configurations for pin configuration options. All GPIF II and GPIO pins support an external load of up to 16pF for every pin. Document Number: 001-52136 Rev. *X Page 13 of 58

CYUSB301X/CYUSB201X Pin Configurations Figure 6. FX3 121-ball BGA Ball Map (Top View) 1 2 3 4 5 6 7 8 9 10 11 A U3VSSQ U3RXVDDQ SSRXM SSRXP SSTXP SSTXM AVDD VSS DP DM NC B VIO4 FSLC[0] R_USB3 FSLC[1] U3TXVDDQ CVDDQ AVSS VSS VSS VDD TRST# C GPIO[54] GPIO[55] VDD GPIO[57] RESET# XTALIN XTALOUT R_USB2 OTG_ID TDO VIO5 D GPIO[50] GPIO[51] GPIO[52] GPIO[53] GPIO[56] CLKIN_32 CLKIN VSS I2C_GPIO[58] I2C_GPIO[59] NC E GPIO[47] VSS VIO3 GPIO[49] GPIO[48] FSLC[2] TDI TMS VDD VBATT VBUS F VIO2 GPIO[45] GPIO[44] GPIO[41] GPIO[46] TCK GPIO[2] GPIO[5] GPIO[1] GPIO[0] VDD G VSS GPIO[42] GPIO[43] GPIO[30] GPIO[25] GPIO[22] GPIO[21] GPIO[15] GPIO[4] GPIO[3] VSS H VDD GPIO[39] GPIO[40] GPIO[31] GPIO[29] GPIO[26] GPIO[20] GPIO[24] GPIO[7] GPIO[6] VIO1 J GPIO[38] GPIO[36] GPIO[37] GPIO[34] GPIO[28] GPIO[16] GPIO[19] GPIO[14] GPIO[9] GPIO[8] VDD K GPIO[35] GPIO[33] VSS VSS GPIO[27] GPIO[23] GPIO[18] GPIO[17] GPIO[13] GPIO[12] GPIO[10] L VSS VSS VSS GPIO[32] VDD VSS VDD INT# VIO1 GPIO[11] VSS Figure 7. FX3 Hi-Speed 121-Ball BGA Ball Map (Top View) 1 2 3 4 5 6 7 8 9 10 11 A VSS VDD NC NC NC NC AVDD VSS DP DM NC B VIO4 FSLC[0] NC FSLC[1] VDD CVDDQ AVSS VSS VSS VDD TRST# C GPIO[54] GPIO[55] VDD GPIO[57] RESET# XTALIN XTALOUT R_USB2 OTG_ID TDO VIO5 D GPIO[50] GPIO[51] GPIO[52] GPIO[53] GPIO[56] CLKIN_32 CLKIN VSS I2C_GPIO[58] I2C_GPIO[59] NC E GPIO[47] VSS VIO3 GPIO[49] GPIO[48] FSLC[2] TDI TMS VDD VBATT VBUS F VIO2 GPIO[45] GPIO[44] GPIO[41] GPIO[46] TCK GPIO[2] GPIO[5] GPIO[1] GPIO[0] VDD G VSS GPIO[42] GPIO[43] GPIO[30] GPIO[25] GPIO[22] GPIO[21] GPIO[15] GPIO[4] GPIO[3] VSS H VDD GPIO[39] GPIO[40] GPIO[31] GPIO[29] GPIO[26] GPIO[20] GPIO[24] GPIO[7] GPIO[6] VIO1 J GPIO[38] GPIO[36] GPIO[37] GPIO[34] GPIO[28] GPIO[16] GPIO[19] GPIO[14] GPIO[9] GPIO[8] VDD K GPIO[35] GPIO[33] VSS VSS GPIO[27] GPIO[23] GPIO[18] GPIO[17] GPIO[13] GPIO[12] GPIO[10] L VSS VSS VSS GPIO[32] VDD VSS VDD INT# VIO1 GPIO[11] VSS Note: A2 and C3 need not be connected for FX3 Hi-Speed part. Document Number: 001-52136 Rev. *X Page 14 of 58

CYUSB301X/CYUSB201X Pin Description Table 7. CYUSB3012 and CYUSB3014 Pin List BGA Power Domain I/O Name Description GPIF II Interface Slave FIFO Interface [2] F10 VIO1 I/O GPIO[0] DQ[0] DQ[0] F9 VIO1 I/O GPIO[1] DQ[1] DQ[1] F7 VIO1 I/O GPIO[2] DQ[2] DQ[2] G10 VIO1 I/O GPIO[3] DQ[3] DQ[3] G9 VIO1 I/O GPIO[4] DQ[4] DQ[4] F8 VIO1 I/O GPIO[5] DQ[5] DQ[5] H10 VIO1 I/O GPIO[6] DQ[6] DQ[6] H9 VIO1 I/O GPIO[7] DQ[7] DQ[7] J10 VIO1 I/O GPIO[8] DQ[8]/A0 [3] DQ[8]/A0 [3] J9 VIO1 I/O GPIO[9] DQ[9]/A1 [3] DQ[9]/A1 [3] K11 VIO1 I/O GPIO[10] DQ[10] DQ[10] L10 VIO1 I/O GPIO[11] DQ[11] DQ[11] K10 VIO1 I/O GPIO[12] DQ[12] DQ[12] K9 VIO1 I/O GPIO[13] DQ[13] DQ[13] J8 VIO1 I/O GPIO[14] DQ[14] [4] DQ[14] [4] G8 VIO1 I/O GPIO[15] DQ[15] [4] DQ[15] [4] J6 VIO1 I/O GPIO[16] PCLK CLK K8 VIO1 I/O GPIO[17] CTL[0] SLCS# K7 VIO1 I/O GPIO[18] CTL[1] SLWR# J7 VIO1 I/O GPIO[19] CTL[2] SLOE# H7 VIO1 I/O GPIO[20] CTL[3] SLRD# G7 VIO1 I/O GPIO[21] CTL[4] FLAGA G6 VIO1 I/O GPIO[22] CTL[5] FLAGB K6 VIO1 I/O GPIO[23] CTL[6] GPIO H8 VIO1 I/O GPIO[24] CTL[7] PKTEND# G5 VIO1 I/O GPIO[25] CTL[8] GPIO H6 VIO1 I/O GPIO[26] CTL[9] GPIO K5 VIO1 I/O GPIO[27] CTL[10] GPIO J5 VIO1 I/O GPIO[28] CTL[11] A1 H5 VIO1 I/O GPIO[29] CTL[12] A0 G4 VIO1 I/O GPIO[30] PMODE[0] PMODE[0] H4 VIO1 I/O GPIO[31] PMODE[1] PMODE[1] L4 VIO1 I/O GPIO[32] PMODE[2] PMODE[2] L8 VIO1 I/O INT# INT#/CTL[15] CTL[15] Notes 2. Slave FIFO is an example configuration of GPIF II Interface. The Slave FIFO control signal assignments can be modified using GPIF-II designer tool. 3. For 8-bit data bus configuration, GPIO[8] and GPIO[9] act as address lines. 4. GPIF II can also be configured as a serial interface. The DQ[15] pin becomes a serial output and DQ[14] becomes a serial input in this mode. Document Number: 001-52136 Rev. *X Page 15 of 58

CYUSB301X/CYUSB201X Table 7. CYUSB3012 and CYUSB3014 Pin List (continued) BGA Power Domain I/O Name Description 16 - bit Data Bus 16 - bit Data 16 - bit 16 - bit 32-bit Data GPIO + UART + SPI + Bus + UART Data Bus + Data Bus + Bus only I2S + GPIO SPI + GPIO I2S + GPIO K2 VIO2 I/O GPIO[33] DQ[16] GPIO GPIO GPIO GPIO GPIO J4 VIO2 I/O GPIO[34] DQ[17] GPIO GPIO GPIO GPIO GPIO K1 VIO2 I/O GPIO[35] DQ[18] GPIO GPIO GPIO GPIO GPIO J2 VIO2 I/O GPIO[36] DQ[19] GPIO GPIO GPIO GPIO GPIO J3 VIO2 I/O GPIO[37] DQ[20] GPIO GPIO GPIO GPIO GPIO J1 VIO2 I/O GPIO[38] DQ[21] GPIO GPIO GPIO GPIO GPIO H2 VIO2 I/O GPIO[39] DQ[22] GPIO GPIO GPIO GPIO GPIO H3 VIO2 I/O GPIO[40] DQ[23] GPIO GPIO GPIO GPIO GPIO F4 VIO2 I/O GPIO[41]/A0 [5] DQ[24] GPIO GPIO GPIO GPIO GPIO G2 VIO2 I/O GPIO[42]/A1 [5] DQ[25] GPIO GPIO GPIO GPIO GPIO G3 VIO2 I/O GPIO[43] DQ[26] GPIO GPIO GPIO GPIO GPIO F3 VIO2 I/O GPIO[44] DQ[27] GPIO GPIO GPIO GPIO GPIO F2 VIO2 I/O GPIO[45] GPIO GPIO GPIO GPIO GPIO GPIO F5 VIO3 I/O GPIO[46] DQ[28] UART_RT S GPIO GPIO GPIO GPIO E1 VIO3 I/O GPIO[47] DQ[29] UART_CT S GPIO GPIO GPIO GPIO E5 VIO3 I/O GPIO[48] DQ[30] UART_TX GPIO GPIO GPIO GPIO E4 VIO3 I/O GPIO[49] DQ[31] UART_R X GPIO GPIO GPIO GPIO D1 VIO3 I/O GPIO[50] I2S_CLK I2S_CLK GPIO GPIO GPIO GPIO D2 VIO3 I/O GPIO[51] I2S_SD I2S_SD GPIO GPIO GPIO GPIO D3 VIO3 I/O GPIO[52] I2S_WS I2S_WS GPIO GPIO GPIO GPIO D4 VIO4 I/O GPIO[53] UART_RTS SPI_SCK UART_RTS SPI_SCK GPIO GPIO C1 VIO4 I/O GPIO[54] UART_CTS SPI_SSN UART_CTS SPI_SSN I2S_CLK GPIO C2 VIO4 I/O GPIO[55] UART_TX SPI_MIS O UART_TX SPI_MISO I2S_SD GPIO D5 VIO4 I/O GPIO[56] UART_RX SPI_MOS I UART_RX SPI_MOSI I2S_WS GPIO C4 VIO4 I/O GPIO[57] I2S_MCLK I2S_MCL K GPIO GPIO I2S_MCLK GPIO USB Port CYUSB301X CYUSB201X A3 U3RXVDDQ I SSRXM SSRX- NC A4 U3RXVDDQ I SSRXP SSRX+ NC A6 U3TXVDDQ O SSTXM SSTX- NC A5 U3TXVDDQ O SSTXP SSTX+ NC B3 U3TXVDDQ I/O R_usb3 Precision resistor for USB 3.0 NC (Connect a 200 ±1% resistor between this pin and GND) C9 VBUS/VBATT I OTG_ID OTG_ID A9 VBUS/VBATT I/O DP D+ A10 VBUS/VBATT I/O DM D– C8 VBUS/VBATT I/O R_usb2 Precision resistor for USB 2.0 (Connect a 6.04 k ±1% resistor between this pin and GND) Note 5. For 24-bit data bus configuration, GPIO[41] and GPIO[42] act as address lines. Document Number: 001-52136 Rev. *X Page 16 of 58

CYUSB301X/CYUSB201X Table 7. CYUSB3012 and CYUSB3014 Pin List (continued) BGA Power Domain I/O Name Description Clock and Reset B2 CVDDQ I FSLC[0] FSLC[0] C6 AVDD I/O XTALIN XTALIN C7 AVDD I/O XTALOUT XTALOUT B4 CVDDQ I FSLC[1] FSLC[1] E6 CVDDQ I FSLC[2] FSLC[2] D7 CVDDQ I CLKIN CLKIN D6 CVDDQ I CLKIN_32 CLKIN_32 C5 CVDDQ I RESET# RESET# I2C and JTAG D9 VIO5 I/O I2C_GPIO[58] I2C_SCL D10 VIO5 I/O I2C_GPIO[59] I2C_SDA E7 VIO5 I TDI TDI C10 VIO5 O TDO TDO B11 VIO5 I TRST# TRST# E8 VIO5 I TMS TMS F6 VIO5 I TCK TCK D11 VIO5 O O[60] GPIO Power E10 PWR VBATT B10 PWR VDD PWR VDD A1 PWR U3VSSQ E11 PWR VBUS D8 PWR VSS H11 PWR VIO1 E2 PWR VSS L9 PWR VIO1 G1 PWR VSS PWR VIO1 PWR VSS F1 PWR VIO2 G11 PWR VSS PWR VIO2 E3 PWR VIO3 L1 PWR VSS B1 PWR VIO4 L6 PWR VSS PWR VSS B6 PWR CVDDQ B5 PWR U3TXVDDQ A2 PWR U3RXVDDQ C11 PWR VIO5 Document Number: 001-52136 Rev. *X Page 17 of 58

CYUSB301X/CYUSB201X Table 7. CYUSB3012 and CYUSB3014 Pin List (continued) BGA Power Domain I/O Name Description L11 PWR VSS A7 PWR AVDD B7 PWR AVSS C3 PWR VDD B8 PWR VSS E9 PWR VDD B9 PWR VSS F11 PWR VDD PWR VSS GND PWR VDD PWR VSS GND PWR VSS GND H1 PWR VDD L7 PWR VDD J11 PWR VDD L5 PWR VDD K4 PWR VSS L3 PWR VSS K3 PWR VSS L2 PWR VSS A8 PWR VSS NC No Connect A11 NC No Connect Document Number: 001-52136 Rev. *X Page 18 of 58

CYUSB301X/CYUSB201X Electrical Specifications ■Additional ESD protection levels on D+, D–, and GND pins, and serial peripheral pins Absolute Maximum Ratings ■± 6-kV contact discharge, ± 8-kV air gap discharge based on Exceeding maximum ratings may shorten the useful life of the IEC61000-4-2 level 3A, ± 8-kV contact discharge, and ± 15-kV device. air gap discharge based on IEC61000-4-2 level 4C Storage temperature .................................... –65°C to +150°C Latch-up current .........................................................> 200mA Ambient temperature with Maximum output short-circuit current power supplied (Industrial) ............................ –40°C to +85°C for all I/Os (cumulative) ................................................–100mA Ambient temperature with Maximum output current per I/O (source or sink) ............20mA power supplied (Commercial) .............................0 °C to +70 °C Operating Conditions Supply voltage to ground potential VDD, AVDDQ ......................................................................1.25V TA (ambient temperature under bias) V ,V , V , V , V ................................................3.6V Industrial ........................................................ –40°C to +85°C IO1 IO2 IO3 IO4 IO5 U3TX , U3RX ...................................................1.25V Commercial ....................................................... 0 °C to +70 °C VDDQ VDDQ DC input voltage to any input pin ............................VCC + 0.3V VDD, AVDDQ, U3TXVDDQ, U3RXVDDQ DC voltage applied to Supply voltage ..................................................1.15V to 1.25V outputs in high Z state ............................................VCC + 0.3V VBATT supply voltage ...............................................3.2V to 6V (VCC is the corresponding I/O voltage) V , V , V , V , C IO1 IO2 IO3 IO4 VDDQ Static discharge voltage ESD protection levels: Supply voltage ......................................................1.7V to 3.6V ■± 2.2-kV HBM based on JESD22-A114 V supply voltage ............................................ 1.15V to 3.6V IO5 DC Specifications Table 8. DC Specifications Parameter Description Min Max Units Notes V Core voltage supply 1.15 1.25 V 1.2-V typical DD A Analog voltage supply 1.15 1.25 V 1.2-V typical VDD V GPIF II I/O power supply domain 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical IO1 V IO2 power supply domain 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical IO2 V IO3 power supply domain 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical IO3 V UART/SPI/I2S power supply 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical IO4 domain V USB voltage supply 3.2 6 V 3.7-V typical BATT V USB voltage supply 4.0 6 V 5-V typical BUS U3TX USB3.0 1.2-V supply 1.15 1.25 V 1.2-V typical. A 22-µF bypass capacitor is required VDDQ on this power supply. N/A for CYUSB201X U3RX USB3.0 1.2-V supply 1.15 1.25 V 1.2-V typical. A 22-µF bypass capacitor is required VDDQ on this power supply. N/A for CYUSB201X C Clock voltage supply 1.7 3.6 V 1.8-, 3.3-V typical VDDQ V I2C and JTAG voltage supply 1.15 3.6 V 1.2-, 1.8-, 2.5-, and 3.3-V typical IO5 V Input HIGH voltage 1 0.625 × VCC + 0.3 V For 2.0V  V  3.6V (except USB port). VCC is IH1 CC VCC the corresponding I/O voltage supply. V Input HIGH voltage 2 VCC – 0.4 VCC + 0.3 V For 1.7V  V 2.0V IH2 CC (except USB port). VCC is the corresponding I/O voltage supply. V Input LOW voltage –0.3 0.25 × VCC V VCC is the corresponding I/O voltage supply. IL Document Number: 001-52136 Rev. *X Page 19 of 58

CYUSB301X/CYUSB201X Table 8. DC Specifications (continued) Parameter Description Min Max Units Notes V Output HIGH voltage 0.9 × VCC – V I (max) = –100µA tested at quarter drive OH OH strength. VCC is the corresponding I/O voltage supply. Refer toTable 9 on page 21 for values of I OH at various drive strength and VCC. V Output LOW voltage – 0.1 × VCC V I (min) = +100 µA tested at quarter drive strength. OL OL VCC is the corresponding I/O voltage supply. Refer to Table 9 on page 21 for values of I measured at OL various drive strength and VCC. I Input leakage current for all pins –1 1 µA All I/O signals held at V IX DDQ except (For I/Os with a pull-up or pull-down resistor SSTXP/SSXM/SSRXP/SSRXM connected, the leakage current increases by V /R or V /R DDQ pu DDQ PD I Output High-Z leakage current for –1 1 µA All I/O signals held at V OZ DDQ all pins except SSTXP/ SSXM/ SSRXP/SSRXM I Core Core and analog voltage – 200 mA Total current through A , V CC VDD DD operating current I USB [6] USB voltage supply operating – 60 [6] mA – CC current I Total suspend current during – – mA Core current: 1.5 mA SB1 suspend mode with USB 3.0 PHY I/O current: 20 µA enabled (L1) USB current: 2 mA For typical PVT (typical silicon, all power supplies at their respective nominal levels at 25°C) I Total suspend current during – – mA Core current: 250 µA SB2 suspend mode with USB 3.0 PHY I/O current: 20 µA disabled (L2) USB current: 1.2 mA For typical PVT (Typical silicon, all power supplies at their respective nominal levels at 25°C) I Total standby current during – – µA Core current: 60 µA SB3 standby mode (L3) I/O current: 20 µA USB current: 40 µA For typical PVT (typical silicon, all power supplies at their respective nominal levels at 25°C) I Total standby current during core – – µA Core current: 0 µA SB4 power-down mode (L4) I/O current: 20 µA USB current: 40 µA For typical PVT (typical silicon, all power supplies at their respective nominal levels at 25°C) V Voltage ramp rate on core and I/O 0.2 50 V/ms Voltage ramp must be monotonic RAMP supplies V Noise level permitted on V and – 100 mV Max p-p noise level permitted on all supplies except N DD I/O supplies A VDD V Noise level permitted on A – 20 mV Max p-p noise level permitted on A N_AVDD VDD VDD supply Note 6. For CYUSB2014 ICC USB is typically 22 mA–23 mA. Document Number: 001-52136 Rev. *X Page 20 of 58

CYUSB301X/CYUSB201X Table 9. I /I values for different drive strength and V values OH OL DDIO V (V) V (V) V (V) Drive Strength I (mA) I (mA) DDIO OH OL OH max OL min 1.7 1.53 0.17 Quarter 1.02 2.21 Half 1.51 3.28 Three-Quarters 1.83 3.85 Full 2.28 4.73 2.5 2.25 0.25 Quarter 5.03 3.96 Half 7.38 5.84 Three-Quarters 8.89 6.89 Full 11.07 8.61 3.6 3.24 0.36 Quarter 7.80 5.74 Half 11.36 8.64 Three-Quarters 13.64 10.15 Full 16.92 12.67 Thermal Characteristics Table 10. Thermal Characteristics Parameter Description Value Unit T Maximum Junction Temperature 125 C J MAX  Thermal resistance (junction to ambient) 34.66 C/W JA  Thermal resistance (junction to board) 27.03 C/W JB  Thermal resistance (junction to case) 13.57 C/W JC AC Timing Parameters GPIF II lines AC characteristics at 100 MHz Table 11. GPIF II lines AC characteristics at 100 MHz Symbol Parameter Min Typ Max Unit Tr Rise time – – 2.5 ns Tf Fall time – – 2.5 ns Tov Overshoot – – 3 % Tun Undershoot – – 3 % GPIF II PCLK Jitter characteristics Table 12. GPIF II PCLK Jitter characteristics Clk Freq (MHz) Period Jitter (ps) C-C min (ps) C-C max (ps) 10.08 354.44 –187.92 204.55 25.2 205.97 –153.54 126.53 50.4 144.62 –100.16 85.769 100.8 171.43 –155.13 157.14 Note: The clock jitter is measured using internally generated PCLK. ie. PCLK is configured as an output from GPIF. The data is measured over 10,000 clock cycles. Document Number: 001-52136 Rev. *X Page 21 of 58

CYUSB301X/CYUSB201X GPIF II Timing Figure 8. GPIF II Timing in Synchronous Mode tCLKH tCLKL CLK tCLK tCO tHZ tCOE tDS tDH tLZ tLZ tDOH tDOH Data1 Data2 DQ- [31:0] Data( IN) (OUT) (OUT) tS tH CTL(IN) tCTLO tCOH CTL (OUT) Table 13. GPIF II Timing Parameters in Synchronous Mode [7] Parameter Description Min Max Units Frequency Interface clock frequency – 100 MHz tCLK Interface clock period 10 – ns tCLKH Clock high time 4 – ns tCLKL Clock low time 4 – ns tS CTL input to clock setup time 2 – ns tH CTL input to clock hold time 0.5 – ns tDS Data in to clock setup time 2 – ns tDH Data in to clock hold time 0.5 – ns tCO Clock to data out propagation delay when DQ bus is already in output direction – 7 ns Clock to data out propagation delay when DQ lines change to output from tristate tCOE – 9 ns and valid data is available on the DQ bus tCTLO Clock to CTL out propagation delay – 8 ns tDOH Clock to data out hold 2 – ns tCOH Clock to CTL out hold 0 – ns tHZ Clock to high-Z – 8 ns tLZ Clock to low-Z 0 – ns Note 7. All parameters guaranteed by design and validated through characterization. Document Number: 001-52136 Rev. *X Page 22 of 58

CYUSB301X/CYUSB201X Figure 9. GPIF II Timing in Asynchronous Mode tDS/ tAS tDH/tAH DATA/ ADDR DATA IN tCHZ tCTLassert_DQlatch CTL# tCTLdeassert_DQlatch (I/P, ALE/DLE) tAA/tDO tCHZ/tOEHZ tCLZ/tOELZ DATA OUT DATA OUT CTL# tCTLassert tCTLdeassert (I/P, non ALE/ DLE tCTLalpha ALPHA O/P tCTLbeta BETA O/P tCTLassert 1 tCTLdeassert 1 tCTL# (O/P) 1. n is an integer >= 0 tDST tDHT DATA/ ADDR tCTLdeassert_DQassert CTL# tCTLassert_DQassert I/P (non DLE/ALE) Figure 10. GPIF II Timing in Asynchronous DDR Mode tDS tCTLdeassert_DqlatchDDR tCTLassert_DQlatchDDR CTL# (I/P) tDS tDH tDH DATA IN Document Number: 001-52136 Rev. *X Page 23 of 58

CYUSB301X/CYUSB201X Table 14. GPIF II Timing in Asynchronous Mode[8, 9] Note The following parameters assume one state transition Parameter Description Min Max Units tDS Data In to DLE setup time. Valid in DDR async mode. 2.3 – ns tDH Data In to DLE hold time. Valid in DDR async mode. 2 – ns tAS Address In to ALE setup time 2.3 – ns tAH Address In to ALE hold time 2 – ns CTL I/O asserted width for CTRL inputs without DQ input association tCTLassert 7 – ns and for outputs. CTL I/O deasserted width for CTRL inputs without DQ input associ- tCTLdeassert 7 – ns ation and for outputs. CTL asserted pulse width for CTL inputs that signify DQ inputs valid tCTLassert_DQassert at the asserting edge but do not employ in-built latches (ALE/DLE) for 20 – ns those DQ inputs. CTL deasserted pulse width for CTL inputs that signify DQ input valid tCTLdeassert_DQassert at the asserting edge but do not employ in-built latches (ALE/DLE) for 7 – ns those DQ inputs. CTL asserted pulse width for CTL inputs that signify DQ inputs valid tCTLassert_DQdeassert at the deasserting edge but do not employ in-built latches (ALE/DLE) 7 – ns for those DQ inputs. CTL deasserted pulse width for CTL inputs that signify DQ inputs valid tCTLdeassert_DQdeassert at the deasserting edge but do not employ in-built latches (ALE/DLE) 20 – ns for those DQ inputs. CTL asserted pulse width for CTL inputs that employ in-built latches tCTLassert_DQlatch (ALE/DLE) to latch the DQ inputs. In this non-DDR case, in-built 7 – ns latches are always close at the deasserting edge. CTL deasserted pulse width for CTL inputs that employ in-built latches tCTLdeassert_DQlatch (ALE/DLE) to latch the DQ inputs. In this non-DDR case, in-built 10 – ns latches always close at the deasserting edge. CTL asserted pulse width for CTL inputs that employ in-built latches tCTLassert_DQlatchDDR 10 – ns (DLE) to latch the DQ inputs in DDR mode. CTL deasserted pulse width for CTL inputs that employ in-built latches tCTLdeassert_DQlatchDDR 10 – ns (DLE) to latch the DQ inputs in DDR mode. DQ/CTL input to DQ output time when DQ change or CTL change tAA needs to be detected and affects internal updates of input and output – 30 ns DQ lines. CTL to data out when the CTL change merely enables the output flop tDO – 25 ns update whose data was already established. CTL designated as OE to low-Z. Time when external devices should tOELZ 0 – ns stop driving data. tOEHZ CTL designated as OE to high-Z 8 8 ns CTL (non-OE) to low-Z. Time when external devices should stop tCLZ 0 – ns driving data. tCHZ CTL (non-OE) to high-Z 30 30 ns tCTLalpha CTL to alpha change at output – 25 ns tCTLbeta CTL to beta change at output – 30 ns tDST Addr/data setup when DLE/ALE not used 2 – ns tDHT Addr/data hold when DLE/ALE not used 20 – ns Notes 8. All parameters guaranteed by design and validated through characterization. 9. "alpha" output corresponds to "early output" and "beta" corresponds to "delayed output". Please refer to the GPIFII Designer Tool for the use of these outputs. Document Number: 001-52136 Rev. *X Page 24 of 58

CYUSB301X/CYUSB201X Slave FIFO Interface FLAG Usage: The FLAG signals are monitored for flow control by the external Synchronous Slave FIFO Read Sequence Description processor. FLAG signals are outputs from FX3 that may be ■FIFO address is stable and SLCS is asserted configured to show empty, full, or partial status for a dedicated thread or the current thread that is addressed. ■FLAG indicates FIFO not empty status Socket Switching Delay (Tssd): ■SLOE is asserted. SLOE is an output-enable only, whose sole The socket-switching delay is measured from the time function is to drive the data bus. EPSWITCH# is asserted by the master, with the new socket ■SLRD is asserted address on the address bus, to the time the Current_Thread_D- MA_Ready flag is asserted. For the Producer socket, the flag is The FIFO pointer is updated on the rising edge of the PCLK, asserted when it is ready to receive data in the DMA buffer. For while the SLRD is asserted. This starts the propagation of data the Consumer socket, the flag is asserted when it is ready to from the newly addressed location to the data bus. After a propa- drive data out of the DMA buffer. For a synchronous slave FIFO gation delay of tco (measured from the rising edge of PCLK), the interface, the switching delay is measured in the number of GPIF new data value is present. N is the first data value read from the interface clock cycles; for an asynchronous slave FIFO interface, FIFO. To have data on the FIFO data bus, SLOE must also be in PIB clock cycles. This is applicable only for the 5-bit Slave asserted. FIFO interface; there is no socket-switching delay in FX3's 2-bit The same sequence of events is applicable for a burst read. Slave FIFO interface, which makes use of thread switching in the GPIF™ II state machine. Note For burst mode, the SLRD# and SLOE# are asserted during the entire duration of the read. When SLOE# is asserted, the data bus is driven (with data from the previously addressed FIFO). For each subsequent rising edge of PCLK, while the SLRD# is asserted, the FIFO pointer is incremented and the next data value is placed on the data bus. Figure 11. Synchronous Slave FIFO Read Mode Synchronous Read Cycle Timing tCYC PCLK tCH tCL tACCD SLCS tAStAH FIFO ADDR An Am tRDStRDH SLRD SLOE Tssd tACCD tCFLG Tssd FLAGA (dedicated thread Flag for An) (1 = Not Empty 0= Empty) tCFLG FLAGB (dedicated thread Flag for Am) (1 = Not Empty 0= Empty) tOELZ tOEZ tCDH tCO t OEZ Data Out High-Z drDivaetna :DN(An) High-Z DN (An) DN(Am) DN+1 (Am) DN+2 (Am) High-Z SLWR( HIGH) Document Number: 001-52136 Rev. *X Page 25 of 58

CYUSB301X/CYUSB201X Synchronous Slave FIFO Write Sequence Description Short Packet: A short packet can be committed to the USB host by using the PKTEND#. The external device or processor should ■FIFO address is stable and the signal SLCS# is asserted be designed to assert the PKTEND# along with the last word of ■External master or peripheral outputs the data to the data bus data and SLWR# pulse corresponding to the last word. The ■SLWR# is asserted FIFOADDR lines must be held constant during the PKTEND# assertion. ■While the SLWR# is asserted, data is written to the FIFO and on the rising edge of the PCLK, the FIFO pointer is incremented Zero-Length Packet: The external device or processor can signal a Zero-Length Packet (ZLP) to FX3 simply by asserting ■The FIFO flag is updated after a delay of t from the rising WFLG PKTEND#, without asserting SLWR#. SLCS# and address must edge of the clock be driven as shown in Figure12. The same sequence of events is also applicable for burst write Note For the burst mode, SLWR# and SLCS# are asserted for the entire duration, during which all the required data values are written. In this burst write mode, after the SLWR# is asserted, the data on the FIFO data bus is written to the FIFO on every rising edge of PCLK. The FIFO pointer is updated on each rising edge of PCLK. Figure 12. Synchronous Slave FIFO Write Mode Synchronous Write Cycle Timing tCYC PCLK tCH tCL SLCS tAS tAH FIFO ADDR An Am Tssd tWRS tWRH SLWR tFAD tCFLG FLAGA dedicated thread FLAG for An (1 = Not Full0 = Full) Tssd tFAD tCFLG FLAGB current thread FLAG for Am (1 = Not Full0 = Full) tDS tDH tDS tDH tDH Data IN High-Z DN(An) DN(Am) DN+1(Am) DN+2(Am) tPEStPEH PKTEND SLOE (HIGH) Document Number: 001-52136 Rev. *X Page 26 of 58

CYUSB301X/CYUSB201X Figure 13. Synchronous Slave FIFO ZLP Write Cycle Timing Synchronous ZLP Write Cycle Timing tCYC PCLK tCH tCL SLCS tAS tAH FIFO ADDR An SLWR (HIGH) tPEStPEH PKTEND FLAGA tCFLG dedicated thread FLAG for An (1 = Not Full 0= Full) FLAGB current thread FLAG for Am (1 = Not Full 0= Full) Data IN High-Z SLOE (HIGH) Table 15. Synchronous Slave FIFO Parameters[10] Parameter Description Min Max Units FREQ Interface clock frequency – 100 MHz tCYC Clock period 10 – ns tCH Clock high time 4 – ns tCL Clock low time 4 – ns tRDS SLRD# to CLK setup time 2 – ns tRDH SLRD# to CLK hold time 0.5 – ns tWRS SLWR# to CLK setup time 2 – ns tWRH SLWR# to CLK hold time 0.5 – ns tCO Clock to valid data – 7 ns tDS Data input setup time 2 – ns tDH CLK to data input hold 0.5 – ns tAS Address to CLK setup time 2 – ns tAH CLK to address hold time 0.5 – ns tOELZ SLOE# to data low-Z 0 – ns tCFLG CLK to flag output propagation delay – 8 ns tOEZ SLOE# deassert to Data Hi Z – 8 ns tPES PKTEND# to CLK setup 2 – ns tPEH CLK to PKTEND# hold 0.5 – ns tCDH CLK to data output hold 2 – ns tSSD Socket switching delay 2 68 Clock cycles tACCD Latency from SLRD# to Data 2 2 Clock cycles tFAD Latency from SLWR# to FLAG 3 3 Clock cycles Note Three-cycle latency from ADDR to DATA/FLAGS. Note 10.All parameters guaranteed by design and validated through characterization. Document Number: 001-52136 Rev. *X Page 27 of 58

CYUSB301X/CYUSB201X Asynchronous Slave FIFO Read Sequence Description In Figure 14, data N is the first valid data read from the FIFO. For data to appear on the data bus during the read cycle, SLOE# ■FIFO address is stable and the SLCS# signal is asserted. must be in an asserted state. SLRD# and SLOE# can also be ■SLOE# is asserted. This results in driving the data bus. tied. The same sequence of events is also shown for a burst read. ■SLRD # is asserted. Note In the burst read mode, during SLOE# assertion, the data ■Data from the FIFO is driven after assertion of SLRD#. This bus is in a driven state (data is driven from a previously data is valid after a propagation delay of tRDO from the falling addressed FIFO). After assertion of SLRD# data from the FIFO edge of SLRD#. is driven on the data bus (SLOE# must also be asserted). The ■FIFO pointer is incremented on deassertion of SLRD# FIFO pointer is incremented after deassertion of SLRD#. Figure 14. Asynchronous Slave FIFO Read Mode Asynchronous Read Cycle Timing SLCS tAS tAH FIFO ADDR An Am t t RDl RDh SLRD SLOE tFLG tRFLG FLAGA dedicated thread Flag for An (1=Not empty 0 = Empty) FLAGB dedicated thread Flag for Am (1=Not empty 0 = Empty) tOE tRDO tOH tOE tRDO tRDO tOH t LZ Data Out High-Z DN(An) DN(An) DN(Am) DN+1(Am) DN+2(Am) SLWR (HIGH) Document Number: 001-52136 Rev. *X Page 28 of 58

CYUSB301X/CYUSB201X Asynchronous Slave FIFO Write Sequence Description Short Packet: A short packet can be committed to the USB host by using the PKTEND#. The external device or processor should ■FIFO address is driven and SLCS# is asserted be designed to assert the PKTEND# along with the last word of ■SLWR# is asserted. SLCS# must be asserted with SLWR# or data and SLWR# pulse corresponding to the last word. The before SLWR# is asserted FIFOADDR lines must be held constant during the PKTEND# assertion. ■Data must be present on the tWRS bus before the deasserting Zero-Length Packet: The external device or processor can edge of SLWR# signal a zero-length packet (ZLP) to FX3 simply by asserting ■Deassertion of SLWR# causes the data to be written from the PKTEND#, without asserting SLWR#. SLCS# and the address data bus to the FIFO, and then the FIFO pointer is incremented must be driven as shown in Figure 16 on page 30. ■The FIFO flag is updated after the tWFLG from the deasserting FLAG Usage: The FLAG signals are monitored by the external edge of SLWR. processor for flow control. FLAG signals are FX3 outputs that can be configured to show empty, full, and partial status for a The same sequence of events is shown for a burst write. dedicated address or the current address. Note that in the burst write mode, after SLWR# deassertion, the data is written to the FIFO, and then the FIFO pointer is incre- mented. Figure 15. Asynchronous Slave FIFO Write Mode Asynchronous Write Cycle Timing SLCS tAS tAH FIFO ADDR An Am tWRl tWRh SLWR t FLG t WFLG F LAGA dedicated thread Flag for An t WFLG (1=Not Full 0 = Full) (1=deNdoicta Fteudll 0 t h = Fr Fe LauAdllG) FBlag for Am StWR tWRH StWR tWRH DATA In High-Z DN(An) DN(Am) DN+1(Am) DN+2(Am) t WRPtE PEh PKTEND SLOE (HIGH) tWRPE: SLWR# de-assert to PKTEND deassert = 2ns min (This means that PKTEND should not be be deasserted before SLWR#) Note: PKTEND must be asserted at the same time as SLWR#. Document Number: 001-52136 Rev. *X Page 29 of 58

CYUSB301X/CYUSB201X Figure 16. Asynchronous ZLP Write Cycle Timing SLCS tAS tAH FIFO ADDR An SLWR (HIGH) tPEl tPEh PKTEND t WFLG F LAGA dedicated thread Flag for An (1= Not Full 0 = Full) F LAGB dedicated thread Flag for Am (1= Not Full 0 = Full) DATA In High-Z SLOE (HIGH) Table 16. Asynchronous Slave FIFO Parameters[11] Parameter Description Min Max Units tRDI SLRD# low 20 – ns tRDh SLRD# high 10 – ns tAS Address to SLRD#/SLWR# setup time 7 – ns tAH SLRD#/SLWR#/PKTEND to address hold time 2 – ns tRFLG SLRD# to FLAGS output propagation delay – 35 ns tFLG ADDR to FLAGS output propagation delay – 22.5 ns tRDO SLRD# to data valid – 25 ns tOE OE# low to data valid – 25 ns tLZ OE# low to data low-Z 0 – ns tOH SLOE# deassert data output hold – 22.5 ns tWRI SLWR# low 20 – ns tWRh SLWR# high 10 – ns tWRS Data to SLWR# setup time 7 – ns tWRH SLWR# to Data Hold time 2 – ns tWFLG SLWR#/PKTEND to Flags output propagation delay – 35 ns tPEI PKTEND low 20 – ns tPEh PKTEND high 7.5 – ns tWRPE SLWR# deassert to PKTEND deassert 2 – ns Note 11.All parameters guaranteed by design and validated through characterization. Document Number: 001-52136 Rev. *X Page 30 of 58

CYUSB301X/CYUSB201X Host Processor Interface (P-Port) Timing Asynchronous SRAM Timing Figure 17. Non-multiplexed Asynchronous SRAM Read Timing Socket Read – Address Transition Controlled Timing (OE# is asserted) A[0] tAA tOH tAH HIGH DATA IMPEDANCE OUT DATA VALID DATA VALID DATA VALID OE# tOE OE# Controlled Timing ADDRESS WE# (HIGH) tAOS CE# tOHC tRC OE# tOHH tOE tOLZ tOEZ HIGH HIGH HIGH IMPEDANCE IMPEDANCE DATA OUT IMPEDANCE DATA DATA VALID VALID Document Number: 001-52136 Rev. *X Page 31 of 58

CYUSB301X/CYUSB201X Figure 18. Non-multiplexed Asynchronous SRAM Write Timing (WE# and CE# Controlled) Write Cycle 1 WE# Controlled, OE# High During Write tWC ADDRESS tCW CE# tAW tAH tWP WE# tAS tWPH OE# tDS tDH DATA I/O VALID DATA VALID DATA tWHZ Write Cycle 2 CE# Controlled, OE# High During Write tWC ADDRESS tAS tCW tCPH CE# tAW tAH tWP WE# OE# tDS tDH DATA I/O VALID DATA VALID DATA tWHZ Document Number: 001-52136 Rev. *X Page 32 of 58

CYUSB301X/CYUSB201X Figure 19. Non-multiplexed Asynchronous SRAM Write Timing (WE# controlled, OE# LOW) Write Cycle 3 WE# Controlled. OE# Low tWC tCW CE# tAW tAH tAS tWP WE# tDS tDH DATA I/O VALID DATA tOW tWHZ Note: tWP must be adjusted such that tWP > tWHZ + tDS Table 17. Asynchronous SRAM Timing Parameters[12] Parameter Description Min Max Units – SRAM interface bandwidth – 61.5 Mbps tRC Read cycle time 32.5 – ns tAA Address to data valid – 30 ns tAOS Address to OE# LOW setup time 7 – ns tOH Data output hold from address change 3 – ns tOHH OE# HIGH hold time 7.5 – ns tOHC OE# HIGH to CE# HIGH 2 – ns tOE OE# LOW to data valid – 25 ns tOLZ OE# LOW to LOW-Z 0 – ns tWC Write cycle time 30 – ns tCW CE# LOW to write end 30 – ns tAW Address valid to write end 30 – ns tAS Address setup to write start 7 – ns tAH Address hold time from CE# or WE# 2 – ns tWP WE# pulse width 20 – ns tWPH WE# HIGH time 10 – ns tCPH CE# HIGH time 10 – ns tDS Data setup to write end 7 – ns tDH Data hold to write end 2 – ns tWHZ Write to DQ HIGH-Z output – 22.5 ns tOEZ OE# HIGH to DQ HIGH-Z output – 22.5 ns tOW End of write to LOW-Z output 0 – ns Note 12.All parameters guaranteed by design and validated through characterization. Document Number: 001-52136 Rev. *X Page 33 of 58

CYUSB301X/CYUSB201X ADMux Timing for Asynchronous Access Figure 20. ADMux Asynchronous Random Read tRC tACC Valid A[0:7]/DQ[0:15] Valid Address Valid Data Addr tAVS tAVH ADV# tVP WE# (HIGH) tCEAV tHZ tCO CE# tCPH tHZ tOLZ OE# tOE tAVOE Note: 1. Multiple read cycles can be executed while keeping CE# low. 2. Read operation ends with either de-assertion of either OE# or CE#, whichever comes earlier. Figure 21. ADMux Asynchronous Random Write tWC Valid A[0:7]/DQ[0:15] Address Valid Data Valid Addr tAW tAVS tAVH tDS tDH ADV# tVP tVPH tCEAV CE# tCPH tCW WE# tWP tWPH tAVWE Note: 1. Multiple write cycles can be executed while keeping CE# low. 2. Write operation ends with de-assertion of either WE# or CE#, whichever comes earlier. Document Number: 001-52136 Rev. *X Page 34 of 58

CYUSB301X/CYUSB201X Table 18. Asynchronous ADMux Timing Parameters[13] Parameter Description Min Max Units Notes ADMux Asynchronous READ Access Timing Parameters Read cycle time (address valid to address This parameter is dependent on when tRC 54.5 – ns valid) the P-port processors deasserts OE# tACC Address valid to data valid – 32 ns – tCO CE# assert to data valid – 34.5 ns – tAVOE ADV# deassert to OE# assert 2 – ns – tOLZ OE# assert to data LOW-Z 0 – ns – tOE OE# assert to data valid – 25 ns – tHZ Read cycle end to data HIGH-Z – 22.5 ns – ADMux Asynchronous WRITE Access Timing Parameters Write cycle time (Address Valid to Address tWC – 52.5 ns – Valid) tAW Address valid to write end 30 – ns – tCW CE# assert to write end 30 – ns – tAVWE ADV# deassert to WE# assert 2 – ns – tWP WE# LOW pulse width 20 – ns – tWPH WE# HIGH pulse width 10 – ns – tDS Data valid setup to WE# deassert 18 – ns – tDH Data valid hold from WE# deassert 2 – ns – ADMux Asynchronous Common READ/WRITE Access Timing Parameters tAVS Address valid setup to ADV# deassert 5 – ns – tAVH Address valid hold from ADV# deassert 2 – ns – tVP ADV# LOW pulse width 7.5 – ns – tCPH CE# HIGH pulse width 10 – ns – tVPH ADV# HIGH pulse width 15 – ns – tCEAV CE# assert to ADV# assert 0 – ns – Note 13.All parameters guaranteed by design and validated through characterization. Document Number: 001-52136 Rev. *X Page 35 of 58

CYUSB301X/CYUSB201X Synchronous ADMux Timing Figure 22. Synchronous ADMux Interface – Read Cycle Timing 2- cycle latency from OE# to DATA tCLK tCLKH tCLKL CLK tCO tS tH A[0:7]/DQ[0:31] Valid Address Valid Data tS tH ADV# tOHZ tS CE# tAVOE tOLZ OE# tKW tKW RDY tCH WE# (HIGH) Note: 1) External P-Port processor and FX3 operate on the same clock edge 2) External processor sees RDY assert 2 cycles after OE # asserts andand sees RDY deassert a cycle after the data appears on the output 3) Valid output data appears 2 cycle after OE # asserted. The data is held until OE # deasserts 4) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader) Figure 23. Synchronous ADMux Interface – Write Cycle Timing 2-cycle latency between WE# and data being latched 2-cycle latency between this clk edge and RDY deassertion seen by the host CLK tCLK tS tH tDS tDH A[0:7]/DQ[0:31] Valid Address Valid Data tS tH ADV# tS CE# tAVWE tS tH WE# tKW RDY tKW Note: 1) External P-Port processor and FX3 operate on the same clock edge 2) External processor sees RDY assert 2 cycles after WE # asserts and deassert 3 cycles after the edge sampling the data. 3) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader) Document Number: 001-52136 Rev. *X Page 36 of 58

CYUSB301X/CYUSB201X Figure 24. Synchronous ADMux Interface – Burst Read Timing 2-cycle latency from OE# to Data tCLK tCLKH tCLKL CLK tCO tS tH tCH A[0:7]/DQ[0:31] Valid Address D0 D1 D2 D3 tS tH ADV# tHZ tS CE# tAVOE tOLZ OE# tKW RDY tKW Note: 1) External P-Port processor and FX3 work operate on the same clock edge 2) External processor sees RDY assert 2 cycles after OE # asserts andand sees RDY deassert a cycle after the last burst data appears on the output 3) Valid output data appears 2 cycle after OE # asserted. The last burst data is held until OE # deasserts 4) Burst size of 4 is shown. Transfer size for the operation must be a multiple of burst size. Burst size is usually power of 2. RDY will not deassert in the middle of the burst. 5) External processor cannot deassert OE in the middle of a burst. If it does so, any bytes remaining in the burst packet could get lost. 6) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader) Figure 25. Sync ADMux Interface – Burst Write Timing 2-cycle latency between WE# and data being latched 2-cycle latency between this clk edge and RDY deassertion seen by the host tCLKH tCLKL CLK tCLK tS tH tDS tDH tDH A[0:7]/DQ[0:31] Valid Address D0 D1 D2 D3 tS tH ADV# tS CE# tAVWE WE# tKW RDY tKW Note: 1) External P-Port processor and FX3 operate on the same clock edge 2) External processor sees RDY assert 2 cycles after WE # asserts and deasserts 3 cycles after the edge sampling the last burst data. 3) Transfer size for the operation must be a multiple of burst size. Burst size is usually power of 2. RDY will not deassert in the middle of the burst. Burst size of 4 is shown 4) External processor cannot deassert WE in the middle of a burst. If it does so, any bytes remaining in the burst packet could get lost. 5)Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader) Document Number: 001-52136 Rev. *X Page 37 of 58

CYUSB301X/CYUSB201X Table 19. Synchronous ADMux Timing Parameters[14] Parameter Description Min Max Unit FREQ Interface clock frequency – 100 MHz tCLK Clock period 10 – ns tCLKH Clock HIGH time 4 – ns tCLKL Clock LOW time 4 – ns tS CE#/WE#/DQ setup time 2 – ns tH CE#/WE#/DQ hold time 0.5 – ns tCH Clock to data output hold time 0 – ns tDS Data input setup time 2 – ns tDH Clock to data input hold 0.5 – ns tAVDOE ADV# HIGH to OE# LOW 0 – ns tAVDWE ADV# HIGH to WE# LOW 0 – ns tHZ CE# HIGH to Data HIGH-Z – 8 ns tOHZ OE# HIGH to Data HIGH-Z – 8 ns tOLZ OE# LOW to Data LOW-Z 0 – ns tKW Clock to RDY valid – 8 ns Serial Peripherals Timing I2C Timing Figure 26. I2C Timing Definition Note 14.All parameters guaranteed by design and validated through characterization. Document Number: 001-52136 Rev. *X Page 38 of 58

CYUSB301X/CYUSB201X Table 20. I2C Timing Parameters[15] Parameter Description Min Max Units I2C Standard Mode Parameters fSCL SCL clock frequency 0 100 kHz tHD:STA Hold time START condition 4 – µs tLOW LOW period of the SCL 4.7 – µs tHIGH HIGH period of the SCL 4 – µs tSU:STA Setup time for a repeated START condition 4.7 – µs tHD:DAT Data hold time 0 – µs tSU:DAT Data setup time 250 – ns tr Rise time of both SDA and SCL signals – 1000 ns tf Fall time of both SDA and SCL signals – 300 ns tSU:STO Setup time for STOP condition 4 – µs tBUF Bus free time between a STOP and START condition 4.7 – µs tVD:DAT Data valid time – 3.45 µs tVD:ACK Data valid ACK – 3.45 µs tSP Pulse width of spikes that must be suppressed by input filter n/a n/a I2C Fast Mode Parameters fSCL SCL clock frequency 0 400 kHz tHD:STA Hold time START condition 0.6 – µs tLOW LOW period of the SCL 1.3 – µs tHIGH HIGH period of the SCL 0.6 – µs tSU:STA Setup time for a repeated START condition 0.6 – µs tHD:DAT Data hold time 0 – µs tSU:DAT Data setup time 100 – ns tr Rise time of both SDA and SCL signals – 300 ns tf Fall time of both SDA and SCL signals – 300 ns tSU:STO Setup time for STOP condition 0.6 – µs tBUF Bus free time between a STOP and START condition 1.3 – µs tVD:DAT Data valid time – 0.9 µs tVD:ACK Data valid ACK – 0.9 µs tSP Pulse width of spikes that must be suppressed by input filter 0 50 ns Note 15.All parameters guaranteed by design and validated through characterization. Document Number: 001-52136 Rev. *X Page 39 of 58

CYUSB301X/CYUSB201X Table 20. I2C Timing Parameters[15] (continued) Parameter Description Min Max Units I2C Fast Mode Plus Parameters (Not supported at I2C_VDDQ=1.2V) fSCL SCL clock frequency 0 1000 kHz tHD:STA Hold time START condition 0.26 – µs tLOW LOW period of the SCL 0.5 – µs tHIGH HIGH period of the SCL 0.26 – µs tSU:STA Setup time for a repeated START condition 0.26 – µs tHD:DAT Data hold time 0 – µs tSU:DAT Data setup time 50 – ns tr Rise time of both SDA and SCL signals – 120 ns tf Fall time of both SDA and SCL signals – 120 ns tSU:STO Setup time for STOP condition 0.26 – µs tBUF Bus-free time between a STOP and START condition 0.5 – µs tVD:DAT Data valid time – 0.45 µs tVD:ACK Data valid ACK – 0.55 µs tSP Pulse width of spikes that must be suppressed by input filter 0 50 ns I2S Timing Diagram Figure 27. I2S Transmit Cycle t T t t TR TF tTL tTH SCK t Thd SA, WS (output) t Td Table 21. I2S Timing Parameters[16] Parameter Description Min Max Units tT I2S transmitter clock cycle Ttr – ns tTL I2S transmitter cycle LOW period 0.35 Ttr – ns tTH I2S transmitter cycle HIGH period 0.35 Ttr – ns tTR I2S transmitter rise time – 0.15 Ttr ns tTF I2S transmitter fall time – 0.15 Ttr ns tThd I2S transmitter data hold time 0 – ns tTd I2S transmitter delay time – 0.8tT ns Note tT is selectable through clock gears. Max Ttr is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz). Note 16.All parameters guaranteed by design and validated through characterization. Document Number: 001-52136 Rev. *X Page 40 of 58

CYUSB301X/CYUSB201X SPI Timing Specification Figure 28. SPI Timing SSN (output) t ssnh t sck t SCK tlead t lag (CPOL=0, rf Output) t t wsck wsck SCK (CPOL=1, Output) t sdi t hoi MISO (input) LSB MSB t t d t tdis sdd v di MOSI LSB MSB (output) SPI Master Timing for CPHA = 0 SSN (output) t ssnh t sck t t t lag SCK lead rf (CPOL=0, Output) t t wsck wsck SCK (CPOL=1, Output) tsdi thoi MISO LSB MSB (input) tdv tdi tdis MOSI LSB MSB (output) SPI Master Timing for CPHA = 1 Document Number: 001-52136 Rev. *X Page 41 of 58

CYUSB301X/CYUSB201X Table 22. SPI Timing Parameters[17] Parameter Description Min Max Units fop Operating frequency 0 33 MHz tsck Cycle time 30 – ns twsck Clock high/low time 13.5 – ns tlead SSN-SCK lead time 1/2 tsck[18]-5 1.5tsck[18]+ 5 ns tlag Enable lag time 0.5 1.5tsck[18]+5 ns trf Rise/fall time – 8 ns tsdd Output SSN to valid data delay time – 5 ns tdv Output data valid time – 5 ns tdi Output data invalid 0 – ns tssnh Minimum SSN high time 10 – ns tsdi Data setup time input 8 – ns thoi Data hold time input 0 – ns tdis Disable data output on SSN high 0 – ns Notes 17.All parameters guaranteed by design and validated through characterization. 18.Depends on LAG and LEAD setting in the SPI_CONFIG register. Document Number: 001-52136 Rev. *X Page 42 of 58

CYUSB301X/CYUSB201X Reset Sequence FX3’s hard reset sequence requirements are specified in this section. Table 23. Reset and Standby Timing Parameters Parameter Definition Conditions Min (ms) Max (ms) Clock Input 1 – tRPW Minimum RESET# pulse width Crystal Input 1 – tRH Minimum high on RESET# – 5 – Clock Input 1 – tRR Reset recovery time (after which Boot loader begins firmware download) Crystal Input 5 Time to enter standby/suspend (from the time MAIN_CLOCK_EN/ tSBY – – 1 MAIN_POWER_EN bit is set) Clock Input 1 – tWU Time to wakeup from standby Crystal Input 5 – tWH Minimum time before Standby/Suspend source may be reasserted – 5 – Figure 29. Reset Sequence VDD ( core) xVDDQ XTALIN/ CLKIN XTALIN/ CLKIN must be stable before exiting Standby/Suspend Mandatory tRR tRh Reset Pulse Hard Reset RESET # tRPW tWH Standby/ tSBY tWU Suspend Source Standby/Suspend source Is asserted Standby/Suspend (MAIN_POWER_EN/ MAIN_CLK_EN bit source Is deasserted is set) Document Number: 001-52136 Rev. *X Page 43 of 58

CYUSB301X/CYUSB201X Package Diagram Figure 30. 121-ball BGA Package Diagram 2X 0.10C E1 E B A (datum B) A1 CORNER 11 10 9 8 7 6 5 4 3 2 1 7 A1 CORNER A B C 6 D SD E D1 D F G (datum A) H J K eD L 0.10C 2X 6 TOP VIEW SE eE BOTTOM VIEW 0.20C DETAIL A A1 0.08C C 121XØb 5 A Ø0.15MCAB Ø0.08MC DETAIL A SIDE VIEW NOTES: DIMENSIONS 1. ALL DIMENSIONS ARE IN MILLIMETERS. SYMBOL MIN. NOM. MAX. 2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. A - - 1.20 3. "e" REPRESENTS THE SOLDER BALL GRID PITCH. A1 0.15 - - 4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. D 10.00 BSC SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX E 10.00 BSC SIZE MD X ME. D1 8.00 BSC E1 8.00 BSC 5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. MD 11 ME 11 6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. N 121 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN0 T0H1E-5 O44U7T1E R*E ROW, b 0.25 0.30 0.35 "SD" OR "SE" = 0. eD 0.80 BSC WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, eE 0.80 BSC "SD" = eD/2 AND "SE" = eE/2. SD 0.00 7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK SE 0.00 METALIZED MARK, INDENTATION OR OTHER MEANS. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER BALLS. 001-54471 *F Document Number: 001-52136 Rev. *X Page 44 of 58

CYUSB301X/CYUSB201X Ordering Information Table 24. Ordering Information Ordering Code USB SRAM (kB) GPIF II Data Bus Width Operating Temperature Package Type CYUSB3011-BZXC USB 3.0 256 16-bit 0 °C to +70 °C 121-ball BGA CYUSB3012-BZXC USB 3.0 256 32-bit 0 °C to +70 °C 121-ball BGA CYUSB3013-BZXC USB 3.0 512 16-bit 0 °C to +70 °C 121-ball BGA CYUSB3014-BZXC USB 3.0 512 32-bit 0 °C to +70 °C 121-ball BGA CYUSB3014-BZXI USB 3.0 512 32-bit –40°C to +85°C 121-ball BGA CYUSB2014-BZXC USB 2.0 512 32-bit 0 °C to +70 °C 121-ball BGA CYUSB2014-BZXI USB 2.0 512 32-bit –40 °C to +85 °C 121-ball BGA Ordering Code Definitions Document Number: 001-52136 Rev. *X Page 45 of 58

CYUSB301X/CYUSB201X Acronyms Document Conventions Units of Measure Acronym Description DMA direct memory access Symbol Unit of Measure FIFO first in, first out °C degree Celsius GPIF general programmable interface µA microamperes HNP host negotiation protocol µs microseconds I2C inter-integrated circuit mA milliamperes I2S inter IC sound Mbps Megabits per second MISO master in, slave out MBps Megabytes per second MOSI master out, slave in MHz mega hertz MMC multimedia card ms milliseconds MSC mass storage class ns nanoseconds MTP media transfer protocol  ohms OTG on-the-go pF pico Farad OVP overvoltage protection V volts PHY physical layer PLL phase locked loop PMIC power management IC PVT process voltage temperature RTOS real-time operating system SCL serial clock line SCLK serial clock SD secure digital SD secure digital SDA serial data clock SDIO secure digital input / output SLC single-level cell SLCS Slave Chip Select SLOE Slave Output Enable SLRD Slave Read SLWR Slave Write SPI serial peripheral interface SRP session request protocol SSN SPI slave select (Active low) UART universal asynchronous receiver transmitter UVC USB Video Class USB universal serial bus Document Number: 001-52136 Rev. *X Page 46 of 58

CYUSB301X/CYUSB201X Errata This section describes the errata for Revision D, C and B of the FX3. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number Device Characteristics CYUSB301x-xxxx All Variants CYUSB201x-xxxx All Variants Qualification Status Product Status: Production Errata Summary The following table defines the errata applicability to available Rev. D EZ-USB FX3 SuperSpeed USB Controller family devices. Items [Part Number] Silicon Revision Fix Status 1. Turning off VIO1 during Normal, Suspend, and Standby CYUSB301x-xxxx Rev. D, C, B Workaround provided modes causes the FX3 to stop working. CYUSB201x-xxxx 2. USB enumeration failure in USB boot mode when FX3 is CYUSB301x-xxxx Rev. D, C, B Workaround provided self-powered. CYUSB201x-xxxx 3. Extra ZLP is generated by the COMMIT action in the GPIF II CYUSB301x-xxxx Rev. D, C, B Workaround provided state. CYUSB201x-xxxx 4. Invalid PID Sequence in USB 2.0 ISOC data transfer. CYUSB301x-xxxx Rev. D, C, B Workaround provided CYUSB201x-xxxx 5. USB data transfer errors are seen when ZLP is followed by CYUSB301x-xxxx Rev. D, C, B Workaround provided data packet within same microframe. CYUSB201x-xxxx 6. Bus collision is seen when the I2C block is used as a master CYUSB301x-xxxx Rev. D, C, B Use FX3 in single-master in the I2C Multi-master configuration. CYUSB201x-xxxx configuration 7. Low Power U1 Fast-Exit Issue with USB3.0 host controller. CYUSB301x-xxxx Rev. D, C, B Workaround provided CYUSB201x-xxxx 8. USB data corruption when operating on hosts with poor link CYUSB301x-xxxx Rev. D, C, B Workaround provided quality. CYUSB201x-xxxx 9. Device treats Rx Detect sequence from the USB 3.0 host as CYUSB301x-xxxx Rev. D, C, B Workaround provided a valid U1 exit LFPS burst. CYUSB201x-xxxx 10. I2C Data Valid (tVD:DAT) specification violation at 400 kHz CYUSB301x-xxxx Rev. D, C, B No workaround needed with a 40/60 duty cycle. CYUSB201x-xxxx 11. FX3 Device does not respond correctly to Port Capability CYUSB301x-xxxx Rev. D, C, B Workaround provided Request from Host after multiple power cycles. CYUSB201x-xxxx Document Number: 001-52136 Rev. *X Page 47 of 58

CYUSB301X/CYUSB201X 1.Turning off VIO1 during Normal, Suspend, and Standby modes causes the FX3 to stop working. ■Problem Definition Turning off the VIO1 during Normal, Suspend, and Standby modes will cause the FX3 to stop working. ■Parameters Affected N/A ■Trigger Conditions This condition is triggered when the VIO1 is turned off during Normal, Suspend, and Standby modes. ■Scope Of Impact FX3 stops working. ■Workaround VIO1 must stay on during Normal, Suspend, and Standby modes. ■Fix Status No fix. Workaround is required. 2.USB enumeration failure in USB boot mode when FX3 is self-powered. ■Problem Definition When FX3 is self-powered and not connected to the USB host, it enters low-power mode and does not wake up when connected to USB host afterwards. This is because the bootloader does not check the VBUS pin on the connector to detect USB connection. It expects that the USB bus is connected to the host when it is powered on. ■Parameters Affected N/A ■Trigger Conditions This condition is triggered when FX3 is self-powered in USB boot mode. ■Scope Of Impact Device does not enumerate ■Workaround Reset the device after connecting to USB host. ■Fix Status No fix. Workaround is required. 3.Extra ZLP is generated by the COMMIT action in the GPIF II state. ■Problem Definition When COMMIT action is used in a GPIF-II state without IN_DATA action then an extra Zero Length Packet (ZLP) is committed along with the data packets. ■Parameters Affected N/A ■Trigger Conditions This condition is triggered when COMMIT action is used in a state without IN_DATA action. ■Scope Of Impact Extra ZLP is generated. ■Workaround Use IN_DATA action along with COMMIT action in the same state. ■Fix Status No fix. Workaround is required. Document Number: 001-52136 Rev. *X Page 48 of 58

CYUSB301X/CYUSB201X 4.Invalid PID Sequence in USB 2.0 ISOC data transfer. ■Problem Definition When the FX3 device is functioning as a high speed USB device with high bandwidth isochronous endpoints, the PID sequence of the ISO data packets is governed solely by the isomult setting. The length of the data packet is not considered while generating the PID sequence during each microframe. For example, even if a short packet is being sent on an endpoint with MULT set to 2; the PID used will be DATA2 ■Parameters Affected N/A ■Trigger Conditions This condition is triggered when high bandwidth ISOC transfer endpoints are used. ■Scope Of Impact ISOC data transfers failure. ■Workaround This problem can be worked around by reconfiguring the endpoint with a lower isomult setting prior to sending short packets, and then switching back to the original value. ■Fix Status No fix. Workaround is required. 5.USB data transfer errors are seen when ZLP is followed by data packet within same microframe. ■Problem Definition Some data transfer errors may be seen if a Zero Length Packet is followed very quickly (within one microframe or 125 us) by another data packet on a burst enabled USB IN endpoint operating at super speed. ■Parameters Affected N/A ■Trigger Conditions This condition is triggered in SuperSpeed transfer with ZLPs ■Scope Of Impact Data failure and lower data speed. ■Workaround The solution is to ensure that some time is allowed to elapse between a ZLP and the next data packet on burst enabled USB IN endpoints. If this cannot be ensured at the data source, the CyU3PDmaChannelSetSuspend() API can be used to suspend the corresponding USB DMA socket on seeing the EOP condition. The channel operation can then be resumed as soon as the suspend callback is received. ■Fix Status No fix. Workaround is required. 6.Bus collision is seen when the I2C block is used as a master in the I2C Multi-master configuration. ■Problem Definition When FX3 is used as a master in the I2C multi-master configuration, there can be occasional bus collisions. ■Parameters Affected NA ■Trigger Conditions This condition is triggered only when the FX3 I2C block operates in Multi-master configuration. ■Scope Of Impact The FX3 I2C block can transmit data when the I2C bus is not idle leading to bus collision. ■Workaround Use FX3 as a single master. ■Fix Status No fix. Document Number: 001-52136 Rev. *X Page 49 of 58

CYUSB301X/CYUSB201X 7.Low Power U1 Fast-Exit Issue with USB3.0 host controller. ■Problem Definition When FX3 device transitions from Low power U1 state to U0 state within 5 µs after entering U1 state, the device sometimes fails to transition back to U0 state, resulting in USB Reset. ■Parameters Affected N/A ■Trigger Conditions This condition is triggered during low power transition mode. ■Scope Of Impact Unexpected USB warm reset during data transfer. ■Workaround This problem can be worked around in the FW by disabling LPM (Link Power Management) during data transfer. ■Fix Status FW workaround is proven and reliable. 8.USB data corruption when operating on hosts with poor link quality. ■Problem Definition If FX3 is operating on a USB 3.0 link with poor signal quality, the device could send corrupted data on any of the IN endpoints (including the control endpoint). ■Parameters Affected N/A ■Trigger Conditions This condition is triggered when the USB3.0 link signal quality is very poor. ■Scope Of Impact Data corruption in any of the IN endpoints (including the control endpoint). ■Workaround The application firmware should perform an error recovery by stalling the endpoint on receiving CYU3P_USBEPSS_RESET_EVT event, and then stop and restart DMA path when the CLEAR_FEATURE request is received. Note: SDK versions 1.3.3 and above internally manages the DMA transfers and performs the endpoint reset when potential error conditions are seen. For more details in application firmware, please refer to GpiftoUsb example available with SDK. ■Fix Status FW Work-around is proven and reliable. Document Number: 001-52136 Rev. *X Page 50 of 58

CYUSB301X/CYUSB201X 9.Device treats Rx Detect sequence from the USB 3.0 host as a valid U1 exit LFPS burst. ■Problem Definition The USB 3.0 PHY in the FX3 device uses an electrical idle detector to determine whether LFPS is being received. The duration for which the receiver does not see an electrical idle condition is timed to detect various LFPS bursts. This implementation causes the device to treat an Rx Detect sequence from the USB host as a valid U1 exit LFPS burst. ■Parameters Affected NA ■Trigger Conditions This condition is triggered when the USB host is initiating an Rx Detect sequence while the USB 3.0 Link State Machine on the FX3 is in the U1 state. Since the host will only perform Rx Detect sequence in the RX Detect and U2 states, the error condition is seen only in cases where the USB link on the host has moved into the U2 state while the link on FX3 is in the U1 state. ■Scope Of Impact FX3 moves into Recovery prematurely leading to a Recovery failure followed by Warm Reset and USB re-enumeration. This sequence can repeat multiple times resulting in data transfer failures. ■Workaround FX3 can be configured to transition from U1 to U2 a few microseconds before the host does so. This will ensure that the link will be in U2 on the device side before the host attempts any Rx Detect sequence; thereby preventing a false detection of U1 exit. ■Fix Status Workaround is implemented in FX3 SDK library 1.3.4 and above. 10.I2C Data Valid (tVD:DAT) specification violation at 400 kHz with a 40/60 duty cycle. ■Problem Definition I2C Data Valid (tVD:DAT) parameter at 400 kHz with a 40/60 duty cycle is 1.0625 µs, which exceeds the I2C specification limit of 0.9 µs. ■Parameters Affected N/A ■Trigger Conditions This violation occurs only at 400 kHz with a 40/60 duty cycle of the I2C clock. ■Scope Of Impact Setup time (t ) is met with a huge margin for the transmitted data for 400 kHz and so t violation will not cause any data SUDAT vd:DAT integrity issues. ■Workaround No workaround needed. ■Fix Status No fix needed. Document Number: 001-52136 Rev. *X Page 51 of 58

CYUSB301X/CYUSB201X 11.FX3 Device does not respond correctly to Port Capability Request from Host after multiple power cycles. ■Problem Definition During multiple power cycles, sometimes the FX3 device does not respond correctly to the Port Capability request (Link Packet) from the USB Controller. In view of this, FX3 does not get the subsequent Port Configuration request from the USB controller, resulting in SS.Disabled state. The device fails to recover from this state and finally results in enumeration failure. ■Parameters Affected N/A ■Trigger Conditions This condition is triggered when the FX3 provides an incorrect response to the Port Capability request from the host. ■Scope Of Impact Device fails to enumerate after multiple retries. ■Workaround Since the host does not send the Port Configuration request to the FX3 device, it causes a Port Configuration request timeout interrupt to be triggered in the device. This interrupt is handled in the FX3 SDK 1.3.4 onwards to generate and signal CY_U3P_US- B_EVENT_LMP_EXCH_FAIL event to the application. This event should be handled in the user application such that it does a USB Interface Block Restart. Refer the Knowledge Base Article (KBA225778) for more details and the firmware workaround example project. ■Fix Status Suggested firmware work-around is proven and reliable. Document Number: 001-52136 Rev. *X Page 52 of 58

CYUSB301X/CYUSB201X Document History Page Document Title: CYUSB301X/CYUSB201X, EZ-USB® FX3: SuperSpeed USB Controller Document Number: 001-52136 Orig. of Submission Revision ECN Description of Change Change Date ** 2669761 VSO / 03/06/2009 New data sheet. PYRS *A 2758370 VSO 09/01/2009 Updated the part# from CYX01XXBB to CYUSB3011-BZXI Changed the title from “ADVANCE” to “ADVANCE INFORMATION” In page 1, the second bullet (Flexible Host Interface), add “32-bit, 100 MHz” to first sub bullet. In page 1, changed the second bullet “Flexible Host Interface” to General Programmable Interface”. In page 1, the second bullet (Flexible Host Interface), removed "DMA Slave Support” and "MMC Slave support with Pass through Boot" sub bullets. In page 1, third bullet, changed "50 A with Core Power" to "60 A with Core Power" In page 1, fifth bullet, added "at 1 MHz" In page 1, seventh bullet, added "up to 4MHz" to UART In page 1, Applications Section, move “Digital Still Cameras” to second line. In page 1, Applications Section, added “Machine Vision” and Industrial Cameras” Added ™ to GPIF and FX3. In page 1, updated Logic Block Diagram. In page 2, section of “Functional Overview”, updated the whole section. In page 2, removed the section of “Product Interface” In page 2, removed the section of “Processor Interface (P-Port)” In page 2, removed the section of “USB Interface (U-Port)” In page 2, removed the section of “Other Interfaces” In page 2, added a section of "GPIF II" In page 2, added a section of "CPU" In page 2, added a section of "JTAG Interface" In page 2, added a section of "Boot Options" In page 2, added a section of "ReNumeration" In page 2, added a section of "Power" In the section of “Package”, replaced “West Bridge USB 3.0 Platform” by FX3. In the section of “Package”, added 0.8 mm pitch in front of BGA. Added Pin List (Table1) *B 2779196 VSO/PYRS 09/29/2009 Features: Added the thrid bullet “Fully accessible 32-bit ARM9 core with 512kB of embedded SRAM” Added the thrid line “EZ USB™ Software and DVK for easy code development” Table1: Pin 74, corrected to NC - No Connect. Changed title to EZ-USB™ FX3: SuperSpeed USB Controller *C 2823531 OSG 12/08/2009 Added data sheet to the USB3.0 EROS spec 001-51884. No technical updates. *D 3080927 OSG 11/08/2010 Changed status from Advance to Preliminary Changed part number from CYUSB3011 to CYUSB3014 Added the following sections: Power, Digital I/Os, Digital I/Os, System-level ESD, DC Specifications, AC Timing Parameters, Reset Sequence, Package Diagram Added DC Specifications table Updated feature list Updated Pin List Added support for selectable clock input frequencies. Updated block diagram Updated part number Updated package diagram Document Number: 001-52136 Rev. *X Page 53 of 58

CYUSB301X/CYUSB201X Document History Page (continued) Document Title: CYUSB301X/CYUSB201X, EZ-USB® FX3: SuperSpeed USB Controller Document Number: 001-52136 Orig. of Submission Revision ECN Description of Change Change Date *E 3204393 OSG 03/24/2011 Updated Slave FIFO protocol and added ZLP signaling protocol Changed GPIFII asynchronous tDO parameter Changed Async Slave FIFO tOE parameter Changed Async Slave FIFO tRDO parameter Added tCOE parameter to GPIFII Sync mode timing parameters Renamed GPIFII Sync mode tDO to tCO and tDO_ss0 to tCO_ss0 Modified description of GPIFII Sync tCO (previously tDO) parameter Changed tAH(address hold time) parameter in Async Slave FIFO modes to be with respect to rising edge of SLWR#/SLRD# instead of falling edge. Correspondingly, changed the tAH number. Removed 24 bit data bus support for GPIFII. *F 3219493 OSG 04/07/2011 Minor ECN - Release to web. No content changes. *G 3235250 GSZ 04/20/2011 Minor updates in Features. *H 3217917 OSG 04/06/2011 Updated GPIFII Synchronous Timing diagram. Added SPI Boot option. Corrected values of R_USB2 and R_USB3. Corrected TCK and TRST# pull-up/pull-down configuration. Minor updates to block diagrams. Corrected Synchronous Slave FIFO tDH parameter. *I 3305568 DSG 07/07/2011 Minor ECN - Correct ECN number in revision *F. No content changes. *J 3369042 OSG 12/06/2011 Changed datasheet status from Preliminary to Final. Changed tWRPE parameter to 2ns Updated tRR and tRPW for crystal input Added clarification regarding I and I OZ IX Updated Sync SLave FIFO Read timing diagram Updated SPI timing diagram Removed tGRANULARITY parameter Updated I2S Timing diagram and tTd parameter Updated 121-ball BGA package diagram. Added clarification regarding VCC in DC Specifications table In Power Modes description, stated that VIO1 cannot be turned off at any time if the GPIFII is used in the application Updated Absolute Maximum Ratings Added requirement for by-pass capacitor on U3RX and U3TX VDDQ VDDQ Updated tPEI parameter in Async Slave FIFO timing table Updated Sync Slave FIFO write and read timing diagrams Updated I2C interface tVD:ACK parameter for 1MHz operation Clarified that CTL[15] is not usable as a GPIO *K 3534275 OSG 02/24/2012 Corrected typo in the block diagram. *L 3649782 OSG 08/16/2012 Changed part number to CYUSB301X. Added 256 KB range for embedded SRAM. Updated Functional Overview, Other Interfaces, and Clocking sections. Added Pin List for CYUSB3011 and CYUSB3013 parts. Updated Ordering Information with new part numbers. *M 3848148 OSG 12/20/2012 Updated 121-ball BGA package diagram to current revision. *N 4016006 OSG 05/31/2013 Included Commercial Temperature Range related information in all instances across the document. Included 131-ball WLCSP Package related information in all instances across the document. Updated Pin Description: Updated Table7. Updated Package Diagram: Added 131-ball WLCSP Package Diagram. Updated Ordering Information: Updated part numbers. Document Number: 001-52136 Rev. *X Page 54 of 58

CYUSB301X/CYUSB201X Document History Page (continued) Document Title: CYUSB301X/CYUSB201X, EZ-USB® FX3: SuperSpeed USB Controller Document Number: 001-52136 Orig. of Submission Revision ECN Description of Change Change Date *O 4368374 RSKV 05/02/2014 Updated Package Diagram: spec 001-62221 – Changed revision from *B to *C. Updated to new template. Completing Sunset Review. *P 4474200 ANOP 08/14/2014 Added CYUSB201x MPNs, ball map, and pin list to the datasheet. *Q 4668496 DBIR 02/24/2015 Updated Features: Updated description. Updated Logic Block Diagram. Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Added More Information. Updated Functional Overview: Updated Application Examples: Updated Figure 1. Updated Figure 2. Updated USB Interface: Updated description. Removed Figure “USB Interface Signals”. Updated Reset: Updated Hard Reset: Updated description. Updated Pin Configurations: Updated Figure 6. Updated Pin Description: Updated Table7: Updated entire table. Modified CVDDQ power domain description. Removed Table “CYUSB3011 and CYUSB3013 Pin List (GPIF II with 16-bit Data Bus Width)”. Removed Table “CYUSB2014 Pin List (GPIF II with 32-bit Data Bus Width)”. Updated DC Specifications: Added ISS parameter and its details. Updated Slave FIFO Interface: Updated Synchronous Slave FIFO Read Sequence Description: Updated Figure11. Updated Synchronous Slave FIFO Write Sequence Description: Updated Figure12. Updated Table15. Updated AC Timing Parameters: Added Host Processor Interface (P-Port) Timing. Updated Acronyms. Added Errata. Replaced West Bridge Benicia with FX3. *R 4703347 AMDK 03/27/2015 Updated Slave FIFO Interface: Updated Synchronous Slave FIFO Read Sequence Description: Updated Figure11. Updated Synchronous Slave FIFO Write Sequence Description: Updated Figure12. Updated Table15: Updated minimum value of tSSD parameter. Added tACCD, tFAD parameters and their details. Document Number: 001-52136 Rev. *X Page 55 of 58

CYUSB301X/CYUSB201X Document History Page (continued) Document Title: CYUSB301X/CYUSB201X, EZ-USB® FX3: SuperSpeed USB Controller Document Number: 001-52136 Orig. of Submission Revision ECN Description of Change Change Date *S 5160624 AJAI 04/07/2016 Updated Electrical Specifications: Updated DC Specifications: Updated Table8 (Removed I parameter and its corresponding details). SS Updated Errata: Updated Errata Summary: Updated description. Added item “Bus collision is seen when the I2C block is used as a master in the I2C Multi-master configuration.” and its corresponding details in the table. *T 5306567 MDDD 06/29/2016 Updated AC Timing Parameters: Updated GPIF II Timing: Updated Table13: Changed maximum value of t parameter from 8 ns to 7 ns. CO Updated Slave FIFO Interface: Updated Synchronous Slave FIFO Write Sequence Description: Updated Table15: Changed maximum value of t parameter from 8 ns to 7 ns. CO Updated to new template. *U 5703914 GNKK 04/20/2017 Updated Cypress logo and copyright information. *V 6033885 DBIR 02/19/2018 Removed 131-ball WLCSP Package related information in all instances across the document. Updated Package Diagram: spec 001-54471 – Changed revision from *E to *F. Updated to new template. *W 6230334 HPPC 09/25/2018 Updated Features: Updated description. Updated More Information: Updated description. Updated Functional Overview: Updated description. Updated USB Interface: Removed “EZ-Dtect”. Updated JTAG Interface: Updated description. Updated Other Interfaces: Updated I2S Interface: Updated description. Updated Boot Options: Updated description. Updated Power: Updated description. Updated Table6. Updated Pin Configurations: Updated Figure6. Updated Figure7. Updated Pin Description: Updated Table7. Updated Electrical Specifications: Updated DC Specifications: Updated Table8. Added Table9. Added Thermal Characteristics. Updated AC Timing Parameters: Added GPIF II lines AC characteristics at 100 MHz. Added GPIF II PCLK Jitter characteristics. Document Number: 001-52136 Rev. *X Page 56 of 58

CYUSB301X/CYUSB201X Document History Page (continued) Document Title: CYUSB301X/CYUSB201X, EZ-USB® FX3: SuperSpeed USB Controller Document Number: 001-52136 Orig. of Submission Revision ECN Description of Change Change Date *W (cont.) 6230334 HPPC 09/25/2018 Updated Errata: Updated description. Updated Errata Summary: Updated description. Updated details in “Silicon Revision” column for all items in the table. Added items “Low Power U1 Fast-Exit Issue with USB3.0 host controller.”, “USB data corruption when operating on hosts with poor link quality.”, “Device treats Rx Detect sequence from the USB 3.0 host as a valid U1 exit LFPS burst.”, “I2C Data Valid (tVD:DAT) specification violation at 400 kHz with a 40/60 duty cycle.” and their corresponding details in the table. *X 6413477 HPPC 12/17/2018 Updated Pin Description: Updated Table7. Updated Errata: Updated Errata Summary: Updated description. Added item “FX3 Device does not respond correctly to Port Capability Request from Host after multiple power cycles.” and its corresponding details in the table. Document Number: 001-52136 Rev. *X Page 57 of 58

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