® PSoC 5LP: CY8C56LP Family Datasheet ® Programmable System-on-Chip (PSoC ) General Description PSoC® 5LP is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a microcontroller on a single chip. The PSoC 5LP architecture boosts performance through: 32-bit ARM® Cortex®-M3 core plus DMA controller and digital filter processor, at up to 80 MHz Ultra low power with industry's widest voltage range Programmable digital and analog peripherals enable custom functions Flexible routing of any analog or digital peripheral function to any pin PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality. Features Operating characteristics Analog peripherals Voltage range: 1.71 to 5.5 V, up to 6 power domains Configurable 8- to 12-bit delta-sigma ADC Temperature range (ambient): –40 to 85 °C[1] Up to two 12-bit SAR ADCs Extended temperature parts: –40 to 105 °C Four 8-bit DACs DC to 80-MHz operation Four comparators Power modes Four opamps • Active mode 3.1 mA at 6 MHz, and 15.4 mA at 48 MHz Four programmable analog blocks, to create: • 2-µA sleep mode • Programmable gain amplifier (PGA) • 300-nA hibernate mode with RAM retention • Transimpedance amplifier (TIA) Boost regulator from 0.5-V input up to 5-V output • Mixer • Sample and hold circuit Performance 32-bit ARM Cortex-M3 CPU, 32 interrupt inputs CapSense® support, up to 62 sensors 24-channel direct memory access (DMA) controller 1.024 V ±0.1% internal voltage reference 24-bit 64-tap fixed-point digital filter processor (DFB) Versatile I/O system Memories 48 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs) Up to 256 KB program flash, with cache and security features Up to eight performance I/O (SIO) pins Up to 32 KB additional flash for error correcting code (ECC) • 25 mA current sink Up to 64 KB RAM • Programmable input threshold and output high voltages 2 KB EEPROM • Can act as a general-purpose comparator Digital peripherals • Hot swap capability and overvoltage tolerance Four 16-bit timer, counter, and PWM (TCPWM) blocks Two USBIO pins that can be used as GPIOs I2C, 1 Mbps bus speed Route any digital or analog peripheral to any GPIO UfaSceB (2T.I0D c#e1r0ti8fi4e0d0 F3u2l)l- Suspienegd i n(FteSrn) a1l2 o Mscbilplast opre[2r]ipheral inter- LCCaDpS deirnescet sduripvpeo frrto fmro amn ya nGyP GIOP,I Oup to 46 × 16 segments Full CAN 2.0b, 16 Rx, 8 Tx buffers 1.2-V to 5.5-V interface voltages, up to four power domains 20 to 24 universal digital blocks (UDB), programmable to create any number of functions: Programming, debug, and trace • 8-, 16-, 24-, and 32-bit timers, counters, and PWMs JTAG (4-wire), serial wire debug (SWD) (2-wire), single wire • I2C, UART, SPI, I2S, LIN 2.0 interfaces viewer (SWV), and Traceport (5-wire) interfaces • Cyclic redundancy check (CRC) ARM debug and trace modules embedded in the CPU core • Pseudo random sequence (PRS) generators Bootloader programming through I2C, SPI, UART, USB, and other interfaces • Quadrature decoders Package options: 68-pin QFN,100-pin TQFP, and 99-pin CSP • Gate-level logic functions Development support with free PSoC Creator™ tool Programmable clocking Schematic and firmware design support 3- to 74-MHz internal oscillator, 1% accuracy at 3 MHz Over 100 PSoC Components™ integrate multiple ICs and 4- to 25-MHz external crystal oscillator system interfaces into one PSoC. Components are free Internal PLL clock generation up to 80 MHz embedded ICs represented by icons. Drag and drop component icons to design systems in PSoC Creator. Low-power internal oscillator at 1, 33, and 100 kHz 32.768-kHz external watch crystal oscillator Icnocmlupdileesr free GCC compiler, supports Keil/ARM MDK 12 clock dividers routable to any peripheral or I/O Supports device programming and debugging Notes 1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. This feature on select devices only. See Ordering Information on page 119 for details. CypressSemiconductorCorporation • 198 Champion Court • SanJose,CA 95134-1709 • 408-943-2600 Document Number: 001-84935 Rev. *L Revised April 20, 2017

® PSoC 5LP: CY8C56LP Family Datasheet More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 5LP: Overview: PSoC Portfolio, PSoC Roadmap Development Kits: Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC5LP CY8CKIT-059 is a low-cost platform for prototyping, with a In addition, PSoC Creator includes a device selection tool. unique snap-away programmer and debugger on the USB connector. Application notes: Cypress offers a large number of PSoC application notes and code examples covering a broad range CY8CKIT-050 is designed for analog performance, for devel- oping high-precision analog, low-power, and low-voltage ap- of topics, from basic to advanced level. Recommended appli- plications. cation notes for getting started with PSoC 5LP are: CY8CKIT-001 provides a common development platform for AN77759: Getting Started With PSoC 5LP any one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP AN77835: PSoC 3 to PSoC 5LP Migration Guide families of devices. AN61290: Hardware Design Considerations The MiniProg3 device provides an interface for flash pro- AN57821: Mixed Signal Circuit Board Layout gramming and debug. AN58304: Pin Selection for Analog Designs Technical Reference Manuals (TRM) AN81623: Digital Design Best Practices Architecture TRM AN73854: Introduction To Bootloaders Registers TRM Programming Specification PSoC Creator PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100 pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can: 1.Drag and drop component icons to build your hardware 3.Configure components using the configuration tools system design in the main design workspace 4.Explore the library of 100+ components 2.Codesign your application firmware with the PSoC hardware, 5.Review component datasheets using the PSoC Creator IDE C compiler Figure 1. Multiple-Sensor Example Project in PSoC Creator 1 2 3 4 5 Document Number: 001-84935 Rev. *L Page 2 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Contents 1. Architectural Overview .................................................4 9. Programming, Debug Interfaces, Resources ............61 2. Pinouts ...........................................................................6 9.1 JTAG Interface .....................................................62 9.2 SWD Interface ......................................................63 3. Pin Descriptions ..........................................................11 9.3 Debug Features ....................................................64 4. CPU ...............................................................................12 9.4 Trace Features .....................................................64 4.1 ARM Cortex-M3 CPU ...........................................12 9.5 SWV and TRACEPORT Interfaces ......................64 4.2 Cache Controller ..................................................14 9.6 Programming Features .........................................64 4.3 DMA and PHUB ...................................................15 9.7 Device Security ....................................................64 4.4 Interrupt Controller ...............................................17 9.8 CSP Package Bootloader .....................................65 5. Memory .........................................................................19 10. Development Support ...............................................65 5.1 Static RAM ...........................................................19 10.1 Documentation ...................................................65 5.2 Flash Program Memory ........................................19 10.2 Online .................................................................65 5.3 Flash Security .......................................................19 10.3 Tools ...................................................................65 5.4 EEPROM ..............................................................19 11. Electrical Specifications ...........................................66 5.5 Nonvolatile Latches (NVLs) ..................................20 11.1 Absolute Maximum Ratings ................................66 5.6 External Memory Interface ...................................21 11.2 Device Level Specifications ................................67 5.7 Memory Map ........................................................22 11.3 Power Regulators ...............................................71 6. System Integration ......................................................23 11.4 Inputs and Outputs .............................................75 6.1 Clocking System ...................................................23 11.5 Analog Peripherals .............................................83 6.2 Power System ......................................................26 11.6 Digital Peripherals ............................................104 6.3 Reset ....................................................................30 11.7 Memory ............................................................108 6.4 I/O System and Routing .......................................32 11.8 PSoC System Resources .................................112 7. Digital Subsystem .......................................................38 11.9 Clocking ............................................................115 7.1 Example Peripherals ............................................39 12. Ordering Information ...............................................119 7.2 Universal Digital Block ..........................................40 12.1 Part Numbering Conventions ...........................120 7.3 UDB Array Description .........................................44 13. Packaging .................................................................121 7.4 DSI Routing Interface Description ........................44 7.5 CAN ......................................................................46 14. Acronyms .................................................................124 7.6 USB ......................................................................47 15. Reference Documents .............................................125 7.7 Timers, Counters, and PWMs ..............................48 16. Document Conventions ..........................................126 7.8 I2C ........................................................................48 16.1 Units of Measure ..............................................126 7.9 Digital Filter Block .................................................50 Document History Page................................................ 127 8. Analog Subsystem ......................................................50 Sales, Solutions, and Legal Information..................... 131 8.1 Analog Routing .....................................................52 Worldwide Sales and Design Support...................... 131 8.2 Delta-sigma ADC ..................................................54 Products................................................................... 131 8.3 Successive Approximation ADCs .........................55 PSoC® Solutions..................................................... 131 8.4 Comparators .........................................................55 Cypress Developer Community................................ 131 8.5 Opamps ................................................................57 Technical Support.................................................... 131 8.6 Programmable SC/CT Blocks ..............................57 8.7 LCD Direct Drive ..................................................58 8.8 CapSense .............................................................59 8.9 Temp Sensor ........................................................59 8.10 DAC ....................................................................59 8.11 Up/Down Mixer ...................................................60 8.12 Sample and Hold ................................................61 Document Number: 001-84935 Rev. *L Page 3 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 1. Architectural Overview Introducing the CY8C56LP family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit PSoC3 and 32-bit PSoC 5LP platform. The CY8C56LP family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure 1-1. Simplified Block Diagram Analog Interconnect Digital Interconnect O Os System Wide Digital System SI PI Resources Universal Digital Block Array (24 x UDB) I2C (4O-2p5tiMonHazl) G Xtal or UDB 8T-imBietU rDBQuadrature DUeDcBoder Sequencer UDB1P6W-BMit 16-BUitD PBRS UDB UDB CAN 2.0 MSalasvteer/ USB 22  3(2O.7p6t8io KnaHl)z GPIOs OIMsOc Clock Tree Usage Example f I2C UUSUlDDDaBBvBe 8-BiUUUt SDDDPBBBI 1L2o-gBUUiUciDDtD SBBBPI 8T-imBieUUUt rDDDBBBLogic UUUDDDBBB UUUDDDBBB CPTo4iWum xnMetre r FS2 U.0SB PHGPIOsY UART 12-Bit PWM RTC Timer System Bus Memory System CPU System Program & Os WDT Debug PI Waankde EEPROM SRAM Cortex M3 CPU CIontnetrrroullpetr Program G GPIOs EMIF FLASH Cache PHUB BoDTuernbaducager &y ILO Controller DMA Scan Clocking System SIOs PoweSry Mstaenmagement LCDDr iDveirect DBFiligloticetakrl AADnCaslog System 4 x + GPIOs POR and 2 x Opamp 3 per LVD SAR - Opamp 4 x SC/CT Blocks ADC Sleep (TIA, PGA, Mixer etc) Power 1.71 to5.5V 1.8V LDO TemSpeenrsaoturre 4x DAC De1l xS ig C4M xP +- GPIOs SMP CapSense ADC 0.5 to 5.5V (Optional) Figure1-1 illustrates the major components of the CY8C56LP PSoC’s digital subsystem provides half of its unique family. They are: configurability. It connects a digital signal from any peripheral to any pin through the digital system interconnect (DSI). It also ARM Cortex-M3 CPU subsystem provides functional flexibility through an array of small, fast, low Nonvolatile subsystem power UDBs. PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, Programming, debug, and test subsystem timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. You can also easily create a digital circuit using Inputs and outputs boolean primitives by means of graphical design entry. Each Clocking UDB contains programmable array logic (PAL)/programmable logic device (PLD) functionality, together with a small state Power machine engine to support a wide variety of peripherals. In Digital subsystem addition to the flexibility of the UDB array, PSoC also provides configurable digital blocks targeted at specific functions. For the Analog subsystem CY8C56LP family these blocks can include four 16-bit timer, counter, and PWM blocks; I2C slave, master, and multi-master; Full-Speed USB; and Full CAN 2.0. Document Number: 001-84935 Rev. *L Page 4 of 131

® PSoC 5LP: CY8C56LP Family Datasheet For more details on the peripherals see the “Example Transimpedance amplifiers Peripherals” section on page39 of this datasheet. For Programmable gain amplifiers information on UDBs, DSI, and other digital blocks, see the Mixers “Digital Subsystem” section on page38 of this datasheet. Other similar analog components PSoC’s analog subsystem is the second half of its unique See the “Analog Subsystem” section on page50 of this configurability. All analog performance is based on a highly datasheet for more details. accurate absolute voltage reference with less than 0.1% error PSoC’s CPU subsystem is built around a 32-bit three-stage over temperature and voltage. The configurable analog pipelined ARM Cortex-M3 processor running at up to 80 MHz. subsystem includes: The Cortex-M3 includes a tightly integrated nested vectored Analog muxes interrupt controller (NVIC) and various debug and trace modules. The overall CPU subsystem includes a DMA controller, flash Comparators cache, and RAM. The NVIC provides low latency, nested Analog mixers interrupts, and tail-chaining of interrupts and other features to increase the efficiency of interrupt handling. The DMA controller Voltage references enables peripherals to exchange data without CPU involvement. This allows the CPU to run slower (saving power) or use those ADCs CPU cycles to improve the performance of firmware algorithms. DACs The flash cache also reduces system power consumption by allowing less frequent flash access. DFB PSoC’s nonvolatile subsystem consists of flash, byte-writeable All GPIO pins can route analog signals into and out of the device EEPROM, and nonvolatile configuration options. It provides up using the internal analog bus. This allows the device to interface to 256KB of on-chip flash. The CPU can reprogram individual up to 62 discrete analog signals. blocks of flash, enabling boot loaders. You can enable an ECC Some CY8C56LP devices offer a fast, accurate, configurable for high reliability applications. A powerful and flexible protection delta-sigma ADC with these features: model secures the user's sensitive information, allowing selective memory block locking for read and write protection. Less than 100 µV offset Two KB of byte-writable EEPROM is available on-chip to store A gain error of 0.2 percent application data. Additionally, selected configuration options such as boot speed and pin drive mode are stored in nonvolatile INL less than ±1 LSB memory. This allows settings to activate immediately after power on reset (POR). DNL less than ±1 LSB The three types of PSoC I/O are extremely flexible. All I/Os have SINAD better than 66 dB many drive modes that are set at POR. PSoC also provides up The CY8C56LP family also offers one or two successive to four I/O voltage domains through the VDDIO pins. Every GPIO approximation register(SAR) ADCs, depending on device has analog I/O, LCD drive, CapSense, flexible interrupt selected. Featuring 12-bit conversions at up to 1 M samples per generation, slew rate control, and digital I/O capability. The SIOs second, they also offer low nonlinearity and offset errors and on PSoC allow V to be set independently of VDDIO when used OH SNR better than 70 dB. They are well suited for a variety of as outputs. When SIOs are in input mode they are high higher speed analog applications. impedance. This is true even when the device is not powered or when the pin voltage goes above the supply voltage. This makes The output of either ADC can optionally feed the programmable the SIO ideally suited for use on an I2C bus where the PSoC may DFB via DMA without CPU intervention. You can configure the not be powered when other devices on the bus are. The SIO pins DFB to perform IIR and FIR digital filters and several user also have high current sink capability for applications such as defined custom functions. The DFB can implement filters with up LED drives. The programmable input threshold feature of the to 64 taps. It can perform a 48-bit multiply-accumulate (MAC) SIO can be used to make the SIO function as a general purpose operation in one clock cycle. analog comparator. For devices with FS USB the USB physical Four high speed voltage or current DACs support 8-bit output interface is also provided (USBIO). When not using USB these signals at an update rate of up to 8 Msps. They can be routed pins may also be used for limited digital functionality and device out of any GPIO pin. You can create higher resolution voltage programming. All the features of the PSoC I/Os are covered in PWM DAC outputs using the UDB array. This can be used to detail in the “I/O System and Routing” section on page32 of this create a pulse width modulated (PWM) DAC of up to 10 bits, at datasheet. up to 48kHz. The digital DACs in each UDB support PWM, PRS, The PSoC device incorporates flexible internal clock generators, or delta-sigma algorithms with programmable widths. designed for high stability and factory trimmed for high accuracy. In addition to the ADCs, DACs, and DFB, the analog subsystem The Internal Main Oscillator (IMO) is the master clock base for provides multiple: the system, and has 1% accuracy at 3 MHz. The IMO can be configured to run from 3 MHz up to 74 MHz. Multiple clock Comparators derivatives can be generated from the main clock frequency to Uncommitted opamps meet application needs. The device provides a PLL to generate system clock frequencies up to 80 MHz from the IMO, external Configurable switched capacitor/continuous time (SC/CT) crystal, or external reference clock. It also contains a separate, blocks. These support: Document Number: 001-84935 Rev. *L Page 5 of 131

® PSoC 5LP: CY8C56LP Family Datasheet very low power internal low-speed oscillator (ILO) for the sleep 2. Pinouts and watchdog timers. A 32.768-kHz external watch crystal is also supported for use in RTC applications. The clocks, together Each VDDIO pin powers a specific set of I/O pins. (The USBIOs with programmable clock dividers, provide the flexibility to are powered from VDDD.) Using the VDDIO pins, a single PSoC integrate most timing requirements. can support multiple voltage levels, reducing the need for The CY8C56LP family supports a wide supply operating range off-chip level shifters. The black lines drawn on the pinout diagrams in Figure2-3 and Figure2-4, as well as Table2-1, from 1.71 to 5.5V. This allows operation from regulated supplies such as 1.8 ± 5%, 2.5V ±10%, 3.3V ± 10%, or 5.0 V ± 10%, or show the pins that are powered by each VDDIO. directly from a wide range of battery types. In addition, it provides Each VDDIO may source up to 100 mA total to its associated I/O an integrated high efficiency synchronous boost converter that pins, as shown in Figure2-1. can power the device from supply voltages as low as 0.5V. This enables the device to be powered directly from a single battery. Figure 2-1. VDDIO Current Limit In addition, you can use the boost converter to generate other voltages required by the device, such as a 3.3V supply for LCD IDDIO X= 100 mA glass drive. The boost’s output is available on the VBOOST pin, allowing other devices in the application to be powered from the PSoC. VDDIO X I/O Pins PSoC supports a wide range of low power modes. These include a 300 nA hibernate mode with RAM retention and a 2 µA sleep mode with RTC. In the second mode the optional 32.768-kHz PSoC watch crystal runs continuously and maintains an accurate RTC. Power to all major functional blocks, including the programmable digital and analog peripherals, can be controlled independently by firmware. This allows low power background processing when some peripherals are not in use. This, in turn, provides a total device current of only 3.1 mA when the CPU is running at 6MHz. The details of the PSoC power modes are covered in the “Power Conversely, for the 100-pin and 68-pin devices, the set of I/O System” section on page26 of this datasheet. pins associated with any VDDIO may sink up to 100 mA total, as PSoC uses JTAG (4 wire) or SWD (2 wire) interfaces for shown in Figure2-2. programming, debug, and test. Using these standard interfaces you can debug or program the PSoC with a variety of hardware Figure 2-2. I/O Pins Current Limit solutions from Cypress or third party vendors. The Cortex-M3 Ipins = 100 mA debug and trace modules include Flash Patch and Breakpoint (FPB), Data Watchpoint and Trace (DWT), Embedded Trace Macrocell (ETM), and Instrumentation Trace Macrocell (ITM). These modules have many features to help solve difficult debug VDDIO X and trace problems. Details of the programming, test, and I/O Pins debugging interfaces are discussed in the “Programming, Debug Interfaces, Resources” section on page61 of this datasheet. PSoC VSSD Note 3. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. Document Number: 001-84935 Rev. *L Page 6 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 2-3. 68-pin QFN Part Pinout[4] F) E R T X E 1]) 0]) R0 PIO, TRACEDATA[ PIO, TRACEDATA[PIO, TRACECLK) PIO)PIO)PIO) GPOI)GPIO) PIO, IDAC2)PIO, IDAC0) PIO, OPAMP2-)PIO, OPAMP2+/SA 2[5] (G DDIO22[4] (G2[3] (G 2[2] (G2[1] (G2[0] (G 15[5] (15[4] (DDDSSDCCD 0[7] (G0[6] (G 0[5] (G0[4] (GDDIO0 P VPP PPP PPVVV PP PPV 6867 6665646362616059 585756 55545352 (TRACEDATA[2], GPIO) P2[6] 1 51 P0[3] (GPIO, OPAMP0-/EXTREF0) (TRACEDATA[3], GPIO) P2[7] 2 50 P0[2] (GPIO, OPAMP0+/SAR1 EXTREF) (I2C0: SCL, SIO) P12[4] 3 49 P0[1] (GPIO, OPAMP0OUT) (I2C0: SDA, SIO) P12[5] 4 Lines show VDDIO 48 P0[0] (GPIO, OPAMP2OUT) to I/O supply VSSB 5 association 47 P12[3] (SIO) IND 6 46 P12[2] (SIO) VBOOST 7 45 VSSD VBAT 8 QFN 44 VDDA VSSD 9 43 VSSA XRES 10 (TOP VIEW) 42 VCCA (TMS, SWDIO, GPIO) P1[0] 11 41 P15[3] (GPIO, KHZ XTAL: XI) (TCK, SWDCK, GPIO) P1[1] 12 40 P15[2] (GPIO, KHZ XTAL: XO) (ConfigurableXRES, GPIO) P1[2] 13 39 P12[1] (SIO, I2C1: SDA) (TDO, SWV, GPIO) P1[3] 14 38 P12[0] (SIO, 12C1: SCL) (TDI, GPIO) P1[4] 15 37 P3[7] (GPIO, OPAMP3OUT) (NTRST, GPIO) P1[5] 16 36 P3[6] (GPIO, OPAMP1OUT) VDDIO1 17 35 VDDIO3 8901234567 8901234 1122222222 2233333 (GPIO) P1[6] (GPIO) P1[7](SIO) P12[6](SIO) P12[7][5](USBIO, D+, SWDIO) P15[6][5](USBIO, D-, SWDCK) P15[7] VDDDVSSDVCCD(MHZ XTAL: XO, GPIO) P15[0] (MHZ XTAL: XI, GPIO) P15[1](IDAC1, GPIO) P3[0](IDAC3, GPIO) P3[1]PAMP3-/EXTREF1, GPIO) P3[2] (OPAMP3+, GPIO) P3[3](OPAMP1-, GPIO) P3[4] (OPAMP1+, GPIO) P3[5] O ( Notes 4. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices. 5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. Document Number: 001-84935 Rev. *L Page 7 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 2-4. 100-pin TQFP Part Pinout F) E R T X E 0]) R0 PIO,TRACEDATA[PIO,TRACECLK])PIO)PIO)PIO)GPIO) GPIO)PIO)PIO)PIO)PIO) PIO)PIO) PIO)PIO)PIO)PIO)PIO,IDAC2)PIO,IDAC0)PIO,OPAMP2-)PIO,OPAMP2+/SA DDIO22[4](G2[3](G2[2](G2[1](G2[0](G15[5]( 15[4](6[3](G6[2](G6[1](G6[0](GDDDSSDCCD4[7](G4[6](G 4[5](G4[4](G4[3](G4[2](G0[7](G0[6](G0[5](G0[4](G VPPPPPP PPPPPVVVPP PPPPPPPP (TRACEDATA[1], GPIO) P2[5] 110099 9897969594939291 908988 87868584838281807978777675 VDDIO0 (TRACEDATA[2], GPIO) P2[6] 2 74 P0[3] (GPIO,O PAMP0-/EXTREF0) (TRACEDATA[3], GPIO) P2[7] 3 Lines show VDDIO 73 P0[2] (GPIO, OPAMP0+/SAR1 EXTREF) (I2C0: SCL, SIO) P12[4] 4 I/O Supply Association 72 P0[1] (GPIO, OPAMPOUT0) (I2C0: SDA, SIO) P12[5] 5 71 P0[0] (GPIO, OPAMPOUT2) (GPIO)P 6[4] 6 70 P4[1] (GPIO) (GPIO)P 6[5] 7 69 P4[0] (GPIO) (GPIO)P 6[6] 8 68 P12[3] (SIO) (GPIO)P 6[7] 9 67 P12[2] (SIO) VSSB 10 66 VSSD IND 11 65 VDDA VBOOST 12 64 VSSA VBAT 13 TQFP 63 VCCA VSSD 14 62 NC XRES 15 61 NC (GPIO)P 5[0] 16 60 NC (GPIO)P 5[1] 17 59 NC (GPIO)P 5[2] 18 58 NC (GPIO)P 5[3] 19 57 NC (TMS, SWDIO, GPIO)P 1[0] 20 56 P15[3] (GPIO, KHZ XTAL: XI) (TCK, SWDCK, GPIO) P1[1] 21 55 P15[2] (GPIO, KHZ XTAL:X O) (ConfigurableXRES, GPIO) P1[2] 22 54 P12[1] (SIO,I 2C1: SDA) (TDO, SWV, GPIO) P1[3] 23 53 P12[0] (SIO,I 2C1: SCL) (TDI, GPIO)P 1[4] 24 52 P3[7] (GPIO, OPAMPOUT3) (NTRST, GPIO)P 1[5] 256789012345 67890123456789051 P3[6] (GPIO, OPAMPOUT1) 2222333333 333344444444445 VDDIO1(GPIO)P1[6](GPIO)P1[7](SIO)P12[6](SIO)P12[7](GPIO)P5[4](GPIO)P5[5](GPIO)P5[6](GPIO)P5[7][6](USBIO,D+,SWDIO)P15[6][6](USBIO,D-,SWDCK)P15[7]VDDDVSSDVCCDNCNC(MHZXTAL:XO,GPIO)P15[0](MHZXTAL:XI,GPIO)P15[1](IDAC1,GPIO)P3[0](IDAC3,GPIO)P3[1](OPAMP3-/EXTREF1,GPIO)P3[2](OPAMP3+,GPIO)P3[3](OPAMP1-,GPIO)P3[4] (OPAMP1+,GPIO)P3[5]VDDIO3 Table 2-1. V and Port Pin Associations DDIO VDDIO Port Pins VDDIO0 P0[7:0], P4[7:0], P12[3:2] VDDIO1 P1[7:0], P5[7:0], P12[7:6] VDDIO2 P2[7:0], P6[7:0], P12[5:4], P15[5:4] VDDIO3 P3[7:0], P12[1:0], P15[3:0] VDDD P15[7:6] (USB D+, D-) Note 6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. Document Number: 001-84935 Rev. *L Page 8 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table2-2 shows the pinout for the 99-pin CSP package. Since there are four V pins, the set of I/O pins associated with any V DDIO DDIO may sink up to 100mA total, same as for the 100-pin and 68-pin devices. Table 2-2. CSP Pinout Ball Name Ball Name Ball Name Ball Name E5 P2[5] L2 VIO1 B2 P3[6] C8 VIO0 G6 P2[6] K2 P1[6] B3 P3[7] D7 P0[4] G5 P2[7] C9 P4[2] C3 P12[0] E7 P0[5] H6 P12[4] E8 P4[3] C4 P12[1] B9 P0[6] K7 P12[5] K1 P1[7] E3 P15[2] D8 P0[7] L8 P6[4] H2 P12[6] E4 P15[3] D9 P4[4] J6 P6[5] F4 P12[7] A1 NC F8 P4[5] H5 P6[6] J1 P5[4] A9 NC F7 P4[6] J5 P6[7] H1 P5[5] L1 NC E6 P4[7] L7 VSSB F3 P5[6] L9 NC E9 VCCD K6 Ind G1 P5[7] A3 VCCA F9 VSSD L6 VBOOST G2 P15[6] A4 VSSA G9 VDDD K5 VBAT F2 P15[7] B7 VSSA H9 P6[0] L5 VSSD E2 VDDD B8 VSSA G8 P6[1] L4 XRES F1 VSSD C7 VSSA H8 P6[2] J4 P5[0] E1 VCCD A5 VDDA J9 P6[3] K4 P5[1] D1 P15[0] A6 VSSD G7 P15[4] K3 P5[2] D2 P15[1] B5 P12[2] F6 P15[5] L3 P5[3] C1 P3[0] A7 P12[3] F5 P2[0] H4 P1[0] C2 P3[1] C5 P4[0] J7 P2[1] J3 P1[1] D3 P3[2] D5 P4[1] J8 P2[2] H3 P1[2] D4 P3[3] B6 P0[0] K9 P2[3] J2 P1[3] B4 P3[4] C6 P0[1] H7 P2[4] G4 P1[4] A2 P3[5] A8 P0[2] K8 VIO2 G3 P1[5] B1 VIO3 D6 P0[3] Figure2-5 and Figure 2-6 on page 11 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog performance on a 2-layer board. The two pins labeled VDDD must be connected together. The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-5 on page 10 and Power System on page 26. The trace between the two VCCD pins should be as short as possible. The two pins labeled VSSD must be connected together. For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board Layout Considerations for PSoC® 3 and PSoC 5. Document Number: 001-84935 Rev. *L Page 9 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 2-5. Example Schematic for 100-pin TQFP Part with Power Connections VDDD VDDD C1 C2 VDDD 1 UF 0.1 UF D VCCD 0C.61 UF VDD VSSD VDDDVSSD VSSD VSSD 100999897969594939291908988878685848382818079787776 VSSD VSSD 11111111112222229123456780123456789012345 VIVVVXPPPPPPPPPPPPPPPPPPPNSBBSR5555111111622211666D[[[[[[[[[[[[[[22[[[SOASE01230123457567456[[BTDS]]]]]]]]]]]]]]45]]]O,,,,,]] S,,SSSTN SSDTWWWTIIIROOVDDIO2VDDIO1DDVS,IC OP2[4]P1[6]TTK,D ,P2[3]P1[7]T OTMP2[2]CP12[6], SIOSKP2[1]P12[7], SIOP2[0]P5[4]P15[5]P5[5]P15[4]P5[6]P6[3]P5[7]P6[2]USB D+, P15[6]P6[1]USB D-, P15[7]P6[0]VDDDVDDDVSSDVSSDVCCDVCCDNCP4[7]NCP4[6]P15[0], MHZXOUTP4[5]P15[1], MHZXINP4[4]P3[0], IDAC1P4[3]P3[1], IDAC3OP4[2]P3[2], OA3-, REF1A0IDAC2, P0[7]P3[3], OA3++OK,IDAC0, P0[6]P3[4], OA1- HASKOOOOA2-, P0[5]0ZAP3[5], OA1+OH-AAAXR,OA2+, AVDDIO3Z 203O1RSSSS1XOOORUESAR0REF, OIIIIIOOUUUOOENTFUVTTFTP0[4],,,,,,0T D,,,,,PPPPPPVVV,V PPPPPPPD111111PCDSS4405220032250I3NNNNNNSCDSO[[[[[[[[[[[[[[01323012701236DCCCCCCAAA0]]]]]]]]]]]]]] 66666667777775555555556664135678901234523456789012 VVVVVVCDSDSSCDSDSSAA0ADDCD.181C U 9UFFVVSSSSDAVVVDDSDDS1A0AACC .11U107 FUF VDDD26272829303132333435363738394041424344454647484950 VDDD C11 0C.11 2UF VDDD VSSD VCCD VSS0D.1 UF VSSD C16 C15 0.1 UF 1 UF VSSD Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure2-6. For more information on pad layout, refer to http://www.cypress.com/cad-resources/psoc-5lp-cad-libraries. Document Number: 001-84935 Rev. *L Page 10 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance VSSA VDDD VSSD VDDA VSSA VSSD Plane Plane 3. Pin Descriptions nTRST Optional JTAG Test Reset programming and debug port IDAC0, IDAC1, IDAC2, IDAC3 connection to reset the JTAG connection. Low resistance output pin for high current DACs (IDAC). SIO. Special I/O provides interfaces to the CPU, digital Opamp0out, Opamp1out, Opamp2out, Opamp3out peripherals and interrupts with a programmable high threshold High current output of uncommitted opamp[7]. voltage, analog comparator, high sink current, and high impedance state when the device is unpowered. Extref0, Extref1 SWDCK External reference input to the analog system. Serial Wire Debug Clock programming and debug port connection. SAR0 EXTREF, SAR1 EXTREF SWDIO External references for SAR ADCs Serial Wire Debug Input and Output programming and debug Opamp0–, Opamp1–, Opamp2–, Opamp3– port connection. Inverting input to uncommitted opamp. TCK Opamp0+, Opamp1+, Opamp2+, Opamp3+ JTAG Test Clock programming and debug port connection. Noninverting input to uncommitted opamp. TDI GPIO JTAG Test Data In programming and debug port connection. General purpose I/O pin provides interfaces to the CPU, digital TDO peripherals, analog peripherals, interrupts, LCD segment drive, and CapSense[7]. JTAG Test Data Out programming and debug port connection. I2C0: SCL, I2C1: SCL TMS I2C SCL line providing wake from sleep on an address match. Any JTAG Test Mode Select programming and debug port connection. I/O pin can be used for I2C SCL if wake from sleep is not required. TRACECLK I2C0: SDA, I2C1: SDA Cortex-M3 TRACEPORT connection, clocks TRACEDATA pins. I2C SDA line providing wake from sleep on an address match. Any TRACEDATA[3:0]. I/O pin can be used for I2C SDA if wake from sleep is not required. Cortex-M3 TRACEPORT connections, output data. Ind SWV. Inductor connection to boost pump. Single Wire Viewer output. kHz XTAL: Xo, kHz XTAL: Xi USBIO, D+ 32.768-kHz crystal oscillator pin. Provides D+ connection directly to a USB 2.0 bus. May be used MHz XTAL: Xo, MHz XTAL: Xi as a digital I/O pin; it is powered from VDDD instead of from a 4 to 25 MHz crystal oscillator pin. VDDIO. Pins are Do Not Use (DNU) on devices without USB. Note 7. GPIOs with opamp outputs are not recommended for use with CapSense. Document Number: 001-84935 Rev. *L Page 11 of 131

® PSoC 5LP: CY8C56LP Family Datasheet USBIO, D– regulator (externally regulated mode), the voltage applied to this pin must not exceed the allowable range of 1.71 V to Provides D– connection directly to a USB 2.0 bus. May be used 1.89 V. When using the internal core regulator (internally as a digital I/O pin; it is powered from VDDD instead of from a regulated mode, the default), do not tie any power to this pin. For VDDIO. Pins are Do Not Use (DNU) on devices without USB. details see Power System on page 26. VBOOST VDDA Power sense connection to boost pump. Supply for all analog peripherals and analog core regulator. VBAT VDDA must be the highest voltage present on the device. All Battery supply to boost pump. other supply pins must be less than or equal to VDDA. VCCA VDDD Output of the analog core regulator or the input to the Supply for all digital peripherals and digital core regulator. VDDD analog core. Requires a 1uF capacitor to VSSA. The regulator must be less than or equal to VDDA. output is not designed to drive external circuits. Note that if you VSSA use the device with an external core regulator (externally Ground for all analog peripherals. regulated mode), the voltage applied to this pin must not VSSB exceed the allowable range of 1.71 V to 1.89 V. When using the internal core regulator, (internally regulated mode, the Ground connection for boost pump. default), do not tie any power to this pin. For details see Power VSSD System on page 26. Ground for all digital logic and I/O pins. VCCD. VDDIO0, VDDIO1, VDDIO2, VDDIO3 Output of the digital core regulator or the input to the digital Supply for I/O pins. Each VDDIO must be tied to a valid operating core. The two VCCD pins must be shorted together, with the voltage (1.71V to 5.5V), and must be less than or equal to trace between them as short as possible, and a 1uF capacitor to VDDA. VSSD. The regulator output is not designed to drive external circuits. Note that if you use the device with an external core XRES. External reset pin. Active low with internal pull-up. 4. CPU 4.1 ARM Cortex-M3 CPU The CY8C56LP family of devices has an ARM Cortex-M3 CPU core. The Cortex-M3 is a low power 32-bit three-stage pipelined Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is intended for deeply embedded applications that require fast interrupt handling features. Document Number: 001-84935 Rev. *L Page 12 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 4-1. ARM Cortex-M3 Block Diagram Data Nested Interrupt Inputs Vectored Cortex M3 CPU Core Watchpoint and Embedded Trace (DWT) Interrupt Trace Module Controller (ETM) (NVIC) Instrumentation Trace Module I-Bus D-Bus S-Bus (ITM) Trace Pins: JTAG/SWD Debug Block Trace Port 5 for TRACEPORT or (Serial and Flash Patch Interface Unit 1 for SWV mode JTAG) and Breakpoint (TPIU) (FPB) C-Bus Cortex M3 Wrapper AHB AHB 32 KB Bus SRAM Matrix Bus 256 KB 1 KB Matrix ECC Cache Flash AHB 32 KB Bus SRAM Matrix AHB Bridge & Bus Matrix DMA PHUB AHB Spokes GPIO & Prog. Prog. Special EMIF Digital Analog Functions Peripherals The Cortex-M3 CPU subsystem includes these features: 4.1.1 Cortex-M3 Features ARM Cortex-M3 CPU The Cortex-M3 CPU features include: Programmable Nested Vectored Interrupt Controller (NVIC), 4 GB address space. Predefined address regions for code, tightly integrated with the CPU core data, and peripherals. Multiple buses for efficient and Full featured debug and trace modules, tightly integrated with simultaneous accesses of instructions, data, and peripherals. the CPU core The Thumb®-2 instruction set, which offers ARM-level Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB performance at Thumb-level code density. This includes 16-bit of SRAM and 32-bit instructions. Advanced instructions include: Cache controller Bit-field control Peripheral HUB (PHUB) Hardware multiply and divide DMA controller Saturation External Memory Interface (EMIF) If-Then Wait for events and interrupts Exclusive access and barrier Special register access The Cortex-M3 does not support ARM instructions. Bit-band support for the SRAM region. Atomic bit-level write and read operations for SRAM addresses. Unaligned data storage and access. Contiguous storage of data of different byte lengths. Operation at two privilege levels (privileged and user) and in two modes (thread and handler). Some instructions can only be executed at the privileged level. There are also two stack pointers: Main (MSP) and Process (PSP). These features support a multitasking operating system running one or more user-level processes. Extensive interrupt and system exception support. Document Number: 001-84935 Rev. *L Page 13 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 4.1.2 Cortex-M3 Operating Modes Table 4-2. Cortex M3 CPU Registers (continued) The Cortex-M3 operates at either the privileged level or the user Register Description level, and in either the thread mode or the handler mode. Because the handler mode is only enabled at the privileged level, R15 R15 is the Program Counter (PC). Bit 0 of the PC there are actually only three states, as shown in Table4-1. is ignored and considered to be 0, so instructions are always aligned to a half word (2 byte) Table 4-1. Operational Level boundary. xPSR The Program status registers are divided into Condition Privileged User three status registers, which are accessed either Running an exception Handler mode Not used together or separately: Running main program Thread mode Thread mode Application Program Status Register (APSR) holds program execution status bits such as At the user level, access to certain instructions, special registers, zero, carry, negative, in bits[27:31]. configuration registers, and debugging components is blocked. Attempts to access them cause a fault exception. At the Interrupt Program Status Register (IPSR) privileged level, access to all instructions and registers is holds the current exception number in bits[0:8]. allowed. Execution Program Status Register (EPSR) The processor runs in the handler mode (always at the privileged holds control bits for interrupt continuable and level) when handling an exception, and in the thread mode when IF-THEN instructions in bits[10:15] and not. [25:26]. Bit 24 is always set to 1 to indicate Thumb mode. Trying to clear it causes a fault 4.1.3 CPU Registers exception. The Cortex-M3 CPU registers are listed in Table4-2. Registers PRIMASK A 1-bit interrupt mask register. When set, it R0-R15 are all 32 bits wide. allows only the nonmaskable interrupt (NMI) and hard fault exception. All other exceptions and Table 4-2. Cortex M3 CPU Registers interrupts are masked. Register Description FAULTMASK A 1-bit interrupt mask register. When set, it R0-R12 General purpose registers R0-R12 have no allows only the NMI. All other exceptions and special architecturally defined uses. Most interrupts are masked. instructions that specify a general purpose BASEPRI A register of up to nine bits that define the register specify R0-R12. masking priority level. When set, it disables all interrupts of the same or higher priority value. If Low Registers: Registers R0-R7 are acces- set to 0 then the masking function is disabled. sible by all instructions that specify a general purpose register. CONTROL A 2-bit register for controlling the operating mode. High Registers: Registers R8-R12 are acces- Bit 0: 0 = privileged level in thread mode, 1 = user sible by all 32-bit instructions that specify a level in thread mode. general purpose register; they are not acces- sible by all 16-bit instructions. Bit 1: 0 = default stack (MSP) is used, 1 = alternate stack is used. If in thread mode or user R13 R13 is the stack pointer register. It is a banked level then the alternate stack is the PSP. There register that switches between two 32-bit stack is no alternate stack for handler mode; the bit pointers: the Main Stack Pointer (MSP) and the must be 0 while in handler mode. Process Stack Pointer (PSP). The PSP is used only when the CPU operates at the user level in thread mode. The MSP is used in all other 4.2 Cache Controller privilege levels and modes. Bits[0:1] of the SP The CY8C56LP family has 1 KB, 4-way set-associative are ignored and considered to be 0, so the SP is instruction cache between the CPU and the flash memory. This always aligned to a word (4 byte) boundary. improves instruction execution rate and reduces system power R14 R14 is the Link Register (LR). The LR stores the consumption by requiring less frequent flash access. return address when a subroutine is called. Document Number: 001-84935 Rev. *L Page 14 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 4.3 DMA and PHUB Transactions can be stalled or canceled The PHUB and the DMA controller are responsible for data Supports transaction size of infinite or 1 to 64k bytes transfer between the CPU and peripherals, and also data transfers between peripherals. The PHUB and DMA also control Large transactions may be broken into smaller bursts of 1 to device configuration during boot. The PHUB consists of: 127 bytes A central hub that includes the DMA controller, arbiter, and TDs may be nested and/or chained for complex transactions router Multiple spokes that radiate outward from the hub to most 4.3.3 Priority Levels peripherals The CPU always has higher priority than the DMA controller There are two PHUB masters: the CPU and the DMA controller. when their accesses require the same bus resources. Due to the Both masters may initiate transactions on the bus. The DMA system architecture, the CPU can never starve the DMA. DMA channels can handle peripheral communication without CPU channels of higher priority (lower priority number) may interrupt intervention. The arbiter in the central hub determines which current DMA transfers. In the case of an interrupt, the current DMA channel is the highest priority if there are multiple requests. transfer is allowed to complete its current transaction. To ensure latency limits when multiple DMA accesses are requested 4.3.1 PHUB Features simultaneously, a fairness algorithm guarantees an interleaved minimum percentage of bus bandwidth for priority levels 2 CPU and DMA controller are both bus masters to the PHUB through 7. Priority levels 0 and 1 do not take part in the fairness Eight multi-layer AHB bus parallel access paths (spokes) for algorithm and may use 100% of the bus bandwidth. If a tie occurs peripheral access on two DMA requests of the same priority level, a simple round robin method is used to evenly share the allocated bandwidth. Simultaneous CPU and DMA access to peripherals located on The round robin allocation can be disabled for each DMA different spokes channel, allowing it to always be at the head of the line. Priority Simultaneous DMA source and destination burst transactions levels 2 to 7 are guaranteed the minimum bus bandwidth shown on different spokes in Table4-4 after the CPU and DMA priority levels 0 and 1 have satisfied their requirements. Supports 8, 16, 24, and 32-bit addressing and data Table 4-3. PHUB Spokes and Peripherals Table 4-4. Priority Levels PHUB Spokes Peripherals Priority Level % Bus Bandwidth 0 SRAM 0 100.0 1 IOs, PICU, EMIF 1 100.0 2 PHUB local configuration, Power manager, 2 50.0 Clocks, IC, SWV, EEPROM, Flash 3 25.0 programming interface 4 12.5 3 Analog interface and trim, Decimator 5 6.2 4 USB, I2C, CAN, Timers, Counters, and PWMs 6 3.1 5 DFB 7 1.5 6 UDBs group 1 7 UDBs group 2 When the fairness algorithm is disabled, DMA access is granted based solely on the priority level; no bus bandwidth guarantees 4.3.2 DMA Features are made. 24 DMA channels 4.3.4 Transaction Modes Supported Each channel has one or more Transaction Descriptors (TDs) The flexible configuration of each DMA channel and the ability to to configure channel behavior. Up to 128 total TDs can be chain multiple channels allow the creation of both simple and defined complex use cases. General use cases include, but are not limited to: TDs can be dynamically updated 4.3.4.1 Simple DMA Eight levels of priority per channel In a simple DMA case, a single TD transfers data between a Any digitally routable signal, the CPU, or another DMA channel, source and sink (peripherals or memory location). The basic can trigger a transaction timing diagrams of DMA read and write cycles are shown in Figure4-2. For more description on other transfer modes, refer Each channel can generate up to two interrupts per transfer to the Technical Reference Manual. Document Number: 001-84935 Rev. *L Page 15 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 4-2. DMA Timing Diagram ADDRESS Phase DATA Phase ADDRESS Phase DATA Phase CLK CLK ADDR 16/32 A B ADDR 16/32 A B WRITE WRITE DATA DATA (A) DATA DATA (A) READY READY Basic DMA Read Transfer without wait states Basic DMA Write Transfer without wait states 4.3.4.2 Auto Repeat DMA in various noncontiguous locations in memory. Scatter gather DMA allows the segments to be concatenated together by using Auto repeat DMA is typically used when a static pattern is multiple TDs in a chain. The chain gathers the data from the repetitively read from system memory and written to a peripheral. multiple locations. A similar concept applies for the reception of This is done with a single TD that chains to itself. data onto the device. Certain parts of the received data may need 4.3.4.3 Ping Pong DMA to be scattered to various locations in memory for software processing convenience. Each TD in the chain specifies the A ping pong DMA case uses double buffering to allow one buffer location for each discrete element in the chain. to be filled by one client while another client is consuming the data previously received in the other buffer. In its simplest form, 4.3.4.7 Packet Queuing DMA this is done by chaining two TDs together so that each TD calls Packet queuing DMA is similar to scatter gather DMA but the opposite TD when complete. specifically refers to packet protocols. With these protocols, 4.3.4.4 Circular DMA there may be separate configuration, data, and status phases associated with sending or receiving a packet. Circular DMA is similar to ping pong DMA except it contains more than two buffers. In this case there are multiple TDs; after the last For instance, to transmit a packet, a memory mapped TD is complete it chains back to the first TD. configuration register can be written inside a peripheral, specifying the overall length of the ensuing data phase. The CPU 4.3.4.5 Indexed DMA can set up this configuration information anywhere in system In an indexed DMA case, an external master requires access to memory and copy it with a simple TD to the peripheral. After the locations on the system bus as if those locations were shared configuration phase, a data phase TD (or a series of data phase memory. As an example, a peripheral may be configured as an TDs) can begin (potentially using scatter gather). When the data SPI or I2C slave where an address is received by the external phase TD(s) finish, a status phase TD can be invoked that reads master. That address becomes an index or offset into the internal some memory mapped status information from the peripheral system bus memory space. This is accomplished with an initial and copies it to a location in system memory specified by the “address fetch” TD that reads the target address location from CPU for later inspection. Multiple sets of configuration, data, and the peripheral and writes that value into a subsequent TD in the status phase “subchains” can be strung together to create larger chain. This modifies the TD chain on the fly. When the “address chains that transmit multiple packets in this way. A similar fetch” TD completes it moves on to the next TD, which has the concept exists in the opposite direction to receive the packets. new address information embedded in it. This TD then carries 4.3.4.8 Nested DMA out the data transfer with the address location required by the external master. One TD may modify another TD, as the TD configuration space is memory mapped similar to any other peripheral. For example, 4.3.4.6 Scatter Gather DMA a first TD loads a second TD’s configuration and then calls the In the case of scatter gather DMA, there are multiple second TD. The second TD moves data as required by the noncontiguous sources or destinations that are required to application. When complete, the second TD calls the first TD, effectively carry out an overall DMA transaction. For example, a which again updates the second TD’s configuration. This packet may need to be transmitted off of the device and the process repeats as often as necessary. packet elements, including the header, payload, and trailer, exist Document Number: 001-84935 Rev. *L Page 16 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 4.4 Interrupt Controller The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in Table4-5. Table 4-5. Cortex-M3 Exceptions and Interrupts Exception Exception Table Exception Type Priority Function Number Address Offset 0x00 Starting value of R13 / MSP 1 Reset –3 (highest) 0x04 Reset 2 NMI –2 0x08 Non maskable interrupt 3 Hard fault –1 0x0C All classes of fault, when the corresponding fault handler cannot be activated because it is currently disabled or masked 4 MemManage Programmable 0x10 Memory management fault, for example, instruction fetch from a nonexecutable region 5 Bus fault Programmable 0x14 Error response received from the bus system; caused by an instruction prefetch abort or data access error 6 Usage fault Programmable 0x18 Typically caused by invalid instructions or trying to switch to ARM mode 7–10 – – 0x1C–0x28 Reserved 11 SVC Programmable 0x2C System service call via SVC instruction 12 Debug monitor Programmable 0x30 Debug monitor 13 – – 0x34 Reserved 14 PendSV Pcrogrammable 0x38 Deferred request for system service 15 SYSTICK Programmable 0x3C System tick timer 16–47 IRQ Programmable 0x40–0x3FC Peripheral interrupt request #0–#31 Bit 0 of each exception vector indicates whether the exception is Support for tail-chaining, and late arrival, of interrupts. This executed using ARM or Thumb instructions. Because the enables back-to-back interrupt processing without the Cortex-M3 only supports Thumb instructions, this bit must overhead of state saving and restoration between interrupts. always be 1. The Cortex-M3 non maskable interrupt (NMI) input Processor state automatically saved on interrupt entry, and can be routed to any pin, via the DSI, or disconnected from all restored on interrupt exit, with no instruction overhead. pins. See “DSI Routing Interface Description” section on page44. If the same priority level is assigned to two or more interrupts, the interrupt with the lower vector number is executed first. Each The Nested Vectored Interrupt Controller (NVIC) handles interrupt vector may choose from three interrupt sources: Fixed interrupts from the peripherals, and passes the interrupt vectors Function, DMA, and UDB. The fixed function interrupts are direct to the CPU. It is closely integrated with the CPU for low latency connections to the most common interrupt sources and provide interrupt handling. Features include: the lowest resource cost connection. The DMA interrupt sources 32 interrupts. Multiple sources for each interrupt. provide direct connections to the two DMA interrupt sources provided per DMA channel. The third interrupt source for vectors Eight priority levels, with dynamic priority control. is from the UDB digital routing array. This allows any digital signal Priority grouping. This allows selection of preempting and non available to the UDB array to be used as an interrupt source. All preempting interrupt levels. interrupt sources may be routed to any interrupt vector using the UDB interrupt source connections. Document Number: 001-84935 Rev. *L Page 17 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 4-6. Interrupt Vector Table Interrupt # Cortex-M3 Exception # Fixed Function DMA UDB 0 16 Low voltage detect (LVD) phub_termout0[0] udb_intr[0] 1 17 Cache/ECC phub_termout0[1] udb_intr[1] 2 18 Reserved phub_termout0[2] udb_intr[2] 3 19 Sleep (Pwr Mgr) phub_termout0[3] udb_intr[3] 4 20 PICU[0] phub_termout0[4] udb_intr[4] 5 21 PICU[1] phub_termout0[5] udb_intr[5] 6 22 PICU[2] phub_termout0[6] udb_intr[6] 7 23 PICU[3] phub_termout0[7] udb_intr[7] 8 24 PICU[4] phub_termout0[8] udb_intr[8] 9 25 PICU[5] phub_termout0[9] udb_intr[9] 10 26 PICU[6] phub_termout0[10] udb_intr[10] 11 27 PICU[12] phub_termout0[11] udb_intr[11] 12 28 PICU[15] phub_termout0[12] udb_intr[12] 13 29 Comparators Combined phub_termout0[13] udb_intr[13] 14 30 Switched Caps Combined phub_termout0[14] udb_intr[14] 15 31 I2C phub_termout0[15] udb_intr[15] 16 32 CAN phub_termout1[0] udb_intr[16] 17 33 Timer/Counter0 phub_termout1[1] udb_intr[17] 18 34 Timer/Counter1 phub_termout1[2] udb_intr[18] 19 35 Timer/Counter2 phub_termout1[3] udb_intr[19] 20 36 Timer/Counter3 phub_termout1[4] udb_intr[20] 21 37 USB SOF Int phub_termout1[5] udb_intr[21] 22 38 USB Arb Int phub_termout1[6] udb_intr[22] 23 39 USB Bus Int phub_termout1[7] udb_intr[23] 24 40 USB Endpoint[0] phub_termout1[8] udb_intr[24] 25 41 USB Endpoint Data phub_termout1[9] udb_intr[25] 26 42 Reserved phub_termout1[10] udb_intr[26] 27 43 LCD phub_termout1[11] udb_intr[27] 28 44 DFB Int phub_termout1[12] udb_intr[28] 29 45 Decimator Int phub_termout1[13] udb_intr[29] 30 46 phub_err_int phub_termout1[14] udb_intr[30] 31 47 eeprom_fault_int phub_termout1[15] udb_intr[31] Document Number: 001-84935 Rev. *L Page 18 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 5. Memory “Device Security” section on page64). For more information on how to take full advantage of the security features in PSoC, see 5.1 Static RAM the PSoC 5 TRM. CY8C56LP Static RAM (SRAM) is used for temporary data Table 5-1. Flash Protection storage. Code can be executed at full speed from the portion of SRAM that is located in the code space. This process is slower Protection Allowed Not Allowed from SRAM above 0x20000000. The device provides up to 64 Setting KB of SRAM. The CPU or the DMA controller can access all of Unprotected External read and write – SRAM. The SRAM can be accessed simultaneously by the + internal read and write Cortex-M3 CPU and the DMA controller if accessing different 32 KB blocks. Factory External write + internal External read Upgrade read and write 5.2 Flash Program Memory Field Upgrade Internal read and write External read and Flash memory in PSoC devices provides nonvolatile storage for write user firmware, user configuration data, bulk data storage, and Full Protection Internal read External read and optional ECC data. The main flash memory area contains up to write + internal write 256 KB of user program space. Up to an additional 32 KB of flash space is available for Error Correcting Codes (ECC). If ECC is not used this space can store Disclaimer device configuration data and bulk user data. User code may not Note the following details of the flash code protection features on be run out of the ECC flash memory section. ECC can correct Cypress devices. one bit error and detect two bit errors per 8 bytes of firmware memory; an interrupt can be generated when an error is Cypress products meet the specifications contained in their detected. The flash output is 9 bytes wide with 8 bytes of data particular Cypress datasheets. Cypress believes that its family of and 1 byte of ECC data. products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be The CPU or DMA controller read both user code and bulk data methods, unknown to Cypress, that can breach the code located in flash through the cache controller. This provides protection features. Any of these methods, to our knowledge, higher CPU performance. If ECC is enabled, the cache controller would be dishonest and possibly illegal. Neither Cypress nor any also performs error checking and correction. other semiconductor manufacturer can guarantee the security of Flash programming is performed through a special interface and their code. Code protection does not mean that we are preempts code execution out of flash. Code execution may be guaranteeing the product as “unbreakable.” done out of SRAM during flash programming. Cypress is willing to work with the customer who is concerned The flash programming interface performs flash erasing, about the integrity of their code. Code protection is constantly programming and setting code protection levels. Flash in-system evolving. We at Cypress are committed to continuously serial programming (ISSP), typically used for production improving the code protection features of our products. programming, is possible through both the SWD and JTAG interfaces. In-system programming, typically used for 5.4 EEPROM bootloaders, is also possible using serial interfaces such as I2C, PSoC EEPROM memory is a byte addressable nonvolatile USB, UART, and SPI, or any communications protocol. memory. The CY8C56LP has 2 KB of EEPROM memory to store user data. Reads from EEPROM are random access at the byte 5.3 Flash Security level. Reads are done directly; writes are done by sending write All PSoC devices include a flexible flash protection model that commands to an EEPROM programming interface. CPU code prevents access and visibility to on-chip flash memory. This execution can continue from flash during EEPROM writes. prevents duplication or reverse engineering of proprietary code. EEPROM is erasable and writeable at the row level. The Flash memory is organized in blocks, where each block contains EEPROM is divided into 128 rows of 16 bytes each. The factory 256 bytes of program or data and 32 bytes of ECC or default values of all EEPROM bytes are 0. configuration data. Because the EEPROM is mapped to the Cortex-M3 Peripheral The device offers the ability to assign one of four protection region, the CPU cannot execute out of EEPROM. There is no levels to each row of flash. Table5-1 lists the protection modes ECC hardware associated with EEPROM. If ECC is required it available. Flash protection levels can only be changed by must be handled in firmware. performing a complete flash erase. The Full Protection and Field It can take as much as 20 milliseconds to write to EEPROM or Upgrade settings disable external access (through a debugging flash. During this time the device should not be reset, or tool such as PSoC Creator, for example). If your application unexpected changes may be made to portions of EEPROM or requires code update through a boot loader, then use the Field flash. Reset sources (see Section6.3.1) include XRES pin, Upgrade setting. Use the Unprotected setting only when no software reset, and watchdog; care should be taken to make security is needed in your application. The PSoC device also sure that these are not inadvertently activated. In addition, the offers an advanced security feature called Device Security which low voltage detect circuits should be configured to generate an permanently disables all test, programming, and debug ports, interrupt instead of a reset. protecting your application from external access (see the Document Number: 001-84935 Rev. *L Page 19 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 5.5 Nonvolatile Latches (NVLs) PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown in Table5-3. Table 5-2. Device Configuration NVL Register Map Register Address 7 6 5 4 3 2 1 0 0x00 PRT3RDM[1:0] PRT2RDM[1:0] PRT1RDM[1:0] PRT0RDM[1:0] 0x01 PRT12RDM[1:0] PRT6RDM[1:0] PRT5RDM[1:0] PRT4RDM[1:0] 0x02 XRESMEN DBGEN PRT15RDM[1:0] 0x03 DIG_PHS_DLY[3:0] ECCEN DPS[1:0] CFGSPEED The details for individual fields and their factory default settings are shown in Table5-3:. Table 5-3. Fields and Factory Default Settings Field Description Settings PRTxRDM[1:0] Controls reset drive mode of the corresponding I/O port. 00b (default) - high impedance analog See “Reset Configuration” on page38. All pins of the port 01b - high impedance digital are set to the same mode. 10b - resistive pull up 11b - resistive pull down XRESMEN Controls whether pin P1[2] is used as a GPIO or as an 0 (default) - GPIO external reset. P1[2] is generally used as a GPIO, and not 1 - external reset as an external reset. DBGEN Debug Enable allows access to the debug system, for 0 - access disabled third-party programmers. 1 (default) - access enabled CFGSPEED Controls the speed of the IMO-based clock during the 0 (default) - 12 MHz IMO device boot process, for faster boot or low-power 1 - 48 MHz IMO operation DPS[1:0] Controls the usage of various P1 pins as a debug port. 00b - 5-wire JTAG See “Programming, Debug Interfaces, Resources” on 01b (default) - 4-wire JTAG page61. 10b - SWD 11b - debug ports disabled ECCEN Controls whether ECC flash is used for ECC or for general 0 - ECC disabled configuration and data storage. See “Flash Program 1 (default) - ECC enabled Memory” on page19. DIG_PHS_DLY[3:0] Selects the digital clock phase delay. See the TRM for details. Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase/write cycles is limited – see “Nonvolatile Latches (NVL)” on page109. Document Number: 001-84935 Rev. *L Page 20 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 5.6 External Memory Interface External memory is located in the Cortex-M3 external RAM space; it can use up to 24 address bits. See Table 5-4 on page CY8C56LP provides an External Memory Interface (EMIF) for 22Memory Map on page 22. The memory can be 8 or 16 bits connecting to external memory devices. The connection allows wide. read and write accesses to external memories. The EMIF operates in conjunction with UDBs, I/O ports, and other Cortex-M3 instructions can be fetched from external memory if it hardware to generate external memory address and control is 16-bit. Other limitations apply; for details, see application note signals. At 33 MHz, each memory access cycle takes four bus AN89610, PSoC® 4 and PSoC 5LP ARM Cortex Code clock cycles. Figure5-1 is the EMIF block diagram. The EMIF Optimization. There is no provision for code security in external supports synchronous and asynchronous memories. The memory. If code must be kept secure, then it should be placed in CY8C56LP only supports one type of external memory device at internal flash. See Flash Security on page 19 and Device a time. Security on page 64. Figure 5-1. EMIF Block Diagram Address Signals I/O External_MEM_ADDR[23:0] PORTs Data, Address, and Control Signals IO IF Data Signals I/O External_MEM_DATA[15:0] PORTs Control Signals I/O Control PHUB PORTs Data, Address, DSI Dynamic Output and Control Control Signals UDB DSI to Port Other EM Control Control Data, Signals Signals Address, and Control Signals EMIF Document Number: 001-84935 Rev. *L Page 21 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 5.7 Memory Map Table 5-5. Peripheral Data Address Map (continued) The Cortex-M3 has a fixed address map, which allows Address Range Purpose peripherals to be accessed by simple memory access 0x40004F00–0x40004FFF Fixed timer/counter/PWMs instructions. 0x40005000–0x400051FF I/O ports control 5.7.1 Address Map 0x40005400–0x400054FF External Memory Interface The 4 GB address space is divided into the ranges shown in (EMIF) control registers Table5-4: 0x40005800–0x40005FFF Analog Subsystem Interface Table 5-4. Address Map 0x40006000–0x400060FF USB Controller 0x40006400–0x40006FFF UDB Working Registers Address Range Size Use 0x40007000–0x40007FFF PHUB Configuration 0x00000000– 0.5 GB Program code. This includes 0x1FFFFFFF the exception vector table at 0x40008000–0x400087FF EEPROM power up, which starts at 0x4000A000–0x4000A400 CAN address 0. 0x4000C000–0x4000C800 Digital Filter Block 0x20000000– 0.5 GB Static RAM. This includes a 1 0x3FFFFFFF MByte bit-band region 0x40010000–0x4001FFFF Digital Interconnect Configuration starting at 0x20000000 and a 0x48000000–0x48007FFF Flash ECC Bytes 32 Mbyte bit-band alias 0x60000000–0x60FFFFFF External Memory Interface region starting at (EMIF) 0x22000000. 0xE0000000–0xE00FFFFF Cortex-M3 PPB Registers, 0x40000000– 0.5 GB Peripherals. including NVIC, debug, and trace 0x5FFFFFFF 0x60000000– 1 GB External RAM. 0x9FFFFFFF The bit-band feature allows individual bits in SRAM to be read or 0xA0000000– 1 GB External peripherals. written as atomic operations. This is done by reading or writing 0xDFFFFFFF bit 0 of corresponding words in the bit-band alias region. For 0xE0000000– 0.5 GB Internal peripherals, including example, to set bit 3 in the word at address 0x20000000, write a 0xFFFFFFFF the NVIC and debug and 1 to address 0x2200000C. To test the value of that bit, read trace modules. address 0x2200000C and the result is either 0 or 1 depending on the value of the bit. Most memory accesses done by the Cortex-M3 are aligned, that Table 5-5. Peripheral Data Address Map is, done on word (4-byte) boundary addresses. Unaligned accesses of words and 16-bit half-words on nonword boundary Address Range Purpose addresses can also be done, although they are less efficient. 0x00000000–0x0003FFFF 256K Flash 5.7.2 Address Map and Cortex-M3 Buses 0x1FFF8000–0x1FFFFFFF 32K SRAM in Code region The ICode and DCode buses are used only for accesses within 0x20000000–0x20007FFF 32K SRAM in SRAM region the Code address range, 0–0x1FFFFFFF. 0x40004000–0x400042FF Clocking, PLLs, and oscillators The System bus is used for data accesses and debug accesses 0x40004300–0x400043FF Power management within the ranges 0x20000000–0xDFFFFFFF and 0xE0100000–0xFFFFFFFF. Instruction fetches can also be 0x40004500–0x400045FF Ports interrupt control done within the range 0x20000000–0x3FFFFFFF, although 0x40004700–0x400047FF Flash programming interface these can be slower than instruction fetches via the ICode bus. 0x40004800–0x400048FF Cache controller The Private Peripheral Bus (PPB) is used within the Cortex-M3 0x40004900–0x400049FF I2C controller to access system control registers and debug and trace module registers. 0x40004E00–0x40004EFF Decimator Document Number: 001-84935 Rev. *L Page 22 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 6. System Integration Key features of the clocking system include: Seven general purpose clock sources 6.1 Clocking System 3- to 74-MHz IMO, ±1% at 3 MHz The clocking system generates, divides, and distributes clocks 4- to 25-MHz External Crystal Oscillator (MHzECO) throughout the PSoC system. For the majority of systems, no Clock doubler provides a doubled clock frequency output for external crystal is required. The IMO and PLL together can the USB block, see USB Clock Domain on page 26 generate up to a 80 MHz clock, accurate to ±1% over voltage and DSI signal from an external I/O pin or other logic temperature. Additional internal and external clock sources allow each design to optimize accuracy, power, and cost. All of the 24- to 80-MHz fractional Phase-Locked Loop (PLL) sourced from IMO, MHzECO, or DSI system clock sources can be used to generate other clock frequencies in the 16-bit clock dividers and UDBs for anything Clock Doubler the user wants, for example a UART baud rate generator. 1-kHz, 33-kHz, 100-kHz ILO for Watch Dog Timer (WDT) and Sleep Timer Clock generation and distribution is automatically configured 32.768-kHz External Crystal Oscillator (kHzECO) for Real through the PSoC Creator IDE graphical interface. This is based Time Clock (RTC) on the complete system’s requirements. It greatly speeds the IMO has a USB mode that auto locks to USB bus clock requiring design process. PSoC Creator allows designers to build clocking no external crystal for USB. (USB equipped parts only) systems with minimal input. The designer can specify desired clock frequencies and accuracies, and the software locates or Independently sourced clock in all clock dividers builds a clock that meets the required specifications. This is possible because of the programmability inherent in PSoC. Eight 16-bit clock dividers for the digital system Four 16-bit clock dividers for the analog system Dedicated 16-bit divider for the CPU bus and CPU clock Automatic clock configuration in PSoC Creator Table 6-1. Oscillator Summary Source Fmin Tolerance at Fmin Fmax Tolerance at Fmax Startup Time IMO 3 MHz ±1% over voltage and temperature 74 MHz ±7% 13µs max MHzECO 4 MHz Crystal dependent 25 MHz Crystal dependent 5 ms typ, max is crystal dependent DSI 0 MHz Input dependent 33 MHz Input dependent Input dependent PLL 24 MHz Input dependent 80 MHz Input dependent 250 µs max Doubler 12 MHz Input dependent 48 MHz Input dependent 1 µs max ILO 1 kHz –50%, +100% 100 kHz –55%, +100% 15 ms max in lowest power mode kHzECO 32 kHz Crystal dependent 32 kHz Crystal dependent 500 ms typ, max is crystal dependent Document Number: 001-84935 Rev. *L Page 23 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 6-1. Clocking Subsystem External IO 3-74 MHz 4-25 MHz 1,33,100 kHz or DSI 32 kHz ECO IMO ECO ILO 0-33 MHz CPU Clock 48 MHz 24-80 MHz System Doubler for PLL Clock Mux USB Bus Clock Bus Clock Divider 16 bit s Digital Clock Digital Clock Analog Clock k Divider 16 bit Divider 16 bit Divider 16 bit e w s Digital Clock Digital Clock Analog Clock k Divider 16 bit Divider 16 bit Divider 16 bit e w 7 7 s Digital Clock Digital Clock Analog Clock k Divider 16 bit Divider 16 bit Divider 16 bit e w s Digital Clock Digital Clock Analog Clock k Divider 16 bit Divider 16 bit Divider 16 bit e w 6.1.1 Internal Oscillators outputs clock frequencies in the range of 24 to 80 MHz. Its input and feedback dividers supply 4032 discrete ratios to create Figure 6-1 shows that there are two internal oscillators. They can almost any desired system clock frequency. The accuracy of the be routed directly or divided. The direct routes may not have a PLL output depends on the accuracy of the PLL input source. 50% duty cycle. Divided clocks have a 50% duty cycle. The most common PLL use is to multiply the IMO clock at 3 MHz, 6.1.1.1 Internal Main Oscillator where it is most accurate, to generate the CPU and system clocks up to the device’s maximum frequency. In most designs the IMO is the only clock source required, due to its ±1% accuracy. The IMO operates with no external The PLL achieves phase lock within 250 µs (verified by bit components and outputs a stable clock. A factory trim for each setting). It can be configured to use a clock from the IMO, frequency range is stored in the device. With the factory trim, MHzECO or DSI (external pin). The PLL clock source can be tolerance varies from ±1% at 3 MHz, up to ±7% at 74 MHz. The used until lock is complete and signaled with a lock bit. The lock IMO, in conjunction with the PLL, allows generation of CPU and signal can be routed through the DSI to generate an interrupt. system clocks up to the device's maximum frequency (see Disable the PLL before entering low power modes. Phase-Locked Loop) 6.1.1.4 Internal Low Speed Oscillator The IMO provides clock outputs at 3, 6, 12, 24, 48, and 74 MHz. The ILO provides clock frequencies for low power consumption, 6.1.1.2 Clock Doubler including the watchdog timer, and sleep timer. The ILO generates up to three different clocks: 1 kHz, 33 kHz, and The clock doubler outputs a clock at twice the frequency of the 100kHz. input clock. The doubler works for input frequency ranges of 6 to 24 MHz (providing 12 to 48 MHz at the output). It can be The 1 kHz clock (CLK1K) is typically used for a background configured to use a clock from the IMO, MHzECO, or the DSI ‘heartbeat’ timer. This clock inherently lends itself to low power (external pin). The doubler is typically used to clock the USB. supervisory operations such as the watchdog timer and long sleep intervals using the central timewheel (CTW). 6.1.1.3 Phase-Locked Loop The central timewheel is a 1 kHz, free running, 13-bit counter The PLL allows low frequency, high accuracy clocks to be clocked by the ILO. The central timewheel is always enabled multiplied to higher frequencies. This is a tradeoff between except in hibernate mode and when the CPU is stopped during higher clock frequency and accuracy and, higher power debug on chip mode. It can be used to generate periodic consumption and increased startup time. interrupts for timing purposes or to wake the system from a low The PLL block provides a mechanism for generating clock power mode. Firmware can reset the central timewheel. frequencies based upon a variety of input sources. The PLL Document Number: 001-84935 Rev. *L Page 24 of 131

® PSoC 5LP: CY8C56LP Family Datasheet The central timewheel can be programmed to wake the system Figure 6-3. 32kHzECO Block Diagram periodically and optionally issue an interrupt. This enables flexible, periodic wakeups from low power modes or coarse timing applications. Systems that require accurate timing should XCLK32K 32 kHz use Real Time Clock capability instead of the central timewheel. Crystal Osc The 100-kHz clock (CLK100K) can be used as a low power system clock to run the CPU. It can also generate time intervals using the fast timewheel. The fast timewheel is a 5-bit counter, clocked by the 100-kHz clock. It features programmable settings and automatically Xi Xo resets when the terminal count is reached. An optional interrupt (Pin P15[3]) (Pin P15[2]) can be generated each time the terminal count is reached. This 32 kHz enables flexible, periodic interrupts of the CPU at a higher rate External crystal than is allowed using the central timewheel. Components Capacitors The 33 kHz clock (CLK33K) comes from a divide-by-3 operation on CLK100K. This output can be used as a reduced accuracy version of the 32.768 kHz ECO clock with no need for a crystal. It is recommended that the external 32.768-kHz watch crystal 6.1.2 External Oscillators have a load capacitance (CL) of 6 pF or 12.5 pF. Check the Figure 6-1 shows that there are two external oscillators. They crystal manufacturer's datasheet. The two external capacitors, can be routed directly or divided. The direct routes may not have CL1 and CL2, are typically of the same value, and their total a 50% duty cycle. Divided clocks have a 50% duty cycle. capacitance, CL1CL2 / (CL1 + CL2), including pin and trace capacitance, should equal the crystal CL value. For more 6.1.2.1 MHz External Crystal Oscillator information, refer to application note AN54439: PSoC 3 and The MHzECO provides high frequency, high precision clocking PSoC 5 External Oscillators. See also pin capacitance using an external crystal (see Figure6-2). It supports a wide specifications in the “GPIO” section on page75. variety of crystal types, in the range of 4 to 25 MHz. When used 6.1.2.3 Digital System Interconnect in conjunction with the PLL, it can generate CPU and system clocks up to the device's maximum frequency (see The DSI provides routing for clocks taken from external clock Phase-Locked Loop on page 24). The GPIO pins connecting to oscillators connected to I/O. The oscillators can also be the external crystal and capacitors are fixed. MHzECO accuracy generated within the device in the digital system and UDBs. depends on the crystal chosen. While the primary DSI clock input provides access to all clocking Figure 6-2. MHzECO Block Diagram resources, up to eight other DSI clocks (internally or externally generated) may be routed directly to the eight digital clock dividers. This is only possible if there are multiple precision clock XCLK_MHZ sources. 4 - 25 MHz Crystal Osc 6.1.3 Clock Distribution All seven clock sources are inputs to the central clock distribution system. The distribution system is designed to create multiple high precision clocks. These clocks are customized for the design’s requirements and eliminate the common problems Xi Xo found with limited resolution prescalers attached to peripherals. (Pin P15[1]) (Pin P15[0]) The clock distribution system generates several types of clock 4 – 25 MHz trees. External crystal Components The system clock is used to select and supply the fastest clock Capacitors in the system for general system clock requirements and clock synchronization of the PSoC device. Bus Clock 16-bit divider uses the system clock to generate the 6.1.2.2 32.768 kHz ECO system’s bus clock used for data transfers and the CPU. The The 32.768 kHz External Crystal Oscillator (32kHzECO) CPU clock is directly derived from the bus clock. provides precision timing with minimal power consumption using Eight fully programmable 16-bit clock dividers generate digital an external 32.768 kHz watch crystal (see Figure6-3). The system clocks for general use in the digital system, as 32kHzECO also connects directly to the sleep timer and provides configured by the design’s requirements. Digital system clocks the source for the Real Time Clock (RTC). The RTC uses a 1 can generate custom clocks derived from any of the seven second interrupt to implement the RTC functionality in firmware. clock sources for any purpose. Examples include baud rate The oscillator works in two distinct power modes. This allows generators, accurate PWM periods, and timer clocks, and users to trade off power consumption with noise immunity from many others. If more than eight digital clock dividers are neighboring circuits. The GPIO pins connected to the external required, the UDBs and fixed function Timer/Counter/PWMs crystal and capacitors are fixed. can also generate clocks. Document Number: 001-84935 Rev. *L Page 25 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Four 16-bit clock dividers generate clocks for the analog system requires a 48 MHz frequency. This frequency can be generated components that require clocking, such as ADCs and mixers. from different sources, including DSI clock at 48 MHz or doubled The analog clock dividers include skew control to ensure that value of 24 MHz from internal oscillator, DSI signal, or crystal critical analog events do not occur simultaneously with digital oscillator. switching events. This is done to reduce analog system noise. 6.2 Power System Each clock divider consists of an 8-input multiplexer, a 16-bit clock divider (divide by 2 and higher) that generates ~50% duty The power system consists of separate analog, digital, and I/O cycle clocks, system clock resynchronization logic, and deglitch supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It logic. The outputs from each digital clock tree can be routed into also includes two internal 1.8V regulators that provide the digital the digital system interconnect and then brought back into the (VCCD) and analog (VCCA) supplies for the internal core logic. clock system as an input, allowing clock chaining of up to 32 bits. The output pins of the regulators (VCCD and VCCA) and the VDDIO pins must have capacitors connected as shown in 6.1.4 USB Clock Domain Figure6-4. The two VCCD pins must be shorted together, with as short a trace as possible, and connected to a 1 µF ±10% X5R The USB clock domain is unique in that it operates largely capacitor. The power system also contains a sleep regulator, an asynchronously from the main clock network. The USB logic contains a synchronous bus interface to the chip, while running I2C regulator, and a hibernate regulator. on an asynchronous clock to process USB data. The USB logic Figure 6-4. PSoC Power System VDDIO2 1µF VDDD VDDIO0 0.1µF 0.1µF 2VDDIO I/O Supply VCCD VSSD VDDD I/O SI2uCpp ly VDDIO0 0.1µF Regulator Sleep Regulator Digital Domain VDDA VDDA VSSB ReDgiguiltaatlo rs RAengaulloagto r VCCA 0.1µF 1µF . VSSA Analog Domain Hibernate Regulator VDDIO1 I/O Supply VCCD VSSD VDDD I/O Supply 3VDDIO 0.1µF 0.1µF 0.1µF VDDIO1 VDDD VDDIO3 Notes The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure2-6. You can power the device in internally regulated mode, where the voltage applied to the VDDx pins is as high as 5.5 V, and the internal regulators provide the core voltages. In this mode, do not apply power to the V pins, and do not tie the V pins CCx DDx to the V pins. CCx You can also power the device in externally regulated mode, that is, by directly powering the VCCD and VCCA pins. In this configuration, the V pins should be shorted to the V pins and the V pin should be shorted to the V pin. The allowed supply range DDD CCD DDA CCA in this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by default, and should be disabled to reduce power consumption. It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias specifications. With some capacitors, the actual capacitance can decrease considerably when the DC bias (V or V in Figure6-4) is a DDX CCX significant percentage of the rated working voltage. Document Number: 001-84935 Rev. *L Page 26 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 6.2.1 Power Modes Active is the main processing mode. Its functionality is configurable. Each power controllable subsystem is enabled or PSoC 5LP devices have four different power modes, as shown disabled by using separate power configuration template in Table6-2 and Table6-3. The power modes allow a design to registers. In alternate active mode, fewer subsystems are easily provide required functionality and processing power while enabled, reducing power. In sleep mode most resources are simultaneously minimizing power consumption and maximizing disabled regardless of the template settings. Sleep mode is battery life in low power and portable devices. optimized to provide timed sleep intervals and Real Time Clock PSoC 5LP power modes, in order of decreasing power functionality. The lowest power mode is hibernate, which retains consumption are: register and SRAM state, but no clocks, and allows wakeup only from I/O pins. Figure6-5 illustrates the allowable transitions Active between power modes. Sleep and hibernate modes should not Alternate Active be entered until all VDDIO supplies are at valid voltage levels. Sleep Hibernate Table 6-2. Power Modes Power Modes Description Entry Condition Wakeup Source Active Clocks Regulator Active Primary mode of operation, Wakeup, reset, Any interrupt Any (programmable) All regulators available. all peripherals available manual register Digital and analog (programmable) entry regulators can be disabled if external regulation used. Alternate Similar to Active mode, and is Manual register Any interrupt Any (programmable) All regulators available. Active typically configured to have entry Digital and analog fewer peripherals active to regulators can be disabled reduce power. One possible if external regulation used. configuration is to use the UDBs for processing, with the CPU turned off Sleep All subsystems automatically Manual register Comparator, ILO/kHzECO Both digital and analog disabled entry PICU, I2C, RTC, regulators buzzed. CTW, LVD Digital and analog regulators can be disabled if external regulation used. Hibernate All subsystems automatically Manual register PICU Only hibernate regulator disabled entry active. Lowest power consuming mode with all peripherals and internal regulators disabled, except hibernate regulator is enabled Configuration and memory contents retained Table 6-3. Power Modes Wakeup Time and Power Consumption Sleep Wakeup Current Code Digital Analog Clock Sources Reset Wakeup Sources Modes Time (Typ) Execution Resources Resources Available Sources Active – 3.1 mA[8] Yes All All All – All Alternate – – User All All All – All Active defined <25 µs 2 µA No I2C Comparator ILO/kHzECO Comparator, XRES, LVD, Sleep PICU, I2C, RTC, WDR CTW, LVD Hibernate <200 µs 300 nA No None None None PICU XRES Note 8. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See Table 11-2 on page 67. Document Number: 001-84935 Rev. *L Page 27 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 6-5. Power Mode Transitions 6.2.1.5 Wakeup Events Wakeup events are configurable and can come from an interrupt Active or device reset. A wakeup event restores the system to active mode. Firmware enabled interrupt sources include internally generated interrupts, power supervisor, central timewheel, and I/O interrupts. Internal interrupt sources can come from a variety of peripherals, such as analog comparators and UDBs. The Manual central timewheel provides periodic interrupts to allow the Sleep Hibernate system to wake up, poll peripherals, or perform real-time functions. Reset event sources include the external reset pin (XRES), WDT, and Precision Reset (PRES). 6.2.2 Boost Converter Applications that use a supply voltage of less than 1.71 V, such Alternate as solar panels or single cell battery supplies, may use the Active on-chip boost converter to generate a minimum of 1.8 V supply voltage. The boost converter may also be used in any system that requires a higher operating voltage than the supply provides 6.2.1.1 Active Mode such as driving 5.0 V LCD glass in a 3.3 V system. With the addition of an inductor, Schottky diode, and capacitors, it Active mode is the primary operating mode of the device. When produces a selectable output voltage sourcing enough current to in active mode, the active configuration template bits control operate the PSoC and other on-board components. which available resources are enabled or disabled. When a The boost converter accepts an input voltage V from 0.5 V to resource is disabled, the digital clocks are gated, analog bias BAT 3.6 V, and can start up with V as low as 0.5 V. The converter currents are disabled, and leakage currents are reduced as BAT provides a user configurable output voltage of 1.8 to 5.0 V (V ) appropriate. User firmware can dynamically control subsystem OUT in 100 mV increments. V is typically less than V ; if V is power by setting and clearing bits in the active configuration BAT OUT BAT greater than or equal to V , then V will be slightly less than template. The CPU can disable itself, in which case the CPU is OUT OUT V due to resistive losses in the boost converter. The block can automatically reenabled at the next wakeup event. BAT deliver up to 50 mA (I ) depending on configuration to both BOOST When a wakeup event occurs, the global mode is always the PSoC device and external components. The sum of all returned to active, and the CPU is automatically enabled, current sinks in the design including the PSoC device, PSoC I/O regardless of its template settings. Active mode is the default pin loads, and external component loads must be less than the global power mode upon boot. I specified maximum current. BOOST 6.2.1.2 Alternate Active Mode Four pins are associated with the boost converter: VBAT, VSSB, VBOOST, and IND. The boosted output voltage is sensed at the Alternate Active mode is very similar to Active mode. In alternate VBOOST pin and must be connected directly to the chip’s supply active mode, fewer subsystems are enabled, to reduce power inputs; VDDA, VDDD, and VDDIO if used to power the PSoC consumption. One possible configuration is to turn off the CPU device. and flash, and run peripherals at full speed. The boost converter requires four components in addition to 6.2.1.3 Sleep Mode those required in a non-boost design, as shown in Figure 6-6 on Sleep mode reduces power consumption when a resume time of page 29. A 22 µF capacitor (CBAT) is required close to the VBAT 15 µs is acceptable. The wake time is used to ensure that the pin to provide local bulk storage of the battery voltage and regulator outputs are stable enough to directly enter active provide regulator stability. A diode between the battery and VBAT mode. pin should not be used for reverse polarity protection because the diodes forward voltage drop reduces the V voltage. BAT 6.2.1.4 Hibernate Mode Between the VBAT and IND pins, an inductor of 4.7 µH, 10 µH, In hibernate mode nearly all of the internal functions are or 22 µH is required. The inductor value can be optimized to disabled. Internal voltages are reduced to the minimal level to increase the boost converter efficiency based on input voltage, keep vital systems alive. Configuration state is preserved in output voltage, temperature, and current. Inductor size is hibernate mode and SRAM memory is retained. GPIOs determined by following the design guidance in this chapter and configured as digital outputs maintain their previous values and electrical specifications. The Inductor must be placed within 1 cm external GPIO pin interrupt settings are preserved. The device of the VBAT and IND pins and have a minimum saturation can only return from hibernate mode in response to an external current of 750mA. Between the IND and VBOOST pins a I/O interrupt. The resume time from hibernate mode is less than Schottky diode must be placed within 1 cm of the pins. The 100µs. Schottky diode shall have a forward current rating of at least 1.0 A and a reverse voltage of at least 20 V. A 22 µF bulk capacitor To achieve an extremely low current, the hibernate regulator has (C ) must be connected close to VBOOST to provide limited capacity. This limits the frequency of any signal present BOOST regulator output stability. It is important to sum the total on the input pins; no GPIO should toggle at a rate greater than capacitance connected to the VBOOST pin and ensure the 10 kHz while in hibernate mode. If pins must be toggled at a high maximum C specification is not exceeded. All capacitors rate while in a low power mode, use sleep mode instead. BOOST must be rated for a minimum of 10 V to minimize capacitive losses due to voltage de-rating. Document Number: 001-84935 Rev. *L Page 28 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 6-6. Application of Boost Converter powering PSoC device PSoC VDDA 0.1 µF 1.0 µF External Load VDDD 0.1 µF 1.0 µF VDDD 0.1 µF 1.0 µF VBOOST Schottky, 1A IND VDDIO0 0.1 µF 4.7 µH Boost VDDIO2 10 µH 0.1 µF Logic 22 µH VDDIO1 VBAT 0.1 µF 22 µF VDDIO3 VSSB 0.1 µF 0.5–3.6 V VSSA 22 µF VSSD All components and values are required The boost converter may also generate a supply that is not used the PSoC device, but with a change to the bulk capacitor directly by the PSoC device. An example of this use case is requirements. A parallel arrangement 22 µF, 1.0 µF, and 0.1 µF boosting a 1.8 V supply to 4.0 V to drive a white LED. If the boost capacitors are all required on the Vout supply and must be converter is not supplying the PSoC devices V , V , and placed within 1 cm of the VBOOST pin to ensure regulator DDA DDD V it must comply with the same design rules as supplying stability. DDIO Figure 6-7. Application of Boost Converter not powering PSoC device V OUT External PSoC Load VDDA VDDD 22 µF 1.0 µF 0.1 µF VDDD VDDA, VDDD, and VBOOST VDDIO connections Schottky, 1A per section 6.2 IND VDDIO0 Power System. 4.7 µH Boost VDDIO2 10 µH Logic 22 µH VDDIO1 VBAT 22 µF VDDIO3 VSSB 0.5–3.6 V VSSA VSSD All components and values are required The switching frequency is set to 400 kHz using an oscillator mode is the normal mode of operation where the boost regulator integrated into the boost converter. The boost converter can be actively generates a regulated output voltage. In standby mode, operated in two different modes: active and standby. Active most boost functions are disabled, thus reducing power Document Number: 001-84935 Rev. *L Page 29 of 131

® PSoC 5LP: CY8C56LP Family Datasheet consumption of the boost circuit. Only minimal power is provided, Figure 11-8 on page 73. If the operating ranges are not met, typically < 5 µA to power the PSoC device in Sleep mode. The modify the operating conditions or use an external boost boost typically draws 250 µA in active mode and 25 µA in regulator. standby mode. The boost operating modes must be used in 3.Determine if the desired ambient temperature (T ) range fits A conjunction with chip power modes to minimize total power the ambient temperature operating range based on the T A consumption. Table6-4 lists the boost power modes available in range over V and V chart, Figure 11-8 on page 73. If BAT OUT different chip power modes. the temperature range is not met, modify the operating condi- tions and return to step 2, or use an external boost regulator. Table 6-4. Chip and Boost Power Modes Compatibility 4.Determine if the desired output current (I ) range fits the OUT Chip Power Modes Boost Power Modes output current operating range based on the I range over OUT Chip-active or alternate Boost must be operated in its active VBAT and VOUT chart, Figure 11-9 on page 73. If the output active mode mode. current range is not met, modify the operating conditions and return to step 2, or use an external boost regulator. Chip-sleep mode Boost can be operated in either active or standby mode. In boost standby 5.Find the allowed inductor values based on the LBOOST values mode, the chip must wake up periodi- over VBAT and VOUT chart, Figure 11-10 on page 73. cally for boost active-mode refresh. 6.Based on the allowed inductor values, inductor dimensions, inductor cost, boost efficiency, and V choose the Chip-hibernate mode Boost can be operated in its active RIPPLE optimum inductor value for the system. Boost efficiency and mode. However, it is recommended not V typical values are provided in the Efficiency vs V to use the boost in chip hibernate mode RIPPLE BAT and V vs V charts, Figure 11-11 on page 74 through due to the higher current consumption RIPPLE BAT Figure 11-14 on page 74. In general, if high efficiency and low in boost active mode. V are most important, then the highest allowed inductor RIPPLE value should be used. If low inductor cost or small inductor 6.2.2.1 Boost Firmware Requirements size are most important, then one of the smaller allowed To ensure boost inrush current is within specification at startup, inductor values should be used. If the allowed inductor(s) the Enable Fast IMO During Startup value must be unchecked efficiency, VRIPPLE, cost or dimensions are not acceptable for in the PSoC Creator IDE. The Enable Fast IMO During Startup the application than an external boost regulator should be option is found in PSoC Creator in the design wide resources used. (cydwr) file System tab. Un-checking this option configures the 6.3 Reset device to run at 12 MHz vs 48 MHz during startup while configuring the device. The slower clock speed results in CY8C56LP has multiple internal and external reset sources reduced current draw through the boost circuit. available. The reset sources are: 6.2.2.2 Boost Design Process Power source monitoring - The analog and digital power Correct operation of the boost converter requires specific voltages, VDDA, VDDD, VCCA, and VCCD are monitored in component values determined for each designs unique several different modes during power up, active mode, and operating conditions. The C capacitor, Inductor, Schottky sleep mode (buzzing). If any of the voltages goes outside BAT diode, and C capacitor components are required with the predetermined ranges then a reset is generated. The monitors BOOST values specified in the electrical specifications, Table 11-7 on are programmable to generate an interrupt to the processor page 73. The only variable component value is the inductor under certain conditions before reaching the reset thresholds. L which is primarily sized for correct operation of the boost BOOST External - The device can be reset from an external source by across operating conditions and secondarily for efficiency. pulling the reset pin (XRES) low. The XRES pin includes an Additional operating region constraints exist for V , V , I , OUT BAT OUT internal pull up to VDDIO1. VDDD, VDDA, and VDDIO1 must and T . A all have voltage applied before the part comes out of reset. The following steps must be followed to determine boost Watchdog timer - A watchdog timer monitors the execution of converter operating parameters and L value. BOOST instructions by the processor. If the watchdog timer is not reset 1.Choose desired VBAT, VOUT, TA, and IOUT operating condition by firmware within a certain period of time, the watchdog timer ranges for the application. generates a reset. 2.Determine if V and V ranges fit the boost operating BAT OUT Software - The device can be reset under program control. range based on the T range over V and V chart, A BAT OUT Document Number: 001-84935 Rev. *L Page 30 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 6-8. Resets services and to reduce wakeup time. At these times the PRES circuit is also buzzed to allow periodic voltage monitoring. VDDD VDDA ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Power Processor Interrupt circuits are available to detect when VDDA and Voltage Interrupt VDDD go outside a voltage range. For AHVI, VDDA is Level compared to a fixed trip level. For ALVI and DLVI, VDDA and Monitors VDDD are compared to trip levels that are programmable, as Reset listed in Table6-5. ALVI and DLVI can also be configured to Pin generate a device reset instead of an interrupt. External Reset System Reset Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High Controller Reset Voltage Interrupt Normal Voltage Available Trip Interrupt Supply Range Settings Watchdog Timer DLVI VDDD 1.71V–5.5V 1.70 V–5.45V in 250-mV increments ALVI VDDA 1.71V–5.5V 1.70 V–5.45V in 250-mV increments Software Reset AHVI VDDA 1.71V–5.5V 5.75V Register The monitors are disabled until after IPOR. During sleep mode these circuits are periodically activated (buzzed). If an interrupt occurs during buzzing then the system first enters its wakeup The term system reset indicates that the processor as well as sequence. The interrupt is then recognized and may be analog and digital peripherals and registers are reset. serviced. A reset status register shows some of the resets or power voltage The buzz frequency is adjustable, and should be set to be less monitoring interrupts. The program may examine this register to than the minimum time that any voltage is expected to be out detect and report certain exception conditions. This register is of range. For details on how to adjust the buzz frequency, see cleared after a power-on reset. For details see the Technical the TRM. Reference Manual. 6.3.1 Reset Sources 6.3.1.2 Other Reset Sources 6.3.1.1 Power Voltage Level Monitors XRES - External Reset IPOR - Initial Power-on-Reset PSoC 5LP has a dedicated XRES pin, which holds the part in At initial power on, IPOR monitors the power voltages VDDD, reset while held active (low). The response to an XRES is the VDDA, VCCD and VCCA. The trip level is not precise. It is set to same as to an IPOR reset. approximately 1 volt (0.75 V to 1.45 V). This is below the lowest The external reset is active low. It includes an internal pull up specified operating voltage but high enough for the internal resistor. XRES is active during sleep and hibernate modes. circuits to be reset and to hold their reset state. The monitor generates a reset pulse that is at least 150 ns wide. It may be After XRES has been deasserted, at least 10 µs must elapse much wider if one or more of the voltages ramps up slowly. before it can be reasserted. After boot, the IPOR circuit is disabled and voltage supervision SRES - Software Reset is handed off to the precise low-voltage reset (PRES) circuit. A reset can be commanded under program control by setting PRES - Precise Low-Voltage Reset a bit in the software reset register. This is done either directly This circuit monitors the outputs of the analog and digital by the program or indirectly by DMA access. The response to internal regulators after power up. The regulator outputs are a SRES is the same as after an IPOR reset. compared to a precise reference voltage. The response to a PRES trip is identical to an IPOR reset. Another register bit exists to disable this function. In normal operating mode, the program cannot disable the WRES - Watchdog Timer Reset digital PRES circuit. The analog regulator can be disabled, The watchdog reset detects when the software program is no which also disables the analog portion of the PRES. The PRES longer being executed correctly. To indicate to the watchdog circuit is disabled automatically during sleep and hibernate timer that it is running correctly, the program must periodically modes, with one exception: During sleep mode the regulators reset the timer. If the timer is not reset before a user-specified are periodically activated (buzzed) to provide supervisory amount of time, then a reset is generated. Document Number: 001-84935 Rev. *L Page 31 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Note IPOR disables the watchdog function. The program must Every pin can be an interrupt source configured as rising enable the watchdog function at an appropriate point in the edge, falling edge or both edges. If required, level sensitive code by setting a register bit. When this bit is set, it cannot be interrupts are supported through the DSI cleared again except by an IPOR power on reset event. Dedicated port interrupt vector for each port Slew rate controlled digital output drive mode 6.4 I/O System and Routing Access port control and configuration registers on either port basis or pin basis PSoC I/Os are extremely flexible. Every GPIO has analog and Separate port read (PS) and write (DR) data registers to avoid digital I/O capability. All I/Os have a large number of drive modes, read modify write errors which are set at POR. PSoC also provides up to four individual Special functionality on a pin by pin basis I/O voltage domains through the VDDIO pins. Additional features only provided on the GPIO pins: There are two types of I/O pins on every device; those with USB LCD segment drive on LCD equipped devices provide a third type. Both General Purpose I/O (GPIO) and CapSense[9] Special I/O (SIO) provide similar digital functionality. The primary Analog input and output capability differences are their analog capability and drive strength. Continuous 100 µA clamp current capability Devices that include USB also provide two USBIO pins that Standard drive strength down to 1.71V support specific USB functionality as well as limited GPIO Additional features only provided on SIO pins: capability. Higher drive strength than GPIO All I/O pins are available for use as digital inputs and outputs for Hot swap capability (5V tolerance at any operating VDD) both the CPU and digital peripherals. In addition, all I/O pins can Programmable and regulated high input and output drive generate an interrupt. The flexible and advanced capabilities of levels down to 1.2V the PSoC I/O, combined with any signal to any pin routability, No analog input, CapSense, or LCD capability greatly simplify circuit design and board layout. All GPIO pins can Overvoltage tolerance up to 5.5V be used for analog input, CapSense[9], and LCD segment drive, SIO can act as a general purpose analog comparator while SIO pins are used for voltages in excess of VDDA and for programmable output voltages. USBIO features: Full speed USB 2.0 compliant I/O Features supported by both GPIO and SIO: Highest drive strength for general purpose use User programmable port reset state Input, output, or both for CPU and DMA Separate I/O supplies and voltages for up to four groups of I/O Input, output, or both for digital peripherals Digital peripherals use DSI to connect the pins Digital output (CMOS) drive mode Input or output or both for CPU and DMA Each pin can be an interrupt source configured as rising Eight drive modes edge, falling edge, or both edges Note 9. GPIOs with opamp outputs are not recommended for use with CapSense. Document Number: 001-84935 Rev. *L Page 32 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 6-9. GPIO Block Diagram Digital Input Path Naming Convention PRT[x]CTL ‘x’ = Port Number PRT[x]DBL_SYNC_IN ‘y’ = Pin Number PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Input Buffer Disable Interrupt Pin Interrupt Signal Logic PICU[x]INTSTAT Digital Output Path PRT[x]SLW PRT[x]SYNC_OUT VddioVddio PRT[x]DR 0 Digital System Output In 1 Vddio PRT[x]BYP PRT[x]DM2 Drive Slew PRT[x]DM1 Logic Cntl PIN PRT[x]DM0 Bidirectional Control PRT[x]BIE OE Analog 1 0 1 0 Capsense Global Control 1 CAPS[x]CFG1 Switches PRT[x]AG Analog Global PRT[x]AMUX Analog Mux LCD Display Data PRT[x]LCD_COM_SEG Logic & MUX PRT[x]LCD_EN LCD Bias Bus 5 Document Number: 001-84935 Rev. *L Page 33 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 6-10. SIO Input/Output Block Diagram Digital Input Path Naming Convention PRT[x]SIO_HYST_EN ‘x’ = Port Number PRT[x]SIO_DIFF Buffer ‘y’ = Pin Number Reference Level Thresholds PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Input Buffer Disable Interrupt Pin Interrupt Signal Logic PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG Driver PRT[x]SLW Vhigh PRT[x]SYNC_OUT PRT[x]DR 0 Digital System Output In 1 PRT[x]BYP PRT[x]DM2 Drive PRT[x]DM1 Logic Slew PIN Cntl PRT[x]DM0 Bidirectional Control PRT[x]BIE OE Figure 6-11. USBIO Block Diagram Digital Input Path Naming Convention ‘y’ = Pin Number USB Receiver Circuitry PRT[15]DBL_SYNC_IN PRT[15]PS[6,7] USBIO_CR1[0,1] Digital System Input PICU[15]INTTYPE[y] PICU[15]INTSTAT Interrupt Pin Interrupt Signal Logic PICU[15]INTSTAT Digital Output Path PRT[15]SYNC_OUT USBIO_CR1[5] USB or I/O D+ pin only USBIO_CR1[2] D+ 1.5 k Vddd VdddVddd USB SIE Control for USB Mode Vddd PRT[15]DR1[7,6] 0 Digital System Output 1 In Drive 5 k 1.5 k PRT[15]BYP Logic PIN PRT[15]DM0[6] D+ Open Drain PRT[15]DM0[7] D- Open Drain PRT[15]DM1[6] D+ 5 k PRT[15]DM1[7] D- 5 k Document Number: 001-84935 Rev. *L Page 34 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 6.4.1 Drive Modes if bypass mode is selected. Note that the actual I/O pin voltage is determined by a combination of the selected drive mode and Each GPIO and SIO pin is individually configurable into one of the load at the pin. For example, if a GPIO pin is configured for the eight drive modes listed in Table6-6. Three configuration bits resistive pull up mode and driven high while the pin is floating, are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] the voltage measured at the pin is a high logic state. If the same registers. Figure6-12 depicts a simplified pin view based on GPIO pin is externally tied to ground then the voltage each of the eight drive modes. Table6-6 shows the I/O pin’s drive unmeasured at the pin is a low logic state. state based on the port data register value or digital array signal Figure 6-12. Drive Mode VDD VDD OInut Pin OInut Pin OInut Pin OInut Pin An An An An 0. High Impedance 1. High Impedance 2. Resistive Pull-Up 3. Resistive Pull-Down Analog Digital VDD VDD VDD OInut Pin OInut Pin OInut Pin OInut Pin An An An An 4. Open Drain, 5. Open Drain, 6. Strong Drive 7. Resistive Pull-Up Drives Low Drives High and Pull-Down The ‘Out’ connection is driven from either the Digital System (when the Digital Output terminal is connected) or the Data Register (when HW connection is disabled). The ‘In’ connection drives the Pin State register, and the Digital System if the Digital Input terminal is enabled and connected. The ‘An’ connection connects to the Analog System. Table 6-6. Drive Modes Diagram Drive Mode PRTxDM2 PRTxDM1 PRTxDM0 PRTxDR = 1 PRTxDR = 0 0 High-impedance analog 0 0 0 High Z High Z 1 High-impedance digital 0 0 1 High Z High Z 2 Resistive pull-up[10] 0 1 0 Res High (5K) Strong Low 3 Resistive pull-down[10] 0 1 1 Strong High Res Low (5K) 4 Open drain, drives low 1 0 0 High Z Strong Low 5 Open drain, drive high 1 0 1 Strong High High Z 6 Strong drive 1 1 0 Strong High Strong Low 7 Resistive pull up and pull down[10] 1 1 1 Res High (5K) Res Low (5K) Note 10.Resistive pull up and pull down are not available with SIO in regulated output mode. Document Number: 001-84935 Rev. *L Page 35 of 131

® PSoC 5LP: CY8C56LP Family Datasheet The USBIO pins (P15[7] and P15[6]), when enabled for I/O mode, have limited drive mode control. The drive mode is set using the PRT15.DM0[7, 6] register. A resistive pull option is also available at the USBIO pins, which can be enabled using the PRT15.DM1[7, 6] register. When enabled for USB mode, the drive mode control has no impact on the configuration of the USB pins. Unlike the GPIO and SIO configurations, the port wide configuration registers do not configure the USB drive mode bits. Table6-7 shows the drive mode configuration for the USBIO pins. Table 6-7. USBIO Drive Modes (P15[7] and P15[6]) PRT15.DM1[7,6] PRT15.DM0[7,6] PRT15.DR[7,6] = 1 PRT15.DR[7,6] = 0 Description Pull up enable Drive Mode enable 0 0 High Z Strong Low Open Drain, Strong Low 0 1 Strong High Strong Low Strong Outputs 1 0 Res High (5k) Strong Low Resistive Pull Up, Strong Low 1 1 Strong High Strong Low Strong Outputs High impedance analog 6.4.2 Pin Registers The default reset state with both the output driver and digital Registers to configure and interact with pins come in two forms input buffer turned off. This prevents any current from flowing that may be used interchangeably. in the I/O’s digital input buffer due to a floating voltage. This All I/O registers are available in the standard port form, where state is recommended for pins that are floating or that support each bit of the register corresponds to one of the port pins. This an analog voltage. High impedance analog pins do not provide register form is efficient for quickly reconfiguring multiple port digital input functionality. pins at the same time. To achieve the lowest chip current in sleep modes, all I/Os I/O registers are also available in pin form, which combines the must either be configured to the high impedance analog mode, eight most commonly used port register bits into a single register or have their pins driven to a power supply rail by the PSoC for each pin. This enables very fast configuration changes to device or by external circuitry. individual pins with a single register write. High impedance digital 6.4.3 Bidirectional Mode The input buffer is enabled for digital signal input. This is the High speed bidirectional capability allows pins to provide both standard high impedance (HiZ) state recommended for digital the high impedance digital drive mode for input signals and a inputs. second user selected drive mode such as strong drive (set using PRTxDM[2:0] registers) for output signals on the same pin, Resistive pull up or resistive pull down based on the state of an auxiliary control bus signal. The Resistive pull up or pull down, respectively, provides a series bidirectional capability is useful for processor busses and resistance in one of the data states and strong drive in the communications interfaces such as the SPI Slave MISO pin that other. Pins can be used for digital input and output in these requires dynamic hardware control of the output buffer. modes. Interfacing to mechanical switches is a common The auxiliary control bus routes up to 16 UDB or digital peripheral application for these modes. Resistive pull up and pull down generated output enable signals to one or more pins. are not available with SIO in regulated output mode. Open drain, drives high and open drain, drives low 6.4.4 Slew Rate Limited Mode Open drain modes provide high impedance in one of the data GPIO and SIO pins have fast and slow output slew rate options states and strong drive in the other. Pins can be used for digital for strong and open drain drive modes, not resistive drive modes. input and output in these modes. A common application for Because it results in reduced EMI, the slow edge rate option is these modes is driving the I2C bus signal lines. recommended for signals that are not speed critical, generally less than 1 MHz. The fast slew rate is for signals between 1 MHz Strong drive and 33 MHz. The slew rate is individually configurable for each Provides a strong CMOS output drive in either high or low pin, and is set by the PRTxSLW registers. state. This is the standard output mode for pins. Strong Drive mode pins must not be used as inputs under normal 6.4.5 Pin Interrupts circumstances. This mode is often used to drive digital output All GPIO and SIO pins are able to generate interrupts to the signals or external FETs. system. All eight pins in each port interface to their own Port Interrupt Control Unit (PICU) and associated interrupt vector. Resistive pull up and pull down Each pin of the port is independently configurable to detect rising Similar to the resistive pull up and resistive pull down modes edge, falling edge, both edge interrupts, or to not generate an except the pin is always in series with a resistor. The high data interrupt. state is pull up while the low data state is pull down. This mode Depending on the configured mode for each pin, each time an is most often used when other signals that may cause shorts interrupt event occurs on a pin, its corresponding status bit of the can drive the bus. Resistive pull up and pull down are not interrupt status register is set to “1” and an interrupt request is available with SIO in regulated output mode. sent to the interrupt controller. Each PICU has its own interrupt Document Number: 001-84935 Rev. *L Page 36 of 131

® PSoC 5LP: CY8C56LP Family Datasheet vector in the interrupt controller and the pin status register which is based on an internally generated reference. Typically a providing easy determination of the interrupt source down to the voltage DAC (VDAC) is used to generate the reference (see pin level. Figure 6-13). The “DAC” section on page59 has more details on VDAC use and reference routing to the SIO pins. Resistive pull Port pin interrupts remain active in all sleep modes allowing the up and pull down drive modes are not available with SIO in PSoC device to wake from an externally generated interrupt. regulated output mode. While level sensitive interrupts are not directly supported; Universal Digital Blocks (UDB) provide this functionality to the 6.4.12 Adjustable Input Level system when needed. This section applies only to SIO pins. SIO pins by default support 6.4.6 Input Buffer Mode the standard CMOS and LVTTL input levels but also support a GPIO and SIO input buffers can be configured at the port level differential mode with programmable levels. SIO pins are for the default CMOS input thresholds or the optional LVTTL grouped into pairs. Each pair shares a reference generator block input thresholds. All input buffers incorporate Schmitt triggers for which, is used to set the digital input buffer reference level for input hysteresis. Additionally, individual pin input buffers can be interface to external signals that differ in voltage from VDDIO. disabled in any drive mode. The reference sets the pins voltage threshold for a high logic level (see Figure 6-13). Available input thresholds are: 6.4.7 I/O Power Supplies 0.5 VDDIO Up to four I/O pin power supplies are provided depending on the 0.4 VDDIO device and package. Each I/O supply must be less than or equal 0.5 VREF to the voltage on the chip’s analog (VDDA) pin. This feature VREF allows users to provide different I/O voltage levels for different pins on the device. Refer to the specific device package pinout Typically a voltage DAC (VDAC) generates the VREF reference. to determine VDDIO capability for a given port and pin. The SIO “DAC” section on page59 has more details on VDAC use and port pins support an additional regulated high output capability, reference routing to the SIO pins. as described in Adjustable Output Level. Figure 6-13. SIO Reference for Input and Output 6.4.8 Analog Connections Input Path These connections apply only to GPIO pins. All GPIO pins may be used as analog inputs or outputs. The analog voltage present on the pin must not exceed the VDDIO supply voltage to which Digital the GPIO belongs. Each GPIO may connect to one of the analog Input global busses or to one of the analog mux buses to connect any Vinref pin to any internal analog resource such as ADC or comparators. In addition, select pins provide direct connections to specific analog features such as the high current DACs or uncommitted opamps. 6.4.9 CapSense SIO_Ref Reference Generator This section applies only to GPIO pins. All GPIO pins may be PIN used to create CapSense buttons and sliders[11]. See the “CapSense” section on page59 for more information. Voutref Output Path 6.4.10 LCD Segment Drive Driver Vhigh This section applies only to GPIO pins. All GPIO pins may be used to generate Segment and Common drive signals for direct glass drive of LCD glass. See the “LCD Direct Drive” section on page58 for details. Digital 6.4.11 Adjustable Output Level Drive Output Logic This section applies only to SIO pins. SIO port pins support the ability to provide a regulated high output level for interface to external signals that are lower in voltage than the SIO’s respective VDDIO. SIO pins are individually configurable to output either the standard V level or the regulated output, DDIO Note 11.GPIOs with opamp outputs are not recommended for use with CapSense. Document Number: 001-84935 Rev. *L Page 37 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 6.4.13 SIO as Comparator 6.4.17 Low Power Functionality This section applies only to SIO pins. The adjustable input level In all low power modes the I/O pins retain their state until the part feature of the SIOs as explained in the Adjustable Input Level is awakened and changed or reset. To awaken the part, use a section can be used to construct a comparator. The threshold for pin interrupt, because the port interrupt logic continues to the comparator is provided by the SIO's reference generator. The function in all low power modes. reference generator has the option to set the analog signal routed through the analog global line as threshold for the 6.4.18 Special Pin Functionality comparator. Note that a pair of SIO pins share the same Some pins on the device include additional special functionality threshold. in addition to their GPIO or SIO functionality. The specific special The digital input path in Figure 6-10 on page 34 illustrates this function pins are listed in “Pinouts” on page6. The special functionality. In the figure, ‘Reference level’ is the analog signal features are: routed through the analog global. The hysteresis feature can Digital also be enabled for the input buffer of the SIO, which increases noise immunity for the comparator. 4 to 25 MHz crystal oscillator 32.768 kHz crystal oscillator 6.4.14 Hot Swap Wake from sleep on I2C address match. Any pin can be used for I2C if wake from sleep is not required. This section applies only to SIO pins. SIO pins support ‘hot swap’ capability to plug into an application without loading the signals JTAG interface pins that are connected to the SIO pins even when no power is SWD interface pins applied to the PSoC device. This allows the unpowered PSoC to SWV interface pins maintain a high impedance load to the external device while also TRACEPORT interface pins preventing the PSoC from being powered through a SIO pin’s External reset protection diode. Analog Powering the device up or down while connected to an Opamp inputs and outputs operational I2C bus may cause transient states on the SIO pins. High current IDAC outputs The overall I2C bus design should take this into account. External reference inputs 6.4.15 Over Voltage Tolerance 6.4.19 JTAG Boundary Scan All I/O pins provide an over voltage tolerance feature at any The device supports standard JTAG boundary scan chains on all operating VDD. pins for board level test. There are no current limitations for the SIO pins as they present a high impedance load to the external circuit. 7. Digital Subsystem The GPIO pins must be limited to 100 µA using a current limiting resistor. GPIO pins clamp the pin voltage to approximately one The digital programmable system creates application specific diode above the VDDIO supply. combinations of both standard and advanced digital peripherals In case of a GPIO pin configured for analog input/output, the and custom logic functions. These peripherals and logic are then analog voltage on the pin must not exceed the VDDIO supply interconnected to each other and to any pin on the device, voltage to which the GPIO belongs. providing a high level of design flexibility and IP security. A common application for this feature is connection to a bus such The features of the digital programmable system are outlined as I2C where different devices are running from different supply here to provide an overview of capabilities and architecture. You voltages. In the I2C case, the PSoC chip is configured into the do not need to interact directly with the programmable digital Open Drain, Drives Low mode for the SIO pin. This allows an system at the hardware and register level. PSoC Creator external pull up to pull the I2C bus voltage above the PSoC pin provides a high level schematic capture graphical interface to supply. For example, the PSoC chip could operate at 1.8V, and automatically place and route resources similar to PLDs. an external device could run from 5V. Note that the SIO pin’s The main components of the digital programmable system are: VIH and VIL levels are determined by the associated VDDIO supply pin. Universal Digital Blocks (UDB) - These form the core The SIO pin must be in one of the following modes: 0 (high functionality of the digital programmable system. UDBs are a impedance analog), 1 (high impedance digital), or 4 (open drain collection of uncommitted logic (PLD) and structural logic drives low). See Figure6-12 for details. Absolute maximum (Datapath) optimized to create all common embedded ratings for the device must be observed for all I/O pins. peripherals and customized functionality that are application or design specific. 6.4.16 Reset Configuration Universal Digital Block array - UDB blocks are arrayed within While reset is active all I/Os are reset to and held in the High a matrix of programmable interconnect. The UDB array Impedance Analog state. After reset is released, the state can be structure is homogeneous and allows for flexible mapping of reprogrammed on a port-by-port basis to pull down or pull up. To digital functions onto the array. The array supports extensive ensure correct reset operation, the port reset configuration data and flexible routing interconnects between UDBs and the is stored in special nonvolatile registers. The stored reset data is Digital System Interconnect. automatically transferred to the port reset configuration registers at reset release. Document Number: 001-84935 Rev. *L Page 38 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Digital System Interconnect (DSI) - Digital signals from Timers Universal Digital Blocks (UDBs), fixed function peripherals, I/O Counters pins, interrupts, DMA, and other system core signals are Logic attached to the Digital System Interconnect to implement full featured device connectivity. The DSI allows any digital function NOT to any pin or other feature routability when used with the OR Universal Digital Block array. XOR AND Figure 7-1. CY8C56LP Digital Programmable Architecture 7.1.2 Example Analog Components Digital Core System The following is a sample of the analog components available in and Fixed Function Peripherals PSoC Creator for the CY8C56LP family. The exact amount of IO Port DSI Routing Interface IO Port hbCayre rada wctooarmr efop rroe tnsheoenu ctr ocvemasrpi e(oSsn Cew/niCtth.T t hbelo cfekast,u rroeust isnegl,e RctAedM ,in f lPasSho)C u sed UDB UDB UDB UDB Amplifiers UDB Array UUUUDDDDBBBB UUUUDDDDBBBB UUUUDDDDBBBB UUUUDDDDBBBB UDB Array ADTPoCpIGAasAmp UDB UDB UDB UDB Delta-Sigma DSI Routing Interface Successive Approximation (SAR) Port Port DACs IO IO Current Digital Core System and Fixed Function Peripherals Voltage PWM 7.1 Example Peripherals Comparators The flexibility of the CY8C56LP family’s Universal Digital Blocks Mixers (UDBs) and Analog Blocks allow the user to create a wide range of components (peripherals). The most common peripherals 7.1.3 Example System Function Components were built and characterized by Cypress and are shown in the The following is a sample of the system function components PSoC Creator component catalog, however, users may also available in PSoC Creator for the CY8C56LP family. The exact create their own custom components using PSoC Creator. Using amount of hardware resources (UDBs, DFB taps, SC/CT blocks, PSoC Creator, users may also create their own components for routing, RAM, flash) used by a component varies with the reuse within their organization, for example sensor interfaces, features selected in PSoC Creator for the component. proprietary algorithms, and display interfaces. CapSense The number of components available through PSoC Creator is too numerous to list in the datasheet, and the list is always LCD Drive growing. An example of a component available for use in LCD Control CY8C56LP family, but, not explicitly called out in this datasheet is the UART component. Filters 7.1.1 Example Digital Components 7.1.4 Designing with PSoC Creator The following is a sample of the digital components available in 7.1.4.1 More Than a Typical IDE PSoC Creator for the CY8C56LP family. The exact amount of hardware resources (UDBs, routing, RAM, flash) used by a A successful design tool allows for the rapid development and component varies with the features selected in PSoC Creator for deployment of both simple and complex designs. It reduces or the component. eliminates any learning curve. It makes the integration of a new design into the production stream straightforward. Communications I2C PSoC Creator is that design tool. UART PSoC Creator is a full featured Integrated Development SPI Environment (IDE) for hardware and software design. It is optimized specifically for PSoC devices and combines a modern, Functions powerful software development platform with a sophisticated EMIF graphical design tool. This unique combination of tools makes PWMs PSoC Creator the most flexible embedded design platform available. Document Number: 001-84935 Rev. *L Page 39 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Graphical design entry simplifies the task of configuring a 7.1.4.5 Nonintrusive Debugging particular part. You can select the required functionality from an With JTAG (4-wire) and SWD (2-wire) debug connectivity extensive catalog of components and place it in your design. All available on all devices, the PSoC Creator debugger offers full components are parameterized and have an editor dialog that control over the target device with minimum intrusion. allows you to tailor functionality to your needs. Breakpoints and code execution commands are all readily PSoC Creator automatically configures clocks and routes the I/O available from toolbar buttons and an impressive lineup of to the selected pins and then generates APIs to give the windows—register, locals, watch, call stack, memory and application complete control over the hardware. Changing the peripherals—make for an unparalleled level of visibility into the PSoC device configuration is as simple as adding a new system. component, setting its parameters, and rebuilding the project. PSoC Creator contains all the tools necessary to complete a At any stage of development you are free to change the design, and then to maintain and extend that design for years to hardware configuration and even the target processor. To come. All steps of the design flow are carefully integrated and retarget your application (hardware and software) to new optimized for ease-of-use and to maximize productivity. devices, even from 8- to 32-bit families, just select the new device and rebuild. 7.2 Universal Digital Block You also have the ability to change the C compiler and evaluate The Universal Digital Block (UDB) represents an evolutionary an alternative. Components are designed for portability and are step to the next generation of PSoC embedded digital peripheral validated against all devices, from all families, and against all functionality. The architecture in first generation PSoC digital supported tool chains Switching compilers is as easy as editing blocks provides coarse programmability in which a few fixed the from the project options and rebuilding the application with functions with a small number of options are available. The new no errors from the generated APIs or boot code. UDB architecture is the optimal balance between configuration granularity and efficient implementation. A cornerstone of this 7.1.4.2 Component Catalog approach is to provide the ability to customize the devices digital The component catalog is a repository of reusable design operation to match application requirements. elements that select device functionality and customize your To achieve this, UDBs consist of a combination of uncommitted PSoC device. It is populated with an impressive selection of logic (PLD), structured logic (Datapath), and a flexible routing content; from simple primitives such as logic gates and device scheme to provide interconnect between these elements, I/O registers, through the digital timers, counters and PWMs, plus connections, and other peripherals. UDB functionality ranges analog components such as ADCs, DACs, and filters, and from simple self contained functions that are implemented in one communication protocols, such as I2C, USB, and CAN. See UDB, or even a portion of a UDB (unused resources are “Example Peripherals” section on page39 for more details about available for other functions), to more complex functions that available peripherals. All content is fully characterized and require multiple UDBs. Examples of basic functions are timers, carefully documented in datasheets with code examples, AC/DC counters, CRC generators, PWMs, dead band generators, and specifications, and user code ready APIs. communications functions, such as UARTs, SPI, and I2C. Also, the PLD blocks and connectivity provide full featured general 7.1.4.3 Design Reuse purpose programmable logic within the limits of the available The symbol editor gives you the ability to develop reusable resources. components that can significantly reduce future design time. Just draw a symbol and associate that symbol with your proven Figure 7-2. UDB Block Diagram design. PSoC Creator allows for the placement of the new symbol anywhere in the component catalog along with the PLD content provided by Cypress. You can then reuse your content Chaining as many times as you want, and in any number of projects, PLD PLD without ever having to revisit the details of the implementation. Clock 12C4 12C4 and Reset (8 PTs) (8 PTs) 7.1.4.4 Software Development Control Anchoring the tool is a modern, highly customizable user interface. It includes project management and integrated editors Status and for C and assembler source code, as well the design entry tools. Control Datapath Datapath Project build control leverages compiler technology from top Chaining commercial vendors such as ARM® Limited, Keil™, and CodeSourcery (GNU). Free versions of Keil C51 and GNU C Compiler (GCC) for ARM, with no restrictions on code size or end product distribution, are included with the tool distribution. Upgrading to more optimizing compilers is a snap with support Routing Channel for the professional Keil C51 product and ARM RealView™ compiler. Document Number: 001-84935 Rev. *L Page 40 of 131

® PSoC 5LP: CY8C56LP Family Datasheet The main component blocks of the UDB are: One 12C4 PLD block is shown in Figure7-3. This PLD has 12 inputs, which feed across eight product terms. Each product term PLD blocks - There are two small PLDs per UDB. These blocks (AND function) can be from 1 to 12 inputs wide, and in a given take inputs from the routing array and form registered or product term, the true (T) or complement (C) of each input can combinational sum-of-products logic. PLDs are used to be selected. The product terms are summed (OR function) to implement state machines, state bits, and combinational logic create the PLD outputs. A sum can be from 1 to 8 product terms equations. PLD configuration is automatically generated from wide. The 'C' in 12C4 indicates that the width of the OR gate (in graphical primitives. this case 8) is constant across all outputs (rather than variable Datapath Module - This 8-bit wide datapath contains structured as in a 22V10 device). This PLA like structure gives maximum logic to implement a dynamically configurable ALU, a variety flexibility and insures that all inputs and outputs are permutable of compare configurations and condition generation. This block for ease of allocation by the software tools. There are two 12C4 also contains input/output FIFOs, which are the primary parallel PLDs in each UDB. data interface between the CPU/DMA system and the UDB. 7.2.2 Datapath Module Status and Control Module - The primary role of this block is to The datapath contains an 8-bit single cycle ALU, with associated provide a way for CPU firmware to interact and synchronize compare and condition generation logic. This datapath block is with UDB operation. optimized to implement embedded functions, such as timers, Clock and Reset Module - This block provides the UDB clocks counters, integrators, PWMs, PRS, CRC, shifters and dead band and reset selection and control. generators and many others. 7.2.1 PLD Module The primary purpose of the PLD blocks is to implement logic expressions, state machines, sequencers, look up tables, and decoders. In the simplest use model, consider the PLD blocks as a standalone resource onto which general purpose RTL is synthesized and mapped. The more common and efficient use model is to create digital functions from a combination of PLD and datapath blocks, where the PLD implements only the random logic and state portion of the function while the datapath (ALU) implements the more structured elements. Figure 7-3. PLD 12C4 Structure P P P P P P P P T T T T T T T T 0 1 2 3 4 5 6 7 IN0 TC TC TC TC TC TC TC TC IN1 TC TC TC TC TC TC TC TC IN2 TC TC TC TC TC TC TC TC IN3 TC TC TC TC TC TC TC TC IN4 TC TC TC TC TC TC TC TC IN5 TC TC TC TC TC TC TC TC AND IN6 TC TC TC TC TC TC TC TC Array IN7 TC TC TC TC TC TC TC TC IN8 TC TC TC TC TC TC TC TC IN9 TC TC TC TC TC TC TC TC IN10 TC TC TC TC TC TC TC TC IN11 TC TC TC TC TC TC TC TC Carry In T T T T T T T T MC0 OUT0 T T T T T T T T MC1 OUT1 T T T T T T T T MC2 OUT2 T T T T T T T T MC3 OUT3 Carry Out OR Array Document Number: 001-84935 Rev. *L Page 41 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 7-4. Datapath Top Level PHUB System Bus R/W Access to All Registers F1 M FIFOs ProgIrnapmRuomt ufartoibnmlge 6MInupxuets Dynamic Configuration RA8 Word X 16 Bit Datapath Control Data ReDDFg001isters To/FroDDAAm0101 Conditions: 2 Compares, 2 Zero Detect, 2 Ones Detect Overflow Detect OMuutxTpeous/t6F romOPRrououtgptirunatgm tom able Previous Chaining Next Datapath Datapath A1 Accumulators A0 PI Parallel Input/Output (To/From Programmable Routing) PO ALU Shift Mask 7.2.2.1 Working Registers configurations. The address input to this RAM controls the sequence, and can be routed from any block connected to the The datapath contains six primary working registers, which are UDB routing matrix, most typically PLD logic, I/O pins, or from accessed by CPU firmware or DMA during normal operation. the outputs of this or other datapath blocks. Table 7-1. Working Datapath Registers ALU Name Function Description The ALU performs eight general-purpose functions. They are: A0 and A1 Accumulators These are sources and sinks for the ALU and also sources for the Increment compares. Decrement D0 and D1 Data Registers These are sources for the ALU Add and sources for the compares. Subtract F0 and F1 FIFOs These are the primary interface Logical AND to the system bus. They can be a data source for the data registers Logical OR and accumulators or they can Logical XOR capture data from the accumu- lators or ALU. Each FIFO is four Pass, used to pass a value through the ALU to the shift register, bytes deep. mask, or another UDB register Independent of the ALU operation, these functions are available: 7.2.2.2 Dynamic Configuration RAM Shift left Dynamic configuration is the ability to change the datapath Shift right function and internal configuration on a cycle-by-cycle basis, Nibble swap under sequencer control. This is implemented using the 8-word Bitwise OR mask x 16-bit configuration RAM, which stores eight unique 16-bit wide Document Number: 001-84935 Rev. *L Page 42 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 7.2.2.3 Conditionals shared with two sets of registers and condition generators. Carry and shift out data from the ALU are registered and can be Each datapath has two compares, with bit masking options. selected as inputs in subsequent cycles. This provides support Compare operands include the two accumulators and the two for 16-bit functions in one (8-bit) datapath. data registers in a variety of configurations. Other conditions include zero detect, all ones detect, and overflow. These 7.2.2.9 Datapath I/O conditions are the primary datapath outputs, a selection of which There are six inputs and six outputs that connect the datapath to can be driven out to the UDB routing matrix. Conditional the routing matrix. Inputs from the routing provide the computation can use the built in chaining to neighboring UDBs configuration for the datapath operation to perform in each cycle, to operate on wider data widths without the need to use routing and the serial data inputs. Inputs can be routed from other UDB resources. blocks, other device peripherals, device I/O pins, and so on. The 7.2.2.4 Variable MSB outputs to the routing can be selected from the generated conditions, and the serial data outputs. Outputs can be routed to The most significant bit of an arithmetic and shift function can be other UDB blocks, device peripherals, interrupt and DMA programmatically specified. This supports variable width CRC controller, I/O pins, and so on. and PRS functions, and in conjunction with ALU output masking, can implement arbitrary width timers, counters and shift blocks. 7.2.3 Status and Control Module 7.2.2.5 Built in CRC/PRS The primary purpose of this circuitry is to coordinate CPU The datapath has built in support for single cycle Cyclic firmware interaction with internal UDB operation. Redundancy Check (CRC) computation and Pseudo Random Figure 7-6. Status and Control Registers Sequence (PRS) generation of arbitrary width and arbitrary polynomial. CRC/PRS functions longer than 8 bits may be System Bus implemented in conjunction with PLD logic, or built in chaining may be use to extend the function into neighboring UDBs. 7.2.2.6 Input/Output FIFOs 8-bit Status Register 8-bit Control Register Each datapath contains two four-byte deep FIFOs, which can be (Read Only) (Write/Read) independently configured as an input buffer (system bus writes to the FIFO, datapath internal reads the FIFO), or an output buffer (datapath internal writes to the FIFO, the system bus reads from the FIFO). The FIFOs generate status that are selectable Routing Channel as datapath outputs and can therefore be driven to the routing, to interact with sequencers, interrupts, or DMA. The bits of the control register, which may be written to by the Figure 7-5. Example FIFO Configurations system bus, are used to drive into the routing matrix, and thus provide firmware with the opportunity to control the state of UDB System Bus System Bus processing. The status register is read-only and it allows internal UDB state to be read out onto the system bus directly from internal routing. This allows firmware to monitor the state of UDB F0 F0 F1 processing. Each bit of these registers has programmable connections to the routing matrix and routing connections are made depending on the requirements of the application. D0/D1 D0 D1 A0/A1/ALU A0/A1/ALU A0/A1/ALU A0 A1 7.2.3.1 Usage Examples As an example of control input, a bit in the control register can be allocated as a function enable bit. There are multiple ways to F1 F0 F1 enable a function. In one method the control bit output would be routed to the clock control block in one or more UDBs and serve as a clock enable for the selected UDB blocks. A status example System Bus System Bus is a case where a PLD or datapath block generated a condition, such as a “compare true” condition that is captured and latched TX/RX Dual Capture Dual Buffer by the status register and then read (and cleared) by CPU firmware. 7.2.2.7 Chaining 7.2.3.2 Clock Generation The datapath can be configured to chain conditions and signals Each subcomponent block of a UDB including the two PLDs, the such as carries and shift data with neighboring datapaths to datapath, and Status and Control, has a clock selection and create higher precision arithmetic, shift, CRC/PRS functions. control block. This promotes a fine granularity with respect to 7.2.2.8 Time Multiplexing allocating clocking resources to UDB component blocks and allows unused UDB resources to be used by other functions for In applications that are over sampled, or do not need high clock maximum system efficiency. rates, the single ALU block in the datapath can be efficiently Document Number: 001-84935 Rev. *L Page 43 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 7.3 UDB Array Description utilize the unused PLD blocks in the 8-bit Timer UDB. Programmable resources in the UDB array are generally Figure7-7 shows an example of a 16 UDB array. In addition to homogeneous so functions can be mapped to arbitrary the array core, there are a DSI routing interfaces at the top and boundaries in the array. bottom of the array. Other interfaces that are not explicitly shown include the system interfaces for bus and clock distribution. The Figure 7-8. Function Mapping Example in a Bank of UDBs UDB array includes multiple horizontal and vertical routing channels each comprised of 96 wires. The wire connections to 8-Bit Quadrature Decoder er 16-Bit 16-Bit PYRS Timer c PWM UDBs, at horizontal/vertical intersection and at the DSI interface n e u are highly permutable providing efficient automatic routing in UDB UDB q UDB UDB e PSoC Creator. Additionally the routing allows wire by wire S segmentation along the vertical and horizontal routing to further HV HV HV HV increase routing flexibility and capability. A B A B Figure 7-7. Digital System Interface Structure System Connections UDB UDB UDB 8-BitU DB Timer Logic 8-Bit SPI HV HV HV HV I2C Slave 12-Bit SPI B A B A UDB UDB UDB UDB UDB UDB UDB UDB HV HV HV HV HV HV HV HV B A B A A B A B Logic UDB UDB UDB UDB UDB UDB UDB UDB UART 12-Bit PWM UDB UDB UDB UDB 7.4 DSI Routing Interface Description HV HV HV HV B A B A The DSI routing interface is a continuation of the horizontal and vertical routing channels at the top and bottom of the UDB array UDB UDB UDB UDB core. It provides general purpose programmable routing between device peripherals, including UDBs, I/Os, analog peripherals, interrupts, DMA and fixed function peripherals. HV HV HV HV A B A B Figure7-9 illustrates the concept of the digital system interconnect, which connects the UDB array routing matrix with other device peripherals. Any digital core or fixed function System Connections peripheral that needs programmable routing is connected to this interface. Signals in this category include: 7.3.1 UDB Array Programmable Resources Figure7-8 shows an example of how functions are mapped into Interrupt requests from all digital peripherals in the system. a bank of 16 UDBs. The primary programmable resources of the DMA requests from all digital peripherals in the system. UDB are two PLDs, one datapath and one status/control register. These resources are allocated independently, because they Digital peripheral data signals that need flexible routing to I/Os. have independently selectable clocks, and therefore unused Digital peripheral data signals that need connections to UDBs. blocks are allocated to other unrelated functions. An example of this is the 8-bit Timer in the upper left corner of Connections to the interrupt and DMA controllers. the array. This function only requires one datapath in the UDB, Connection to I/O pins. and therefore the PLD resources may be allocated to another function. A function such as a Quadrature Decoder may require Connection to analog system digital signals. more PLD logic than one UDB can supply and in this case can Document Number: 001-84935 Rev. *L Page 44 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 7-9. Digital System Interconnect 7.4.1 I/O Port Routing There are a total of 20 DSI routes to a typical 8-bit I/O port, 16 Timer Interrupt DMA I/O Port Global CAN I2C for data and four for drive strength control. Counters Controller Controller Pins Clocks When an I/O pin is connected to the routing, there are two primary connections available, an input and an output. In conjunction with drive strength control, this can implement a bidirectional I/O pin. A data output signal has the option to be single synchronized (pipelined) and a data input signal has the option to be double synchronized. The synchronization clock is Digital System Routing I/F the system clock (see Figure6-1). Normally all inputs from pins are synchronized as this is required if the CPU interacts with the signal or any signal derived from it. Asynchronous inputs have rare uses. An example of this is a feed through of combinational UDB ARRAY PLD logic from input pins to output pins. Figure 7-11. I/O Pin Synchronization Routing Digital System Routing I/F DO DI Delta- Global I/O Port SAR SC/CT EMIF Sigma DACS Comparators Clocks Pins ADC Blocks ADC Figure 7-12. I/O Pin Output Connectivity 8 IO Data Output Connections from the Interrupt and DMA routing is very flexible in the CY8C56LP UDB Array Digital System Interface programmable architecture. In addition to the numerous fixed function peripherals that can generate interrupt requests, any data signal in the UDB array routing can also be used to generate a request. A single peripheral may generate multiple independent interrupt requests simplifying system and firmware design. Figure7-10 shows the structure of the IDMUX (Interrupt/DMA Multiplexer). Figure 7-10. Interrupt and DMA Processing in the IDMUX Interrupt and DMA Processing in IDMUX DO DO DO DO DO DO DO DO Fixed Function IRQs PIN 0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 0 1 Interrupt IRQs Controller Port i 2 UDB Array Edge 3 Detect There are four more DSI connections to a given I/O port to DRQs implement dynamic output enable control of pins. This DMA termout (IRQs) connectivity gives a range of options, from fully ganged 8-bits controlled by one signal, to up to four individually controlled pins. 0 Fixed Function DRQs DMA The output enable signal is useful for creating tri-state 1 Controller bidirectional pins and buses. Edge 2 Detect Document Number: 001-84935 Rev. *L Page 45 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 7-13. I/O Pin Output Enable Connectivity 7.5 CAN 4 IO Control Signal Connections from The CAN peripheral is a fully functional Controller Area Network UDB Array Digital System Interface (CAN) supporting communication baud rates up to 1 Mbps. The CAN controller implements the CAN2.0A and CAN2.0B specifications as defined in the Bosch specification and conforms to the ISO-11898-1 standard. The CAN protocol was originally designed for automotive applications with a focus on a high level of fault detection. This ensures high communication reliability at a low cost. Because of its success in automotive applications, CAN is used as a standard communication protocol for motion oriented machine control networks (CANOpen) and OE OE OE OE OE OE OE OE factory automation applications (DeviceNet). The CAN controller PIN 0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 features allow the efficient implementation of higher level protocols without affecting the performance of the microcontroller CPU. Full configuration support is provided in Port i PSoC Creator. Figure 7-14. CAN Bus System Implementation CAN Node 1 CAN Node 2 CAN Node n PSoC CAN Drivers CAN Controller En Tx Rx CAN Transceiver CAN_H CAN_L CAN_H CAN_L CAN_H CAN_L CAN Bus 7.5.1 CAN Features Receive path CAN2.0A/B protocol implementation - ISO 11898 compliant 16 receive buffers each with its own message filter Standard and extended frames with up to 8 bytes of data per Econvhearnsc tehde hIDar, dIDwEar aen md eRsTsaRge filter implementation that frame Message filter capabilities DeviceNet addressing support Remote Transmission Request (RTR) support Mmuelstispaleg ere acreraivye buffers linkable to build a larger receive Programmable bit rate up to 1 Mbps Automatic transmission request (RTR) response handler Listen Only mode Lost received message notification SW readable error counter and indicator Transmit path Sleep mode: Wake the device from sleep with activity on the Eight transmit buffers Rx pin Programmable transmit priority Round robin Supports two or three wire interface to external transceiver (Tx, Fixed priority Rx, and Enable). The three-wire interface is compatible with Message transmissions abort capability the Philips PHY; the PHY is not included on-chip. The three wires can be routed to any I/O 7.5.2 Software Tools Support Enhanced interrupt controller CAN Controller configuration integrated into PSoC Creator: CAN receive and transmit buffers status CAN Configuration walkthrough with bit timing analyzer CAN controller error status including BusOff Receive filter setup Document Number: 001-84935 Rev. *L Page 46 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 7-15. CAN Controller Block Diagram TxMessage0 TxReq TxAbort Tx Buffer TxMessage1 Bit Timing Status TxReq TxReq TxAbort Pending Priority Tx TxMessage6 Arbiter Tx CRC TxReq CAN Generator TxInterrupt TxAbort Framer Request (if enabled) TxMessage7 TxReq TxAbort Error Status  Error Active  Error Passive RTR RxMessages  Bus Off 0-15 Tx Error Counter Rx Error Counter Rx Buffer RxMessage0 Acceptance Code 0 Acceptance Mask 0 Status RxMessage RxMessage1 Acceptance Code 1 Acceptance Mask 1 Rx Available Rx RxMessage CAN CRC Check Handler Framer RxMessage14 Acceptance Code 14 Acceptance Mask 14 RxInterrupt Request RxMessage15 Acceptance Code 15 Acceptance Mask 15 (if enabled) WakeUp Error Detection Request CRC Form ErrInterrupt ACK Request Bit Stuffing (if enabled) Bit Error Overload Arbitration 7.6 USB Internal 48 MHz oscillator that auto locks to USB bus clock, requiring no external crystal for USB (USB equipped parts only) PSoC includes a dedicated FS (12 Mbps) USB 2.0 transceiver supporting all four USB transfer types: control, interrupt, bulk, Interrupts on bus and each endpoint event, with device wakeup and isochronous. PSoC Creator provides full configuration support. USB interfaces to hosts through two dedicated USBIO USB Reset, Suspend, and Resume operations pins, which are detailed in the “I/O System and Routing” section Bus powered and self powered modes on page32. Figure 7-16. USB USB includes the following features: Eight unidirectional data endpoints 512 X 8 Arbiter SRAM One bidirectional control endpoint 0 (EP0) External 22  Shared 512-byte buffer for the eight data endpoints us D+ Resistors B S I E Dedicated 8-byte buffer for EP0 stem (SerEianl gIninteer)face UI/SOB y Three memory modes S Interrupts D– Manual Memory Management with No DMA Access 48 MHz Manual Memory Management with Manual DMA Access IMO Automatic Memory Management with Automatic DMA Access Internal 3.3V regulator for transceiver Document Number: 001-84935 Rev. *L Page 47 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 7.7 Timers, Counters, and PWMs 7.8 I2C The Timer/Counter/PWM peripheral is a 16-bit dedicated PSoC includes a single fixed-function I2C peripheral. Additional peripheral providing three of the most common embedded I2C interfaces can be instantiated using Universal Digital Blocks peripheral features. As almost all embedded systems use some (UDBs) in PSoC Creator, as required. combination of timers, counters, and PWMs. Four of them have The I2C peripheral provides a synchronous two-wire interface been included on this PSoC device family. Additional and more designed to interface the PSoC device with a two-wire I2C serial advanced functionality timers, counters, and PWMs can also be communication bus. It is compatible[13] with I2C Standard-mode, instantiated in Universal Digital Blocks (UDBs) as required. Fast-mode, and Fast-mode Plus devices as defined in the NXP PSoC Creator allows you to choose the timer, counter, and PWM I2C-bus specification and user manual (UM10204). The I2C bus features that they require. The tool set utilizes the most optimal I/O may be implemented with GPIO or SIO in open-drain modes. resources available. To eliminate the need for excessive CPU intervention and The Timer/Counter/PWM peripheral can select from multiple overhead, I2C specific support is provided for status detection clock sources, with input and output signals connected through and generation of framing bits. I2C operates as a slave, a master, the DSI routing. DSI routing allows input and output connections or multimaster (Slave and Master)[13]. In slave mode, the unit to any device pin and any internal digital signal accessible always listens for a start condition to begin sending or receiving through the DSI. Each of the four instances has a compare data. Master mode supplies the ability to generate the Start and output, terminal count output (optional complementary compare Stop conditions and initiate transactions. Multimaster mode output), and programmable interrupt request line. The provides clock synchronization and arbitration to allow multiple Timer/Counter/PWMs are configurable as free running, one shot, masters on the same bus. If Master mode is enabled and Slave or Enable input controlled. The peripheral has timer reset and mode is not enabled, the block does not generate interrupts on capture inputs, and a kill input for control of the comparator externally generated Start conditions. I2C interfaces through the outputs. The peripheral supports full 16-bit capture. DSI routing and allows direct connections to any GPIO or SIO pins. Timer/Counter/PWM features include: I2C provides hardware address detect of a 7-bit address without 16-bit Timer/Counter/PWM (down count only) CPU intervention. Additionally the device can wake from low Selectable clock source power modes on a 7-bit hardware address match. If wakeup functionality is required, I2C pin connections are limited to one of PWM comparator (configurable for LT, LTE, EQ, GTE, GT) two specific pairs of SIO pins. See descriptions of SCL and SDA pins in Pin Descriptions on page 11. Period reload on start, reset, and terminal count Interrupt on terminal count, compare true, or capture I2C features include: Dynamic counter reads Slave and master, transmitter, and receiver operation Timer capture mode Byte processing for low CPU overhead Count while enable signal is asserted mode Interrupt or polling CPU interface Free run mode Support for bus speeds up to 1 Mbps One Shot mode (stop at end of period) 7 or 10-bit addressing (10-bit addressing requires firmware support) Complementary PWM outputs with deadband SMBus operation (through firmware support - SMBus PWM output kill supported in hardware in UDBs) Figure 7-17. Timer/Counter/PWM 7-bit hardware address compare Clock Wake from low power modes on address match IRQ Reset Timer / Counter / Glitch filtering (active and alternate-active modes only) Enable TC / Compare! Capture PWM 16-bit Compare Data transfers follow the format shown in Figure7-18. After the Kill START condition (S), a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W) - a 'zero' indicates a transmission (WRITE), a 'one' indicates a request for data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master. Notes 12.The I2C peripheral is non-compliant with the NXP I2C specification in the following areas: analog glitch filter, I/O VOL/IOL, I/O hysteresis. The I2C Block has a digital glitch filter (not available in sleep mode). The Fast-mode minimum fall-time specification can be met by setting the I/Os to slow speed mode. See the I/O Electrical Specifications in “Inputs and Outputs” section on page75 for details. 13.Fixed-block I2C does not support undefined bus conditions, nor does it support Repeated Start in Slave mode. These conditions should be avoided, or the UDB-based I2C component should be used instead. Document Number: 001-84935 Rev. *L Page 48 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 7-18. I2C Complete Transfer Timing SDA SCL 1 - 7 8 9 1 - 7 8 9 1 - 7 8 9 START STOP ADDRESS R/W ACK DATA ACK DATA ACK Condition Condition 7.8.1 External Electrical Connections Equation 1: As Figure 7-19 shows, the I2C bus requires external pull-up R = V max–V maxI min PMIN DD OL OL resistors (R ). These resistors are primarily determined by the P supply voltage, bus speed, and bus capacitance. For detailed Equation 2: information on how to calculate the optimum pull-up resistor R = T max0.8473C max value for your design, we recommend using the UM10204 PMAX R B I2C-bus specification and user manual Rev 6, or newer, available Equation 3: from the NXP website at www.nxp.com. R = V min–V min+V minI max PMAX DD IH NH IH Figure 7-19. Connection of Devices to the I2C Bus Equation parameters: V = Nominal supply voltage for I2C bus DD V = Maximum output low voltage of bus devices. OL I = Low-level output current from I2C specification OL T = Rise Time of bus from I2C specification R C = Capacitance of each bus line including pins and PCB traces B V = Minimum high-level input voltage of all bus devices IH V = Minimum high-level input noise margin from I2C specifi- NH cation IIH = Total input leakage current of all devices on the bus The supply voltage (V ) limits the minimum pull-up resistor DD value due to bus devices maximum low output voltage (V ) For most designs, the default values in Table7-2 will provide OL specifications. Lower pull-up resistance increases current excellent performance without any calculations. The default though the pins and can, therefore, exceed the spec conditions values were chosen to use standard resistor values between the of V . Equation 1 is derived using Ohm's law to determine the minimum and maximum limits. The values in Table7-2 work for OH minimum resistance that will still meet the V specification at designs with 1.8 V to 5.0V V , less than 200-pF bus capaci- OL DD 3mA for standard and fast modes, and 20 mA for fast mode plus tance (C ), up to 25 µA of total input leakage (I ), up to 0.4V B IL at the given V . output voltage level (V ), and a max V of 0.7 * V . Standard DD OL IH DD Mode and Fast Mode can use either GPIO or SIO PSoC pins. Equation 2 determines the maximum pull-up resistance due to Fast Mode Plus requires use of SIO pins to meet the V spec bus capacitance. Total bus capacitance is comprised of all pin, OL at 20 mA. Calculation of custom pull-up resistor values is wire, and trace capacitance on the bus. The higher the bus required; if your design does not meet the default assumptions, capacitance, the lower the pull-up resistance required to meet you use series resistors (RS) to limit injected noise, or you need the specified bus speeds rise time due to RC delays. Choosing to maximize the resistor value for low power consumption. a pull-up resistance higher than allowed can result in failing timing requirements resulting in communication errors. Most Table 7-2. Recommended default Pull-up Resistor Values designs with five or less I2C devices and up to 20 centimeters of R Units bus trace length have less than 100 pF of bus capacitance. P Standard Mode – 100 kbps 4.7 k, 5% Ω A secondary effect that limits the maximum pull-up resistor value is total bus leakage calculated in Equation 3. The primary source Fast Mode – 400 kbps 1.74 k, 1% Ω of leakage is I/O pins connected to the bus. If leakage is too high, Fast Mode Plus – 1 Mbps 620, 5% Ω the pull-ups will have difficulty maintaining an acceptable V IH level causing communication errors. Most designs with five or Calculation of the ideal pull-up resistor value involves finding a less I2C devices on the bus have less than 10 µA of total leakage value between the limits set by three equations detailed in the current. NXP I2C specification. These equations are: Document Number: 001-84935 Rev. *L Page 49 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 7.9 Digital Filter Block The DFB processes this data and passes the result to another on chip resource such as a DAC or main memory through DMA Some devices in the CY8C56LP family of devices have a on the system bus. dedicated HW accelerator block used for digital filtering. The DFB has a dedicated multiplier and accumulator that calculates Data movement in or out of the DFB is typically controlled by the a 24-bit by 24-bit multiply accumulate in one system clock cycle. system DMA controller but can be moved directly by the MCU. This enables the mapping of a direct form FIR filter that 8. Analog Subsystem approaches a computation rate of one FIR tap for each clock cycle. The MCU can implement any of the functions performed by this block, but at a slower rate that consumes significant MCU The analog programmable system creates application specific bandwidth. combinations of both standard and advanced analog signal processing blocks. These blocks are then interconnected to The PSoC Creator interface provides a wizard to implement FIR each other and also to any pin on the device, providing a high and IIR digital filters with coefficients for LPF, BPF, HPF, Notch level of design flexibility and IP security. The features of the and arbitrary shape filters. 64 pairs of data and coefficients are analog subsystem are outlined here to provide an overview of stored. This enables a 64 tap FIR filter or up to 4 16 tap filters of capabilities and architecture. either FIR or IIR formulation. Flexible, configurable analog routing architecture provided by Figure 7-20. DFB Application Diagram (pwr/gnd not shown) analog globals, analog mux bus, and analog local buses High resolution Delta-Sigma ADC BUSCLK read_data Data Source Two successive approximation (SAR) ADCs write_data (PHUB) System Four 8-bit DACs that provide either voltage or current output Bus addr Digital Digital Filter Four comparators with optional connection to configurable LUT Routing Block Data outputs Dest (PHUB) Four configurable switched capacitor/continuos time (SC/CT) DMA blocks for functions that include opamp, unity gain buffer, Request programmable gain amplifier, transimpedance amplifier, and DMA CTRL mixer Four opamps for internal use and connection to GPIO that can be used as high current output buffers The typical use model is for data to be supplied to the DFB over CapSense subsystem to enable capacitive touch sensing the system bus from another on-chip system data source such as an ADC. The data typically passes through main memory or Precision reference for generating an accurate analog voltage is directly transferred from another chip resource through DMA. for internal analog blocks Document Number: 001-84935 Rev. *L Page 50 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 8-1. Analog Subsystem Block Diagram SAR SAR ADC ADC DAC DAC DelSig ADC RPerefecriseinocne A DAC DAC A N N A A L L O SC/CT Block SC/CT Block O GPIO G G GPIO Port R OpAmp SC/CT Block SC/CT Block AmpOp R Port O O U U T Opmp Comparators AmO T I A pp I N CMP CMP CMP CMP N G G CapSense Subsystem Analog Config & Status Interface PHUB CPU Registers DSI Clock Decimator Array Distribution The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and various analog resources and also connections from one analog resource to another. PSoC Creator also provides component libraries that allow you to configure the various analog blocks to perform application specific functions (PGA, transimpedance amplifier, voltage DAC, current DAC, and so on). The tool also generates API interface libraries that allow you to write firmware that allows the communication between the analog peripheral and CPU/Memory. Document Number: 001-84935 Rev. *L Page 51 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 8.1 Analog Routing 8.1.2 Functional Description The PSoC 5LP family of devices has a flexible analog routing Analog globals (AGs) and analog mux buses (AMUXBUS) architecture that provides the capability to connect GPIOs and provide analog connectivity between GPIOs and the various different analog blocks, and also route signals between different analog blocks. There are 16 AGs in the PSoC 5LP family. The analog blocks. One of the strong points of this flexible routing analog routing architecture is divided into four quadrants as architecture is that it allows dynamic routing of input and output shown in Figure8-2. Each quadrant has four analog globals connections to the different analog blocks. (AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is connected to the corresponding AG through an analog switch. For information on how to make pin selections for optimal analog The analog mux bus is a shared routing resource that connects routing, refer to the application note, AN58304 - PSoC® 3 and to every GPIO through an analog switch. There are two PSoC® 5 - Pin Selection for Analog Designs. AMUXBUS routes in PSoC 5LP, one in the left half (AMUXBUSL) and one in the right half (AMUXBUSR), as shown in Figure8-2. 8.1.1 Features Analog local buses (abus) are routing resources located within Flexible, configurable analog routing architecture the analog subsystem and are used to route signals between 16 Analog globals (AG) and two analog mux buses different analog blocks. There are eight abus routes in (AMUXBUS) to connect GPIOs and the analog blocks PSoC5LP, four in the left half (abusl [0:3]) and four in the right half (abusr [0:3]) as shown in Figure8-2. Using the abus saves Each GPIO is connected to one analog global and one analog the analog globals and analog mux buses from being used for mux bus interconnecting the analog blocks. 8 Analog local buses (abus) to route signals between the Multiplexers and switches exist on the various buses to direct different analog blocks signals into and out of the analog blocks. A multiplexer can have only one connection on at a time, whereas a switch can have Multiplexers and switches for input and output selection of the multiple connections on simultaneously. In Figure8-2, analog blocks multiplexers are indicated by grayed ovals and switches are indicated by transparent ovals. Document Number: 001-84935 Rev. *L Page 52 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 8-2. CY8C56LP Analog Interconnect V V V V d s c s d s c s a* a* a* d* Vddio0*swP0[3]inn*GPIOswP0[2]inp*GPIOP0[1]*GPIOP0[0]*GPIOP4[1]GPIOP4[0]GPIOP12[3]SIOP12[2]SIO AMUXBUSL AMUXBUSRP15[3]*GPIOP15[2]*GPIOP12[1]*SIOP12[0]*SIOP3[7]GPIOP3[6]GPIO Vddio3* AGL[4] AGR[4] AGL[5] AGR[5] AGL[6] AGR[6] USL AGL[7] AGR[7] GPIO swAMUXBinpAGL[4]AGL[5]AGL[6]AGL[7] EExxVVrreeffLL1 opamp0 opamp2 01234Ex5V6re7fL20123 3210 76543210 opamp3 opamp1 sswwiinnpn GP3P[I5O] P0[4*] swfol swfol swfol swfol GPIO GP0P[I5O*] swinn swinp GP3P[I4O] GGP0PP[II6OO] * i0 ab(u1f._0v2r4eVf_)int swout swin ionu0t0 LPF oiunt11 swin swout ab(u1f._0v2r4eVf_)int ExVrefR swinn GPP33P[[I32O]] P0[7]* i2 +- comp0 comp1 +- i3 GP3P[I1O] GGGPP44PPP[[III32OOO]] VrdVecbfrdb(demcg1aufmd_bfv./p_vuap02(rdv0f_0_e2ram_ev._f42fr_uvr1eVex5c rf(sv2e)16m_n .f(eV[0 11pn2.):2104V]V )) cmprefbufl_1_cmpvrefcmp1_vref bg_vda_swabusl0 +-orCeuftcOoCmMpA2PPASRENATScoOmEpR3oreuft+- cmp1_vref refbufr_cmp rreecffbb(mu1uff_.p_0vv0r2re_e4ff2v1V r ((1e)1.f.20 V2)4V) i1 **PPGGGP11PP3P55[XXI[[0O01TT]]] in refbufl refbufr in GPP44P[[I45O]] refsel[1:0] vssa Vscin0 sVcin1 Vssa refsel[1:0] AGR[7]AGR[6]AGR[5]AGR[4]XBUSR GGP4PP[II6OO] ss((cc1102..00__22bb44ggVVrree))ff VoVurinetf SC/CT VVorieunft s(c1s3(.c01_12.b0_4g2bVr4ge)Vrf e)f AMU *Vccd PV4c[c7d]* oVsucre2tf Vsorceu3ft **VVdsdsdd * Vssd ABUSL0 ABUSR0 ABUSL1 ABUSR1 ABUSL2 ABUSR2 ABUSL3 ABUSR3 * Vddd GPIO vi00DAC0VIDACDAC1vi11 *UPS1B5[ 7IO] P6[0] USB IO GP6P[I1O] vi22DAC2 DAC3vi33 *PG1P5IO[6] GPIO dac_vref (0.256V) P5[7] GGPP66PP[[II32OO]] ddssmm00__vvccmm__vvrreeff12v s((v00sc..dm87sVVe))l[1:0] vssa +v-cDqmtSzM_r0ef reDfsS M GGPP55PP[[II65OO]] P15[4] dsm0_qtz_vref2 (1.2V) vref_vss_ext GPIO PGGP12PP5[II[0OO5]] dsm0_qtz_vref1 V(V1dd.d0da2a/4/34V) refmux[2:0] VVVpnr e((+-f)h)iSE_oAxuVRtr0efL SEAVxRVrer1feh(f(i+R_-))o VVutnp PPSS152II[OO4[7]] GP2P[I1O] SASRA_Rvr_evfr1e (f21 .(012.24VV)) refsSAR ADCrefs SSAARR__vvrreeff21 ((11..022V4)V) PG1P2I[O6] GGP2PP[II2OO] VVddddaa/2 en_resvdaAreMfmuUx[2X:0]BUSL01234567 0123 ExVrefL1 ExVrefL2 3210 76543210 AMUrXefmBuxU[2:0S]Ren_resvda VVddddaa/2 **GPP11P[[I67O]] P2[3]* ANALOG ANALOG ANALOG ANALOG GPIO GLOBALS BUS BUS GLOBALS VPd2d[i4o]2**MUXBUSLAGL[0]AGL[1]AGL[2]AGL[3] : ATDSC VVssB Eref LPF AGL[3] AGR[3] AGR[3]AGR[2]AGR[1]AGR[0]AMUXBUSR A AGL[2] AGR[2] AGL[1] AGR[1] AGL[0] AGR[0] AMUXBUSL AMUXBUSR * * * * * SCwMoinutcnxh eG cGtrirooounupp GPIO*P2[5]GPIO*P2[6]GPIO*P2[7]SIOP12[4]SIOP12[5]GPIOP6[4]GPIOP6[5]GPIOP6[6]GPIOP6[7] GPIOP5[0]GPIOP5[1]GPIOP5[2]GPIOP5[3]GPIOP1[0]GPIOP1[1]GPIOP1[2]GPIOP1[3]GPIO*P1[4]GPIO*P1[5] Vddio1 Switch Resistance * * * * * Notes: SLmaraglel (( ~~827000 OOhhmmss )) Ind Vssb Vbat Vboost Vssd XRES * DLCenDo tseigsn painlss a orne anlol tp sahcokwagne.s Rev #60 10-Feb-2012 To preserve detail of this image, this image is best viewed with a PDF display program or printed on 11” × 17” paper. Document Number: 001-84935 Rev. *L Page 53 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 8.2 Delta-sigma ADC Figure 8-4. Delta-sigma ADC Block Diagram Some CY8C36 devices offer a delta-sigma ADC. This ADC Positive offers differential input, high resolution and excellent linearity, Input Mux making it a good ADC choice for measurement applications. The Input Delta 12 to 20 Bit converter can be configured to output 12-bit resolution at data (Analog Routing) Buffer MSodigumlaato r Decimator Result rates of up to 192 ksps. At a fixed clock rate, resolution can be Negative EOC Input Mux traded for faster data rates as shown in Table8-1 and Figure8-3. SOC Table 8-1. Delta-sigma ADC Performance Maximum Sample Rate Bits SINAD (dB) Resolution and sample rate are controlled by the Decimator. (sps) Data is pipelined in the decimator; the output is a function of the 12 192 k 66 last four samples. When the input multiplexer is switched, the 8 384 k 43 output data is not valid until after the fourth sample after the switch. 8.2.2 Operational Modes Figure 8-3. Delta-sigma ADC Sample Rates, Range = ±1.024V The ADC can be configured by the user to operate in one of four 1,000,000 modes: Single Sample, Multi Sample, Continuous, or Multi Sample (Turbo). All four modes are started by either a write to the start bit in a control register or an assertion of the Start of Conversion (SoC) signal. When the conversion is complete, a status bit is set and the output signal End of Conversion (EoC) 100,000 asserts high and remains high until the value is read by either the DMA controller or the CPU. 8.2.2.1 Single Sample s sp 10,000 In Single Sample mode, the ADC performs one sample s, conversion on a trigger. In this mode, the ADC stays in standby e at state waiting for the SoC signal to be asserted. When SoC is ple r signaled the ADC performs four successive conversions. The am first three conversions prime the decimator. The ADC result is S 1,000 valid and available after the fourth conversion, at which time the Continuous EoC signal is generated. To detect the end of conversion, the Multi-Sample system may poll a control register for status or configure the external EoC signal to generate an interrupt or invoke a DMA 100 request. When the transfer is done the ADC reenters the standby 7 8 9 10 11 12 13 state where it stays until another SoC event. Resolution, bits 8.2.2.2 Continuous Continuous sample mode is used to take multiple successive samples of a single input signal. Multiplexing multiple inputs 8.2.1 Functional Description should not be done with this mode. There is a latency of three The ADC connects and configures three basic components, conversion times before the first conversion result is available. input buffer, delta-sigma modulator, and decimator. The basic This is the time required to prime the decimator. After the first block diagram is shown in Figure8-4. The signal from the input result, successive conversions are available at the selected muxes is delivered to the delta-sigma modulator either directly or sample rate. through the input buffer. The delta-sigma modulator performs the actual analog to digital conversion. The modulator over-samples 8.2.2.3 Multi Sample the input and generates a serial data stream output. This high Multi sample mode is similar to continuous mode except that the speed data stream is not useful for most applications without ADC is reset between samples. This mode is useful when the some type of post processing, and so is passed to the decimator input is switched between multiple signals. The decimator is through the Analog Interface block. The decimator converts the re-primed between each sample so that previous samples do not high speed serial data stream into parallel ADC results. The affect the current conversion. Upon completion of a sample, the modulator/decimator frequency response is [(sin x)/x]4. next sample is automatically initiated. The results can be transferred using either firmware polling, interrupt, or DMA. More information on output formats is provided in the Technical Reference Manual. Document Number: 001-84935 Rev. *L Page 54 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 8.2.3 Start of Conversion Input 8.3.2 Conversion Signals The SoC signal is used to start an ADC conversion. A digital Writing a start bit or assertion of a Start of Frame (SOF) signal is clock or UDB output can be used to drive this input. It can be used to start a conversion. SOF can be used in applications used when the sampling period must be longer than the ADC where the sampling period is longer than the conversion time, or conversion time or when the ADC must be synchronized to other when the ADC needs to be synchronized to other hardware. This hardware. This signal is optional and does not need to be signal is optional and does not need to be connected if the SAR connected if ADC is running in a continuous mode. ADC is running in a continuous mode. A digital clock or UDB output can be used to drive this input. When the SAR is first 8.2.4 End of Conversion Output powered up or awakened from any of the sleeping modes, there The EoC signal goes high at the end of each ADC conversion. is a power up wait time of 10 µs before it is ready to start the first This signal may be used to trigger either an interrupt or DMA conversion. request. When the conversion is complete, a status bit is set and the output signal End of Frame (EOF) asserts and remains asserted 8.3 Successive Approximation ADCs until the value is read by either the DMA controller or the CPU. The CY8C56LP family of devices has one or two Successive The EOF signal may be used to trigger an interrupt or a DMA Approximation (SAR) ADCs, depending on device selected. request. These ADCs are 12-bit at up to 1 Msps, with single-ended or 8.3.3 Operational Modes differential inputs, making them useful for a wide variety of sampling and control applications. A ONE_SHOT control bit is used to set the SAR ADC conversion mode to either continuous or one conversion per SOF signal. 8.3.1 Functional Description DMA transfer of continuous samples, without CPU intervention, In a SAR ADC an analog input signal is sampled and compared is supported. with the output of a DAC. A binary search algorithm is applied to 8.4 Comparators the DAC and used to determine the output bits in succession from MSB to LSB. A block diagram of one SAR ADC is shown in The CY8C56LP family of devices contains four comparators. Figure8-5. Comparators have these features: Figure 8-5. SAR ADC Block Diagram Input offset factory trimmed to less than 5 mV vin S/H Rail-to-rail common mode input range (VSSA to VDDA) SAR vrefp DAC comparator digital D0:D11 Speed and power can be traded off by using one of three array modes: fast, slow, or ultra low power vrefn 1 1 Comparator outputs can be routed to look up tables to perform D autozero D0: reset simple logic functions and then can also be routed to digital clock blocks The positive input of the comparators may be optionally passed clock through a low pass filter. Two filters are provided POWER power vrefp GROUND filtering vrefn Comparator inputs can be connections to GPIO, DAC outputs and SC block outputs 8.4.1 Input and Output Interface The input is connected to the analog globals and muxes. The frequency of the clock is 18 times the sample rate; the clock rate The positive and negative inputs to the comparators come from ranges from 1 to 18 MHz. the analog global buses, the analog mux line, the analog local bus and precision reference through multiplexers. The output from each comparator could be routed to any of the two input LUTs. The output of that LUT is routed to the UDB Digital System Interface. Document Number: 001-84935 Rev. *L Page 55 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 8-6. Analog Comparator ANAIF From + Analog comp0 + From _ Routing comp1 Analog _ Routing + From comp3 Analog From + _ Routing Analog comp2 _ Routing 4 4 4 4 4 4 4 4 LUT0 LUT1 LUT2 LUT3 UDBs 8.4.2 LUT Table 8-2. LUT Function vs. Program Word and Inputs The CY8C56LP family of devices contains four LUTs. The LUT Control Word Output (A and B are LUT inputs) is a two input, one output lookup table that is driven by any one 0000b FALSE (‘0’) or two of the comparators in the chip. The output of any LUT is 0001b A AND B routed to the digital system interface of the UDB array. From the 0010b A AND (NOT B) digital system interface of the UDB array, these signals can be 0011b A connected to UDBs, DMA controller, I/O, or the interrupt controller. 0100b (NOT A) AND B 0101b B The LUT control word written to a register sets the logic function on the output. The available LUT functions and the associated 0110b A XOR B control word is shown in Table8-2. 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b NOT B 1011b A OR (NOT B) 1100b NOT A 1101b (NOT A) OR B 1110b A NAND B 1111b TRUE (‘1’) Document Number: 001-84935 Rev. *L Page 56 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 8.5 Opamps The opamp has three speed modes, slow, medium, and fast. The slow mode consumes the least amount of quiescent power and The CY8C56LP family of devices contain four general purpose the fast mode consumes the most power. The inputs are able to opamps. swing rail-to-rail. The output swing is capable of rail-to-rail Figure 8-7. Opamp operation at low current output, within 50 mV of the rails. When driving high current loads (about 25 mA) the output voltage may only get within 500 mV of the rails. GPIO 8.6 Programmable SC/CT Blocks Analog Global Bus The CY8C56LP family of devices contains four switched Analog Opamp GPIO capacitor/continuous time (SC/CT) blocks. Each switched Global Bus capacitor/continuous time block is built around a single rail-to-rail VREF high bandwidth opamp. Analog Switched capacitor is a circuit design technique that uses Internal Bus capacitors plus switches instead of resistors to create analog = Analog Switch functions. These circuits work by moving charge between GPIO capacitors by opening and closing different switches. Nonoverlapping in phase clock signals control the switches, so that not all switches are ON simultaneously. The opamp is uncommitted and can be configured as a gain stage or voltage follower on external or internal signals. The PSoC Creator tool offers a user friendly interface, which allows you to easily program the SC/CT blocks. Switch control See Figure8-8. In any configuration, the input and output signals and clock phase control configuration is done by PSoC Creator can all be connected to the internal global signals and monitored so users only need to determine the application use parameters with an ADC, or comparator. The configurations are such as gain, amplifier polarity, V connection, and so on. implemented with switches between the signals and GPIO pins. REF The same opamps and block interfaces are also connectable to Figure 8-8. Opamp Configurations an array of resistors which allows the construction of a variety of continuous time functions. a) Voltage Follower The opamp and resistor array is programmable to perform various analog functions including Naked Operational Amplifier - Continuous Mode Opamp Vout to Pin Unity-Gain Buffer - Continuous Mode Vin Programmable Gain Amplifier (PGA) - Continuous Mode Transimpedance Amplifier (TIA) - Continuous Mode b) External Uncommitted Up/Down Mixer - Continuous Mode Opamp Sample and Hold Mixer (NRZ S/H) - Switched Cap Mode First Order Analog to Digital Modulator - Switched Cap Mode 8.6.1 Naked Opamp Opamp Vout to GPIO The Naked Opamp presents both inputs and the output for connection to internal or external signals. The opamp has a unity gain bandwidth greater than 6.0 MHz and output drive current up Vp to GPIO to 650 µA. This is sufficient for buffering internal signals (such as Vn to GPIO DAC outputs) and driving external loads greater than 7.5 kohms. 8.6.2 Unity Gain c) Internal Uncommitted The Unity Gain buffer is a Naked Opamp with the output directly Opamp connected to the inverting input for a gain of 1.00. It has a -3 dB bandwidth greater than 6.0 MHz. Vn To Internal Signals Opamp Vout to Pin Vp GPIO Pin Document Number: 001-84935 Rev. *L Page 57 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 8.6.3 PGA Table 8-4. Feedback Resistor Settings The PGA amplifies an external or internal signal. The PGA can 101b 250 be configured to operate in inverting mode or noninverting mode. 110b 500 The PGA function may be configured for both positive and negative gains as high as 50 and 49 respectively. The gain is 111b 1000 adjusted by changing the values of R1 and R2 as illustrated in Figure8-9. The schematic in Figure8-9 shows the configuration Figure 8-10. Continuous Time TIA Schematic and possible resistor settings for the PGA. The gain is switched from inverting and non inverting by changing the shared select value of the both the input muxes. The bandwidth for each gain Rfb case is listed in Table8-3. Table 8-3. Bandwidth Gain Bandwidth 1 6.0 MHz Iin 24 340 kHz Vout 48 220 kHz Vref 50 215 kHz Figure 8-9. PGA Resistor Settings The TIA configuration is used for applications where an external sensor's output is current as a function of some type of stimulus R1 R2 Vin 0 such as temperature, light, magnetic flux etc. In a common application, the voltage DAC output can be connected to the V 1 V TIA input to allow calibration of the external sensor bias ref 20 k or 40 k 20 k to 980 k REF current by adjusting the voltage DAC output voltage. S 8.7 LCD Direct Drive Vref 0 The PSoC Liquid Crystal Display (LCD) driver system is a highly configurable peripheral designed to allow PSoC to directly drive V 1 a broad range of LCD glass. All voltages are generated on chip, in eliminating the need for external components. With a high multiplex ratio of up to 1/16, the CY8C56LP family LCD driver system can drive a maximum of 736 segments. The PSoC LCD The PGA is used in applications where the input signal may not driver module was also designed with the conservative power be large enough to achieve the desired resolution in the ADC, or budget of portable devices in mind, enabling different LCD drive dynamic range of another SC/CT block such as a mixer. The gain modes and power down modes to conserve power. is adjustable at runtime, including changing the gain of the PGA PSoC Creator provides an LCD segment drive component. The prior to each ADC sample. component wizard provides easy and flexible configuration of LCD resources. You can specify pins for segments and 8.6.4 TIA commons along with other options. The software configures the The Transimpedance Amplifier (TIA) converts an internal or device to meet the required specifications. This is possible external current to an output voltage. The TIA uses an internal because of the programmability inherent to PSoC devices. feedback resistor in a continuous time configuration to convert Key features of the PSoC LCD segment system are: input current to output voltage. For an input current I , the output in voltage is V - I x R , where V is the value placed on the LCD panel direct driving REF in fb REF non inverting input. The feedback resistor Rfb is programmable Type A (standard) and Type B (low power) waveform support between 20 K and 1M through a configuration register. Table8-4 shows the possible values of Rfb and associated Wide operating voltage range support (2V to 5V) for LCD panels configuration settings. Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels Table 8-4. Feedback Resistor Settings Internal bias voltage generation through internal resistor ladder Configuration Word Nominal R (K) fb Up to 62 total common and segment outputs 000b 20 Up to 1/16 multiplex for a maximum of 16 backplane/common 001b 30 outputs 010b 40 Up to 62 front plane/segment outputs for direct drive 011b 60 Drives up to 736 total segments (16 backplane x 46 front plane) 100b 120 Up to 64 levels of software controlled contrast Document Number: 001-84935 Rev. *L Page 58 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Ability to move display data from memory buffer to LCD driver 8.7.4 LCD DAC through DMA (without CPU intervention) The LCD DAC generates the contrast control and bias voltage Adjustable LCD refresh rate from 10 Hz to 150 Hz for the LCD system. The LCD DAC produces up to five LCD drive voltages plus ground, based on the selected bias ratio. The bias Ability to invert LCD display for negative image voltages are driven out to GPIO pins on a dedicated LCD bias Three LCD driver drive modes, allowing power optimization bus, as required. Figure 8-11. LCD System 8.8 CapSense LCD Global The CapSense system provides a versatile and efficient means DAC Clock for measuring capacitance in applications such as touch sense buttons, sliders, proximity detection, etc. The CapSense system uses a configuration of system resources, including a few hardware functions primarily targeted for CapSense. Specific UDB PIN resource usage is detailed in the CapSense component in PSoC LCD Driver Creator. Block A capacitive sensing method using a delta-sigma modulator (CSD) is used. It provides capacitance sensing using a switched Display DMA RAM capacitor technique with a delta-sigma modulator to convert the sensing current to a digital code. 8.9 Temp Sensor Die temperature is used to establish programming parameters PHUB for writing flash. Die temperature is measured using a dedicated sensor based on a forward biased transistor. The temperature sensor has its own auxiliary ADC. 8.7.1 LCD Segment Pin Driver Each GPIO pin contains an LCD driver circuit. The LCD driver 8.10 DAC buffers the appropriate output of the LCD DAC to directly drive The CY8C56LP parts contain four Digital to Analog Convertors the glass of the LCD. A register setting determines whether the (DACs). Each DAC is 8-bit and can be configured for either pin is a common or segment. The pin’s LCD driver then selects voltage or current output. The DACs support CapSense, power one of the six bias voltages to drive the I/O pin, as appropriate supply regulation, and waveform generation. Each DAC has the for the display data. following features. 8.7.2 Display Data Flow Adjustable voltage or current output in 255 steps The LCD segment driver system reads display data and Programmable step size (range selection) generates the proper output voltages to the LCD glass to produce the desired image. Display data resides in a memory Eight bits of calibration to correct ± 25% of gain error buffer in the system SRAM. Each time you need to change the common and segment driver voltages, the next set of pixel data Source and sink option for current output moves from the memory buffer into the Port Data Registers via 8 Msps conversion rate for current output DMA. 1 Msps conversion rate for voltage output 8.7.3 UDB and LCD Segment Control Monotonic in nature A UDB is configured to generate the global LCD control signals and clocking. This set of signals is routed to each LCD pin driver Data and strobe inputs can be provided by the CPU or DMA, through a set of dedicated LCD global routing channels. In or routed directly from the DSI addition to generating the global LCD control signals, the UDB Dedicated low-resistance output pin for high-current mode also produces a DMA request to initiate the transfer of the next frame of LCD data. Document Number: 001-84935 Rev. *L Page 59 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 8-12. DAC Block Diagram I Range  source  1x, 8x, 64x Vout Reference  Scaler Iout R Source 3R I Range     sink  1x, 8x, 64x 8.10.1 Current DAC frequency components at odd integer multiples of the local oscillator frequency. The local oscillator frequency is provided by The current DAC (IDAC) can be configured for the ranges 0 to the selected clock source for the mixer. 31.875 µA, 0 to 255 µA, and 0 to 2.04 mA. The IDAC can be configured to source or sink current. Continuous time up and down mixing works for applications with input signals and local oscillator frequencies up to 1 MHz. 8.10.2 Voltage DAC Figure 8-13. Mixer Configuration For the voltage DAC (VDAC), the current DAC output is routed through resistors. The two ranges available for the VDAC are 0 C2 = 1.7 pF to 1.02V and 0 to 4.08V. In voltage mode any load connected to the output of a DAC should be purely capacitive (the output of C1 = 850 fF the VDAC is not buffered). Rmix 0 20 k or 40 k 8.11 Up/Down Mixer In continuous time mode, the SC/CT block components are used to build an up or down mixer. Any mixing application contains an Rmix 0 20 k or 40 k sc_clk input signal frequency and a local oscillator frequency. The Vin polarity of the clock, Fclk, switches the amplifier between Vout 0 inverting or noninverting gain. The output is the product of the Vref 1 input and the switching function from the local oscillator, with frequency components at the local oscillator plus and minus the sc_clk signal frequency (Fclk + Fin and Fclk - Fin) and reduced-level Document Number: 001-84935 Rev. *L Page 60 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 8.12 Sample and Hold 9. Programming, Debug Interfaces, The main application for a sample and hold, is to hold a value Resources stable while an ADC is performing a conversion. Some applications require multiple signals to be sampled The Cortex-M3 has internal debugging components, tightly simultaneously, such as for power calculations (V and I). PSoC integrated with the CPU, providing the following features: Creator offers a sample and hold component to support this JTAG or SWD access function. Flash Patch and Breakpoint (FPB) block for implementing Figure 8-14. Sample and Hold Topology breakpoints and code patches (1 and 2 are opposite phases of a clock)   Data Watchpoint and Trigger (DWT) block for implementing Vi 1 C1 C2 1 Vref watchpoints, trigger resources, and system profiling n Embedded Trace Macrocell (ETM) for instruction trace 2 1 2 Vout Instrumentation Trace Macrocell (ITM) for support of printf-style 2 debugging PSoC devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. 1 Four interfaces are available: JTAG, SWD, SWV, and TRACEPORT. JTAG and SWD support all programming and 1 2 1 dsceabnu gc hfeaaintusr efosr obfo thaerd d leevviecel t.e JsTtA aGn da lcshoa sinuipnpgo mrtsu slttiapnled JaTrdA JGT AG V ref devices to a single JTAG connection. The SWV and V TRACEPORT provide trace output from the DWT, ETM, and 2 C3 C4 2 ref ITM. TRACEPORT is faster but uses more pins. SWV is slower but uses only one pin. 8.12.1 Down Mixer For more information on PSoC 5 programming, refer to the The S+H can be used as a mixer to down convert an input signal. application note PSoC 5 Device Programming Specifications. This circuit is a high bandwidth passive sample network that can Cortex-M3 debug and trace functionality enables full device sample input signals up to 14 MHz. This sampled value is then debugging in the final system using the standard production held using the opamp with a maximum clock rate of 4 MHz. The device. It does not require special interfaces, debugging pods, output frequency is at the difference between the input frequency simulators, or emulators. Only the standard programming and the highest integer multiple of the Local Oscillator that is less connections are required to fully support debug. than the input. The PSoC Creator IDE software provides fully integrated 8.12.2 First Order Modulator - SC Mode programming and debug support for PSoC devices. The low cost MiniProg3 programmer and debugger is designed to provide full A first order modulator is constructed by placing the switched programming and debug support of PSoC devices in conjunction capacitor block in an integrator mode and using a comparator to with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV provide a 1-bit feedback to the input. Depending on this bit, a interfaces are fully compatible with industry standard third party reference voltage is either subtracted or added to the input tools. signal. The block output is the output of the comparator and not the integrator in the modulator case. The signal is downshifted All Cortex-M3 debug and trace modules are disabled by default and buffered and then processed by a decimator to make a and can only be enabled in firmware. If not enabled, the only way delta-sigma converter or a counter to make an incremental to reenable them is to erase the entire device, clear flash converter. The accuracy of the sampled data from the first-order protection, and reprogram the device with new firmware that modulator is determined from several factors. enables them. Disabling debug and trace features, robust flash protection, and hiding custom analog and digital functionality The main application for this modulator is for a low frequency inside the PSoC device provide a level of security not possible ADC with high accuracy. Applications include strain gauges, with multichip application solutions. Additionally, all device thermocouples, precision voltage, and current measurement interfaces can be permanently disabled (Device Security) for applications concerned about phishing attacks due to a maliciously reprogrammed device. Permanently disabling interfaces is not recommended in most applications because the designer then cannot access the device later. Because all programming, debug, and test interfaces are disabled when Device Security is enabled, PSoCs with Device Security enabled may not be returned for failure analysis. Document Number: 001-84935 Rev. *L Page 61 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 9.1 JTAG Interface transfers, whichever is least. By default, the JTAG pins are enabled on new devices but the JTAG interface can be disabled, The IEEE 1149.1 compliant JTAG interface exists on four or five allowing these pins to be used as General Purpose I/O (GPIO) pins (the nTRST pin is optional). The JTAG clock frequency can instead. The JTAG interface is used for programming the flash be up to 12 MHz, or 1/3 of the CPU clock frequency for 8 and memory, debugging, I/O scan chains, and JTAG device chaining. 16-bit transfers, or 1/5 of the CPU clock frequency for 32-bit Figure 9-1. JTAG Interface Connections between PSoC 5LP and Programmer V DD Host Programmer PSoC 5 VDD V , V , V , V , V , V 1, 2, 3, 4 DDD DDA DDIO0 DDIO1 DDIO2 DDIO3 TCK TCK (P1[1] TMS  5 TMS (P1[0])  5 TDO TDI (P1[4]) TDI TDO (P1[3]) nTRST 6 nTRST (P1[5]) 6 XRES XRES 4 GND V , V SSD SSA GND 1 The voltage levels of Host Programmer and the PSoC 5 voltage domains involved in Programming should be same. The Port 1 JTAG pins and XRES pin are powered by V . So, V of PSoC 5 should be at same DDIO1 DDIO1 voltage level as host V . Rest of PSoC 5 voltage domains (V , V , V , V , V ) need not be at the same DD DDD DDA DDIO0 DDIO2 DDIO3 voltage level as host Programmer. 2 Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 5. 3 For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 5. This may typically require external interface circuitry to toggle power which will depend on the programming setup. The power supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other supplies. 4 For JTAG Programming, Device reset can also be done without connecting to the XRES pin or Power cycle mode by using the TMS,TCK,TDI, TDO pins of PSoC 5, and writing to a specific register. But this requires that the DPS setting in NVL is not equal to “Debug Ports Disabled”. 5 By default, PSoC 5 is configured for 4-wire JTAG mode unless user changes the DPS setting. So the TMS pin is unidirectional. But if the DPS setting is changed to non-JTAG mode, the TMS pin in JTAG is bi-directional as the SWD Protocol has to be used for acquiring the PSoC 5 device initially. After switching from SWD to JTAG mode, the TMS pin will be uni-directional. In such a case, unidirectional buffer should not be used on TMS line. 6 nTRST JTAG pin (P1[5]) cannot be used to reset the JTAG TAP controlller during first time programming of PSoC 5 as the default setting is 4-wire JTAG (nTRST disabled). Use the TMS, TCK pins to do a reset of JTAG TAP controller. Document Number: 001-84935 Rev. *L Page 62 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 9.2 SWD Interface (JTAG or USB) receives a predetermined acquire sequence of 1s and 0s. If the NVL latches are set for SWD (see Section5.5), The SWD interface is the preferred alternative to the JTAG this sequence need not be applied to the JTAG pin pair. The interface. It requires only two pins instead of the four or five acquire sequence must always be applied to the USB pin pair. needed by JTAG. SWD provides all of the programming and debugging features of JTAG at the same speed. SWD does not SWD is used for debugging or for programming the flash provide access to scan chains or device chaining. The SWD memory. clock frequency can be up to 1/3 of the CPU clock frequency. The SWD interface can be enabled from the JTAG interface or SWD uses two pins, either two of the JTAG pins (TMS and TCK) disabled, allowing its pins to be used as GPIO. Unlike JTAG, the or the USBIO D+ and D- pins. The USBIO pins are useful for in SWD interface can always be reacquired on any device during system programming of USB solutions that would otherwise the key window. It can then be used to reenable the JTAG require a separate programming connector. One pin is used for interface, if desired. When using SWD or JTAG pins as standard the data clock and the other is used for data input and output. GPIO, make sure that the GPIO functionality and PCB circuits do not interfere with SWD or JTAG use. SWD can be enabled on only one of the pin pairs at a time. This only happens if, within 8 μs (key window) after reset, that pin pair Figure 9-2. SWD Interface Connections between PSoC 5LP and Programmer V DD Host Programmer PSoC 5 VDD VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3 1, 2, 3 SWDCK SWDCK (P1[1] or P15[7]) SWDIO SWDIO (P1[0] or P15[6]) XRES XRES  3 GND V , V SSD SSA GND 1 The voltage levels of the Host Programmer and the PSoC 5 voltage domains involved in programming should be the same. The XRES pin is powered by V . The USB SWD DDIO1 pins are powered by V . So for Programming using the USB SWD pins with XRES pin, the V , V DDD DDD DDIO1  of PSoC 5 should be at the same voltage level as Host V . Rest of PSoC 5 voltage domains DD (V , V , V , V ) need not be at the same voltage level as host Programmer. The Port 1 SWD DDA DDIO0 DDIO2 DDIO3 pins are powered by V . So V of PSoC 5 should be at same voltage level as host V for DDIO1 DDIO1 DD Port 1 SWD programming. Rest of PSoC 5 voltage domains (V ,  V , V , V , V ) need not DDD DDA DDIO0 DDIO2 DDIO3 be at the same voltage level as host Programmer. 2 Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 5. 3 For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 5. This may typically require external interface circuitry to toggle power which will depend on the programming setup. The power supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other supplies. Document Number: 001-84935 Rev. *L Page 63 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 9.3 Debug Features Table 9-1. Debug Configurations The CY8C56LP supports the following debug features: Debug and Trace Configuration GPIO Pins Used Halt and single-step the CPU All debug and trace disabled 0 View and change CPU and peripheral registers, and RAM JTAG 4 or 5 addresses SWD 2 Six program address breakpoints and two literal access SWV 1 breakpoints TRACEPORT 5 Data watchpoint events to CPU JTAG + TRACEPORT 9 or 10 Patch and remap instruction from flash to SRAM SWD + SWV 3 Debugging at the full speed of the CPU SWD + TRACEPORT 7 Compatible with PSoC Creator and MiniProg3 programmer and 9.6 Programming Features debugger The JTAG and SWD interfaces provide full programming Standard JTAG programming and debugging interfaces make support. The entire device can be erased, programmed, and CY8C56LP compatible with other popular third-party tools (for verified. Designers can increase flash protection levels to protect example, ARM / Keil) firmware IP. Flash protection can only be reset after a full device erase. Individual flash blocks can be erased, programmed, and 9.4 Trace Features verified, if block security settings permit. The following trace features are supported: 9.7 Device Security Instruction trace PSoC 5LP offers an advanced security feature called device Data watchpoint on access to data address, address range, or security, which permanently disables all test, programming, and data value debug ports, protecting your application from external access. The device security is activated by programming a 32-bit key Trace trigger on data watchpoint (0x50536F43) to a Write Once Latch (WOL). Debug exception trigger The Write Once Latch is a type of nonvolatile latch (NVL). The cell itself is an NVL with additional logic wrapped around it. Each Code profiling WOL device contains four bytes (32 bits) of data. The wrapper Counters for measuring clock cycles, folded instructions, outputs a ‘1’ if a super-majority (28 of 32) of its bits match a load/store operations, sleep cycles, cycles per instruction, pre-determined pattern (0x50536F43); it outputs a ‘0’ if this interrupt overhead majority is not reached. When the output is 1, the Write Once NV latch locks the part out of Debug and Test modes; it also Interrupt events trace permanently gates off the ability to erase or alter the contents of the latch. Matching all bits is intentionally not required, so that Software event monitoring, “printf-style” debugging single (or few) bit failures do not deassert the WOL output. The 9.5 SWV and TRACEPORT Interfaces state of the NVL bits after wafer processing is truly random with no tendency toward 1 or 0. The SWV and TRACEPORT interfaces provide trace data to a The WOL only locks the part after the correct 32-bit key debug host via the Cypress MiniProg3 or an external trace port (0x50536F43) is loaded into the NVL's volatile memory, analyzer. The 5 pin TRACEPORT is used for rapid transmission programmed into the NVL's nonvolatile cells, and the part is of large trace streams. The single pin SWV mode is used to reset. The output of the WOL is only sampled on reset and used minimize the number of trace pins. SWV is shared with a JTAG to disable the access. This precaution prevents anyone from pin. If debugging and tracing are done at the same time then reading, erasing, or altering the contents of the internal memory. SWD may be used with either SWV or TRACEPORT, or JTAG may be used with TRACEPORT, as shown in Table9-1. The user can write the key into the WOL to lock out external access only if no flash protection is set (see “Flash Security” section on page19). However, after setting the values in the WOL, a user still has access to the part until it is reset. Therefore, a user can write the key into the WOL, program the flash protection data, and then reset the part to lock it. Document Number: 001-84935 Rev. *L Page 64 of 131

® PSoC 5LP: CY8C56LP Family Datasheet If the device is protected with a WOL setting, Cypress cannot 10. Development Support perform failure analysis and, therefore, cannot accept RMAs from customers. The WOL can be read out via Serial Wire Debug The CY8C56LP family has a rich set of documentation, (SWD) port to electrically identify protected parts. The user can development tools, and online resources to assist you during write the key in WOL to lock out external access only if no flash your development process. Visit protection is set. For more information on how to take full psoc.cypress.com/getting-started to find out more. advantage of the security features in PSoC see the PSoC 5 TRM. 10.1 Documentation Disclaimer A suite of documentation, to ensure that you can find answers to your questions quickly, supports the CY8C56LP family. This Note the following details of the flash code protection features on section contains a list of some of the key documents. Cypress devices. Software User Guide: A step-by-step guide for using PSoC Cypress products meet the specifications contained in their Creator. The software user guide shows you how the PSoC particular Cypress datasheets. Cypress believes that its family of Creator build process works in detail, how to use source control products is one of the most secure families of its kind on the with PSoC Creator, and much more. market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code Component Datasheets: The flexibility of PSoC allows the protection features. Any of these methods, to our knowledge, creation of new peripherals (components) long after the device would be dishonest and possibly illegal. Neither Cypress nor any has gone into production. Component datasheets provide all of other semiconductor manufacturer can guarantee the security of the information needed to select and use a particular component, their code. Code protection does not mean that we are including a functional description, API documentation, example guaranteeing the product as “unbreakable.” code, and AC/DC specifications. Cypress is willing to work with the customer who is concerned Application Notes: PSoC application notes discuss a particular about the integrity of their code. Code protection is constantly application of PSoC in depth; examples include brushless DC evolving. We at Cypress are committed to continuously motor control and on-chip filtering. Application notes often improving the code protection features of our products. include example projects in addition to the application note document. 9.8 CSP Package Bootloader Technical Reference Manual: PSoC Creator makes designing A factory-installed bootloader program is included in all devices with PSoC as easy as dragging a peripheral onto a schematic, with CSP packages. The bootloader is compatible with PSoC but, when low level details of the PSoC device are required, use Creator 3.0 bootloadable project files, and has the following the technical reference manual (TRM) as your guide. features: Note Visit www.arm.com for detailed documentation about the I2C-based Cortex-M3 CPU. SCLK and SDAT available at P1[6] and P1[7], respectively 10.2 Online External pull-up resistors required In addition to print documentation, the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from I2C slave, address 4, data rate = 100 kbps around the world, 24 hours a day, 7 days a week. Single application 10.3 Tools Wait 2 seconds for bootload command With industry standard cores, programming, and debugging Other bootloader options are as set by the PSoC Creator 3.0 interfaces, the CY8C56LP family is part of a development tool Bootloader Component default ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use PSoC Creator Occupies the bottom 9 Kbytes of flash IDE, supported third party compilers, programmers, debuggers, For more information on this bootloader, see the following and development kits. Cypress application notes: AN73854, PSoC 3 and PSoC 5 LP Introduction to Bootloaders AN60317, PSoC 3 and PSoC 5 LP I2C Bootloader Note that a PSoC Creator bootloadable project must be associated with .hex and .elf files for a bootloader project that is configured for the target device. Bootloader .hex and .elf files can be found at www.cypress.com/go/PSoC5LPdatasheet. The factory-installed bootloader can be overwritten using JTAG or SWD programming. Document Number: 001-84935 Rev. *L Page 65 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11. Electrical Specifications Specifications are valid for –40 °C  T  105 °C and T  120 °C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, see the component datasheets for full AC/DC specifications of individual functions. See the “Example Peripherals” section on page39 for further explanation of PSoC Creator components. 11.1 Absolute Maximum Ratings Table 11-1. Absolute Maximum Ratings DC Specifications[14] Parameter Description Conditions Min Typ Max Units V Analog supply voltage relative to –0.5 – 6 V DDA V SSA V Digital supply voltage relative to –0.5 – 6 V DDD V SSD V I/O supply voltage relative to V –0.5 – 6 V DDIO SSD V Direct analog core voltage input –0.5 – 1.95 V CCA V Direct digital core voltage input –0.5 – 1.95 V CCD V Analog ground voltage V – 0.5 – V + 0.5 V SSA SSD SSD V [15] DC input voltage on GPIO Includes signals sourced by V V – 0.5 – V + 0.5 V GPIO DDA SSD DDIO and routed internal to the pin. V DC input voltage on SIO Output disabled V – 0.5 – 7 V SIO SSD Output enabled V – 0.5 – 6 V SSD V Voltage at boost converter input 0.5 – 5.5 V IND V Boost converter supply V – 0.5 – 5.5 V BAT SSD I Current per V supply pin – – 100 mA VDDIO DDIO I GPIO current –30 – 41 mA GPIO I SIO current –49 – 28 mA SIO I USBIO current –56 – 59 mA USBIO LU Latch up current[16] –140 – 140 mA ESD Electrostatic discharge voltage Human Body Model 2000 – – V HBM ESD Electrostatic discharge voltage Charge Device Model 500 – – V CDM Notes 14.Usage above the absolute maximum conditions listed in Table11-1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification. 15.The VDDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin VDDIO  VDDA. 16.Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test. Document Number: 001-84935 Rev. *L Page 66 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.2 Device Level Specifications Specifications are valid for –40 °C  T  105 °C and T  120 °C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. Unless otherwise specified, all charts and graphs show typical values. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter Description Conditions Min Typ Max Units V Analog supply voltage and input to analog core regulator Analog core regulator enabled 1.8 – 5.5 V DDA V Analog supply voltage, analog regulator bypassed Analog core regulator disabled 1.71 1.8 1.89 V DDA 1.8 – V [17] V Digital supply voltage relative to V Digital core regulator enabled DDA V DDD SSD – – V + 0.1[19] DDA V Digital supply voltage, digital regulator bypassed Digital core regulator disabled 1.71 1.8 1.89 V DDD 1.71 – V [17] V [18] I/O supply voltage relative to V DDA V DDIO SSIO – – V + 0.1[19] DDA V Direct analog core voltage input (Analog regulator bypass)Analog core regulator disabled 1.71 1.8 1.89 V CCA V Direct digital core voltage input (Digital regulator bypass) Digital core regulator disabled 1.71 1.8 1.89 V CCD I [20] Active Mode DD Sinucmlu doef dd.i gital and analog IDDD + IDDA. IDDIOX for I/Os not VFDDX == 23.7M VH tzo[2 51.]5 V; T = –40 °C – 1.9 3.8 mA CPU T = 25 °C – 1.9 3.8 IMO enabled, bus clock and CPU clock enabled. CPU executing complex program from flash. T = 85 °C – 2 3.8 T = 105 °C – 2 3.8 V = 2.7 V to 5.5 V; T = –40 °C – 3.1 5 DDX F = 6MHz CPU T = 25 °C – 3.1 5 T = 85 °C – 3.2 5 T = 105 °C – 3.2 5 V = 2.7 V to 5.5 V; T = –40 °C – 5.4 7 FDDX = 12MHz[21] CPU T = 25 °C – 5.4 7 T = 85 °C – 5.6 7 T = 105 °C – 5.6 7 V = 2.7 V to 5.5 V; T = –40 °C – 8.9 10.5 FDDX = 24MHz[21] CPU T = 25 °C – 8.9 10.5 T = 85 °C – 9.1 10.5 T = 105 °C – 9.1 10.5 V = 2.7 V to 5.5 V; T = –40 °C – 15.5 17 FDDX = 48MHz[21] CPU T = 25 °C – 15.4 17 T = 85 °C – 15.7 17 T = 105 °C – 15.7 17.25 V = 2.7 V to 5.5 V; T = –40 °C – 18 19.5 DDX F = 62MHz CPU T = 25 °C – 18 19.5 T = 85 °C – 18.5 19.5 T = 105 °C – 19 21 V = 2.7 V to 5.5 V; T = –40 °C – 26.5 30 DDX F = 74MHz CPU T = 25 °C – 26.5 30 T = 85 °C – 27 30 T = 105 °C – 27 30 V = 2.7 V to 5.5 V; T = –40 °C – 22 25.5 DDX F = 80MHz, IMO CPU T = 25 °C – 22 25.5 = 3 MHz with PLL T = 85 °C – 22.5 25.5 T = 105 °C – 22.5 25.5 Notes 17.The power supplies can be brought up in any sequence however once stable VDDA must be greater than or equal to all other supplies. 18.The VDDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin VDDIO  VDDA. 19.Guaranteed by design, not production tested. 20.The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular system from the device datasheet and component datasheets. 21.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 67 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 11-2. DC Specifications (continued) Parameter Description Conditions Min Typ Max Units I [22] Sleep Mode[23] DD V = V = T = –40°C – 1.9 3.1 µA DD DDIO 4.5–5.5V T = 25°C – 2.4 3.6 T = 85°C – 5 16 CPU = OFF T = 105 °C – 5 16 RTC = ON (= ECO32K ON, in low-power mode) Sleep timer = ON (= ILO ON at 1kHz)[24] VDD = VDDIO = T = –40°C – 1.7 3.1 WDT = OFF 2.7–3.6V T = 25°C – 2 3.6 I2C Wake = OFF Comparator = OFF T = 85°C – 4.2 16 POR = ON T = 105 °C – 4.2 16 Boost = OFF V = V = T = –40°C – 1.6 3.1 SIO pins in single ended input, unregulated output mode DD DDIO 1.71–1.95V T = 25°C – 1.9 3.6 T = 85°C – 4.2 16 T = 105 °C – 4.2 16 Comparator = ON V = V = T = 25°C – 3 4.2 µA CPU = OFF 2.D7D–3.6VDD[2I5O] RTC = OFF Sleep timer = OFF WDT = OFF I2C Wake = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode I2C Wake = ON V = V = T = 25°C – 1.7 3.6 µA CPU = OFF 2.D7D–3.6VDD[2I5O] RTC = OFF Sleep timer = OFF WDT = OFF Comparator = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode Notes 22.The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular system from the device datasheet and component datasheets. 23.If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV. 24.Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off. 25.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 68 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 11-2. DC Specifications (continued) Parameter Description Conditions Min Typ Max Units I [26] Hibernate Mode DD V = V = T = –40°C – 0.2 2 µA DD DDIO 4.5–5.5V T = 25°C – 0.24 2 T = 85°C – 2.6 15 T = 105 °C – 2.6 15 Hibernate mode current V = V = T = –40°C – 0.11 2 All regulators and oscillators off. 2.D7D–3.6VDDIO SRAM retention T = 25°C – 0.3 2 GPIO interrupts are active T = 85°C – 2 15 Boost = OFF SIO pins in single ended input, unregulated output mode T = 105 °C – 2 15 V = V = T = –40°C – 0.9 2 DD DDIO 1.71–1.95V T = 25°C – 0.11 2 T = 85°C – 1.8 15 T = 105 °C – 1.8 15 I [27] Analog current consumption while device is reset V  3.6V – 0.3 0.6 mA DDAR DDA V  3.6V – 1.4 3.3 mA DDA I [27] Digital current consumption while device is reset V  3.6V – 1.1 3.1 mA DDDR DDD V  3.6V – 0.7 3.1 mA DDD I [25] Current consumption while device programming. Sum of – 15 21 mA DD_PROG digital, analog, and IOs: IDDD + IDDA + IDDIOX. Notes 26.The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular system from the device datasheet and component datasheets. 27.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 69 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 11-1. Active Mode Current vs F , V = 3.3 V, Figure 11-2. I vs Frequency at 25 °C CPU DD DD Temperature = 25 °C 0.7 25 0.6 20 0.5 z H M 0.4 mA 15 A/A nt, Curren 10 I, mDD 00..23 5 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:8)(cid:9)(cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:4)(cid:14)(cid:9)(cid:15)(cid:16) 0.1 0 0 0 20 40 60 80 0 20 40 60 80 Bus Clock, MHz CPU Frequency, MHz Figure 11-3. Active Mode Current vs Temperature and F , Figure 11-4. Active Mode Current vs V and Temperature, CPU DD V = 3.3 V F = 24 MHz DD CPU 10 25 20 8 80 MHz 105 °C mA 15 24 MHz mA 6 25 °C t, Curren 10 66 MMHHz t, Curren 4 -40 °C 5 2 0 0 -40 -20 0 20 40 60 80 100 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Temperature, °C VDD, V Table 11-3. AC Specifications Parameter Description Conditions Min Typ Max Units F CPU frequency 1.71V  V  5.5V DC – 80.01 MHz CPU DDD F Bus frequency 1.71V  V  5.5V DC – 80.01 MHz BUSCLK DDD S [28] V ramp rate – – 0.066 V/µs VDD DD T [28] Time from V /V /V /V IPOR – – 10 µs IO_INIT DDD DDA CCD CCA to I/O ports set to their reset states T [28] Time from V /V /V /V  PRES V /V = regulated from V /V , no – – 33 µs STARTUP DDD DDA CCD CCA CCA DDA DDA DDD to CPU executing code at reset vector PLL used, fast IMO boot mode (48 MHz typ.) V /V = regulated from V /V , no – – 66 µs CCA CCD DDA DDD PLL used, slow IMO boot mode (12 MHz typ.) T [28] Wakeup from sleep mode – – – 25 µs SLEEP Application of non-LVD interrupt to beginning of execution of next CPU instruction T [28] Wakeup form hibernate mode – Application – – 150 µs HIBERNATE of external interrupt to beginning of execution of next CPU instruction Note 28.Based on device characterization (not production tested). Document Number: 001-84935 Rev. *L Page 70 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.3 Power Regulators Specifications are valid for –40 °C  T  105 °C and T  120 °C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description Conditions Min Typ Max Units V Input voltage 1.8 – 5.5 V DDD V Output voltage – 1.80 – V CCD Regulator output capacitor ±10%, X5R ceramic or better. The two V 0.9 1 1.1 µF CCD pins must be shorted together, with as short a trace as possible, see Power System on page 26 Figure 11-5. Analog and Digital Regulators, V vs V , Figure 11-6. Digital Regulator PSRR vs Frequency and V CC DD DD 10 mA Load 100 80 B 60 d R, R R PS 40 Vdd=4.5V Vdd=3.6V 20 Vdd=2.7V 0 0.1 1 10 100 1000 Frequency, kHz 11.3.2 Analog Core Regulator Table 11-5. Analog Core Regulator DC Specifications Parameter Description Conditions Min Typ Max Units V Input voltage 1.8 – 5.5 V DDA V Output voltage – 1.80 – V CCA Regulator output capacitor ±10%, X5R ceramic or better 0.9 1 1.1 µF Figure 11-7. Analog Regulator PSRR vs Frequency and V DD 100 80 B 60 d R, R R PS 40 Vdd=4.5V Vdd=3.6V 20 Vdd=2.7V 0 0.1 1 10 100 1000 Frequency, KHz Document Number: 001-84935 Rev. *L Page 71 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.3.3 Inductive Boost Regulator Unless otherwise specified, operating conditions are: V = 0.5 V–3.6 V, V = 1.8 V–5.0 V, I = 0 mA–50 mA, BAT OUT OUT L = 4.7 µH–22 µH, C = 22 µF || 3 × 1.0 µF || 3 × 0.1 µF, C = 22 µF, I = 1.0 A, excludes 99-pin CSP package. For BOOST BOOST BAT F information on using boost with 99-pin CSP package please contact Cypress support. Unless otherwise specified, all charts and graphs show typical values. Table 11-6. Inductive Boost Regulator DC Specifications Parameter Description Conditions Min Typ Max Units VOUT Boost output voltage[29] vsel = 1.8 V in register BOOST_CR0 1.71 1.8 1.89 V vsel = 1.9 V in register BOOST_CR0 1.81 1.90 2.00 V vsel = 2.0 V in register BOOST_CR0 1.90 2.00 2.10 V vsel = 2.4 V in register BOOST_CR0 2.16 2.40 2.64 V vsel = 2.7 V in register BOOST_CR0 2.43 2.70 2.97 V vsel = 3.0 V in register BOOST_CR0 2.70 3.00 3.30 V vsel = 3.3 V in register BOOST_CR0 2.97 3.30 3.63 V vsel = 3.6 V in register BOOST_CR0 3.24 3.60 3.96 V vsel = 5.0 V in register BOOST_CR0 4.50 5.00 5.50 V VBAT Input voltage to boost[30] IOUT = 0 mA–5 mA vsel = 1.8 V–2.0 V, 0.5 – 0.8 V T = 0 °C–70 °C A I = 0 mA–15 mA vsel = 1.8 V–5.0 V[31], 1.6 – 3.6 V OUT T = –10 °C–85 °C A I = 0 mA–25 mA vsel = 1.8 V–2.7 V, 0.8 – 1.6 V OUT T = –10 °C–85 °C A I = 0 mA–50 mA vsel = 1.8 V–3.3 V[31], 1.8 – 2.5 V OUT T = –40 °C–85 °C A vsel = 1.8 V–3.3 V[31], 1.3 – 2.5 V T = –10 °C–85 °C A vsel = 2.5 V–5.0 V[31], 2.5 – 3.6 V T = –10 °C–85 °C A I Output current T = 0 °C–70 °C V = 0.5 V–0.8 V 0 – 5 mA OUT A BAT T = –10 °C–85 °C V = 1.6 V–3.6 V 0 – 15 mA A BAT V = 0.8 V–1.6 V 0 – 25 mA BAT V = 1.3 V–2.5 V 0 – 50 mA BAT V = 2.5 V–3.6 V 0 – 50 mA BAT T = –40 °C–85 °C V = 1.8 V–2.5 V 0 – 50 mA A BAT I Inductor peak current – – 700 mA LPK I Quiescent current Boost active mode – 250 – µA Q Boost sleep mode, I < 1 µA – 25 – µA OUT Reg Load regulation – – 10 % LOAD Reg Line regulation – – 10 % LINE Notes 29.Listed vsel options are characterized. Additional vsel options are valid and guaranteed by design. 30.The boost will start at all valid VBAT conditions including down to VBAT = 0.5 V. 31.If VBAT is greater than or equal to VOUT boost setting, then VOUT will be less than VBAT due to resistive losses in the boost circuit. Document Number: 001-84935 Rev. *L Page 72 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 11-7. Recommended External Components for Boost Circuit Parameter Description Conditions Min Typ Max Units L Boost inductor 4.7 µH nominal 3.7 4.7 5.7 µH BOOST 10 µH nominal 8.0 10.0 12.0 µH 22 µH nominal 17.0 22.0 27.0 µH C Total capacitance sum of 17.0 26.0 31.0 µF BOOST V , V , V [32] DDD DDA DDIO C Battery filter capacitor 17.0 22.0 27.0 µF BAT I Schottky diode average 1.0 – – A F forward current V Schottky reverse voltage 20.0 – – V R Figure 11-8. T range over V and V Figure 11-9. I range over V and V A BAT OUT OUT BAT OUT (cid:8)(cid:3)(cid:23) (cid:8)(cid:3)(cid:23) (cid:14)(cid:6)(cid:2)(cid:11)(cid:10)(cid:5)(cid:4)(cid:11)(cid:15)(cid:13) (cid:2)(cid:14)(cid:9)(cid:4)(cid:11)(cid:30)(cid:25) (cid:14)(cid:9)(cid:2)(cid:11)(cid:10)(cid:5)(cid:4)(cid:11)(cid:12)(cid:13) (cid:6)(cid:3)(cid:4) (cid:6)(cid:3)(cid:4) (cid:2)(cid:14)(cid:4)(cid:2)(cid:11)(cid:30)(cid:25) (cid:24)(cid:27)(cid:11)(cid:24)(cid:20)(cid:25)(cid:26) (cid:9)(cid:9)(cid:3)(cid:3)(cid:23)(cid:5) (cid:14)(cid:16)(cid:2)(cid:14)(cid:16)(cid:11)(cid:10)(cid:2)(cid:11)(cid:5)(cid:10)(cid:4)(cid:5)(cid:11)(cid:12)(cid:4)(cid:13)(cid:11)(cid:17)(cid:13) (cid:24)(cid:27)(cid:11)(cid:24)(cid:20)(cid:25)(cid:26) (cid:9)(cid:3)(cid:23) (cid:2)(cid:14)(cid:9)(cid:4)(cid:11)(cid:30)(cid:25) (cid:9)(cid:3)(cid:8) (cid:9)(cid:3)(cid:8) (cid:2)(cid:14)(cid:6)(cid:4)(cid:11)(cid:30)(cid:25) (cid:2)(cid:3)(cid:5) (cid:18)(cid:19)(cid:11)(cid:20)(cid:19)(cid:19)(cid:21)(cid:22) (cid:2)(cid:3)(cid:5) (cid:18)(cid:19)(cid:11)(cid:20)(cid:19)(cid:19)(cid:21)(cid:22) (cid:2)(cid:3)(cid:4) (cid:2)(cid:10)(cid:7)(cid:2)(cid:11)(cid:12)(cid:13) (cid:2)(cid:3)(cid:4) (cid:2)(cid:14)(cid:4)(cid:11)(cid:30)(cid:25) (cid:2) (cid:2) (cid:9)(cid:3)(cid:2) (cid:9)(cid:3)(cid:5) (cid:6)(cid:3)(cid:2) (cid:6)(cid:3)(cid:7) (cid:8)(cid:3)(cid:8) (cid:4)(cid:3)(cid:2) (cid:9)(cid:3)(cid:2) (cid:9)(cid:3)(cid:5) (cid:6)(cid:3)(cid:2) (cid:6)(cid:3)(cid:4)(cid:6)(cid:3)(cid:7) (cid:8)(cid:3)(cid:8) (cid:4)(cid:3)(cid:2) (cid:24)(cid:28)(cid:29)(cid:26)(cid:27)(cid:11)(cid:24) (cid:24)(cid:28)(cid:29)(cid:26)(cid:27)(cid:11)(cid:24) Figure 11-10. L values over V and V BOOST BAT OUT (cid:8)(cid:3)(cid:23) (cid:16)(cid:3)(cid:7)(cid:11)(cid:31) ! "#(cid:11)(cid:6)(cid:4)(cid:11)(cid:30)(cid:25)$(cid:11)(cid:16)(cid:3)(cid:7)(cid:11)(cid:31) (cid:27)(cid:11)(cid:9)(cid:2)(cid:11)(cid:31) (cid:11) (cid:28)(cid:29)(cid:26) (cid:9)(cid:2)(cid:11)(cid:31) ! "#(cid:11)(cid:4)(cid:2)(cid:11)(cid:30)(cid:25)$(cid:11)(cid:16)(cid:3)(cid:7)(cid:11)(cid:31) (cid:11) (cid:28)(cid:29)(cid:26) (cid:6)(cid:3)(cid:4) (cid:24) (cid:16)(cid:3)(cid:7)(cid:11)(cid:31) (cid:16)(cid:3)(cid:7)(cid:11)(cid:31) (cid:24)(cid:27)(cid:11)(cid:20)(cid:25)(cid:26) (cid:9)(cid:3)(cid:23) (cid:9)(cid:6)(cid:2)(cid:6)(cid:11)(cid:11)(cid:31)(cid:31) (cid:9)(cid:2)(cid:11)(cid:31) (cid:9)(cid:3)(cid:8) (cid:16)(cid:3)(cid:7)(cid:11)(cid:31) (cid:9)(cid:2)(cid:11)(cid:31) (cid:2)(cid:3)(cid:5) (cid:18)(cid:19)(cid:11)(cid:20)(cid:19)(cid:19)(cid:21)(cid:22) (cid:2)(cid:3)(cid:4) (cid:9)(cid:2)(cid:11)(cid:31) (cid:2) (cid:9)(cid:3)(cid:2) (cid:9)(cid:3)(cid:5) (cid:6)(cid:3)(cid:2) (cid:6)(cid:3)(cid:4) (cid:6)(cid:3)(cid:7) (cid:8)(cid:3)(cid:8) (cid:4)(cid:3)(cid:2) (cid:24) (cid:27)(cid:11)(cid:24) (cid:28)(cid:29)(cid:26) Note 32.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 73 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 11-11. Efficiency vs V , L = 4.7 µH [33] Figure 11-12. Efficiency vs V , L = 10 µH [33] BAT BOOST BAT BOOST 100% 100% 95% Vout = 1.8 V 95% 90% Vout = 2.4 V 90% 85% Vout = 3.3 V 85% % Efficiency 778050%%% Vout = 5.0 V % Efficiency 778050%%% VVoouutt == 12..84 VV 6655%% 6655%% VVoouutt == 33.33 VV 60% 60% Vout = 5.0 V 55% 55% 50% 50% 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 VBAT, V VBAT, V Figure 11-13. Efficiency vs V , L = 22 µH [33] Figure 11-14. V vs V [33] BAT BOOST RIPPLE BAT 100% 300 95% 250 90% 85% 200 % Efficiency 778050%%% VVoouutt == 12..84 VV V, mVRIPPLE110500 LLbboooosstt == 41.07 uuHH 6655%% Vout = 3.3 V Lboost = 22 uH 60% 50 55% 0 50% 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 VBAT, V VBAT, V Note 33.Typical example. Actual values may vary depending on external component selection, PCB layout, and other design parameters. Document Number: 001-84935 Rev. *L Page 74 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.4 Inputs and Outputs Specifications are valid for –40 °C  T  105 °C and T  120 °C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. Unless otherwise specified, all charts and graphs show typical values. When the power supplies ramp up, there are low-impedance connections between each GPIO pin and its V supply. This causes DDIO the pin voltages to track V until both V and V reach the IPOR voltage, which can be as high as 1.45 V. At that point the DDIO DDIO DDA low-impedance connections no longer exist, and the pins change to their normal NVL settings. Also, if V is less than V , a low-impedance path may exist between a GPIO and V , causing the GPIO to track V until DDA DDIO DDA DDA V becomes greater than or equal to V . DDA DDIO 11.4.1 GPIO Table 11-8. GPIO DC Specifications Parameter Description Conditions Min Typ Max Units V Input voltage high threshold CMOS Input, PRT[x]CTL = 0 0.7  V – – V IH DDIO V Input voltage low threshold CMOS Input, PRT[x]CTL = 0 – – 0.3 V V IL DDIO V Input voltage high threshold LVTTL Input, PRT[x]CTL = 1,V < 2.7V 0.7 x V – – V IH DDIO DDIO V Input voltage high threshold LVTTL Input, PRT[x]CTL = 1, V  2.7V 2.0 – – V IH DDIO V Input voltage low threshold LVTTL Input, PRT[x]CTL = 1,V < 2.7V – – 0.3 × V V IL DDIO DDIO V Input voltage low threshold LVTTL Input, PRT[x]CTL = 1, V  2.7V – – 0.8 V IL DDIO V Output voltage high I = 4 mA at 3.3 V V – 0.6 – – V OH OH DDIO DDIO I = 1 mA at 1.8 V V – 0.5 – – V OH DDIO DDIO V Output voltage low I = 8 mA at 3.3 V – – 0.6 V OL OL DDIO I = 3 mA at 3.3 V – – 0.4 V OL DDIO I = 4 mA at 1.8 V – – 0.6 V OL DDIO Rpullup Pull up resistor 3.5 5.6 8.5 k Rpulldown Pull down resistor 3.5 5.6 8.5 k I Input leakage current 25°C, V = 3.0 V – – 2 nA IL DDIO (absolute value)[34] C Input capacitance[34] P0.0, P0.1, P0.2, P3.6, P3.7 – 17 20 pF IN P0.3, P0.4, P3.0, P3.1, P3.2 – 10 15 pF P0.6, P0.7, P15.0, P15.6, P15.7[35] – 7 12 pF All other GPIOs – 5 9 pF V Input voltage hysteresis – 40 – mV H (Schmitt–Trigger)[34] Idiode Current through protection – – 100 µA diode to V and V DDIO SSIO Rglobal Resistance pin to analog 25°C, V = 3.0 V – 320 –  DDIO global bus Rmux Resistance pin to analog mux 25°C, V = 3.0 V – 220 –  DDIO bus Notes 34.Based on device characterization (Not production tested). 35.For information on designing with PSoC oscillators, refer to the application note, AN54439 - PSoC® 3 and PSoC 5 External Oscillator. Document Number: 001-84935 Rev. *L Page 75 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 11-15. GPIO Output High Voltage and Current Figure 11-16. GPIO Output Low Voltage and Current Table 11-9. GPIO AC Specifications[36] Parameter Description Conditions Min Typ Max Units TriseF Rise time in Fast Strong Mode 3.3V V Cload = 25 pF – – 6 ns DDIO TfallF Fall time in Fast Strong Mode 3.3V V Cload = 25 pF – – 6 ns DDIO TriseS Rise time in Slow Strong Mode 3.3V V Cload = 25 pF – – 60 ns DDIO TfallS Fall time in Slow Strong Mode 3.3V V Cload = 25 pF – – 60 ns DDIO GPIO output operating frequency 2.7V < V < 5.5V, fast strong drive mode 90/10% V into 25 pF – – 33 MHz DDIO DDIO Fgpioout 1.71V < V < 2.7V, fast strong drive mode 90/10% V into 25 pF – – 20 MHz DDIO DDIO 3.3V < V < 5.5V, slow strong drive mode 90/10% V into 25 pF – – 7 MHz DDIO DDIO 1.71V < V < 3.3V, slow strong drive mode 90/10% V into 25 pF – – 3.5 MHz DDIO DDIO Fgpioin GPIO input operating frequency 90/10% V – – 33 MHz DDIO Note 36.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 76 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.4.2 SIO Table 11-10. SIO DC Specifications Parameter Description Conditions Min Typ Max Units Vinmax Maximum input voltage All allowed values of V and – – 5.5 V DDIO V , see Section11.1 DDD Vinref Input voltage reference (Differential 0.5 – 0.52 V V DDIO input mode) Output voltage reference (Regulated output mode) Voutref V > 3.7 1 – V –1 V DDIO DDIO V < 3.7 1 – V – 0.5 V DDIO DDIO Input voltage high threshold V GPIO mode CMOS input 0.7  V – – V IH DDIO Differential input mode[37] Hysteresis disabled SIO_ref + 0.2 – – V Input voltage low threshold V GPIO mode CMOS input – – 0.3 V V IL DDIO Differential input mode[37] Hysteresis disabled – – SIO_ref – 0.2 V Output voltage high Unregulated mode I = 4 mA, V = 3.3V V – 0.4 – – V OH DDIO DDIO V Regulated mode[37] I = 1 mA SIO_ref – 0.65 – SIO_ref + 0.2 V OH OH I = 0.1 mA SIO_ref – 0.3 – SIO_ref + 0.2 V OH no load, I = 0 SIO_ref – 0.1 – SIO_ref + 0.1 V OH V Output voltage low V = 3.30 V, I = 25 mA – – 0.8 V OL DDIO OL V = 3.30 V, I = 20 mA – – 0.4 V DDIO OL V = 1.80 V, I = 4 mA – – 0.4 V DDIO OL Rpullup Pull up resistor 3.5 5.6 8.5 k Rpulldown Pull down resistor 3.5 5.6 8.5 k I Input leakage current (absolute IL value)[38] V < V 25°C, V = 3.0 V, V = 3.0 V – – 14 nA IH DDSIO DDSIO IH V > V 25°C, V = 0 V, V = 3.0 V – – 10 µA IH DDSIO DDSIO IH C Input capacitance[38] – – 9 pF IN Input voltage hysteresis Single ended mode (GPIO mode) – 115 – mV VH (Schmitt–Trigger)[38] Differential mode – 50 – mV Current through protection diode to – – 100 µA Idiode V SSIO Notes 37.See Figure 6-10 on page 34 and Figure 6-13 on page 37 for more information on SIO reference. 38.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 77 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 11-17. SIO Output High Voltage and Current, Figure 11-18. SIO Output Low Voltage and Current, Unregulated Mode Unregulated Mode Figure 11-19. SIO Output High Voltage and Current, Regulat- ed Mode Document Number: 001-84935 Rev. *L Page 78 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 11-11. SIO AC Specifications[39] Parameter Description Conditions Min Typ Max Units TriseF Rise time in Fast Strong Mode Cload = 25 pF, V = 3.3V – – 12 ns DDIO (90/10%) TfallF Fall time in Fast Strong Mode Cload = 25 pF, V = 3.3V – – 12 ns DDIO (90/10%) TriseS Rise time in Slow Strong Mode Cload = 25 pF, V = 3.0 V – – 75 ns DDIO (90/10%) TfallS Fall time in Slow Strong Mode Cload = 25 pF, V = 3.0 V – – 60 ns DDIO (90/10%) SIO output operating frequency 2.7V < V < 5.5V, Unregulated 90/10% V into 25 pF – – 33 MHz DDIO DDIO output (GPIO) mode, fast strong drive mode 1.71V < V < 2.7V, Unregu- 90/10% V into 25 pF – – 16 MHz DDIO DDIO lated output (GPIO) mode, fast strong drive mode 3.3V < V < 5.5V, Unregulated 90/10% V into 25 pF – – 5 MHz DDIO DDIO output (GPIO) mode, slow strong drive mode Fsioout 1.71V < V < 3.3V, Unregu- 90/10% V into 25 pF – – 4 MHz DDIO DDIO lated output (GPIO) mode, slow strong drive mode 2.7V < V < 5.5V, Regulated Output continuously switching into – – 20 MHz DDIO output mode, fast strong drive mode 25 pF 1.71V < V < 2.7V, Regulated Output continuously switching into – – 10 MHz DDIO output mode, fast strong drive mode 25 pF 1.71V < V < 5.5V, Regulated Output continuously switching into – – 2.5 MHz DDIO output mode, slow strong drive 25 pF mode SIO input operating frequency Fsioin 1.71V < V < 5.5V 90/10% V – – 33 MHz DDIO DDIO Figure 11-20. SIO Output Rise and Fall Times, Fast Strong Figure 11-21. SIO Output Rise and Fall Times, Slow Strong Mode, V = 3.3 V, 25 pF Load Mode, V = 3.3 V, 25 pF Load DDIO DDIO Note 39.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 79 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 11-12. SIO Comparator Specifications[40] Parameter Description Conditions Min Typ Max Units Vos Offset voltage V = 2 V – – 68 mV DDIO V = 2.7 V – – 72 DDIO V = 5.5 V – – 82 DDIO TCVos Offset voltage drift with temp – – 250 μV/°C CMRR Common mode rejection ratio V = 2 V 30 – – dB DDIO V = 2.7 V 35 – – DDIO V = 5.5 V 40 – – DDIO Tresp Response time – – 30 ns 11.4.3 USBIO For operation in GPIO mode, the standard range for V applies, see Device Level Specifications on page 67. DDD Table 11-13. USBIO DC Specifications Parameter Description Conditions Min Typ Max Units Rusbi USB D+ pull-up resistance[40] With idle bus 0.900 – 1.575 k Rusba USB D+ pull-up resistance[40] While receiving traffic 1.425 – 3.090 k Vohusb Static output high[40] 15 k ±5% to V , internal pull-up 2.8 – 3.6 V SS enabled Volusb Static output low[40] 15 k ±5% to V , internal pull-up – – 0.3 V SS enabled Vihgpio Input voltage high, GPIO mode[40] V = 1.8V 1.5 – – V DDD V = 3.3V 2 – – V DDD V = 5.0V 2 – – V DDD Vilgpio Input voltage low, GPIO mode[40] V = 1.8V – – 0.8 V DDD V = 3.3V – – 0.8 V DDD V = 5.0V – – 0.8 V DDD Vohgpio Output voltage high, GPIO mode[40] I = 4mA, V = 1.8V 1.6 – – V OH DDD I = 4mA, V = 3.3V 3.1 – – V OH DDD I = 4mA, V = 5.0V 4.2 – – V OH DDD Volgpio Output voltage low, GPIO mode[40] I = 4mA, V = 1.8V – – 0.3 V OL DDD I = 4mA, V = 3.3V – – 0.3 V OL DDD I = 4mA, V = 5.0V – – 0.3 V OL DDD V Differential input sensitivity |(D+)–(D–)| – – 0.2 V DI Vcm Differential input common mode range 0.8 – 2.5 V Vse Single ended receiver threshold 0.8 – 2 V Rps2 PS/2 pull-up resistance[40] In PS/2 mode, with PS/2 pull-up 3 – 7 k enabled Rext External USB series resistor [40] In series with each USB pin 21.78 22 22.22  (–1%) (+1%) Zo USB driver output impedance[40] Including Rext 28 – 44  C USB transceiver input capacitance – – 20 pF IN I Input leakage current (absolute value)[40] 25°C, V = 3.0 V – – 2 nA IL DDD Note 40.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 80 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 11-22. USBIO Output High Voltage and Current, Figure 11-23. USBIO Output Low Voltage and Current, GPIO Mode GPIO Mode Table 11-14. USBIO AC Specifications[41] Parameter Description Conditions Min Typ Max Units Tdrate Full–speed data rate average bit rate 12 – 0.25% 12 12 + 0.25% MHz Tjr1 Receiver data jitter tolerance to next transition –8 – 8 ns Tjr2 Receiver data jitter tolerance to pair transition –5 – 5 ns Tdj1 Driver differential jitter to next transition –3.5 – 3.5 ns Tdj2 Driver differential jitter to pair transition –4 – 4 ns Tfdeop Source jitter for differential transition to SE0 –2 – 5 ns transition Tfeopt Source SE0 interval of EOP 160 – 175 ns Tfeopr Receiver SE0 interval of EOP 82 – – ns Tfst Width of SE0 interval during differential – – 14 ns transition Fgpio_out GPIO mode output operating frequency 3V  V  5.5V – – 20 MHz DDD V = 1.71V – – 6 MHz DDD Tr_gpio Rise time, GPIO mode, 10%/90% V V > 3V, 25 pF load – – 12 ns DDD DDD V = 1.71V, 25 pF load – – 40 ns DDD Tf_gpio Fall time, GPIO mode, 90%/10% V V > 3V, 25 pF load – – 12 ns DDD DDD V = 1.71V, 25 pF load – – 40 ns DDD Note 41.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 81 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 11-24. USBIO Output Rise and Fall Times, GPIO Mode, V = 3.3 V, 25 pF Load DDD Table 11-15. USB Driver AC Specifications[42] Parameter Description Conditions Min Typ Max Units Tr Transition rise time – – 20 ns Tf Transition fall time – – 20 ns TR Rise/fall time matching V , V , see USB DC 90% – 111% USB_5 USB_3.3 Specifications on page 106 Vcrs Output signal crossover voltage 1.3 – 2 V 11.4.4 XRES Table 11-16. XRES DC Specifications Parameter Description Conditions Min Typ Max Units V Input voltage high threshold 0.7  V – – V IH DDIO V Input voltage low threshold – – 0.3  V IL V DDIO Rpullup Pull up resistor 3.5 5.6 8.5 k C Input capacitance – 3 pF IN V Input voltage hysteresis – 100 – mV H (Schmitt-trigger) Idiode Current through protection diode to – – 100 µA V and V DDIO SSIO Table 11-17. XRES AC Specifications[42] Parameter Description Conditions Min Typ Max Units T Reset pulse width 1 – – µs RESET Note 42.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 82 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.5 Analog Peripherals Specifications are valid for –40 °C  T  105 °C and T  120 °C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.5.1 Opamp Table 11-18. Opamp DC Specifications Parameter Description Conditions Min Typ Max Units V Input voltage range V – V V I SSA DDA Vos Input offset voltage – – 2.5 mV Operating temperature –40°C to – – 2 mV 70°C TCVos Input offset voltage drift with temperature Power mode = high – – ±30 µV / °C Ge1 Gain error, unity gain buffer mode Rload = 1 k – – ±0.1 % Cin Input capacitance Routing from pin – – 18 pF Vo Output voltage range 1 mA, source or sink, power mode V + 0.05 – V – 0.05 V SSA DDA = high Iout Output current capability, source or sink V + 500 mV Vout  V 25 – – mA SSA DDA –500mV, V > 2.7V DDA V + 500 mV  Vout  V 16 – – mA SSA DDA –500mV, 1.7 V = V  2.7V DDA Idd Quiescent current[39] Power mode = min – 250 400 uA Power mode = low – 250 400 uA Power mode = med – 330 950 uA Power mode = high – 1000 2500 uA CMRR Common mode rejection ratio[39] 80 – – dB PSRR Power supply rejection ratio[39] V  2.7 V 85 – – dB DDA V < 2.7 V 70 – – dB DDA I Input bias current[39] 25 °C – 10 – pA IB Figure 11-25. Opamp Vos Histogram, 7020 samples/1755 Figure 11-26. Opamp Vos vs Temperature, V = 5V DDA parts, 30 °C, VDDA = 3.3 V 20 0.2 18 16 0.1 14 12 V 0 %% 1100 m s, 8 o V -0.1 6 4 -0.2 2 0 -0.3 5 4 3 2 1 0 1 2 3 4 5 -40 -20 0 20 40 60 80 100 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. - - - - - Temperature, °C Vos, mV Note 39.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 83 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 11-27. Opamp Vos vs Vcommon and V 25 °C Figure 11-28. Opamp Output Voltage vs Load Current and DDA, Temperature, High Power Mode, 25 °C, V = 2.7 V DDA 0.3 3 0.25 2.5 0.2 V 2 m VVddddaa == 55.55 VV Vos, 000.11.155 Vdda = 2.7 V out, VVo 1.5 VViinn == 20. 7V V Vdda = 1.7 V 1 0.05 0.5 0 0 1 2 3 4 5 6 0 Vcommon, V 0 5 10 15 20 25 Iload, Source / Sink, mA Figure 11-29. Opamp Operating Current vs V and Power DDA Mode 1 0.8 A m 0.6 nt, e rur 0.4 C 0.2 0 1 2 3 4 5 V , V DDA High Power Mode Medium Low, Minimum Table 11-19. Opamp AC Specifications[40] Parameter Description Conditions Min Typ Max Units GBW Gain-bandwidth product Power mode = minimum, 15pF load 1 – – MHz Power mode = low, 15pF load 2 – – MHz Power mode = medium, 200pF load 1 – – MHz Power mode = high, 200pF load 3 – – MHz SR Slew rate, 20% - 80% Power mode = minimum, 15pF load 1.1 – – V/µs Power mode = low, 15pF load 1.1 – – V/µs Power mode = medium, 200pF load 0.9 – – V/µs Power mode = high, 200pF load 3 – – V/µs e Input noise density Power mode = high, V = 5 V, – 45 – nV/sqrtHz n DDA at 100 kHz Note 40.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 84 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 11-30. Opamp Noise vs Frequency, Figure 11-31. Opamp Step Response, Rising Power Mode = High, V = 5V DDA 1000 1.2 V 1 s, al gn 0.8 qrtHzsq 110000 put Siutp 00.66 V/ O Input n nd 0.4 a Output ut np 0.2 I 10 0 0.01 0.1 1 10 100 1000 -1 -0.5 0 0.5 1 Frequency, kHz Time,μs Figure 11-32. Opamp Step Response, Falling 1.2 V 1 s, al n 0.8 g Si ut pu 00.66 Inpput ut Output O d 0.4 n a ut p 0.2 n I 0 -1 -0.5 0 0.5 1 Time, μs Document Number: 001-84935 Rev. *L Page 85 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.5.2 Delta-Sigma ADC Unless otherwise specified, operating conditions are: Operation in continuous sample mode fclk = 6.144 MHz Reference = 1.024 V internal reference bypassed on P3.2 or P0.3 Unless otherwise specified, all charts and graphs show typical values Table 11-20. 12-bit Delta-sigma ADC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution 8 – 12 bits No. of Number of channels, single ended – – – GPIO Differential pair is formed using a No. of Number of channels, differential – – – pair of GPIOs. GPIO/2 Monotonic Yes – – – – Buffered, buffer gain = 1, Ge Gain error – – ±0.4 % Range = ±1.024V, 25 °C Buffered, buffer gain = 1, ppm/° Gd Gain drift – – 50 Range = ±1.024V C Buffered, 16-bit mode, full voltage – – ±0.2 mV range Vos Input offset voltage Buffered, 16-bit mode, – – ±0.1 mV V = 1.8V ±5%, 25 °C DDA Temperature coefficient, input offset Buffer gain = 1, 12-bit, TCVos – – 1 µV/°C voltage Range = ±1.024 V Input voltage range, single ended[41] V – V V SSA DDA Input voltage range, differential unbuf- fered[41] VSSA – VDDA V Input voltage range, differential, buffered[41] VSSA – VDDA – 1 V INL12 Integral non linearity[41] Range = ±1.024V, unbuffered – – ±1 LSB DNL12 Differential non linearity[41] Range = ±1.024V, unbuffered – – ±1 LSB INL8 Integral non linearity[41] Range = ±1.024V, unbuffered – – ±1 LSB DNL8 Differential non linearity[41] Range = ±1.024V, unbuffered – – ±1 LSB Rin_Buff ADC input resistance Input buffer used 10 – – M Rin_ADC12 ADC input resistance Input buffer bypassed, 12 bit, Range – 148[42] – k = ±1.024V Rin_ExtRef ADC external reference input resistance – 70[42, 43] – k ADC external reference input voltage, see Vextref also internal reference in Voltage Pins P0[3], P3[2] 0.9 – 1.3 V Reference on page 88 Current Consumption I Current consumption, 12 bit[41] 192 ksps, unbuffered – – 1.4 mA DD_12 I Buffer current consumption[41] – – 2.5 mA BUFF Notes 41.Based on device characterization (not production tested). 42.By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual. 43.Recommend an external reference device with an output impedance <100 Ω, for example, the LM185/285/385 family. A 1 µF capacitor is recommended. For more information, see AN61290 - PSoC® 3 and PSoC 5LP Hardware Design Considerations. Document Number: 001-84935 Rev. *L Page 86 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 11-21. Delta-sigma ADC AC Specifications Parameter Description Conditions Min Typ Max Units Startup time – – 4 Samples THD Total harmonic distortion[44] Buffer gain = 1, 12-bit, – – 0.0032 % Range = ±1.024V 12-Bit Resolution Mode SR12 Sample rate, continuous, high power[44] Range = ±1.024V, unbuffered 4 – 192 ksps BW12 Input bandwidth at max sample rate[44] Range = ±1.024V, unbuffered – 44 – kHz SINAD12int Signal to noise ratio, 12-bit, internal reference[44] Range = ±1.024V, unbuffered 66 – – dB 8-Bit Resolution Mode SR8 Sample rate, continuous, high power[44] Range = ±1.024V, unbuffered 8 – 384 ksps BW8 Input bandwidth at max sample rate[44] Range = ±1.024V, unbuffered – 88 – kHz SINAD8int Signal to noise ratio, 8-bit, internal reference[44] Range = ±1.024V, unbuffered 43 – – dB Table 11-22. Delta-sigma ADC Sample Rates, Range = ±1.024V Resolution, Continuous Multi-Sample Bits Min Max Min Max 8 8000 384000 1911 91701 9 6400 307200 1543 74024 10 5566 267130 1348 64673 11 4741 227555 1154 55351 12 4000 192000 978 46900 Figure 11-33. Delta-sigma ADC IDD vs sps, Range = ±1.024 V, Continuous Sample Mode, Input Buffer Bypassed 2 1.5 A m nt, 1 e urr C 0.5 0 1 10 100 100 Sample Rate, Ksps Note 44.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 87 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.5.3 Voltage Reference Table 11-23. Voltage Reference Specifications Parameter Description Conditions Min Typ Max Units V [45] Precision reference voltage Initial trimming, 25 °C 1.023 1.024 1.025 V REF (–0.1%) (+0.1%) After typical PCB assembly, post Typical (non-optimized) –40 °C – ±0.5 – % reflow board layout and 250°C 25 °C – ±0.2 – % solder reflow. Device may 85 °C – ±0.2 – % be calibrated after assembly to improve 105 °C – ±0.3 – % performance. Temperature drift[46] – – 30 ppm/°C Long term drift[46] – 100 – ppm/Khr Thermal cycling drift (stability)[46] – 100 – ppm Figure 11-34. Vref vs Temperature Figure 11-35. Vref Long-term Drift 1025 1024.5 V mm 11002244 ef, Vr 1.95V 1023.5 1.8V 1.71V 1023 -40 -20 0 20 40 60 80 100 Temperature, °C Notes 45.VREF is measured after packaging, and thus accounts for substrate and die attach stresses. 46.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 88 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.5.4 SAR ADC Table 11-24. SAR ADC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution – – 12 bits Number of channels – single-ended – – No of GPIO Number of channels – differential Differential pair is formed using a – – No of pair of neighboring GPIO. GPIO/2 Monotonicity[47] Yes – – Ge Gain error[48] External reference – – ±0.1 % V Input offset voltage – – ±2 mV OS I Current consumption[47] – – 1 mA DD Input voltage range – single-ended[47] V – V V SSA DDA Input voltage range – differential[47] V – V V SSA DDA PSRR Power supply rejection ratio[47] 70 – – dB CMRR Common mode rejection ratio 70 – – dB INL Integral non linearity[47] V 1.71 to 5.5 V, 1 Msps, V – – +2/–1.5 LSB DDA REF 1 to 5.5 V, bypassed at ExtRef pin V 2.0 to 3.6 V, 1 Msps, V 2 – – ±1.2 LSB DDA REF to V DDA, bypassed at ExtRef pin V 1.71 to 5.5 V, 500 ksps, V – – ±1.3 LSB DDA REF 1 to 5.5 V, bypassed at ExtRef pin DNL Differential non linearity[47] V 1.71 to 5.5 V, 1 Msps, V – – +2/–1 LSB DDA REF 1 to 5.5 V, bypassed at ExtRef pin V 2.0 to 3.6 V, 1 Msps, V 2 – – 1.7/–0.99 LSB DDA REF to V , bypassed at ExtRef pin DDA No missing codes V 1.71 to 5.5 V, 500 ksps, V – – +2/–0.99 LSB DDA REF 1 to 5.5 V, bypassed at ExtRef pin No missing codes R Input resistance[47] – 180 – kΩ IN Notes 47.Based on device characterization (Not production tested). 48.For total analog system Idd < 5 mA, depending on package used. With higher total analog system currents it is recommended that the SAR ADC be used in differential mode. Document Number: 001-84935 Rev. *L Page 89 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 11-36. SAR ADC DNL vs Output Code, Figure 11-37. SAR ADC INL vs Output Code, Bypassed Internal Reference Mode Bypassed Internal Reference Mode 1 1 0.5 0.5 B S B , LNL 00 LSL, L 00 D N I -0.5 -0.5 -1 -1 -2048 0 2048 -2048 0 2048 Code (12 bit) Code (12 bit) Figure 11-38. SAR ADC I vs sps, V = 5 V, Continuous DD DDA Sample Mode, External Reference Mode 0.5 0.4 mA 0.3 t, n e urr 0.2 C 0.1 0 0 250 500 750 1000 Sample Rate, ksps Document Number: 001-84935 Rev. *L Page 90 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 11-25. SAR ADC AC Specifications[49] Parameter Description Conditions Min Typ Max Units A_SAMP_1 Sample rate with external reference – – 1 Msps bypass cap A_SAMP_2 Sample rate with no bypass cap. – – 500 Ksps Reference = V DD A_SAMP_3 Sample rate with no bypass cap. – – 100 Ksps Internal reference Startup time – – 10 µs SINAD Signal-to-noise ratio 68 – – dB THD Total harmonic distortion – – 0.02 % Figure 11-39. SAR ADC Noise Histogram, 100 ksps, Internal Figure 11-40. SAR ADC Noise Histogram, 1 msps, Internal Reference No Bypass Reference Bypassed 100 100 80 80 60 60 %% %% 40 40 20 20 0 0 1021 1022 1023 1024 1025 1022 1023 1024 1025 1026 Counts, 12 bit Counts, 12 bit Figure 11-41. SAR ADC Noise Histogram, 1 msps, External Reference 100 80 60 %% 40 20 0 0 1 2 3 4 2 2 2 2 2 0 0 0 0 0 1 1 1 1 1 Counts, 12 bit Note 49.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 91 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.5.5 Analog Globals Table 11-26. Analog Globals DC Specifications Parameter Description Conditions Min Typ Max Units Rppag Resistance pin-to-pin through V = 3.0 V – 1500 2200  DDA P2[4], AGL0, DSM INP, AGL1, V = 1.71V – 1200 1700  P2[5][50] DDA Rppmuxbus Resistance pin-to-pin through V = 3.0 V – 700 1100  DDA P2[3], amuxbusL, P2[4][50] V = 1.71V – 600 900  DDA Table 11-27. Analog Globals AC Specifications Parameter Description Conditions Min Typ Max Units Inter-pair crosstalk for analog 106 – – dB routes[51, 52] BWag Analog globals 3 db bandwidth[52] V = 3.0 V, 25 °C – 26 – MHz DDA 11.5.6 Comparator Table 11-28. Comparator DC Specifications[53] Parameter Description Conditions Min Typ Max Units Input offset voltage in fast mode Factory trim, V > 2.7 V, – 10 mV DDA VOS VIN  0.5 V Input offset voltage in slow mode Factory trim, Vin  0.5 V – 9 mV Input offset voltage in fast mode Custom trim – – 4 mV V OS Input offset voltage in slow mode[53] Custom trim – – 4 mV V Input offset voltage in ultra low – ±12 – mV OS power mode TCVos Temperature coefficient, input offset V = V / 2, fast mode – 63 85 µV/°C CM DDA voltage V = V / 2, slow mode – 15 20 CM DDA V Hysteresis Hysteresis enable mode – 10 32 mV HYST V Input common mode voltage High current / fast mode V – V V ICM SSA DDA Low current / slow mode V – V V SSA DDA Ultra low power mode V – V – V SSA DDA 1.15 CMRR Common mode rejection ratio – 50 – dB I High current mode/fast mode – – 400 µA CMP Low current mode/slow mode – – 100 µA Ultra low power mode – 6 – µA Table 11-29. Comparator AC Specifications[53] Parameter Description Conditions Min Typ Max Units Response time, high current mode 50 mV overdrive, measured – 75 110 ns pin-to-pin Response time, low current mode 50 mV overdrive, measured – 155 200 ns T RESP pin-to-pin Response time, ultra low power 50 mV overdrive, measured – 55 – µs mode pin-to-pin Notes 50.Based on device characterization (Not production tested). 51.This value is calculated, not measured. 52.Pin P6[4] to del-sig ADC input; calculated, not measured. 53.The recommended procedure for using a custom trim value for the on-chip comparators are found in the TRM. Document Number: 001-84935 Rev. *L Page 92 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.5.7 Current Digital-to-analog Converter (IDAC) All specifications are based on use of the low-resistance IDAC output pins (see Pin Descriptions on page 11 for details). See the IDAC component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-30. IDAC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution – – 8 bits I Output current at code = 255 Range = 2.04 mA, code = 255, – 2.04 – mA OUT VDDA  2.7 V, Rload = 600  Range = 2.04 mA, High mode, – 2.04 – mA code = 255, V  2.7 V, DDA Rload = 300  Range = 255 µA, code = 255, – 255 – µA Rload = 600  Range = 31.875 µA, code = 255, – 31.875 – µA Rload = 600  Monotonicity – – Yes Ezs Zero scale error – 0 ±1 LSB Eg Gain error Range = 2.04 mA – – ±2.5 % Range = 255 µA – – ±2.5 % Range = 31.875 µA – – ±3.5 % TC_Eg Temperature coefficient of gain Range = 2.04 mA – – 0.045 % / °C error Range = 255 µA – – 0.045 % / °C Range = 31.875 µA – – 0.05 % / °C INL Integral nonlinearity Sink mode, range = 255 µA, Codes – ±0.9 ±1 LSB 8 – 255, Rload = 2.4 k, Cload = 15 pF Source mode, range = 255 µA, – ±1.2 ±1.6 LSB Codes 8 – 255, Rload = 2.4 k, Cload = 15 pF Source mode, range = 31.875 µA, – ±0.9 ±2 LSB Codes 8 - 255, Rload = 20 kΩ, Cload = 15 pF[54] Sink mode, range = 31.875 µA, – ±0.9 ±2 LSB Codes 8 - 255, Rload = 20 kΩ, Cload = 15 pF[54] Source mode, range = 2.04 mA, – ±0.9 ±2 LSB Codes 8 - 255, Rload = 600 Ω, Cload = 15 pF[54] Sink mode, range = 2.04 mA, – ±0.6 ±1 LSB Codes 8 - 255, Rload = 600 Ω, Cload = 15 pF[54] Note 54.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 93 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 11-30. IDAC DC Specifications (continued) Parameter Description Conditions Min Typ Max Units DNL Differential nonlinearity Sink mode, range = 255 µA, – ±0.3 ±1 LSB Rload = 2.4k, Cload = 15 pF Source mode, range = 255 µA, – ±0.3 ±1 LSB Rload = 2.4 k, Cload = 15 pF Source mode, range = 31.875 µA, – ±0.2 ±1 LSB Rload = 20 kΩ, Cload = 15 pF[55] Sink mode, range = 31.875 µA, – ±0.2 ±1 LSB Rload = 20 kΩ, Cload = 15 pF[55] Source mode, range = 2.0 4mA, – ±0.2 ±1 LSB Rload = 600 Ω, Cload = 15 pF[55] Sink mode, range = 2.0 4mA, – ±0.2 ±1 LSB Rload = 600 Ω, Cload = 15 pF[55] Vcompliance Dropout voltage, source or sink Voltage headroom at max current, 1 – – V mode Rload to V or Rload to V , DDA SSA Vdiff from V DDA I Operating current, code = 0 Slow mode, source mode, range = – 44 100 µA DD 31.875 µA Slow mode, source mode, range = – 33 100 µA 255 µA, Slow mode, source mode, range = – 33 100 µA 2.04 mA Slow mode, sink mode, range = – 36 100 µA 31.875 µA Slow mode, sink mode, range = – 33 100 µA 255 µA Slow mode, sink mode, range = – 33 100 µA 2.04 mA Fast mode, source mode, range = – 310 500 µA 31.875 µA Fast mode, source mode, range = – 305 500 µA 255 µA Fast mode, source mode, range = – 305 500 µA 2.04 mA Fast mode, sink mode, range = – 310 500 µA 31.875 µA Fast mode, sink mode, range = – 300 500 µA 255µA Fast mode, sink mode, range = – 300 500 µA 2.04 mA Note 55.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 94 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 11-42. IDAC INL vs Input Code, Range = 255 µA, Figure 11-43. IDAC INL vs Input Code, Range = 255µA, Sink Source Mode Mode 1 1 0.5 0.5 B B LSNL, L 00 LSNL, L 00 I I -0.5 -0.5 -1 -1 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Code, 8-bit Code, 8-bit Figure 11-44. IDAC DNL vs Input Code, Range = 255 µA, Figure 11-45. IDAC DNL vs Input Code, Range = 255 µA, Sink Source Mode Mode 0.5 0.5 0.25 0.25 B B S S LNL, 00 LNL, 00 D D -0.25 -0.25 -0.5 -0.5 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Code, 8-bit Code, 8-bit Figure 11-46. IDAC INL vs Temperature, Range = 255 µA, Fast Figure 11-47. IDAC DNL vs Temperature, Range = 255 µA, Mode Fast Mode 1 0.5 Source mode Source mode 0.75 0.4 Sink mode Sink mode LSBINL, L 00.55 LSBDNL, 00..32 0.25 0.1 0 0 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 Temperature, °C Temperature, °C Document Number: 001-84935 Rev. *L Page 95 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 11-48. IDAC Full Scale Error vs Temperature, Range Figure 11-49. IDAC Full Scale Error vs Temperature, Range = 255 µA, Source Mode = 255 µA, Sink Mode 1.5 1.5 1 1 % % Error, Full Scale -00..0505 Error, Full Scale -00..0505 -1 -1 -1.5 -1.5 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 Temperature, °C Temperature, °C Figure 11-50. IDAC Operating Current vs Temperature, Figure 11-51. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Source Mode Range = 255 µA, Code = 0, Sink Mode 350 350 300 300 A A Current, μC 220500 FSSallooswwt MMMooodddeee Current, μC 220500 FSSallooswwt MMMooodddeee Operating 110500 Operating 110500 50 50 0 0 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 Temperature, °C Temperature, °C Table 11-31. IDAC AC Specifications[56] Parameter Description Conditions Min Typ Max Units F Update rate – – 8 Msps DAC T Settling time to 0.5 LSB Range = 31.875 µA, full scale – – 125 ns SETTLE transition, fast mode, 600 15-pF load Range = 255 µA, full scale – – 125 ns transition, fast mode, 600  15-pF load Current noise Range = 255µA, source mode, fast – 340 – pA/sqrtHz mode, Vdda = 5V, 10kHz Note 56.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 96 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 11-52. IDAC Step Response, Codes 0x40 - 0xC0, Figure 11-53. IDAC Glitch Response, Codes 0x7F - 0x80, 255 µA Mode, Source Mode, Fast Mode, V = 5 V 255 µA Mode, Source Mode, Fast Mode, V = 5 V DDA DDA 250 134 132 200 130 A 150 A 128 μ μ Iout, 100 Iout, 126 124 50 122 0 120 0 0.5 1 1.5 2 0 0.5 1 1.5 2 Time, μs Time, μs Figure 11-54. IDAC PSRR vs Frequency Figure 11-55. IDAC Current Noise, 255µA Mode, Source Mode, Fast Mode, V = 5 V DDA 60 10000 50 1000 40 B d R, 30 Hz PSRP 2200 qrtA / sq 110000 p 10 10 0 0.1 1 10 100 1000 10000 1 Frequency, kHz 0.01 0.1 1 10 100 255 (cid:2)A, code 0x7F 255 (cid:2)A, code 0xFF Frequency, kHz Document Number: 001-84935 Rev. *L Page 97 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.5.8 Voltage Digital to Analog Converter (VDAC) See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-32. VDAC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution – 8 – bits INL1 Integral nonlinearity 1 V scale – ±2.1 ±2.5 LSB INL4 Integral nonlinearity[57] 4 V scale – ±2.1 ±2.5 LSB DNL1 Differential nonlinearity 1 V scale – ±0.3 ±1 LSB DNL4 Differential nonlinearity[57] 4 V scale – ±0.3 ±1 LSB Rout Output resistance 1 V scale – 4 – k 4 V scale – 16 – k V Output voltage range, code = 255 1 V scale – 1.02 – V OUT 4 V scale, V = 5 V – 4.08 – V DDA Monotonicity – – Yes – V Zero scale error – 0 ±0.9 LSB OS Eg Gain error 1 V scale – – ±2.5 % 4 V scale – – ±2.5 % TC_Eg Temperature coefficient, gain error 1 V scale – – 0.03 %FSR / °C 4 V scale – – 0.03 %FSR / °C I Operating current[57] Slow mode – – 100 µA DD Fast mode – – 500 µA Figure 11-56. VDAC INL vs Input Code, 1 V Mode Figure 11-57. VDAC DNL vs Input Code, 1 V Mode 1 0.5 0.5 0.25 B B S S LNL, L 00 LNL, 00 I D -0.5 -0.25 -1 -0.5 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Code, 8-bit Code, 8-bit Note 57.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 98 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 11-58. VDAC INL vs Temperature, 1 V Mode Figure 11-59. VDAC DNL vs Temperature, 1 V Mode 1 0.5 0.4 0.75 B B 0.3 S S LL, L 00.55 LL, IN DN 0.2 0.25 0.1 0 0 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 Temperature, °C Temperature, °C Figure 11-60. VDAC Full Scale Error vs Temperature, 1 V Figure 11-61. VDAC Full Scale Error vs Temperature, 4 V Mode Mode 1 2 % 0.75 % 1.5 Error, Full Scale 000.2.555 Error, Full Scale 0.151 0 0 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 Temperature, °C Temperature, °C Figure 11-62. VDAC Operating Current vs Temperature, 1V Figure 11-63. VDAC Operating Current vs Temperature, 1 V Mode, Slow Mode Mode, Fast Mode 50 400 40 Current, μAC 30 Current, μAC 232000000 Operating 1200 Operating 100 0 0 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 Temperature, °C Temperature, °C Document Number: 001-84935 Rev. *L Page 99 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 11-33. VDAC AC Specifications[58] Parameter Description Conditions Min Typ Max Units F Update rate 1 V scale – – 1000 ksps DAC 4 V scale – – 250 ksps TsettleP Settling time to 0.1%, step 25% to 1 V scale, Cload = 15 pF – 0.45 1 µs 75% 4 V scale, Cload = 15 pF – 0.8 3.2 µs TsettleN Settling time to 0.1%, step 75% to 1 V scale, Cload = 15 pF – 0.45 1 µs 25% 4 V scale, Cload = 15 pF – 0.7 3 µs Voltage noise Range = 1V, fast mode, V = – 750 – nV/sqrtHz DDA 5V, 10kHz Figure 11-64. VDAC Step Response, Codes 0x40 - 0xC0, 1V Figure 11-65. VDAC Glitch Response, Codes 0x7F - 0x80, 1V Mode, Fast Mode, V = 5 V Mode, Fast Mode, V = 5 V DDA DDA 1 0.54 0.75 0.52 V V t, Vout 00.55 t, Vout 0.5 0.25 0 0.48 0 0.5 1 1.5 2 0 0.5 1 1.5 2 Time, μs Time, μs Figure 11-66. VDAC PSRR vs Frequency Figure 11-67. VDAC Voltage Noise, 1V Mode, Fast Mode, V = 5V DDA 50 100000 40 10000 B d 30 R, Hz SR 20 qrtq 11000000 PP s V/ n 10 100 0 0.1 1 10 100 1000 Frequency, kHz 10 0.01 0.1 1 10 100 4 V, code 0x7F 4 V, code 0xFF Frequency, kHz Note 58.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 100 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.5.9 Mixer The mixer is created using a SC/CT analog block; see the Mixer component datasheet in PSoC Creator for full electrical specifications and APIs. Table 11-34. Mixer DC Specifications Parameter Description Conditions Min Typ Max Units V Input offset voltage High power mode, V = 1.024V, – – 15 mV OS IN V = 1.024V REF Quiescent current – 0.9 2 mA G Gain – 0 – dB Table 11-35. Mixer AC Specifications[59] Parameter Description Conditions Min Typ Max Units f Local oscillator frequency Down mixer mode – – 4 MHz LO f Input signal frequency Down mixer mode – – 14 MHz in f Local oscillator frequency Up mixer mode – – 1 MHz LO f Input signal frequency Up mixer mode – – 1 MHz in SR Slew rate 3 – – V/µs 11.5.10 Transimpedance Amplifier The TIA is created using a SC/CT analog block; see the TIA component datasheet in PSoC Creator for full electrical specifications and APIs. Table 11-36. Transimpedance Amplifier (TIA) DC Specifications Parameter Description Conditions Min Typ Max Units V Input offset voltage – – 10 mV IOFF Rconv Conversion resistance[60] R = 20K; 40 pF load –25 – +35 % R = 30K; 40 pF load –25 – +35 % R = 40K; 40 pF load –25 – +35 % R = 80K; 40 pF load –25 – +35 % R = 120K; 40 pF load –25 – +35 % R = 250K; 40 pF load –25 – +35 % R= 500K; 40 pF load –25 – +35 % R = 1M; 40 pF load –25 – +35 % Quiescent current[59] – 1.1 2 mA Table 11-37. Transimpedance Amplifier (TIA) AC Specifications[59] Parameter Description Conditions Min Typ Max Units BW Input bandwidth (–3 dB) R = 20K; –40 pF load 1200 – – kHz R = 120K; –40 pF load 240 – – kHz R = 1M; –40 pF load 25 – – kHz Notes 59.Based on device characterization (Not production tested). 60.Conversion resistance values are not calibrated. Calibrated values and details about calibration are provided in PSoC Creator component datasheets. External precision resistors can also be used. Document Number: 001-84935 Rev. *L Page 101 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.5.11 Programmable Gain Amplifier The PGA is created using a SC/CT analog block; see the PGA component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, operating conditions are: Operating temperature = 25 °C for typical values Unless otherwise specified, all charts and graphs show typical values Table 11-38. PGA DC Specifications Parameter Description Conditions Min Typ Max Units Vin Input voltage range Power mode = minimum Vssa – V V DDA Vos Input offset voltage Power mode = high, – – 10 mV gain = 1 TCVos Input offset voltage drift Power mode = high, – – ±30 µV/°C with temperature gain = 1 Ge1 Gain error, gain = 1 – – ±0.15 % Ge16 Gain error, gain = 16 – – ±2.5 % Ge50 Gain error, gain = 50 – – ±5 % Vonl DC output nonlinearity Gain = 1 – – ±0.01 % of FSR Cin Input capacitance – – 7 pF Voh Output voltage swing Power mode = high, V – 0.15 – – V DDA gain = 1, Rload = 100 k to V / 2 DDA Vol Output voltage swing Power mode = high, – – V + 0.15 V SSA gain = 1, Rload = 100 k to V / 2 DDA Vsrc Output voltage under load Iload = 250 µA, V  – – 300 mV DDA 2.7V, power mode = high Idd Operating current[61] Power mode = high – 1.5 1.65 mA PSRR Power supply rejection 48 – – dB ratio Figure 11-68. PGA Voffset Histogram, 4096 samples/ 1024 parts Note 61.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 102 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 11-39. PGA AC Specifications[62] Parameter Description Conditions Min Typ Max Units BW1 –3 dB bandwidth Power mode = high, 6.7 8 – MHz gain = 1, input = 100 mV peak-to-peak T ≤ 105 °C 6 8 – A SR1 Slew rate Power mode = high, 3 – – V/µs gain = 1, 20% to 80% e Input noise density Power mode = high, – 43 – nV/sqrtHz n V = 5 V, at 100 kHz DDA Figure 11-69. Bandwidth vs. Temperature, at Different Gain Figure 11-70. Noise vs. Frequency, Vdda = 5V, Settings, Power Mode = High Power Mode = High 1000 10 Hz 1 Hz , MBW, qrtnV/sq 100 0.1 -40 -20 0 20 40 60 80 100 10 Temperature, °C 0.01 0.1 1 10 100 1000 Gain = 1 Gain = 24 Gain = 48 Frequency, kHz 11.5.12 Temperature Sensor Table 11-40. Temperature Sensor Specifications Parameter Description Conditions Min Typ Max Units Temp sensor accuracy Range: –40 °C to +105 °C – ±5 – °C 11.5.13 LCD Direct Drive Table 11-41. LCD Direct Drive DC Specifications[62] Parameter Description Conditions Min Typ Max Units I LCD Block (no glass) Device sleep mode with wakeup at – 81 – A CC 400 Hz rate to refresh LCD, bus, clock = 3MHz, Vddio = Vdda = 3 V, 8 commons, 16 segments, 1/5 duty cycle, 40 Hz frame rate, no glass connected I Current per segment driver Strong drive mode – 260 – µA CC_SEG V LCD bias range (V refers to the main V  3V and V  V 2 – 5 V BIAS BIAS DDA DDA BIAS output voltage(V0) of LCD DAC) LCD bias step size V  3V and V  V – 9.1 × V – mV DDA DDA BIAS DDA LCD capacitance per segment/ Drivers may be combined – 500 5000 pF common driver Maximum segment DC offset V 3V and V  V – – 20 mV DDA DDA BIAS I Output drive current per segment driver) V = 5.5V, strong drive mode 355 – 710 µA OUT DDIO Note 62.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 103 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 11-42. LCD Direct Drive AC Specifications[63] Parameter Description Conditions Min Typ Max Units f LCD frame rate 10 50 150 Hz LCD 11.6 Digital Peripherals Specifications are valid for –40 °C  T  105 °C and T  120 °C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.6.1 Timer The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for more information, see the Timer component datasheet in PSoC Creator. Table 11-43. Timer DC Specifications[63] Parameter Description Conditions Min Typ Max Units Block current consumption 16-bit timer, at listed input clock – – – µA frequency 3 MHz – 15 – µA 12 MHz – 60 – µA 48 MHz – 260 – µA 80 MHz – 360 – µA Table 11-44. Timer AC Specifications[63] Parameter Description Conditions Min Typ Max Units Operating frequency DC – 80.01 MHz Capture pulse width (Internal)[64] 15 – – ns Capture pulse width (external) 30 – – ns Timer resolution[64] 15 – – ns Enable pulse width[64] 15 – – ns Enable pulse width (external) 30 – – ns Reset pulse width[64] 15 – – ns Reset pulse width (external) 30 – – ns 11.6.2 Counter The following specifications apply to the Timer/Counter/PWM peripheral, in counter mode. Counters can also be implemented in UDBs; for more information, see the Counter component datasheet in PSoC Creator. Table 11-45. Counter DC Specifications[63] Parameter Description Conditions Min Typ Max Units Block current consumption 16-bit counter, at listed input clock – – – µA frequency 3 MHz – 15 – µA 12 MHz – 60 – µA 48 MHz – 260 – µA 80 MHz – 360 – µA Notes 63.Based on device characterization (Not production tested). 64.For correct operation, the minimum Timer/Counter/PWM input pulse width is the period of bus clock. Document Number: 001-84935 Rev. *L Page 104 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 11-46. Counter AC Specifications[65] Parameter Description Conditions Min Typ Max Units Operating frequency DC – 80.01 MHz Capture pulse[66] 15 – – ns Resolution[66] 15 – – ns Pulse width[66] 15 – – ns Pulse width (external) 30 ns Enable pulse width[66] 15 – – ns Enable pulse width (external) 30 – – ns Reset pulse width[66] 15 – – ns Reset pulse width (external) 30 – – ns 11.6.3 Pulse Width Modulation The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented in UDBs; for more information, see the PWM component datasheet in PSoC Creator. Table 11-47. PWM DC Specifications[65] Parameter Description Conditions Min Typ Max Units Block current consumption 16-bit PWM, at listed input clock – – – µA frequency 3 MHz – 15 – µA 12 MHz – 60 – µA 48 MHz – 260 – µA 80 MHz – 360 – µA Table 11-48. PWM AC Specifications[65] Parameter Description Conditions Min Typ Max Units Operating frequency DC – 80.01 MHz Pulse width[66] 15 – – ns Pulse width (external) 30 – – ns Kill pulse width[66] 15 – – ns Kill pulse width (external) 30 – – ns Enable pulse width[66] 15 – – ns Enable pulse width (external) 30 – – ns Reset pulse width[66] 15 – – ns Reset pulse width (external) 30 – – ns 11.6.4 I2C Table 11-49. Fixed I2C DC Specifications[65] Parameter Description Conditions Min Typ Max Units Block current consumption Enabled, configured for 100 kbps – – 250 µA Enabled, configured for 400 kbps – – 260 µA Notes 65.Based on device characterization (Not production tested). 66.For correct operation, the minimum Timer/Counter/PWM input pulse width is the period of bus clock. Document Number: 001-84935 Rev. *L Page 105 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 11-50. Fixed I2C AC Specifications[67] Parameter Description Conditions Min Typ Max Units Bit rate – – 1 Mbps 11.6.5 Controller Area Network Table 11-51. CAN DC Specifications[67, 68] Parameter Description Conditions Min Typ Max Units I Block current consumption – – 200 µA DD Table 11-52. CAN AC Specifications[67, 68] Parameter Description Conditions Min Typ Max Units Bit rate Minimum 8 MHz clock – – 1 Mbit 11.6.6 Digital Filter Block Table 11-53. DFB DC Specifications[68] Parameter Description Conditions Min Typ Max Units DFB operating current 64-tap FIR at F DFB 500 kHz (6.7 ksps) – 0.16 0.27 mA 1 MHz (13.4 ksps) – 0.33 0.53 mA 10 MHz (134 ksps) – 3.3 5.3 mA 48 MHz (644 ksps) – 15.7 25.5 mA 80 MHz (1.07 Msps) – 26.0 42.5 mA Table 11-54. DFB AC Specifications[68] Parameter Description Conditions Min Typ Max Units F DFB operating frequency DC – 80.01 MHz DFB 11.6.7 USB Table 11-55. USB DC Specifications Parameter Description Conditions Min Typ Max Units V Device supply (V ) for USB USB configured, USB regulator 4.35 – 5.25 V USB_5 DDD operation enabled V USB configured, USB regulator 3.15 – 3.6 V USB_3.3 bypassed V USB configured, USB regulator 2.85 – 3.6 V USB_3 bypassed[69] I Device supply current in device V = 5 V, F = 1.5 MHz – 10 – mA USB_Configured DDD CPU active mode, bus clock and IMO = V = 3.3 V, F = 1.5 MHz – 8 – mA DDD CPU 24 MHz I Device supply current in device V = 5 V, connected to USB – 0.5 – mA USB_Suspended DDD sleep mode host, PICU configured to wake on USB resume signal V = 5 V, disconnected from – 0.3 – mA DDD USB host V = 3.3 V, connected to USB – 0.5 – mA DDD host, PICU configured to wake on USB resume signal V = 3.3 V, disconnected from – 0.3 – mA DDD USB host Notes 67.Based on device characterization (Not production tested). 68.Refer to ISO 11898 specification for details. 69.Rise/fall time matching (TR) not guaranteed, see Table 11-15 on page 82. Document Number: 001-84935 Rev. *L Page 106 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.6.8 Universal Digital Blocks (UDBs) PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications, APIs, and example code. Table 11-56. UDB AC Specifications[70] Parameter Description Conditions Min Typ Max Units Datapath Performance F Maximum frequency of 16-bit timer in – – 67.01 MHz MAX_TIMER a UDB pair F Maximum frequency of 16-bit adder in – – 67.01 MHz MAX_ADDER a UDB pair F Maximum frequency of 16-bit – – 67.01 MHz MAX_CRC CRC/PRS in a UDB pair PLD Performance F Maximum frequency of a two-pass – – 67.01 MHz MAX_PLD PLD function in a UDB pair Clock to Output Performance t Propagation delay for clock in to data 25 °C, V  2.7 V – 20 25 ns CLK_OUT DDD out, see Figure11-71. t Propagation delay for clock in to data Worst-case placement, routing, – – 55 ns CLK_OUT out, see Figure11-71. and pin selection Figure 11-71. Clock to Output Performance Note 70.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 107 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.7 Memory Specifications are valid for –40 °C  T  105 °C and T  120 °C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.7.1 Flash Table 11-57. Flash DC Specifications Parameter Description Conditions Min Typ Max Units Erase and program voltage V pin 1.71 – 5.5 V DDD Table 11-58. Flash AC Specifications Parameter Description Conditions Min Typ Max Units T Row write time (erase + program) – 15 20 ms WRITE T Row erase time – 10 13 ms ERASE Row program time – 5 7 ms T Bulk erase time (256 KB) – – 140 ms BULK Sector erase time (16 KB) – – 15 ms T Total device programming time No overhead[71] – 5 7.5 seconds PROG Flash data retention time, retention Average ambient temp. T  55°C, 20 – – years A period measured from last erase cycle 100 K erase/program cycles Average ambient temp. T  85 °C, 10 – – A 10K erase/program cycles Ambient temp. T ≤ 105 °C, 10 – – A 10 K erase/program cycles, ≤ one year at T ≥ 75 °C [72] A 11.7.2 EEPROM Table 11-59. EEPROM DC Specifications Parameter Description Conditions Min Typ Max Units Erase and program voltage 1.71 – 5.5 V Table 11-60. EEPROM AC Specifications Parameter Description Conditions Min Typ Max Units T Single row erase/write cycle time – 10 20 ms WRITE EEPROM data retention time, retention Average ambient temp, T  25 °C, 20 – – years A period measured from last erase cycle 1M erase/program cycles Average ambient temp, T  55 °C, 20 – – A 100K erase/program cycles Average ambient temp. T 85 °C, 10 – – A 10K erase/program cycles Ambient temp. T ≤ 105 °C, 10 – – A 10K erase/program cycles, ≤ one year at T ≥75 °C [72] A Notes 71.See PSoC 5 Device Programming Specifications for a description of a low-overhead method of programming PSoC 5 flash. 72.Cypress provides a retention calculator to calculate the retention lifetime based on customers' individual temperature profiles for operation over the –40 °C to +105°C ambient temperature range. Contact customercare@cypress.com. Document Number: 001-84935 Rev. *L Page 108 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.7.3 Nonvolatile Latches (NVL) Table 11-61. NVL DC Specifications Parameter Description Conditions Min Typ Max Units Erase and program voltage V pin 1.71 – 5.5 V DDD Table 11-62. NVL AC Specifications Parameter Description Conditions Min Typ Max Units NVL endurance Programmed at 25 °C 1K – – program/ erase cycles Programmed at 0 °C to 70 °C 100 – – program/ erase cycles NVL data retention time Average ambient temp. T ≤ 55 °C 20 – – years A Average ambient temp. T ≤ 85 °C 10 – – A Ambient temp. T ≤ 105 °C, 10 – – A ≤ one year at T ≥ 75 °C [73] A 11.7.4 SRAM Table 11-63. SRAM DC Specifications Parameter Description Conditions Min Typ Max Units V SRAM retention voltage[74] 1.2 – – V SRAM Table 11-64. SRAM AC Specifications Parameter Description Conditions Min Typ Max Units F SRAM operating frequency DC – 80.01 MHz SRAM Notes 73.Cypress provides a retention calculator to calculate the retention lifetime based on customers' individual temperature profiles for operation over the –40 °C to +105°C ambient temperature range. Contact customercare@cypress.com. 74.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 109 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.7.5 External Memory Interface Figure 11-72. Asynchronous Write and Read Cycle Timing, No Wait States Tbus_clock Bus Clock EM_Addr EM_CE EM_WE EM_OE Twr_setup Trd_setup Trd_hold EM_Data Write Cycle Read Cycle Minimum of 4 bus clock cycles between successive EMIF accesses Table 11-65. Asynchronous Write and Read Timing Specifications[72] Parameter Description Conditions Min Typ Max Units Fbus_clock Bus clock frequency[73] – – 33 MHz Tbus_clock Bus clock period[74] 30.3 – – ns Twr_Setup Time from EM_data valid to rising edge of Tbus_clock – 10 – – ns EM_WE and EM_CE Trd_setup Time that EM_data must be valid before rising 5 – – ns edge of EM_OE Trd_hold Time that EM_data must be valid after rising 5 – – ns edge of EM_OE Notes 72.Based on device characterization (Not production tested). 73.EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page75. 74.EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency. Document Number: 001-84935 Rev. *L Page 110 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 11-73. Synchronous Write and Read Cycle Timing, No Wait States Tbus_clock Bus Clock EM_Clock EM_Addr EM_CE EM_ADSC EM_WE EM_OE Twr_setup Trd_setup Trd_hold EM_Data Write Cycle Read Cycle Minimum of 4 bus clock cycles between successive EMIF accesses Table 11-66. Synchronous Write and Read Timing Specifications[75] Parameter Description Conditions Min Typ Max Units Fbus_clock Bus clock frequency[76] – – 33 MHz Tbus_clock Bus clock period[77] 30.3 – – ns Twr_Setup Time from EM_data valid to rising edge of Tbus_clock – 10 – – ns EM_Clock Trd_setup Time that EM_data must be valid before rising 5 – – ns edge of EM_OE Trd_hold Time that EM_data must be valid after rising 5 – – ns edge of EM_OE Notes 75.Based on device characterization (Not production tested). 76.EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page75. 77.EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency. Document Number: 001-84935 Rev. *L Page 111 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.8 PSoC System Resources Specifications are valid for –40 °C  T  105 °C and T  120 °C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.8.1 POR with Brown Out For brown out detect in regulated mode, V and V must be  2.0 V. Brown out detect is not available in externally regulated DDD DDA mode. Table 11-67. Precise Low-Voltage Reset (PRES) with Brown Out DC Specifications Parameter Description Conditions Min Typ Max Units PRESR Rising trip voltage Factory trim 1.64 – 1.68 V PRESF Falling trip voltage 1.62 – 1.66 V Table 11-68. Power On Reset (POR) with Brown Out AC Specifications[78] Parameter Description Conditions Min Typ Max Units PRES_TR[79] Response time – – 0.5 µs V /V droop rate Sleep mode – 5 – V/sec DDD DDA 11.8.2 Voltage Monitors Table 11-69. Voltage Monitors DC Specifications Parameter Description Conditions Min Typ Max Units LVI Trip voltage LVI_A/D_SEL[3:0] = 0000b 1.68 1.73 1.77 V LVI_A/D_SEL[3:0] = 0001b 1.89 1.95 2.01 V LVI_A/D_SEL[3:0] = 0010b 2.14 2.20 2.27 V LVI_A/D_SEL[3:0] = 0011b 2.38 2.45 2.53 V LVI_A/D_SEL[3:0] = 0100b 2.62 2.71 2.79 V LVI_A/D_SEL[3:0] = 0101b 2.87 2.95 3.04 V LVI_A/D_SEL[3:0] = 0110b 3.11 3.21 3.31 V LVI_A/D_SEL[3:0] = 0111b 3.35 3.46 3.56 V LVI_A/D_SEL[3:0] = 1000b 3.59 3.70 3.81 V LVI_A/D_SEL[3:0] = 1001b 3.84 3.95 4.07 V LVI_A/D_SEL[3:0] = 1010b 4.08 4.20 4.33 V LVI_A/D_SEL[3:0] = 1011b 4.32 4.45 4.59 V LVI_A/D_SEL[3:0] = 1100b 4.56 4.70 4.84 V LVI_A/D_SEL[3:0] = 1101b 4.83 4.98 5.13 V LVI_A/D_SEL[3:0] = 1110b 5.05 5.21 5.37 V LVI_A/D_SEL[3:0] = 1111b 5.30 5.47 5.63 V HVI Trip voltage 5.57 5.75 5.92 V Table 11-70. Voltage Monitors AC Specifications Parameter Description Conditions Min Typ Max Units LVI_tr[79] Response time – – 1 µs Notes 78.Based on device characterization (Not production tested). 79.This value is calculated, not measured. Document Number: 001-84935 Rev. *L Page 112 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.8.3 Interrupt Controller Table 11-71. Interrupt Controller AC Specifications Parameter Description Conditions Min Typ Max Units Delay from interrupt signal input to ISR – – 12 Tcy CPU code execution from main line code[80] Delay from interrupt signal input to ISR – – 6 Tcy CPU code execution from ISR code (tail-chaining)[80] 11.8.4 JTAG Interface Figure 11-74. JTAG Interface Timing (1/f_TCK) TCK T_TDI_setup T_TDI_hold TDI T_TDO_valid T_TDO_hold TDO T_TMS_setup T_TMS_hold TMS Table 11-72. JTAG Interface AC Specifications[81] Parameter Description Conditions Min Typ Max Units f_TCK TCK frequency 3.3V  V  5V – – 12[82] MHz DDD 1.71V  V < 3.3V – – 7[82] MHz DDD T_TDI_setup TDI setup before TCK high (T/10) – 5 – – ns T_TMS_setup TMS setup before TCK high T/4 – – T_TDI_hold TDI, TMS hold after TCK high T = 1/f_TCK max T/4 – – T_TDO_valid TCK low to TDO valid T = 1/f_TCK max – – 2T/5 T_TDO_hold TDO hold after TCK high T = 1/f_TCK max T/4 – – T_nTRST Minimum nTRST pulse width f_TCK = 2 MHz 8 – – ns Notes 80.ARM Cortex-M3 NVIC spec. Visit www.arm.com for detailed documentation about the Cortex-M3 CPU. 81.Based on device characterization (Not production tested). 82.f_TCK must also be no more than 1/3 CPU clock frequency. Document Number: 001-84935 Rev. *L Page 113 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.8.5 SWD Interface Figure 11-75. SWD Interface Timing (1/f_SWDCK) SWDCK T_SWDI_setup T_SWDI_hold SWDIO (PSoC input) T_SWDO_valid T_SWDO_hold SWDIO (PSoC output) Table 11-73. SWD Interface AC Specifications[83] Parameter Description Conditions Min Typ Max Units f_SWDCK SWDCLK frequency 3.3V  V  5V – – 12[84] MHz DDD 1.71V  V < 3.3V – – 7[84] MHz DDD 1.71V  V < 3.3V, SWD over – – 5.5[84] MHz DDD USBIO pins T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max T/4 – – T_SWDI_hold SWDIO input hold after SWDCK high T = 1/f_SWDCK max T/4 – – T_SWDO_valid SWDCK high to SWDIO output T = 1/f_SWDCK max – – T/2 T_SWDO_hold SWDIO output hold after SWDCK high T = 1/f_SWDCK max 1 – – ns 11.8.6 TPIU Interface Table 11-74. TPIU Interface AC Specifications[83] Parameter Description Conditions Min Typ Max Units TRACEPORT (TRACECLK) frequency – – 33[85] MHz SWV bit rate – – 33[85] Mbit Notes 83.Based on device characterization (Not production tested). 84.f_SWDCK must also be no more than 1/3 CPU clock frequency. 85.TRACEPORT signal frequency and bit rate are limited by GPIO output frequency, see Table 11-9 on page 76. Document Number: 001-84935 Rev. *L Page 114 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.9 Clocking Specifications are valid for –40 °C  T  105 °C and T  120 °C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. Unless otherwise specified, all charts and graphs show typical values. 11.9.1 Internal Main Oscillator Table 11-75. IMO DC Specifications[86] Parameter Description Conditions Min Typ Max Units Supply current 74.7 MHz – – 730 µA 62.6 MHz – – 600 µA 48 MHz – – 500 µA Icc_imo 24 MHz – USB mode With oscillator locking to USB bus – – 500 µA 24 MHz – non USB mode – – 300 µA 12 MHz – – 200 µA 6 MHz – – 180 µA 3 MHz – – 150 µA Figure 11-76. IMO Current vs. Frequency 700 600 500 A nt, μn 400 e urr 300 C 200 100 0 0 10 20 30 40 50 60 70 80 Frequency, MHz Note 86.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 115 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 11-76. IMO AC Specifications Parameter Description Conditions Min Typ Max Units IMO frequency stability (with factory trim) 74.7 MHz –7 – 7 % 62.6 MHz –7 – 7 % 48 MHz –5 – 5 % 24 MHz – Non USB mode –4 – 4 % 24 MHz – USB mode With oscillator locking to USB bus –0.25 – 0.25 % F [87] 12 MHz –3 – 3 % IMO 6 MHz –2 – 2 % 3 MHz 0 °C to 70 °C –1 – 1 % –40 °C to 105 °C –1.5 – 1.5 % 3 MHz frequency stability after typical Typical (non-optimized) board – ±2% – % PCB assembly post-reflow layout and 250 °C solder reflow. Device may be calibrated after assembly to improve performance. Tstart_imo Startup time[88] From enable (during normal system – – 13 µs operation) Jitter (peak to peak)[88] Jp–p F = 24 MHz – 0.9 – ns F = 3 MHz – 1.6 – ns Jitter (long term)[88] Jperiod F = 24 MHz – 0.9 – ns F = 3 MHz – 12 – ns Figure 11-77. IMO Frequency Variation vs. Temperature Figure 11-78. IMO Frequency Variation vs. V CC 0.5 62.6 MHz 24 MHz 0.25 3 MHz 00 n o ati ari V -0.25 % -0.5 -40 -20 0 20 40 60 80 100 Temperature, °C Notes 87.FIMO is measured after packaging, and thus accounts for substrate and die attach stresses. 88.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 116 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.9.2 Internal Low-Speed Oscillator Table 11-77. ILO DC Specifications Parameter Description Conditions Min Typ Max Units Operating current[89] F = 1 kHz – – 1.7 µA OUT I F = 33 kHz – – 2.6 µA CC OUT F = 100 kHz – – 2.6 µA OUT Leakage current[89] Power down mode – – 15 nA Table 11-78. ILO AC Specifications[90] Parameter Description Conditions Min Typ Max Units Tstart_ilo Startup time, all frequencies Turbo mode – – 2 ms ILO frequencies F 100 kHz 45 100 200 kHz ILO 1 kHz 0.5 1 2 kHz Figure 11-79. ILO Frequency Variation vs. Temperature Figure 11-80. ILO Frequency Variation vs. V DD 50 20 25 10 Variation 0 iationari 00 % % V 100 kHz 100 kHz -25 1 kHz -10 1 kHz -50 -20 -40 -20 0 20 40 60 80 100 1.5 2.5 3.5 4.5 5.5 Temperature, °C V , V DDD Notes 89.This value is calculated, not measured. 90.Based on device characterization (Not production tested). Document Number: 001-84935 Rev. *L Page 117 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 11.9.3 MHz External Crystal Oscillator For more information on crystal or ceramic resonator selection for the MHzECO, refer to application note AN54439: PSoC3 and PSoC5 External Oscillators. Table 11-79. MHzECO DC Specifications Parameter Description Conditions Min Typ Max Units I Operating current[91] 13.56 MHz crystal – 3.8 – mA CC Table 11-80. MHzECO AC Specifications Parameter Description Conditions Min Typ Max Units F Crystal frequency range 4 – 25 MHz 11.9.4 kHz External Crystal Oscillator Table 11-81. kHzECO DC Specifications[91] Parameter Description Conditions Min Typ Max Units I Operating current Low power mode; CL = 6pF – 0.25 1.0 µA CC DL Drive level – – 1 µW Table 11-82. kHzECO AC Specifications[91] Parameter Description Conditions Min Typ Max Units F Frequency – 32.768 – kHz T Startup time High power mode – 1 – s ON 11.9.5 External Clock Reference Table 11-83. External Clock Reference AC Specifications[91] Parameter Description Conditions Min Typ Max Units External frequency range 0 – 33 MHz Input duty cycle range Measured at V /2 30 50 70 % DDIO Input edge rate V to V 0.5 – – V/ns IL IH 11.9.6 Phase–Locked Loop Table 11-84. PLL DC Specifications Parameter Description Conditions Min Typ Max Units I PLL operating current In = 3 MHz, Out = 80 MHz – 650 – µA DD In = 3 MHz, Out = 67 MHz – 400 – µA In = 3 MHz, Out = 24 MHz – 200 – µA Table 11-85. PLL AC Specifications Parameter Description Conditions Min Typ Max Units Fpllin PLL input frequency[92] 1 – 48 MHz PLL intermediate frequency[93] Output of prescaler 1 – 3 MHz Fpllout PLL output frequency[92] 24 – 80 MHz Lock time at startup – – 250 µs Jperiod–rms Jitter (rms)[91] – – 250 ps Notes 91.Based on device characterization (Not production tested). 92.This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL. 93.PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16. Document Number: 001-84935 Rev. *L Page 118 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 12. Ordering Information In addition to the features listed in Table12-1, every CY8C56LP device includes: up to 256K flash, 64K SRAM, 2K EEPROM, a precision on–chip voltage reference, precision oscillators, flash, ECC, DMA, a fixed function I2C, JTAG/SWD programming and debug, external memory interface, boost, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C56LP derivatives incorporate device and flash security in user-selectable security levels; see the TRM for details. Table 12-1. CY8C56LP Family with ARM Cortex-M3 CPU MCU Core Analog Digital I/O[96] 4] 9 [s Part Number CPU Speed (MHz) Flash (KB) SRAM (KB) EEPROM (KB) LCD Segment Drive ADCs DAC Comparators SC/CT Analog BlockOpamps DFB CapSense [95]UDBs 16-bit Timer/PWM FS USB CAN 2.0b Total I/O GPIO SIO USBIO Package JTAG ID[97] CY8C5668AXI-LP010 67 256 64 2 ✔ 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ – 72 62 8 2 100-TQFP 0x2E10A069 CY8C5668AXI-LP013 67 256 64 2 ✔ 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ ✔ 72 62 8 2 100-TQFP 0x2E10D069 CY8C5668LTI-LP014 67 256 64 2 ✔ 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ – 48 38 8 2 68-QFN 0x2E10E069 CY8C5667AXI-LP006 67 128 32 2 ✔ 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ – 72 62 8 2 100-TQFP 0x2E106069 CY8C5667LTI-LP008 67 128 32 2 ✔ 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ – 48 38 8 2 68-QFN 0x2E108069 CY8C5667LTI-LP009 67 128 32 2 ✔ 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ ✔ 48 38 8 2 68-QFN 0x2E109069 CY8C5666AXI-LP001 67 64 16 2 ✔ 12-bit Del-Sig, 4 4 4 4 ✔ ✔ 20 4 – – 70 62 8 0 100-TQFP 0x2E101069 1x12-bit SAR CY8C5666AXI-LP004 67 64 16 2 ✔ 12-bit Del-Sig, 4 4 4 4 ✔ ✔ 20 4 ✔ – 72 62 8 2 100-TQFP 0x2E104069 1x12-bit SAR CY8C5666AXQ-LP004 67 64 16 2 ✔ 12-bit Del-Sig, 4 4 4 4 ✔ ✔ 20 4 ✔ – 72 62 8 2 100-TQFP 0x2E104069 1x12-bit SAR CY8C5666LTI-LP005 67 64 16 2 ✔ 12-bit Del-Sig, 4 4 4 4 ✔ ✔ 20 4 ✔ – 48 38 8 2 68-QFN 0x2E105069 1x12-bit SAR CY8C5667AXI-LP040 67 128 32 2 ✔ 12-bit Del-Sig, 4 4 4 4 ✔ ✔ 24 4 ✔ – 72 62 8 2 100-TQFP 0x2E128069 1x12-bit SAR CY8C5667AXQ-LP040 67 128 32 2 ✔ 12-bit Del-Sig, 4 4 4 4 ✔ ✔ 24 4 ✔ – 72 62 8 2 100-TQFP 0x2E128069 1x12-bit SAR CY8C5668AXI-LP034 67 256 64 2 ✔ 12-bit Del-Sig, 4 4 4 4 ✔ ✔ 24 4 ✔ – 72 62 8 2 100-TQFP 0x2E122069 1x12-bit SAR CY8C5667LTI-LP041 67 128 32 2 ✔ 12-bit Del-Sig, 4 4 4 4 ✔ ✔ 24 4 ✔ – 48 38 8 2 68-QFN 0x2E129069 1x12-bit SAR CY8C5688AXI-LP099 80 256 64 2 4 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ ✔ 72 62 8 2 100-TQFP 0x2E163069 CY8C5688LTI-LP086 80 256 64 2 4 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ – 48 38 8 2 68-QFN 0x2E156069 CY8C5688FNI-LP211 80 256 64 2 ✔ 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ ✔ 72 62 8 2 99-WLCSP 0x2E1D3069 Notes 94.Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 39 for more information on how analog blocks can be used. 95.UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 39 for more information on how UDBs can be used. 96.The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 32 for details on the functionality of each of these types of I/O. 97.The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID. Document Number: 001-84935 Rev. *L Page 119 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 12.1 Part Numbering Conventions PSoC 5LP devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9, A, B, …, Z) unless stated otherwise. CY8Cabcdefg-LPxxx a: Architecture ef: Package code 3: PSoC 3 Two character alphanumeric 5: PSoC 5 AX: TQFP b: Family group within architecture LT: QFN 2: CY8C52LP family PV: SSOP 4: CY8C54LP family FN: CSP 6: CY8C56LP family g: Temperature Range 8: CY8C58LP family C: Commercial c: Speed grade I: Industrial 6: 67 MHz Q: Extended 8: 80 MHz A: Automotive xxx: Peripheral set d: Flash capacity 5: 32 KB Three character numeric 6: 64 KB No meaning is associated with these three characters 7: 128 KB 8: 256 KB Examples CY8C 5 6 8 8 AX/PVI -LPx x x Cypress Prefix 5: PSoC 5 Architecture 6: CY8C56LP Family Family Group within Architecture 8: 80 MHz Speed Grade 8: 256 KB Flash Capacity AX: TQFP, PV: SSOP Package Code I: Industrial Temperature Range Peripheral Set Tape and reel versions of these devices are available and are marked with a "T" at the end of the part number. All devices in the PSoC 5LP CY8C56LP family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages. A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of life” requirements. Document Number: 001-84935 Rev. *L Page 120 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 13. Packaging Table 13-1. Package Characteristics Parameter Description Conditions Min Typ Max Units T Operating ambient temperature –40 25 105 °C A T Operating junction temperature –40 – 120 °C J T Package  (68-pin QFN) – 15 – °C/Watt JA JA T Package  (100-pin TQFP) – 34 – °C/Watt JA JA T Package  (68-pin QFN) – 13 – °C/Watt JC JC T Package  (100-pin TQFP) – 10 – °C/Watt JC JC T Operating ambient temperature For CSP parts –40 25 85 °C A T Operating junction temperature For CSP parts –40 – 100 °C J T Package  (99-ball CSP) 16.5 °C/Watt JA JA T Package  (99-ball CSP) – 0.1 – °C/Watt Jc JC Table 13-2. Solder Reflow Peak Temperature Maximum Peak Maximum Time at Package Temperature Peak Temperature 68-pin QFN 260 °C 30 seconds 100-pin TQFP 260 °C 30 seconds 99-pin CSP 255 °C 30 seconds Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 68-pin QFN MSL 3 100-pin TQFP MSL 3 99-pin CSP MSL 1 Document Number: 001-84935 Rev. *L Page 121 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 13-1. 68-pin QFN 8 × 8 with 0.4 mm Pitch Package Outline (Sawn Version) 001-09618 *E Figure 13-2. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline 51-85048 *J Document Number: 001-84935 Rev. *L Page 122 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Figure 2. WLCSP Package (5.192 × 5.940 × 0.6 mm) 001-88034 *B Document Number: 001-84935 Rev. *L Page 123 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 14. Acronyms Table 14-1. Acronyms Used in this Document (continued) Table 14-1. Acronyms Used in this Document Acronym Description FIR finite impulse response, see also IIR Acronym Description FPB flash patch and breakpoint abus analog local bus FS full-speed ADC analog-to-digital converter GPIO general-purpose input/output, applies to a PSoC AG analog global pin AHB AMBA (advanced microcontroller bus archi- HVI high-voltage interrupt, see also LVI, LVD tecture) high-performance bus, an ARM data transfer bus IC integrated circuit ALU arithmetic logic unit IDAC current DAC, see also DAC, VDAC AMUXBUS analog multiplexer bus IDE integrated development environment API application programming interface I2C, or IIC Inter-Integrated Circuit, a communications protocol APSR application program status register ARM® advanced RISC machine, a CPU architecture IIR infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO ATM automatic thump mode IMO internal main oscillator, see also ILO BW bandwidth INL integral nonlinearity, see also DNL CAN Controller Area Network, a communications protocol I/O input/output, see also GPIO, DIO, SIO, USBIO CMRR common-mode rejection ratio IPOR initial power-on reset CPU central processing unit IPSR interrupt program status register CRC cyclic redundancy check, an error-checking IRQ interrupt request protocol ITM instrumentation trace macrocell DAC digital-to-analog converter, see also IDAC, VDAC LCD liquid crystal display DFB digital filter block LIN Local Interconnect Network, a communications DIO digital input/output, GPIO with only digital protocol. capabilities, no analog. See GPIO. LR link register DMA direct memory access, see also TD LUT lookup table DNL differential nonlinearity, see also INL LVD low-voltage detect, see also LVI DNU do not use LVI low-voltage interrupt, see also HVI DR port write data registers LVTTL low-voltage transistor-transistor logic DSI digital system interconnect MAC multiply-accumulate DWT data watchpoint and trace MCU microcontroller unit ECC error correcting code MISO master-in slave-out ECO external crystal oscillator NC no connect EEPROM electrically erasable programmable read-only NMI nonmaskable interrupt memory NRZ non-return-to-zero EMI electromagnetic interference NVIC nested vectored interrupt controller EMIF external memory interface NVL nonvolatile latch, see also WOL EOC end of conversion opamp operational amplifier EOF end of frame PAL programmable array logic, see also PLD EPSR execution program status register PC program counter ESD electrostatic discharge PCB printed circuit board ETM embedded trace macrocell PGA programmable gain amplifier Document Number: 001-84935 Rev. *L Page 124 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Table 14-1. Acronyms Used in this Document (continued) Table 14-1. Acronyms Used in this Document (continued) Acronym Description Acronym Description PHUB peripheral hub TIA transimpedance amplifier PHY physical layer TRM technical reference manual PICU port interrupt control unit TTL transistor-transistor logic PLA programmable logic array TX transmit PLD programmable logic device, see also PAL UART Universal Asynchronous Transmitter Receiver, a communications protocol PLL phase-locked loop UDB universal digital block PMDD package material declaration datasheet USB Universal Serial Bus POR power-on reset USBIO USB input/output, PSoC pins used to connect to PRES precise low-voltage reset a USB port PRS pseudo random sequence VDAC voltage DAC, see also DAC, IDAC PS port read data register WDT watchdog timer PSoC® Programmable System-on-Chip™ WOL write once latch, see also NVL PSRR power supply rejection ratio WRES watchdog timer reset PWM pulse-width modulator XRES external reset pin RAM random-access memory XTAL crystal RISC reduced-instruction-set computing RMS root-mean-square RTC real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC/CT switched capacitor/continuous time SCL I2C serial clock SDA I2C serial data S/H sample and hold SIO special input/output, GPIO with advanced features. See GPIO. SNR signal-to-noise ratio SOC start of conversion SOF start of frame SPI Serial Peripheral Interface, a communications protocol SR slew rate SRAM static random access memory SRES software reset SWD serial wire debug, a test protocol SWV single-wire viewer TD transaction descriptor, see also DMA THD total harmonic distortion Document Number: 001-84935 Rev. *L Page 125 of 131

® PSoC 5LP: CY8C56LP Family Datasheet 15. Document Conventions 15.1 Units of Measure Table 15-1. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohours kHz kilohertz k kilohms ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz M megaohms Msps megasamples per second µA microamperes µF microfarads µH microhenrys µs microseconds µV microvolts µW microwatts mA milliamperes ms milliseconds mV millivolts nA nanoamperes ns nanoseconds nV nanovolts  ohms pF picofarads ppm parts per million ps picoseconds s seconds sps samples per second sqrtHz square root of hertz V volts Document Number: 001-84935 Rev. *L Page 126 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Document History Page Description Title: PSoC® 5LP: CY8C56LP Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-84935 Orig. of Submission Revision ECN Description of Change Change Date ** 3825653 MKEA 12/07/2012 Datasheet for new CY8C56LP family. *A 3897878 MKEA 02/07/2013 Removed Preliminary status. Updated characterization footnotes in Electrical Specifications. Changed number of opamps in Ordering Information Updated conditions for SAR ADC INL and DNL specifications in Table11-24 Updated Table11-78 (ILO AC Specifications). Changed “UDB Configuration" to "UDB Working Registers” in Table5-5. Removed references to CAN. Updated VIDAC INL spec. *B 3902085 MKEA 02/12/2013 Changed Hibernate wakeup time from 125 µs to 200 µs in Table6-3 and Table11-3. *C 3917994 MKEA 01/08/2013 Added Controller Area Network (CAN) content. Added CY8C5667AXI-LP040, CY8C5668AXI-LP034, and CY8C5667LTI-LP041 parts in Ordering Information. *D 4114902 MKEA 09/30/2013 Added information about 1 KB cache in Features. Added warning on reset devices in the EEPROM section. Added DBGEN field in Table5-3. Deleted statement about repeat start from the I2C section. Removed T spec from Table11-1 and added a note clarifying the maximum STG storage temperature range. Updated chip Idd, regulator, opamp, delta-sigma ADC, SAR ADC, IDAC, and VDAC graphs. Added min and max values for the Regulator Output Capacitor parameter. Updated C specs in GPIO DC Specifications and SIO DC Specifications. IN Updated rise and fall time specs in Fast Strong mode in Table11-9, and deleted related graphs. Added I parameter in Opamp DC Specifications IB Updated Vos spec conditions and changed TCVos max value from 0.55 to 1 in Table11-20. Updated Voltage Reference Specifications and IMO AC Specifications. Updated F spec (3 MHz). IMO Updated 100-TQFP package diagram. Added Appendix for CSP package (preliminary). *E 4225729 MKEA 12/24/2013 Added SIO Comparator Specifications. Changed THIBERNATE wakeup spec from 200 to 150 µs. Updated CSP package details and ordering information. Added 80 MHz parts in Table 12-1. *F 4386988 MKEA 05/22/2014 Updated General Description and Features. Added More Information and PSoC Creator sections. Updated JTAG IDs in Ordering Information. Updated 100-TQFP package diagram. *G 4587100 MKEA 12/08/2014 Added link to AN72845 in Note 3. Updated interrupt priority numbers in Section4.4. Updated Section5.4 to clarify the factory default values of EEPROM. Corrected ECCEN settings in Table5-3. Updated Section6.1.1 and Section6.1.2. Added a note below Figure6-4. Updated Figure6-12. Changed ‘Control Store RAM’ to ‘Dynamic Configuration RAM’ in Figure7-4 and changed Section7.2.2.2 heading to ‘Dynamic Configuration RAM’. Updated Section7.8. Document Number: 001-84935 Rev. *L Page 127 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Document History Page (continued) Description Title: PSoC® 5LP: CY8C56LP Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-84935 Orig. of Submission Revision ECN Description of Change Change Date *H 4698847 AVER / 03/24/2015 Updated Features: MKEA / Added “Extended temperature parts: –40 to 105 °C” as indented under GJV “Temperature range (ambient)” under “Operating characteristics”. Updated System Integration: Updated Power System: Updated Boost Converter: Updated entire section. Updated Electrical Specifications: Replaced “Specifications are valid for –40 °C ≤ T ≤ 85 °C and T ≤ 100 °C, A J except where noted.” with “Specifications are valid for –40 °C ≤ T ≤ 105 °C A and T ≤ 120 °C, except where noted.” in all instances. J Updated Device Level Specifications: Updated Table11-2: Added details of I parameter corresponding to “T = 105 °C”. DD Updated Figure11-3 and Figure11-4. Updated Power Regulators: Updated Inductive Boost Regulator: Updated Table11-6: Updated details of V , I , V , Reg , Reg parameters. BAT OUT OUT LOAD LINE Removed V : V parameter and its details. OUT BAT Removed Table “Inductive Boost Regulator AC Specifications”. Updated Table11-7: Updated details of L , C parameters. BOOST BOOST Added C parameter and its details. BAT Added Figure11-8, Figure11-9, Figure11-10, Figure11-11, Figure11-12, Figure11-13, Figure11-14. Removed Figure “Efficiency vs I V = 3.3 V, L = 10 μH”. OUT BOOST BOOST Removed Figure “Efficiency vs I V = 3.3 V, L = 22 μH”. OUT BOOST BOOST Updated Analog Peripherals: Updated Opamp: Updated Figure11-26. Updated Voltage Reference: Updated Table11-23: Added details of V parameter corresponding to condition “105 °C”. REF Updated Figure11-34. Updated Current Digital-to-analog Converter (IDAC): Updated Figure11-46, Figure11-47, Figure11-48, Figure11-49, Figure11-50, Figure11-51. Updated Voltage Digital to Analog Converter (VDAC): Updated Figure11-58, Figure11-59, Figure11-60, Figure11-61, Figure11-62, Figure11-63. Updated Programmable Gain Amplifier: Updated Table11-39: Added details of BW1 parameter corresponding to condition “T ≤ 105 °C”. A Updated Figure11-69. Updated Temperature Sensor: Updated Table11-40: Replaced 85 °C with 105 °C. Document Number: 001-84935 Rev. *L Page 128 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Document History Page (continued) Description Title: PSoC® 5LP: CY8C56LP Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-84935 Orig. of Submission Revision ECN Description of Change Change Date *H (cont.) 4698847 AVER / 03/24/2015 Updated Electrical Specifications: MKEA / Updated Memory: GJV Updated Flash: Updated Table11-58: Updated details in “Conditions” column corresponding to “Flash data retention time” parameter. Added Note 72 and referred the same note in last condition corresponding to “Flash data retention time” parameter. Updated EEPROM: Updated Table11-60: Updated details in “Conditions” column corresponding to “EEPROM data retention time” parameter. Added Note 72 and referred the same note in last condition corresponding to “EEPROM data retention time” parameter. Updated Nonvolatile Latches (NVL): Updated Table11-62: Updated details in “Conditions” column corresponding to “NVL data retention time” parameter. Added Note 73 and referred the same note in last condition corresponding to “NVL data retention time” parameter. Updated Clocking: Updated Internal Main Oscillator: Updated Table11-76: Replaced 85 °C with 105 °C. Updated Figure11-78. Updated Ordering Information: Updated Part Numbering Conventions: Added “Q: Extended” as sub bullet under “g: Temperature Range”. Updated Packaging: Updated Table13-1: Changed maximum value of TA parameter from 85 °C to 105 °C. Changed maximum value of T parameter from 100 °C to 120 °C. J Updated : Updated : spec 001-88034 – Changed revision from ** to *A. *I 4839323 MKEA 07/15/2015 Added reference to code examples in More Information. Updated typ value of T from 2 to 10 in EEPROM AC specs table. WRITE Changed “Device supply for USB operation" to "Device supply (V ) for USB DDD operation" in USB DC Specifications. Clarified power supply sequencing and margin for V and V . DDA DDD Updated Serial Wire Debug Interface with limitations of debugging on Port 15. Updated Delta-sigma ADC DC Specifications Document Number: 001-84935 Rev. *L Page 129 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Document History Page (continued) Description Title: PSoC® 5LP: CY8C56LP Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-84935 Orig. of Submission Revision ECN Description of Change Change Date *J 5030641 MKEA 11/30/2015 Added Table2-1. Removed the configurable XRES information. Updated Section5.6 Updated Section6.3.1.1. Updated values for DSI Fmax, Fgpioin max, and Fsioin max. Corrected the web link for the PSoC 5 Device Programming Specifications in Section9. Updated CSP Package Bootloader section. Added MHzECO DC Specifications. Updated 99-WLCSP and 100-pin TQFP package drawings. Added a footnote reference for the "CY8C5287AXI-LP095" part in Table12-1 clarifying that it has 256 KB flash. Added the CY8C5667AXQ-LP040 part in Table12-1. *K 5478402 MKEA 10/25/2016 Updated More Information. Add Links to CAD Libraries in Section2. Corrected typos in External Electrical Connections. *L 5703770 GNKK 04/20/2017 Updated the Cypress logo and copyright information. Document Number: 001-84935 Rev. *L Page 130 of 131

® PSoC 5LP: CY8C56LP Family Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions ARM® Cortex® Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Forums | WICED IOT Forums | Projects | Video | Blogs | Interface cypress.com/interface Training | Components Internet of Things cypress.com/iot Technical Support Memory cypress.com/memory cypress.com/support Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless © Cypress Semiconductor Corporation, 2012-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-84935 Rev. *L Revised April 20, 2017 Page 131 of 131

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: C ypress Semiconductor: CY8C5868LTI-LP038 CY8C5868LTI-LP039 CY8C5868AXI-LP032 CY8C5867LTI-LP025 CY8C5667AXI-LP040 CY8C5668AXI-LP034 CY8C5667LTI-LP041 CY8C5666AXQ-LP004 CY8C5688FNI-LP211T CY8C5667AXQ-LP040