® PSoC 3: CY8C38 Family Datasheet ® Programmable System-on-Chip (PSoC ) General Description PSoC® 3 is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a microcontroller on a single chip. The PSoC 3 architecture boosts performance through: 8051 core plus DMA controller and digital filter processor, at up to 67 MHz Ultra low power with industry's widest voltage range Programmable digital and analog peripherals enable custom functions Flexible routing of any analog or digital peripheral function to any pin PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality. Features Operating characteristics Analog peripherals Voltage range: 1.71 to 5.5 V, up to six power domains Configurable 8- to 20-bit delta-sigma ADC Temperature range (ambient) –40 to 85 °C[1] Up to four 8-bit DACs DC to 67-MHz operation Up to four comparators Power modes Up to four opamps • Active mode 1.2 mA at 6 MHz, and 12 mA at 48 MHz Up to four programmable analog blocks, to create: • 1-µA sleep mode • Programmable gain amplifier (PGA) • 200-nA hibernate mode with RAM retention • Transimpedance amplifier (TIA) Boost regulator from 0.5-V input up to 5-V output • Mixer • Sample and hold circuit Performance 8-bit 8051 CPU, 32 interrupt inputs CapSense® support, up to 62 sensors 24-channel direct memory access (DMA) controller 1.024 V ±0.1% internal voltage reference 24-bit 64-tap fixed-point digital filter processor (DFB) Versatile I/O system Memories 29 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs) Up to 64 KB program flash, with cache and security features Up to eight performance I/O (SIO) pins • 25 mA current sink Up to 8 KB additional flash for error correcting code (ECC) Up to 8 KB RAM • Programmable input threshold and output high voltages Up to 2 KB EEPROM • Can act as a general-purpose comparator • Hot swap capability and overvoltage tolerance Digital peripherals Two USBIO pins that can be used as GPIOs FI2oCu, r1 1 M6-bbpits t ibmuesr ,s cpoeuendter, and PWM (TCPWM) blocks RLCoDut ed iarencyt ddirgivitea l foror man aanloyg G pPeIrOip,h uepr atol t o4 6a n×y 1 G6 PseIOgments UinSteBrf a2c.0e c(TeIrDtif#ie4d0 7F7u0ll-0S5p3e) euds i(nFgS i)n 1te2r nMabl poss cpilelaritpohr[e2r]al CapSense support from any GPIO 1.2-V to 5.5-V interface voltages, up to four power domains Full CAN 2.0b, 16 Rx, 8 Tx buffers 16 to 24 universal digital blocks (UDB), programmable to Programming and debug create any number of functions: JTAG (4-wire), serial wire debug (SWD) (2-wire), and single • 8-, 16-, 24-, and 32-bit timers, counters, and PWMs wire viewer (SWV) interfaces • I2C, UART, SPI, I2S, LIN 2.0 interfaces Bootloader programming through I2C, SPI, UART, USB, and other interfaces • Cyclic redundancy check (CRC) • Pseudo random sequence (PRS) generators Package options: 48-pin SSOP, 48-pin QFN, 68-pin QFN, • Quadrature decoders 100-pin TQFP, and 72-pin WLCSP • Gate-level logic functions Development support with free PSoC Creator™ tool Programmable clocking Schematic and firmware design support 3- to 62-MHz internal oscillator, 1% accuracy at 3 MHz Over 100 PSoC Components™ integrate multiple ICs and 4- to 25-MHz external crystal oscillator system interfaces into one PSoC. Components are free embedded ICs represented by icons. Drag and drop Internal PLL clock generation up to 67 MHz component icons to design systems in PSoC Creator. Low-power internal oscillator at 1, 33, and 100 kHz 32.768-kHz external watch crystal oscillator Includes free Keil 8051 compiler 12 clock dividers routable to any peripheral or I/O Supports device programming and debugging Notes 1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. This feature on select devices only. See Ordering Information on page 123 for details. CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-11729 Rev. AG Revised April 27, 2017

® PSoC 3: CY8C38 Family Datasheet More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 3: Overview: PSoC Portfolio, PSoC Roadmap Development Kits: Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC5LP CY8CKIT-030 is designed for analog performance, for devel- oping high-precision analog, low-power, and low-voltage ap- In addition, PSoC Creator includes a device selection tool. plications. Application notes: Cypress offers a large number of PSoC CY8CKIT-001 provides a common development platform for application notes and code examples covering a broad range any one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP of topics, from basic to advanced level. Recommended appli- families of devices. cation notes for getting started with PSoC3 are: The MiniProg3 device provides an interface for flash pro- AN54181: Getting Started With PSoC 3 gramming and debug. AN61290: Hardware Design Considerations Technical Reference Manuals (TRM) AN57821: Mixed Signal Circuit Board Layout Architecture TRM AN58304: Pin Selection for Analog Designs Registers TRM AN81623: Digital Design Best Practices Programming Specification AN73854: Introduction To Bootloaders PSoC Creator PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100 pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can: 1.Drag and drop component icons to build your hardware 3.Configure components using the configuration tools system design in the main design workspace 4.Explore the library of 100+ components 2.Codesign your application firmware with the PSoC hardware, 5.Review component datasheets using the PSoC Creator IDE C compiler Figure 1. Multiple-Sensor Example Project in PSoC Creator Document Number: 001-11729 Rev. AG Page 2 of 140

® PSoC 3: CY8C38 Family Datasheet Contents 1. Architectural Overview .....................................................4 9. Programming, Debug Interfaces, Resources ................65 2. Pinouts ...............................................................................6 9.1 JTAG Interface .........................................................65 9.2 Serial Wire Debug Interface .....................................67 3. Pin Descriptions ..............................................................12 9.3 Debug Features ........................................................68 4. CPU ...................................................................................13 9.4 Trace Features .........................................................68 4.1 8051 CPU .................................................................13 9.5 Single Wire Viewer Interface ....................................68 4.2 Addressing Modes ....................................................13 9.6 Programming Features .............................................68 4.3 Instruction Set ..........................................................14 9.7 Device Security ........................................................68 4.4 DMA and PHUB .......................................................18 9.8 CSP Package Bootloader .........................................69 4.5 Interrupt Controller ...................................................19 10. Development Support ...................................................70 5. Memory .............................................................................23 10.1 Documentation .......................................................70 5.1 Static RAM ...............................................................23 10.2 Online .....................................................................70 5.2 Flash Program Memory ............................................23 10.3 Tools .......................................................................70 5.3 Flash Security ...........................................................23 11. Electrical Specifications ...............................................71 5.4 EEPROM ..................................................................23 11.1 Absolute Maximum Ratings ....................................71 5.5 Nonvolatile Latches (NVLs) ......................................24 11.2 Device Level Specifications ....................................72 5.6 External Memory Interface .......................................25 11.3 Power Regulators ...................................................76 5.7 Memory Map ............................................................26 11.4 Inputs and Outputs .................................................80 6. System Integration ..........................................................28 11.5 Analog Peripherals .................................................88 6.1 Clocking System .......................................................28 11.6 Digital Peripherals ................................................108 6.2 Power System ..........................................................31 11.7 Memory ................................................................112 6.3 Reset ........................................................................35 11.8 PSoC System Resources .....................................116 6.4 I/O System and Routing ...........................................37 11.9 Clocking ................................................................119 7. Digital Subsystem ...........................................................44 12. Ordering Information ...................................................123 7.1 Example Peripherals ................................................44 12.1 Part Numbering Conventions ...............................124 7.2 Universal Digital Block ..............................................46 13. Packaging .....................................................................125 7.3 UDB Array Description .............................................49 7.4 DSI Routing Interface Description ............................49 14. Acronyms .....................................................................129 7.5 CAN ..........................................................................51 15. Reference Documents .................................................130 7.6 USB ..........................................................................53 16. Document Conventions ..............................................131 7.7 Timers, Counters, and PWMs ..................................53 16.1 Units of Measure ..................................................131 7.8 I2C ............................................................................54 17. Revision History .........................................................132 7.9 Digital Filter Block .....................................................56 18. Sales, Solutions, and Legal Information ...................140 8. Analog Subsystem ..........................................................56 Worldwide Sales and Design Support.......................... 140 8.1 Analog Routing .........................................................57 Products....................................................................... 140 8.2 Delta-sigma ADC ......................................................59 PSoC® Solutions......................................................... 140 8.3 Comparators .............................................................60 Cypress Developer Community.................................... 140 8.4 Opamps ....................................................................61 Technical Support........................................................ 140 8.5 Programmable SC/CT Blocks ..................................61 8.6 LCD Direct Drive ......................................................62 8.7 CapSense .................................................................63 8.8 Temp Sensor ............................................................63 8.9 DAC ..........................................................................64 8.10 Up/Down Mixer .......................................................64 8.11 Sample and Hold ....................................................64 Document Number: 001-11729 Rev. AG Page 3 of 140

® PSoC 3: CY8C38 Family Datasheet 1. Architectural Overview Introducing the CY8C38 family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C38 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure 1-1. Simplified Block Diagram Analog Interconnect Digital Interconnect S PIOs SRyessteomur Wceisde Universal Digital Block Array D(2i4g xi UtaDlB S)ystem CAN I2C IO 43(2tO(o.7Op62p8t5it oiMoKnnHaHa)lzz)l GPIOsG OIXMtsaOcl Clock Tree Usage Example for UDB 8IT2-iCbm iSteUUU UlraDDDDvBBBBeQuadratu8r-eb iDtUUUU SeDDDDcPBBBBoIder Sequencer1L2o-gbUUUiUictDDD DSBBBBP1PI6W-bMit 18T6-ib-mbiteUUUiU tr DDDDPBBBBRLSogic UUUUDDDDBBBB UUUUDDDDBBBB CPTo4Wium xnMet2re. r0 FMSSa2l asU.v0teeSr/B UPHSGPIOBY 22  UART 12-bit PWM s RTC Timer System Bus Memory System CPU System Program & G P WDT Debug IO and 8051 or Interrupt s Wake EEPROM SRAM Cortex M3C PU Controller Program GPIOs EMIF FLASH PHUB BDoeTubrnuadgcae &ry ILO DMA Scan Clocking System G Analog System P SIOs PoweSry Mstaenmagement LCDD Driivreect DBFiilgloticetakrl ADC 4 x + IOs POR and Opamp 3 per LVD - Opamp 4 x SC/CT Blocks Sleep (TIA, PGA, Mixer etc) Power 1 x 1.71 toV5.5V 1.8V LDO TemSpeenrsaoturre 4 x DAC DAeDl CSig C4M xP +- GPIOs SMP CapSense 0.5 Vto 5.5V (Optiona)l Figure1-1 illustrates the major components of the CY8C38 PSoC’s digital subsystem provides half of its unique family. They are: configurability. It connects a digital signal from any peripheral to any pin through the digital system interconnect (DSI). It also 8051 CPU subsystem provides functional flexibility through an array of small, fast, Nonvolatile subsystem low-power UDBs. PSoC Creator provides a library of prebuilt and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, Programming, debug, and test subsystem timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. You can also easily create a digital circuit using Inputs and outputs boolean primitives by means of graphical design entry. Each Clocking UDB contains programmable array logic (PAL)/programmable logic device (PLD) functionality, together with a small state Power machine engine to support a wide variety of peripherals. Digital subsystem In addition to the flexibility of the UDB array, PSoC also provides configurable digital blocks targeted at specific functions. For the Analog subsystem CY8C38 family these blocks can include four 16-bit timers, counters, and PWM blocks; I2C slave, master, and multimaster; FS USB; and Full CAN 2.0b. Document Number: 001-11729 Rev. AG Page 4 of 140

® PSoC 3: CY8C38 Family Datasheet For more details on the peripherals see the “Example PSoC’s 8051 CPU subsystem is built around a single cycle Peripherals” section on page44 of this data sheet. For pipelined 8051 8-bit processor running at up to 67 MHz. The information on UDBs, DSI, and other digital blocks, see the CPU subsystem includes a programmable nested vector “Digital Subsystem” section on page44 of this data sheet. interrupt controller, DMA controller, and RAM. PSoC’s nested vector interrupt controller provides low latency by allowing the PSoC’s analog subsystem is the second half of its unique CPU to vector directly to the first address of the interrupt service configurability. All analog performance is based on a highly routine, bypassing the jump instruction required by other accurate absolute voltage reference with less than 0.1-percent architectures. The DMA controller enables peripherals to error over temperature and voltage. The configurable analog exchange data without CPU involvement. This allows the CPU subsystem includes: to run slower (saving power) or use those CPU cycles to improve Analog muxes the performance of firmware algorithms. The single cycle 8051 Comparators CPU runs ten times faster than a standard 8051 processor. The processor speed itself is configurable, allowing you to tune active Voltage references power consumption for specific applications. Analog-to-digital converter (ADC) PSoC’s nonvolatile subsystem consists of flash, byte-writeable Digital-to-analog converters (DACs) EEPROM, and nonvolatile configuration options. It provides up Digital filter block (DFB) to 64 KB of on-chip flash. The CPU can reprogram individual All GPIO pins can route analog signals into and out of the device blocks of flash, enabling bootloaders. You can enable an error using the internal analog bus. This allows the device to interface correcting code (ECC) for high reliability applications. A powerful up to 62 discrete analog signals. The heart of the analog and flexible protection model secures the user's sensitive subsystem is a fast, accurate, configurable delta-sigma ADC information, allowing selective memory block locking for read with these features: and write protection. Up to 2 KB of byte-writeable EEPROM is available on-chip to store application data. Additionally, selected Less than 100 µV offset configuration options such as boot speed and pin drive mode are A gain error of 0.2 percent stored in nonvolatile memory. This allows settings to activate INL less than ±2 LSB immediately after POR. DNL less than ±1 LSB The three types of PSoC I/O are extremely flexible. All I/Os have many drive modes that are set at POR. PSoC also provides up SINAD better than 84 dB in 16-bit mode to four I/O voltage domains through the VDDIO pins. Every GPIO This converter addresses a wide variety of precision analog has analog I/O, LCD drive[3], CapSense[4], flexible interrupt applications, including some of the most demanding sensors. generation, slew rate control, and digital I/O capability. The SIOs The output of the ADC can optionally feed the programmable on PSoC allow V to be set independently of Vddio when used OH DFB through the DMA without CPU intervention. You can as outputs. When SIOs are in input mode they are high configure the DFB to perform IIR and FIR digital filters and impedance. This is true even when the device is not powered or several user-defined custom functions. The DFB can implement when the pin voltage goes above the supply voltage. This makes filters with up to 64 taps. It can perform a 48-bit the SIO ideally suited for use on an I2C bus where the PSoC may multiply-accumulate (MAC) operation in one clock cycle. not be powered when other devices on the bus are. The SIO pins Four high-speed voltage or current DACs support 8-bit output also have high current sink capability for applications such as signals at an update rate of up to 8 Msps. They can be routed LED drives. The programmable input threshold feature of the out of any GPIO pin. You can create higher resolution voltage SIO can be used to make the SIO function as a general purpose PWM DAC outputs using the UDB array. This can be used to analog comparator. For devices with Full-Speed USB the USB create a pulse width modulated (PWM) DAC of up to 10 bits, at physical interface is also provided (USBIO). When not using up to 48 kHz. The digital DACs in each UDB support PWM, PRS, USB these pins may also be used for limited digital functionality or delta-sigma algorithms with programmable widths. In addition and device programming. All of the features of the PSoC I/Os are to the ADC, DACs, and DFB, the analog subsystem provides covered in detail in the “I/O System and Routing” section on multiple: page37 of this data sheet. Uncommitted opamps The PSoC device incorporates flexible internal clock generators, Configurable switched capacitor/continuous time (SC/CT) designed for high stability and factory trimmed for high accuracy. The internal main oscillator (IMO) is the clock base for the blocks. These support: system, and has 1-percent accuracy at 3 MHz. The IMO can be Transimpedance amplifiers configured to run from 3 MHz up to 62 MHz. Multiple clock Programmable gain amplifiers derivatives can be generated from the main clock frequency to Mixers meet application needs. The device provides a PLL to generate Other similar analog components clock frequencies up to 67 MHz from the IMO, external crystal, See the “Analog Subsystem” section on page56 of this data or external reference clock. sheet for more details. Notes 3. This feature on select devices only. See Ordering Information on page 123 for details. 4. GPIOs with opamp outputs are not recommended for use with CapSense. Document Number: 001-11729 Rev. AG Page 5 of 140

® PSoC 3: CY8C38 Family Datasheet It also contains a separate, very low-power internal low-speed 2. Pinouts oscillator (ILO) for the sleep and watchdog timers. A 32.768-kHz external watch crystal is also supported for use in real-time Each VDDIO pin powers a specific set of I/O pins. (The USBIOs clock(RTC) applications. The clocks, together with are powered from VDDD.) Using the VDDIO pins, a single PSoC programmable clock dividers, provide the flexibility to integrate can support multiple voltage levels, reducing the need for most timing requirements. off-chip level shifters. The black lines drawn on the pinout diagrams in Figure2-3 through Figure2-6, as well as Table2-1, The CY8C38 family supports a wide supply operating range from 1.71 V to 5.5V. This allows operation from regulated supplies show the pins that are powered by each VDDIO. such as 1.8 V ± 5%, 2.5V ±10%, 3.3V ± 10%, or 5.0 V ± 10%, Each VDDIO may source up to 100 mA total to its associated I/O or directly from a wide range of battery types. In addition, it pins, as shown in Figure2-1. provides an integrated high efficiency synchronous boost converter that can power the device from supply voltages as low Figure 2-1. VDDIO Current Limit as 0.5V. This enables the device to be powered directly from a single battery or solar cell. In addition, you can use the boost IDDIO X= 100 mA converter to generate other voltages required by the device, such as a 3.3-V supply for LCD glass drive. The boost’s output is available on the VBOOST pin, allowing other devices in the VDDIO X I/O Pins application to be powered from the PSoC. PSoC supports a wide range of low-power modes. These include a 200-nA hibernate mode with RAM retention and a 1-µA sleep PSoC mode with RTC. In the second mode, the optional 32.768-kHz watch crystal runs continuously and maintains an accurate RTC. Power to all major functional blocks, including the programmable digital and analog peripherals, can be controlled independently by firmware. This allows low-power background processing when some peripherals are not in use. This, in turn, provides a total device current of only 1.2 mA when the CPU is running at 6MHz, or 0.8 mA running at 3 MHz. Conversely, for the 100-pin and 68-pin devices, the set of I/O The details of the PSoC power modes are covered in the “Power pins associated with any VDDIO may sink up to 100 mA total, as System” section on page31 of this data sheet. shown in Figure2-2. PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for programming, debug, and test. The 1-wire SWV may also be Figure 2-2. I/O Pins Current Limit used for ‘printf’ style debugging. By combining SWD and SWV, Ipins = 100 mA you can implement a full debugging interface with just three pins. Using these standard interfaces you can debug or program the PSoC with a variety of hardware solutions from Cypress or third party vendors. PSoC supports on-chip break points and 4-KB VDDIO X instruction and data race memory for debug. Details of the I/O Pins programming, test, and debugging interfaces are discussed in the “Programming, Debug Interfaces, Resources” section on page65 of this data sheet. PSoC VSSD For the 48-pin devices, the set of I/O pins associated with VDDIO0 plus VDDIO2 may sink up to 100 mA total. The set of I/O pins associated with VDDIO1 plus VDDIO3 may sink up to a total of 100 mA. Document Number: 001-11729 Rev. AG Page 6 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 2-3. 48-pin SSOP Part Pinout (SIO) P12[2] 1 48 VDDA (SIO) P12[3] 2 47 VSSA (Opamp2OUT, GPIO) P0[0] 3 Lines show 46 VCCA VDDIO to I/O (Opamp0OUT, GPIO) P0[1] 4 45 P15[3] (GPIO, KHZ XTAL: XI) supply (Opamp0+, GPIO) P0[2] 5 association 44 P15[2] (GPIO, KHZ XTAL: XO) (Opamp0-/Extref0, GPIO) P0[3] 6 43 P12[1] (SIO, I2C1: SDA) VDDIO0 7 42 P12[0] (SIO, I2C1: SCL) (Opamp2+, GPIO) P0[4] 8 41 VDDIO3 (Opamp2-, GPIO) P0[5] 9 40 P15[1] (GPIO, MHZ XTAL: XI) (IDAC0, GPIO) P0[6] 10 39 P15[0] (GPIO, MHZ XTAL: XO) (IDAC2, GPIO) P0[7] 11 38 VCCD VCCD 12 SSOP 37 VSSD VSSD 13 36 VDDD [5] VDDD 14 35 P15[7] (USBIO, D-, SWDCK) [5] (GPIO) P2[3] 15 34 P15[6] (USBIO, D+, SWDIO) (GPIO) P2[4] 16 33 P1[7] (GPIO) VDDIO2 17 32 P1[6] (GPIO) (GPIO) P2[5] 18 31 VDDIO1 (GPIO) P2[6] 19 30 P1[5] (GPIO, nTRST) (GPIO) P2[7] 20 29 P1[4] (GPIO, TDI) VSSB 21 28 P1[3] (GPIO, TDO, SWV) IND 22 27 P1[2] (GPIO, ConfigurableXRES) VBOOST 23 26 P1[1] (GPIO, TCK, SWDCK) VBAT 24 25 P1[0] (GPIO, TMS, SWDIO) Figure 2-4. 48-pin QFN Part Pinout[6] O) O) P2[5] (GPIO)VDDIO2 P2[4] (GPIO) P2[3] (GPIO) VDDDVSSD VCCDP0[7] (IDAC2, GPIO) P0[6] (IDAC0, GPIO)P0[5] (Opamp2-, GPI P0[4] (Opamp2+, GPI VDDIO0 (GPIO) P2[6] 148 47 464544 43 42 414039 383736 P0[3] (Opamp0-/Extref0, GPIO) (GPIO) P2[7] 2 35 P0[2] (Opamp0+, GPIO) Lines show VSSB 3 VDDIO to I/O 34 P0[1] (Opamp0OUT, GPIO) IND 4 supply association 33 P0[0] (Opamp2OUT, GPIO) VBOOST 5 32 P12[3] (SIO) VBAT 6 QFN 31 P12[2] (SIO) (GPIO, TMS, SWDIO) P1[0] 7 (Top View) 30 VDDA (GPIO, TCK, SWDCK) P1[1] 8 29 VSSA (GPIO, Configurable XRES) P1[2] 9 28 VCCA (GPIO, TDO, SWV) P1[3] 10 27 P15[3] (GPIO, KHZ XTAL: XI) (GPIO, TDI) P1[4] 11 26 P15[2] (GPIO, KHZ XTAL: XO) (GPIO, nTRST) P1[5] 121314 1516 171819202122232425 P12[1] (SIO, I2C1: SDA) VDDIO1 (GPIO) P1[6] (GPIO) P1[7]5](USBIO, D+, SWDIO) P15[6]5](USBIO, D-, SWDCK) P15[7]VDDDVSSDVCCD (GPIO, MHZ XTAL: XO) P15[0] (GPIO, MHZ XTAL: XI) P15[1]VDDIO3 (SIO, I2C1: SCL) P12[0] [ [ Notes 5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. 6. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices. Document Number: 001-11729 Rev. AG Page 7 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 2-5. 68-pin QFN Part Pinout[7] 2-)2+) C2)C0)mpmp PIO) PIO)PIO)PIO)PIO)PIO) GPOI)GPIO) PIO, IDAPIO, IDAPIO, OpaPIO, Opa 2[5] (GDDIO22[4] (G2[3] (G2[2] (G2[1] (G2[0] (G 15[5] (15[4] (DDDSSDCCD0[7] (G0[6] (G0[5] (G0[4] (GDDIO0 PVPPPPP PPVVVPPPPV 87654321098765432 66666666655555555 (GPIO) P2[6] 1 51 P0[3] (GPIO, Opamp0-/EXTREF0) (GPIO) P2[7] 2 50 P0[2] (GPIO, Opamp0+) (I2C0: SCL, SIO) P12[4] 3 LINES SHOW 49 P0[1] (GPIO, Opamp0OUT) (I2C0: SDA, SIO) P12[5] 4 VDDIO TO I/O 48 P0[0] (GPIO, Opamp2OUT) VSSB 5 SUPPLY 47 P12[3] (SIO) IND 6 ASSOCIATION 46 P12[2] (SIO) VBOOST 7 45 VSSD VBAT 8 44 VDDA QFN VSSD 9 43 VSSA XRES 10 (TOP VIEW) 42 VCCA (TMS, SWDIO, GPIO) P1[0] 11 41 P15[3] (GPIO, KHZ XTAL: XI) (TCK, SWDCK, GPIO) P1[1] 12 40 P15[2] (GPIO, KHZ XTAL: XO) (ConfigurableXRES, GPIO) P1[2] 13 39 P12[1] (SIO, I2C1: SDA) (TDO, SWV, GPIO) P1[3] 14 38 P12[0] (SIO, 12C1: SCL) (TDI, GPIO) P1[4] 15 37 P3[7] (GPIO, Opamp3OUT) (nTRST, GPIO) P1[5] 16 36 P3[6] (GPIO, Opamp1OUT) VDDIO1 17 35 VDDIO3 89012345678901234 11222222222233333 (GPIO) P1[6](GPIO) P1[7](SIO) P12[6](SIO) P12[7][8](USBIO, D+, SWDIO) P15[6]8](USBIO, D-, SWDCK) P15[7]VDDDVSSDVCCD(MHZ XTAL: XO, GPIO) P15[0] (MHZ XTAL: XI, GPIO) P15[1](IDAC1, GPIO) P3[0](IDAC3, GPIO) P3[1](OpAmp3-/Extref1, GPIO) P3[2](Opamp3+, GPIO) P3[3]Opamp(1-, GPIO) P3[4](Opamp1+, GPIO) P3[5] [ Notes 7. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices 8. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. Document Number: 001-11729 Rev. AG Page 8 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 2-6. 100-pin TQFP Part Pinout 2-)2+) PIO)PIO)PIO)PIO)PIO)GPIO) GPIO)PIO)PIO)PIO)PIO) PIO)PIO) PIO)PIO)PIO)PIO)PIO, IDAC2)PIO, IDAC0)PIO, OpampPIO, Opamp DDIO22[4] (G2[3] (G2[2] (G2[1] (G2[0] (G15[5] ( 15[4] (6[3] (G6[2] (G6[1] (G6[0] (GDDDSSDCCD4[7] (G4[6] (G 4[5] (G4[4] (G4[3] (G4[2] (G0[7] (G0[6] (G0[5] (G0[4] (G VPPPPPP PPPPPVVVPP PPPPPPPP (GPIO) P2[5] 110099 9897969594939291908988 87868584838281807978 777675 VDDIO0 (GPIO) P2[6] 2 74 P0[3] (GPIO, Opamp0-/Extref0) (GPIO) P2[7] 3 73 P0[2] (GPIO, Opamp0+) (I2C0: SCL, SIO) P12[4] 4 Lines showVDDIO 72 P0[1] (GPIO, Opamp0OUT) to I/O supply (I2C0: SDA, SIO) P12[5] 5 association 71 P0[0] (GPIO, Opamp2OUT) (GPIO) P6[4] 6 70 P4[1] (GPIO) (GPIO) P6[5] 7 69 P4[0] (GPIO) (GPIO) P6[6] 8 68 P12[3] (SIO) (GPIO) P6[7] 9 67 P12[2] (SIO) VSSB 10 66 VSSD IND 11 65 VDDA VBOOST 12 64 VSSA VBAT 13 TQFP 63 VCCA VSSD 14 62 NC XRES 15 61 NC (GPIO) P5[0] 16 60 NC (GPIO) P5[1] 17 59 NC (GPIO) P5[2] 18 58 NC (GPIO) P5[3] 19 57 NC (TMS, SWDIO, GPIO) P1[0] 20 56 P15[3] (GPIO, KHZ XTAL: XI) (TCK, SWDCK, GPIO) P1[1] 21 55 P15[2] (GPIO, KHZ XTAL: XO) (ConfigurableXRES, GPIO) P1[2] 22 54 P12[1] (SIO, I2C1: SDA) (TDO, SWV, GPIO) P1[3] 23 53 P12[0] (SIO, I2C1: SCL) (TDI, GPIO) P1[4] 24 52 P3[7] (GPIO, Opamp3OUT) (nTRST, GPIO) P1[5] 256789012345 67890123456789051 P3[6] (GPIO, Opamp1OUT) 2222333333 333344444444445 VDDIO1(GPIO) P1[6](GPIO) P1[7](SIO) P12[6](SIO) P12[7](GPIO) P5[4](GPIO) P5[5](GPIO) P5[6](GPIO) P5[7](USBIO, D+, SWDIO) P15[6] (USBIO, D-, SWDCK) P15[7]VDDDVSSDVCCDNCNC(MHZ XTAL: XO, GPIO) P15[0](MHZ XTAL: XI, GPIO) P15[1](IDAC1, GPIO) P3[0](IDAC3, GPIO) P3[1]OpampP3-/Extref1, GPIO) P3[2](Opamp3+, GPIO) P3[3](Opamp1-, GPIO) P3[4] (Opamp1+, GPIO) P3[5]VDDIO3 [9] [9] ( Table 2-1. V and Port Pin Associations DDIO VDDIO Port Pins VDDIO0 P0[7:0], P4[7:0], P12[3:2] VDDIO1 P1[7:0], P5[7:0], P12[7:6] VDDIO2 P2[7:0], P6[7:0], P12[5:4], P15[5:4] VDDIO3 P3[7:0], P12[1:0], P15[3:0] VDDD P15[7:6] (USB D+, D-) Note 9. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. Document Number: 001-11729 Rev. AG Page 9 of 140

® PSoC 3: CY8C38 Family Datasheet Table2-2 shows the pinout for the 72-pin CSP package. Since there are four V pins, the set of I/O pins associated with any V DDIO DDIO may sink up to 100mA total, same as for the 100-pin and 68-pin devices. Table 2-2. CSP Pinout Ball Name Ball Name Ball Name G6 P2[5] F1 VDDD A5 VDDA E5 P2[6] E1 VSSD A6 VSSD F5 P2[7] E2 VCCD B6 P12[2] J7 P12[4] C1 P15[0] C6 P12[3] H6 P12[5] C2 P15[1] A7 P0[0] J6 VSSB D2 P3[0] B7 P0[1] J5 Ind D3 P3[1] B5 P0[2] H5 VBOOST D4 P3[2] C5 P0[3] J4 VBAT D5 P3[3] A8 VIO0 H4 VSSD B4 P3[4] D6 P0[4] J3 XRES_N B3 P3[5] D7 P0[5] H3 P1[0] A1 VIO3 C7 P0[6] G3 P1[1] B2 P3[6] C8 P0[7] H2 P1[2] A2 P3[7] E8 VCCD J2 P1[3] C3 P12[0] F8 VSSD G4 P1[4] C4 P12[1] G8 VDDD G5 P1[5] E3 P15[2] E7 P15[4] J1 VIO1 E4 P15[3] F7 P15[5] F4 P1[6] B1[10] NC G7 P2[0] F3 P1[7] B8[10] NC H7 P2[1] H1 P12[6] D1[10] NC H8 P2[2] G1 P12[7] D8[10] NC F6 P2[3] G2 P15[6] A3 VCCA E6 P2[4] F2 P15[7] A4 VSSA J8 VIO2 Figure2-7 and Figure2-8 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog performance on a two-layer board. The two pins labeled VDDD must be connected together. The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure2-7 and Power System on page 31. The trace between the two VCCD pins should be as short as possible. The two pins labeled VSSD must be connected together. For information on circuit board layout issues for mixed signals, refer to the application note, AN57821 - Mixed Signal Circuit Board Layout Considerations for PSoC® 3 and PSoC 5. Note 10.These pins are Do Not Use (DNU); they must be left floating. Document Number: 001-11729 Rev. AG Page 10 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 2-7. Example Schematic for 100-pin TQFP Part with Power Connections VDDD VDDD C1 C2 VDDD 1uF 0.1uF D VCCD D DD C6 VD VSSD DDSS VSSD 0.1uF VV 0 0987654321098765432109876 VSSD 1999999999988888888887777 1 P2[5] VDDIO2P2[4]P2[3]P2[2]P2[1]P2[0]P15[5]P15[4]P6[3]P6[2]P6[1]P6[0]VDDDVSSDVCCDP4[7]P4[6]P4[5]P4[4]P4[3]P4[2]DAC2, P0[7]DAC0, P0[6]OA2-, P0[5]OA2+, P0[4] VDDIO0 75 VDDD VDDA 234 PPP221[[267[]]4], SIO IOIAO0-A, 0OROEAUF0T+0,,, PPP000[[[213]]] 777243 C0.81uF C17 5 P12[5], SIO OA2OUT, P0[0] 71 1uF 6 P6[4] P4[1] 70 7 P6[5] P4[0] 69 VSSD 8 P6[6] SIO, P12[3] 68 VSSA 9 P6[7] SIO, P12[2] 67 10 VSSB VSSD 66 VSSD VDDA 11 IND VDDA 65 VDDA 12 VBOOST VSSA 64 VSSA VSSD 13 VBAT VCCA 63 VCCA VSSD 1145 VXSRSEDS NNCC 6612 C9 C10 16 P5[0] NC 60 1uF 0.1uF 17 P5[1] NC 59 18 P5[2] NC 58 19 P5[3] NC 57 20 P1[0], SWIO, TMS KHZXIN, P15[3] 56 VSSA 21 P1[1], SWDIO, TCK KHZXOUT, P15[2] 55 22 P1[2] SIO, P12[1] 54 222345 PPP111[[[345]]],,, STNDWTRIVVDDIO1S, TP1[6]TDP1[7]OP12[6], SIOP12[7], SIOP5[4]P5[5]P5[6]P5[7]P15[6], USB D+P15[7], USB D-VDDDVSSDVCCDNCNCP15[0], MHZXOUTP15[1], MHZXINP3[0], IDAC1P3[1], IDAC3P3[2], OA3-, REF1P3[3], OA3+P3[4], OA1-P3[5], OA1+OOAAVDDIO313SOOIUUOTT, P,, PP1233[[[067]]] 555123 VDDD 26272829303132333435363738394041424344454647484950 VDDD C11 C12 0.1uF 0.1uF VDDD VSSD VCCD VSSD VSSD C16 C15 0.1uF 1uF VSSD Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-8 on page 12. For more information on pad layout, refer to http://www.cypress.com/cad-resources/psoc-3-cad-libraries. Document Number: 001-11729 Rev. AG Page 11 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 2-8. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance VSSA VDDD VSSD VDDA VSSA VSSD Plane Plane 3. Pin Descriptions kHz XTAL: Xo, kHz XTAL: Xi 32.768-kHz crystal oscillator pin. IDAC0, IDAC1, IDAC2, IDAC3 MHz XTAL: Xo, MHz XTAL: Xi Low resistance output pin for high current DACs (IDAC). 4- to 25-MHz crystal oscillator pin. Opamp0OUT, Opamp1OUT, Opamp2OUT, Opamp3OUT nTRST High current output of uncommitted opamp[11]. Optional JTAG test reset programming and debug port Extref0, Extref1 connection to reset the JTAG connection. External reference input to the analog system. SIO Opamp0–, Opamp1–, Opamp2–, Opamp3– Special I/O provides interfaces to the CPU, digital peripherals Inverting input to uncommitted opamp. and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state Opamp0+, Opamp1+, Opamp2+, Opamp3+ when the device is unpowered. Noninverting input to uncommitted opamp. SWDCK GPIO Serial wire debug clock programming and debug port General purpose I/O pin provides interfaces to the CPU, digital connection. peripherals, analog peripherals, interrupts, LCD segment drive, SWDIO and CapSense[11]. Serial wire debug input and output programming and debug port I2C0: SCL, I2C1: SCL connection. I2C SCL line providing wake from sleep on an address match. SWV Any I/O pin can be used for I2C SCL if wake from sleep is not required. Single wire viewer debug output. I2C0: SDA, I2C1: SDA TCK I2C SDA line providing wake from sleep on an address match. JTAG test clock programming and debug port connection. Any I/O pin can be used for I2C SDA if wake from sleep is not TDI required. JTAG test data in programming and debug port connection. IND TDO Inductor connection to boost pump. JTAG test data out programming and debug port connection. Note 11.GPIOs with opamp outputs are not recommended for use with CapSense. Document Number: 001-11729 Rev. AG Page 12 of 140

® PSoC 3: CY8C38 Family Datasheet TMS VDDIO0, VDDIO1, VDDIO2, VDDIO3 JTAG test mode select programming and debug port connection. Supply for I/O pins. Each VDDIO must be tied to a valid operating voltage (1.71V to 5.5V), and must be less than or equal to USBIO, D+ VDDA. Provides D+ connection directly to a USB 2.0 bus. May be used XRES (and configurable XRES) as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are Do Not Use (DNU) on devices without USB. External reset pin. Active low with internal pull-up. Pin P1[2] may be configured to be a XRES pin; see “Nonvolatile Latches USBIO, D– (NVLs)” on page24. Provides D– connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a 4. CPU VDDIO. Pins are Do Not Use (DNU) on devices without USB. 4.1 8051 CPU VBOOST The CY8C38 devices use a single cycle 8051 CPU, which is fully Power sense connection to boost pump. compatible with the original MCS-51 instruction set. The VBAT CY8C38 family uses a pipelined RISC architecture, which executes most instructions in 1 to 2 cycles to provide peak Battery supply to boost pump. performance of up to 33 MIPS with an average of 2 cycles per VCCA. instruction. The single cycle 8051 CPU runs ten times faster than a standard 8051 processor. Output of the analog core regulator or the input to the analog core. Requires a 1uF capacitor to VSSA. The regulator The 8051 CPU subsystem includes these features: output is not designed to drive external circuits. Note that if you Single cycle 8051 CPU use the device with an external core regulator (externally Up to 64 KB of flash memory, up to 2 KB of EEPROM, and up regulated mode), the voltage applied to this pin must not to 8 KB of SRAM exceed the allowable range of 1.71 V to 1.89 V. When using the internal core regulator, (internally regulated mode, the 512-byte instruction cache between CPU and flash default), do not tie any power to this pin. For details see Power Programmable nested vector interrupt controller System on page 31. DMA controller VCCD. Peripheral HUB (PHUB) Output of the digital core regulator or the input to the digital External memory interface (EMIF) core. The two VCCD pins must be shorted together, with the trace between them as short as possible, and a 1uF capacitor to 4.2 Addressing Modes VSSD. The regulator output is not designed to drive external circuits. Note that if you use the device with an external core The following addressing modes are supported by the 8051: regulator (externally regulated mode), the voltage applied to Direct Addressing: The operand is specified by a direct 8-bit this pin must not exceed the allowable range of 1.71 V to address field. Only the internal RAM and the SFRs can be 1.89 V. When using the internal core regulator (internally accessed using this mode. regulated mode, the default), do not tie any power to this pin. For details see Power System on page 31. Indirect Addressing: The instruction specifies the register which contains the address of the operand. The registers R0 or R1 VDDA are used to specify the 8-bit address, while the data pointer Supply for all analog peripherals and analog core regulator. (DPTR) register is used to specify the 16-bit address. VDDA must be the highest voltage present on the device. All other supply pins must be less than or equal to VDDA. Register Addressing: Certain instructions access one of the registers (R0 to R7) in the specified register bank. These VDDD instructions are more efficient because there is no need for an Supply for all digital peripherals and digital core regulator. VDDD address field. must be less than or equal to VDDA. Register Specific Instructions: Some instructions are specific VSSA to certain registers. For example, some instructions always act on the accumulator. In this case, there is no need to specify the Ground for all analog peripherals. operand. VSSB Immediate Constants: Some instructions carry the value of the Ground connection for boost pump. constants directly instead of an address. VSSD Indexed Addressing: This type of addressing can be used only for a read of the program memory. This mode uses the Data Ground for all digital logic and I/O pins. Pointer as the base and the accumulator value as an offset to read a program memory. Bit Addressing: In this mode, the operand is one of 256 bits. Document Number: 001-11729 Rev. AG Page 13 of 140

® PSoC 3: CY8C38 Family Datasheet 4.3 Instruction Set Data transfer instructions The 8051 instruction set is highly optimized for 8-bit handling and Boolean instructions Boolean operations. The types of instructions supported include: Program branching instructions Arithmetic instructions Logical instructions 4.3.1 Instruction Set Summary 4.3.1.1 Arithmetic Instructions Arithmetic instructions support the direct, indirect, register, immediate constant, and register-specific instructions. Arithmetic modes are used for addition, subtraction, multiplication, division, increment, and decrement operations. Table4-1 lists the different arithmetic instructions. Table 4-1. Arithmetic Instructions Mnemonic Description Bytes Cycles ADD A,Rn Add register to accumulator 1 1 ADD A,Direct Add direct byte to accumulator 2 2 ADD A,@Ri Add indirect RAM to accumulator 1 2 ADD A,#data Add immediate data to accumulator 2 2 ADDCA,Rn Add register to accumulator with carry 1 1 ADDCA,Direct Add direct byte to accumulator with carry 2 2 ADDCA,@Ri Add indirect RAM to accumulator with carry 1 2 ADDCA,#data Add immediate data to accumulator with carry 2 2 SUBBA,Rn Subtract register from accumulator with borrow 1 1 SUBBA,Direct Subtract direct byte from accumulator with borrow 2 2 SUBBA,@Ri Subtract indirect RAM from accumulator with borrow 1 2 SUBBA,#data Subtract immediate data from accumulator with borrow 2 2 INC A Increment accumulator 1 1 INC Rn Increment register 1 2 INC Direct Increment direct byte 2 3 INC @Ri Increment indirect RAM 1 3 DEC A Decrement accumulator 1 1 DEC Rn Decrement register 1 2 DEC Direct Decrement direct byte 2 3 DEC @Ri Decrement indirect RAM 1 3 INC DPTR Increment data pointer 1 1 MUL Multiply accumulator and B 1 2 DIV Divide accumulator by B 1 6 DAA Decimal adjust accumulator 1 3 Document Number: 001-11729 Rev. AG Page 14 of 140

® PSoC 3: CY8C38 Family Datasheet 4.3.1.2 Logical Instructions The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. Table4-2 shows the list of logical instructions and their description. Table 4-2. Logical Instructions Mnemonic Description Bytes Cycles ANL A,Rn AND register to accumulator 1 1 ANL A,Direct AND direct byte to accumulator 2 2 ANL A,@Ri AND indirect RAM to accumulator 1 2 ANL A,#data AND immediate data to accumulator 2 2 ANL Direct, A AND accumulator to direct byte 2 3 ANL Direct, #data AND immediate data to direct byte 3 3 ORL A,Rn OR register to accumulator 1 1 ORL A,Direct OR direct byte to accumulator 2 2 ORL A,@Ri OR indirect RAM to accumulator 1 2 ORL A,#data OR immediate data to accumulator 2 2 ORL Direct, A OR accumulator to direct byte 2 3 ORL Direct, #data OR immediate data to direct byte 3 3 XRL A,Rn XOR register to accumulator 1 1 XRL A,Direct XOR direct byte to accumulator 2 2 XRL A,@Ri XOR indirect RAM to accumulator 1 2 XRL A,#data XOR immediate data to accumulator 2 2 XRL Direct, A XOR accumulator to direct byte 2 3 XRL Direct, #data XOR immediate data to direct byte 3 3 CLR A Clear accumulator 1 1 CPL A Complement accumulator 1 1 RL A Rotate accumulator left 1 1 RLC A Rotate accumulator left through carry 1 1 RR A Rotate accumulator right 1 1 RRC A Rotate accumulator right though carry 1 1 SWAPA Swap nibbles within accumulator 1 1 4.3.1.3 Data Transfer Instructions addressing mode. Table4-3 lists the various data transfer instructions available. The data transfer instructions are of three types: the core RAM, xdata RAM, and the lookup tables. The core RAM transfer 4.3.1.4 Boolean Instructions includes transfer between any two core RAM locations or SFRs. The 8051 core has a separate bit-addressable memory location. These instructions can use direct, indirect, register, and It has 128 bits of bit addressable RAM and a set of SFRs that are immediate addressing. The xdata RAM transfer includes only the bit addressable. The instruction set includes the whole menu of transfer between the accumulator and the xdata RAM location. bit operations such as move, set, clear, toggle, OR, and AND It can use only indirect addressing. The lookup tables involve instructions and the conditional jump instructions. Table4-4 lists nothing but the read of program memory using the Indexed the available Boolean instructions. Document Number: 001-11729 Rev. AG Page 15 of 140

® PSoC 3: CY8C38 Family Datasheet Table 4-3. Data Transfer Instructions Mnemonic Description Bytes Cycles MOV A,Rn Move register to accumulator 1 1 MOV A,Direct Move direct byte to accumulator 2 2 MOV A,@Ri Move indirect RAM to accumulator 1 2 MOV A,#data Move immediate data to accumulator 2 2 MOV Rn,A Move accumulator to register 1 1 MOV Rn,Direct Move direct byte to register 2 3 MOV Rn, #data Move immediate data to register 2 2 MOV Direct, A Move accumulator to direct byte 2 2 MOV Direct, Rn Move register to direct byte 2 2 MOV Direct, Direct Move direct byte to direct byte 3 3 MOV Direct, @Ri Move indirect RAM to direct byte 2 3 MOV Direct, #data Move immediate data to direct byte 3 3 MOV @Ri, A Move accumulator to indirect RAM 1 2 MOV @Ri, Direct Move direct byte to indirect RAM 2 3 MOV @Ri, #data Move immediate data to indirect RAM 2 2 MOV DPTR, #data16 Load data pointer with 16 bit constant 3 3 MOVC A, @A+DPTR Move code byte relative to DPTR to accumulator 1 5 MOVC A, @A + PC Move code byte relative to PC to accumulator 1 4 MOVX A,@Ri Move external RAM (8-bit) to accumulator 1 4 MOVX A, @DPTR Move external RAM (16-bit) to accumulator 1 3 MOVX @Ri, A Move accumulator to external RAM (8-bit) 1 5 MOVX @DPTR, A Move accumulator to external RAM (16-bit) 1 4 PUSH Direct Push direct byte onto stack 2 3 POP Direct Pop direct byte from stack 2 2 XCH A, Rn Exchange register with accumulator 1 2 XCH A, Direct Exchange direct byte with accumulator 2 3 XCH A, @Ri Exchange indirect RAM with accumulator 1 3 XCHD A, @Ri Exchange low order indirect digit RAM with accumulator 1 3 Table 4-4. Boolean Instructions Mnemonic Description Bytes Cycles CLR C Clear carry 1 1 CLR bit Clear direct bit 2 3 SETB C Set carry 1 1 SETB bit Set direct bit 2 3 CPL C Complement carry 1 1 CPL bit Complement direct bit 2 3 ANL C, bit AND direct bit to carry 2 2 Document Number: 001-11729 Rev. AG Page 16 of 140

® PSoC 3: CY8C38 Family Datasheet Table 4-4. Boolean Instructions (continued) Mnemonic Description Bytes Cycles ANL C, /bit AND complement of direct bit to carry 2 2 ORL C, bit OR direct bit to carry 2 2 ORL C, /bit OR complement of direct bit to carry 2 2 MOV C, bit Move direct bit to carry 2 2 MOV bit, C Move carry to direct bit 2 3 JC rel Jump if carry is set 2 3 JNC rel Jump if no carry is set 2 3 JB bit, rel Jump if direct bit is set 3 5 JNB bit, rel Jump if direct bit is not set 3 5 JBC bit, rel Jump if direct bit is set and clear bit 3 5 4.3.1.5 Program Branching Instructions The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. Table4-5 shows the list of jump instructions. Table 4-5. Jump Instructions Mnemonic Description Bytes Cycles ACALL addr11 Absolute subroutine call 2 4 LCALL addr16 Long subroutine call 3 4 RET Return from subroutine 1 4 RETI Return from interrupt 1 4 AJMP addr11 Absolute jump 2 3 LJMP addr16 Long jump 3 4 SJMP rel Short jump (relative address) 2 3 JMP @A + DPTR Jump indirect relative to DPTR 1 5 JZ rel Jump if accumulator is zero 2 4 JNZ rel Jump if accumulator is nonzero 2 4 CJNE A,Direct, rel Compare direct byte to accumulator and jump if not equal 3 5 CJNE A, #data, rel Compare immediate data to accumulator and jump if not equal 3 4 CJNE Rn, #data, rel Compare immediate data to register and jump if not equal 3 4 CJNE @Ri, #data, rel Compare immediate data to indirect RAM and jump if not equal 3 5 DJNZ Rn,rel Decrement register and jump if not zero 2 4 DJNZ Direct, rel Decrement direct byte and jump if not zero 3 5 NOP No operation 1 1 Document Number: 001-11729 Rev. AG Page 17 of 140

® PSoC 3: CY8C38 Family Datasheet 4.4 DMA and PHUB Transactions can be stalled or canceled The PHUB and the DMA controller are responsible for data Supports transaction size of infinite or 1 to 64 KB transfer between the CPU and peripherals, and also data transfers between peripherals. The PHUB and DMA also control TDs may be nested and/or chained for complex transactions device configuration during boot. The PHUB consists of: 4.4.3 Priority Levels A central hub that includes the DMA controller, arbiter, and The CPU always has higher priority than the DMA controller router when their accesses require the same bus resources. Due to the Multiple spokes that radiate outward from the hub to most system architecture, the CPU can never starve the DMA. DMA peripherals channels of higher priority (lower priority number) may interrupt current DMA transfers. In the case of an interrupt, the current There are two PHUB masters: the CPU and the DMA controller. transfer is allowed to complete its current transaction. To ensure Both masters may initiate transactions on the bus. The DMA latency limits when multiple DMA accesses are requested channels can handle peripheral communication without CPU simultaneously, a fairness algorithm guarantees an interleaved intervention. The arbiter in the central hub determines which minimum percentage of bus bandwidth for priority levels 2 DMA channel is the highest priority if there are multiple requests. through 7. Priority levels 0 and 1 do not take part in the fairness algorithm and may use 100 percent of the bus bandwidth. If a tie 4.4.1 PHUB Features occurs on two DMA requests of the same priority level, a simple CPU and DMA controller are both bus masters to the PHUB round robin method is used to evenly share the allocated bandwidth. The round robin allocation can be disabled for each Eight multi-layer AHB bus parallel access paths (spokes) for DMA channel, allowing it to always be at the head of the line. peripheral access Priority levels 2 to 7 are guaranteed the minimum bus bandwidth shown in Table4-7 after the CPU and DMA priority levels 0 and Simultaneous CPU and DMA access to peripherals located on 1 have satisfied their requirements. different spokes Table 4-7. Priority Levels Simultaneous DMA source and destination burst transactions on different spokes Priority Level % Bus Bandwidth Supports 8-, 16-, 24-, and 32-bit addressing and data 0 100.0 1 100.0 Table 4-6. PHUB Spokes and Peripherals 2 50.0 PHUB Spokes Peripherals 3 25.0 0 SRAM 4 12.5 1 IOs, PICU, EMIF 5 6.2 2 PHUB local configuration, Power manager, 6 3.1 Clocks, IC, SWV, EEPROM, Flash programming interface 7 1.5 3 Analog interface and trim, Decimator When the fairness algorithm is disabled, DMA access is granted 4 USB, CAN, I2C, Timers, Counters, and PWMs based solely on the priority level; no bus bandwidth guarantees 5 DFB are made. 6 UDBs group 1 4.4.4 Transaction Modes Supported 7 UDBs group 2 The flexible configuration of each DMA channel and the ability to chain multiple channels allow the creation of both simple and 4.4.2 DMA Features complex use cases. General use cases include, but are not limited to: 24 DMA channels 4.4.4.1 Simple DMA Each channel has one or more transaction descriptors (TD) to configure channel behavior. Up to 128 total TDs can be defined In a simple DMA case, a single TD transfers data between a source and sink (peripherals or memory location). The basic TDs can be dynamically updated timing diagrams of DMA read and write cycles are shown in Figure4-1. For more description on other transfer modes, refer Eight levels of priority per channel to the Technical Reference Manual. Any digitally routable signal, the CPU, or another DMA channel, can trigger a transaction Each channel can generate up to two interrupts per transfer Document Number: 001-11729 Rev. AG Page 18 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 4-1. DMA Timing Diagram ADDRESS Phase DATA Phase ADDRESS Phase DATA Phase CLK CLK ADDR 16/32 A B ADDR 16/32 A B WRITE WRITE DATA DATA (A) DATA DATA (A) READY READY Basic DMA Read Transfer without wait states Basic DMA Write Transfer without wait states 4.4.4.2 Auto Repeat DMA phase TD(s) finish, a status phase TD can be invoked that reads some memory mapped status information from the peripheral Auto repeat DMA is typically used when a static pattern is and copies it to a location in system memory specified by the repetitively read from system memory and written to a peripheral. CPU for later inspection. Multiple sets of configuration, data, and This is done with a single TD that chains to itself. status phase ‘subchains’ can be strung together to create larger 4.4.4.3 Ping Pong DMA chains that transmit multiple packets in this way. A similar concept exists in the opposite direction to receive the packets. A ping pong DMA case uses double buffering to allow one buffer to be filled by one client while another client is consuming the 4.4.4.7 Nested DMA data previously received in the other buffer. In its simplest form, One TD may modify another TD, as the TD configuration space this is done by chaining two TDs together so that each TD calls is memory mapped similar to any other peripheral. For example, the opposite TD when complete. a first TD loads a second TD’s configuration and then calls the 4.4.4.4 Circular DMA second TD. The second TD moves data as required by the application. When complete, the second TD calls the first TD, Circular DMA is similar to ping pong DMA except it contains more which again updates the second TD’s configuration. This than two buffers. In this case there are multiple TDs; after the last process repeats as often as necessary. TD is complete it chains back to the first TD. 4.4.4.5 Scatter Gather DMA 4.5 Interrupt Controller In the case of scatter gather DMA, there are multiple The interrupt controller provides a mechanism for hardware noncontiguous sources or destinations that are required to resources to change program execution to a new address, effectively carry out an overall DMA transaction. For example, a independent of the current task being executed by the main packet may need to be transmitted off of the device and the code. The interrupt controller provides enhanced features not packet elements, including the header, payload, and trailer, exist found on original 8051 interrupt controllers: in various noncontiguous locations in memory. Scatter gather Thirty-two interrupt vectors DMA allows the segments to be concatenated together by using multiple TDs in a chain. The chain gathers the data from the Jumps directly to ISR anywhere in code space with dynamic multiple locations. A similar concept applies for the reception of vector addresses data onto the device. Certain parts of the received data may need to be scattered to various locations in memory for software Multiple sources for each vector processing convenience. Each TD in the chain specifies the Flexible interrupt to vector matching location for each discrete element in the chain. Each interrupt vector is independently enabled or disabled 4.4.4.6 Packet Queuing DMA Each interrupt can be dynamically assigned one of eight Packet queuing DMA is similar to scatter gather DMA but priorities specifically refers to packet protocols. With these protocols, there may be separate configuration, data, and status phases Eight level nestable interrupts associated with sending or receiving a packet. Multiple I/O interrupt vectors For instance, to transmit a packet, a memory mapped configuration register can be written inside a peripheral, Software can send interrupts specifying the overall length of the ensuing data phase. The CPU Software can clear pending interrupts can set up this configuration information anywhere in system memory and copy it with a simple TD to the peripheral. After the Figure 4-2 on page 20 represents typical flow of events when an configuration phase, a data phase TD (or a series of data phase interrupt triggered. Figure 4-3 on page 21 shows the interrupt TDs) can begin (potentially using scatter gather). When the data structure and priority polling. Document Number: 001-11729 Rev. AG Page 19 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 4-2. Interrupt Processing Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 S Arrival of new Interrupt S Pend bit is set on next clock active edge POST and PEND bits cleared after IRQ is sleared S Interrupt is posted to ascertain the priority S IRQ cleared after receiving IRA Interrupt request sent to core for processing S S The active interrupt NA 0x0010 number is posted to core S S The active interrupt ISR NA address is posted to core NA S S S Int. State Interrupt generation and posting to CPU CPU Response Clear Completing current instruction and branching to vector address Complete ISR and return Notes 1: Interrupt triggered asynchronous to the clock 2: The PEND bit is set on next active clock edge to indicate the interrupt arrival 3: POST bit is set following the PEND bit 4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks) 5: ISR address is posted to CPU core for branching 6: CPU acknowledges the interrupt request 7: ISR address is read by CPU for branching 8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core 10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles) 11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status The total interrupt latency (ISR execution) = POST + PEND + IRQ + IRA + Completing current instruction and branching = 1+1+1+2+7 cycles = 12 cycles Document Number: 001-11729 Rev. AG Page 20 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 4-3. Interrupt Structure Interrupts form Fixed Interrupt Polling logic function blocks, DMA and UDBs Highest Priority Interrupt Enable/ Disable, PEND and Interrupts 0 to 31 POST logic from UDBs 0 Interrupts 0 to 31 from Fixed 1 Function Blocks IRQ 0 to 31 ACTIVE_INT_NUM Individual Enable Disable P I3n1te frrroumpt sD 0M tAo rtooIus nstotieenulrgerrc culeotp sg3t i2c bits Interrupt 2 ind8Ptef eorLcirroeor uarvdiplteely tlr s olling se [15:0] INT_VECT_ADDR to 30 quen c e IRA IRC 31 Global Enable Lowest Priority disable bit When an interrupt is pending, the current instruction is completed and the program direct connections to the most common interrupt sources and provide the lowest counter is pushed onto the stack. Code execution then jumps to the program address resource cost connection. The DMA interrupt sources provide direct connections to provided by the vector. After the ISR is completed, a RETI instruction is executed the two DMA interrupt sources provided per DMA channel. The third interrupt source and returns execution to the instruction following the previously interrupted for vectors is from the UDB digital routing array. This allows any digital signal instruction. To do this the RETI instruction pops the program counter from the stack. available to the UDB array to be used as an interrupt source. Fixed function interrupts and all interrupt sources may be routed to any interrupt vector using the UDB If the same priority level is assigned to two or more interrupts, the interrupt with the interrupt source connections. lower vector number is executed first. Each interrupt vector may choose from three interrupt sources: Fixed Function, DMA, and UDB. The fixed function interrupts are Document Number: 001-11729 Rev. AG Page 21 of 140

® PSoC 3: CY8C38 Family Datasheet Table 4-8. Interrupt Vector Table # Fixed Function DMA UDB 0 LVD phub_termout0[0] udb_intr[0] 1 Cache/ECC phub_termout0[1] udb_intr[1] 2 Reserved phub_termout0[2] udb_intr[2] 3 Sleep (Pwr Mgr) phub_termout0[3] udb_intr[3] 4 PICU[0] phub_termout0[4] udb_intr[4] 5 PICU[1] phub_termout0[5] udb_intr[5] 6 PICU[2] phub_termout0[6] udb_intr[6] 7 PICU[3] phub_termout0[7] udb_intr[7] 8 PICU[4] phub_termout0[8] udb_intr[8] 9 PICU[5] phub_termout0[9] udb_intr[9] 10 PICU[6] phub_termout0[10] udb_intr[10] 11 PICU[12] phub_termout0[11] udb_intr[11] 12 PICU[15] phub_termout0[12] udb_intr[12] 13 Comparators Combined phub_termout0[13] udb_intr[13] 14 Switched Caps Combined phub_termout0[14] udb_intr[14] 15 I2C phub_termout0[15] udb_intr[15] 16 CAN phub_termout1[0] udb_intr[16] 17 Timer/Counter0 phub_termout1[1] udb_intr[17] 18 Timer/Counter1 phub_termout1[2] udb_intr[18] 19 Timer/Counter2 phub_termout1[3] udb_intr[19] 20 Timer/Counter3 phub_termout1[4] udb_intr[20] 21 USB SOF Int phub_termout1[5] udb_intr[21] 22 USB Arb Int phub_termout1[6] udb_intr[22] 23 USB Bus Int phub_termout1[7] udb_intr[23] 24 USB Endpoint[0] phub_termout1[8] udb_intr[24] 25 USB Endpoint Data phub_termout1[9] udb_intr[25] 26 Reserved phub_termout1[10] udb_intr[26] 27 LCD phub_termout1[11] udb_intr[27] 28 DFB Int phub_termout1[12] udb_intr[28] 29 Decimator Int phub_termout1[13] udb_intr[29] 30 PHUB Error Int phub_termout1[14] udb_intr[30] 31 EEPROM Fault Int phub_termout1[15] udb_intr[31] Document Number: 001-11729 Rev. AG Page 22 of 140

® PSoC 3: CY8C38 Family Datasheet 5. Memory about how to take full advantage of the security features in PSoC, see the PSoC 3 TRM. 5.1 Static RAM Table 5-1. Flash Protection CY8C38 SRAM is used for temporary data storage. Up to 8 KB Protection of SRAM is provided and can be accessed by the 8051 or the Setting Allowed Not Allowed DMA controller. See Memory Map on page 26. Simultaneous access of SRAM by the 8051 and the DMA controller is possible Unprotected External read and write – if different 4-KB blocks are accessed. + internal read and write Factory External write + internal External read 5.2 Flash Program Memory Upgrade read and write Flash memory in PSoC devices provides nonvolatile storage for Field Upgrade Internal read and write External read and user firmware, user configuration data, bulk data storage, and write optional ECC data. The main flash memory area contains up to 64 KB of user program space. Full Protection Internal read External read and write + internal write Up to an additional 8 KB of flash space is available for ECC. If ECC is not used this space can store device configuration data Disclaimer and bulk user data. User code may not be run out of the ECC flash memory section. ECC can correct one bit error and detect Note the following details of the flash code protection features on two bit errors per 8 bytes of firmware memory; an interrupt can Cypress devices. be generated when an error is detected. Cypress products meet the specifications contained in their The CPU reads instructions located in flash through a cache particular Cypress data sheets. Cypress believes that its family controller. This improves instruction execution rate and reduces of products is one of the most secure families of its kind on the system power consumption by requiring less frequent flash market today, regardless of how they are used. There may be access. The cache has 8 lines at 64 bytes per line for a total of methods, unknown to Cypress, that can breach the code 512 bytes. It is fully associative, automatically controls flash protection features. Any of these methods, to our knowledge, power, and can be enabled or disabled. If ECC is enabled, the would be dishonest and possibly illegal. Neither Cypress nor any cache controller also performs error checking and correction, other semiconductor manufacturer can guarantee the security of and interrupt generation. their code. Code protection does not mean that we are guaranteeing the product as ‘unbreakable’. Cypress is willing to Flash programming is performed through a special interface and work with the customer who is concerned about the integrity of preempts code execution out of flash. The flash programming their code. Code protection is constantly evolving. We at Cypress interface performs flash erasing, programming and setting code are committed to continuously improving the code protection protection levels. Flash in-system serial programming (ISSP), features of our products. typically used for production programming, is possible through both the SWD and JTAG interfaces. In-system programming, 5.4 EEPROM typically used for bootloaders, is also possible using serial interfaces such as I2C, USB, UART, and SPI, or any PSoC EEPROM memory is a byte-addressable nonvolatile communications protocol. memory. The CY8C38 has up to 2 KB of EEPROM memory to store user data. Reads from EEPROM are random access at the 5.3 Flash Security byte level. Reads are done directly; writes are done by sending write commands to an EEPROM programming interface. CPU All PSoC devices include a flexible flash-protection model that code execution can continue from flash during EEPROM writes. prevents access and visibility to on-chip flash memory. This EEPROM is erasable and writeable at the row level. The prevents duplication or reverse engineering of proprietary code. EEPROM is divided into 128 rows of 16 bytes each. The factory Flash memory is organized in blocks, where each block contains default values of all EEPROM bytes are 0. 256 bytes of program or data and 32 bytes of ECC or configuration data. A total of up to 256 blocks is provided on Because the EEPROM is mapped to the 8051 xdata space, the 64-KB flash devices. CPU can not execute out of EEPROM. There is no ECC hardware associated with EEPROM. If ECC is required it must The device offers the ability to assign one of four protection be handled in firmware. levels to each row of flash. Table5-1 lists the protection modes available. Flash protection levels can only be changed by It can take as much as 20 milliseconds to write to EEPROM or performing a complete flash erase. The Full Protection and Field flash. During this time the device should not be reset, or Upgrade settings disable external access (through a debugging unexpected changes may be made to portions of EEPROM or tool such as PSoC Creator, for example). If your application flash. Reset sources (see Section6.3.1) include XRES pin, requires code update through a bootloader, then use the Field software reset, and watchdog; care should be taken to make Upgrade setting. Use the Unprotected setting only when no sure that these are not inadvertently activated. In addition, the security is needed in your application. The PSoC device also low voltage detect circuits should be configured to generate an offers an advanced security feature called Device Security which interrupt instead of a reset. permanently disables all test, programming, and debug ports, protecting your application from external access (see the “Device Security” section on page68). For more information Document Number: 001-11729 Rev. AG Page 23 of 140

® PSoC 3: CY8C38 Family Datasheet 5.5 Nonvolatile Latches (NVLs) PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown in Table5-2. Table 5-2. Device Configuration NVL Register Map Register Address 7 6 5 4 3 2 1 0 0x00 PRT3RDM[1:0] PRT2RDM[1:0] PRT1RDM[1:0] PRT0RDM[1:0] 0x01 PRT12RDM[1:0] PRT6RDM[1:0] PRT5RDM[1:0] PRT4RDM[1:0] 0x02 XRESMEN DBGEN PRT15RDM[1:0] 0x03 DIG_PHS_DLY[3:0] ECCEN DPS[1:0] CFGSPEED The details for individual fields and their factory default settings are shown in Table5-3:. Table 5-3. Fields and Factory Default Settings Field Description Settings PRTxRDM[1:0] Controls reset drive mode of the corresponding IO 00b (default) - high impedance analog port. See “Reset Configuration” on page43. All pins 01b - high impedance digital of the port are set to the same mode. 10b - resistive pull up 11b - resistive pull down XRESMEN Controls whether pin P1[2] is used as a GPIO or as 0 (default for 68-pin, 72-pin, and 100-pin parts) - GPIO an external reset. See “Pin Descriptions” on 1 (default for 48-pin parts) - external reset page12, XRES description. DBGEN Debug Enable allows access to the debug system, 0 - access disabled for third-party programmers. 1 (default) - access enabled CFGSPEED Controls the speed of the IMO-based clock during 0 (default) - 12 MHz IMO the device boot process, for faster boot or 1 - 48 MHz IMO low-power operation DPS[1:0] Controls the usage of various P1 pins as a debug 00b - 5-wire JTAG port. See “Programming, Debug Interfaces, 01b (default) - 4-wire JTAG Resources” on page65. 10b - SWD 11b - debug ports disabled ECCEN Controls whether ECC flash is used for ECC or for 0 - ECC disabled general configuration and data storage. See “Flash 1 (default) - ECC enabled Program Memory” on page23. DIG_PHS_DLY[3:0] Selects the digital clock phase delay. See the TRM for details. Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase / write cycles is limited – see “Nonvolatile Latches (NVL))” on page113. Document Number: 001-11729 Rev. AG Page 24 of 140

® PSoC 3: CY8C38 Family Datasheet 5.6 External Memory Interface CY8C38 provides an EMIF for connecting to external memory devices. The connection allows read and write accesses to external memories. The EMIF operates in conjunction with UDBs, I/O ports, and other hardware to generate external memory address and control signals. At 33 MHz, each memory access cycle takes four bus clock cycles. Figure5-1 is the EMIF block diagram. The EMIF supports synchronous and asynchronous memories. The CY8C38 supports only one type of external memory device at a time. External memory can be accessed through the 8051 xdata space; up to 24 address bits can be used. See “xdata Space” section on page27. The memory can be 8 or 16 bits wide. Figure 5-1. EMIF Block Diagram Address Signals I/O External_MEM_ADDR[23:0] PORTs Data, Address, and Control Signals IO IF Data Signals I/O External_MEM_DATA[15:0] PORTs Control Signals I/O Control PHUB PORTs Data, Address, DSI Dynamic Output and Control Control Signals UDB DSI to Port Other EM Control Control Data, Signals Signals Address, and Control Signals EMIF Document Number: 001-11729 Rev. AG Page 25 of 140

® PSoC 3: CY8C38 Family Datasheet 5.7 Memory Map Figure 5-2. 8051 Internal Data Space The CY8C38 8051 memory map is very similar to the MCS-51 0x00 memory map. 4 Banks, R0-R7 Each 0x1F 5.7.1 Code Space 0x20 Bit-Addressable Area The CY8C38 8051 code space is 64 KB. Only main flash exists 0x2F in this space. See the Flash Program Memory on page 23. 0x30 Lower Core RAM Shared with Stack Space 5.7.2 Internal Data Space (direct and indirect addressing) 0x7F The CY8C38 8051 internal data space is 384 bytes, compressed 0x80 within a 256-byte space. This space consists of 256 bytes of Upper Core RAM Shared SFR RAM (in addition to the SRAM mentioned in Static RAM on page with Stack Space Special Function Registers 23) and a 128-byte space for special function registers (SFR). (indirect addressing) (direct addressing) 0xFF See Figure5-2. The lowest 32 bytes are used for 4 banks of registers R0-R7. The next 16 bytes are bit-addressable. In addition to the register or bit address modes used with the lower 48 bytes, the lower 128 bytes can be accessed with direct or indirect addressing. With direct addressing mode, the upper 128 bytes map to the SFRs. With indirect addressing mode, the upper 128 bytes map to RAM. Stack operations use indirect addressing; the 8051 stack space is 256 bytes. See the “Addressing Modes” section on page13. 5.7.3 SFRs The SFR space provides access to frequently accessed registers. The memory map for the SFR memory space is shown in Table5-4. Table 5-4. SFR Map Address 0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F 0×F8 SFRPRT15DR SFRPRT15PS SFRPRT15SEL – – – – – 0×F0 B – SFRPRT12SEL – – – – – 0×E8 SFRPRT12DR SFRPRT12PS MXAX – – – – – 0×E0 ACC – – – – – – – 0×D8 SFRPRT6DR SFRPRT6PS SFRPRT6SEL – – – – – 0×D0 PSW – – – – – – – 0×C8 SFRPRT5DR SFRPRT5PS SFRPRT5SEL – – – – – 0×C0 SFRPRT4DR SFRPRT4PS SFRPRT4SEL – – – – – 0×B8 – – – – – 0×B0 SFRPRT3DR SFRPRT3PS SFRPRT3SEL – – – – – 0×A8 IE – – – – – – – 0×A0 P2AX – SFRPRT1SEL – – – – – 0×98 SFRPRT2DR SFRPRT2PS SFRPRT2SEL – – – – – 0×90 SFRPRT1DR SFRPRT1PS – DPX0 – DPX1 – – 0×88 – SFRPRT0PS SFRPRT0SEL – – – – – 0×80 SFRPRT0DR SP DPL0 DPH0 DPL1 DPH1 DPS – The CY8C38 family provides the standard set of registers found on industry standard 8051 devices. In addition, the CY8C38 devices add SFRs to provide direct access to the I/O ports on the device. The following sections describe the SFRs added to the CY8C38 family. Document Number: 001-11729 Rev. AG Page 26 of 140

® PSoC 3: CY8C38 Family Datasheet 5.7.4 XData Space Access SFRs 5.7.5.1 xdata Space The 8051 core features dual DPTR registers for faster data The 8051 xdata space is 24-bit, or 16 MB in size. The majority of transfer operations. The data pointer select SFR, DPS, selects this space is not ‘external’—it is used by on-chip components. which data pointer register, DPTR0 or DPTR1, is used for the See Table5-5. External, that is, off-chip, memory can be following instructions: accessed using the EMIF. See External Memory Interface on page 25. MOVX @DPTR, A MOVX A, @DPTR Table 5-5. XDATA Data Address Map MOVC A, @A+DPTR Address Range Purpose JMP @A+DPTR 0×00 0000 – 0×00 1FFF SRAM 0×00 4000 – 0×00 42FF Clocking, PLLs, and oscillators INC DPTR 0×00 4300 – 0×00 43FF Power management MOV DPTR, #data16 0×00 4400 – 0×00 44FF Interrupt controller The extended data pointer SFRs, DPX0, DPX1, MXAX, and 0×00 4500 – 0×00 45FF Ports interrupt control P2AX, hold the most significant parts of memory addresses during access to the xdata space. These SFRs are used only 0×00 4700 – 0×00 47FF Flash programming interface with the MOVX instructions. 0×00 4800 - 0×00 48FF Cache controller During a MOVX instruction using the DPTR0/DPTR1 register, 0×00 4900 – 0×00 49FF I2C controller the most significant byte of the address is always equal to the contents of DPX0/DPX1. 0×00 4E00 – 0×00 4EFF Decimator During a MOVX instruction using the R0 or R1 register, the most 0×00 4F00 – 0×00 4FFF Fixed timer/counter/PWMs significant byte of the address is always equal to the contents of 0×00 5000 – 0×00 51FF I/O ports control MXAX, and the next most significant byte is always equal to the contents of P2AX. 0×00 5400 – 0×00 54FF EMIF control registers 0×00 5800 – 0×00 5FFF Analog subsystem interface 5.7.5 I/O Port SFRs 0×00 6000 – 0×00 60FF USB controller The I/O ports provide digital input sensing, output drive, pin interrupts, connectivity for analog inputs and outputs, LCD, and 0×00 6400 – 0×00 6FFF UDB Working Registers access to peripherals through the DSI. Full information on I/O 0×00 7000 – 0×00 7FFF PHUB configuration ports is found in I/O System and Routing on page 37. 0×00 8000 – 0×00 8FFF EEPROM I/O ports are linked to the CPU through the PHUB and are also 0×00 A000 – 0×00 A400 CAN available in the SFRs. Using the SFRs allows faster access to a limited set of I/O port registers, while using the PHUB allows boot 0×00 C000 – 0×00 C800 DFB configuration and access to all I/O port registers. 0×01 0000 – 0×01 FFFF Digital Interconnect Each SFR supported I/O port provides three SFRs: configuration 0×05 0220 – 0×05 02F0 Debug controller SFRPRTxDR sets the output data state of the port (where × is port number and includes ports 0–6, 12 and 15). 0×08 0000 – 0×08 1FFF Flash ECC bytes The SFRPRTxSEL selects whether the PHUB PRTxDR 0×80 0000 – 0×FF FFFF External memory interface register or the SFRPRTxDR controls each pin’s output buffer within the port. If a SFRPRTxSEL[y] bit is high, the corresponding SFRPRTxDR[y] bit sets the output state for that pin. If a SFRPRTxSEL[y] bit is low, the corresponding PRTxDR[y] bit sets the output state of the pin (where y varies from 0 to 7). The SFRPRTxPS is a read only register that contains pin state values of the port pins. Document Number: 001-11729 Rev. AG Page 27 of 140

® PSoC 3: CY8C38 Family Datasheet 6. System Integration Key features of the clocking system include: Seven general purpose clock sources 6.1 Clocking System 3- to 62-MHz IMO, ±1% at 3 MHz The clocking system generates, divides, and distributes clocks 4- to 25-MHz external crystal oscillator (MHzECO) throughout the PSoC system. For the majority of systems, no Clock doubler provides a doubled clock frequency output for external crystal is required. The IMO and PLL together can the USB block, see USB Clock Domain on page 30. generate up to a 66 MHz clock, accurate to ±1 percent over DSI signal from an external I/O pin or other logic voltage and temperature. Additional internal and external clock sources allow each design to optimize accuracy, power, and 24- to 67-MHz fractional PLL sourced from IMO, MHzECO, or DSI cost. Any of the clock sources can be used to generate other clock frequencies in the 16-bit clock dividers and UDBs for 1-kHz, 33-kHz, 100-kHz ILO for WDT and sleep timer anything the user wants, for example a UART baud rate 32.768-kHz external crystal oscillator (kHzECO) for RTC generator. IMO has a USB mode that auto locks to the USB bus clock requiring no external crystal for USB (USB equipped parts only) Clock generation and distribution is automatically configured through the PSoC Creator IDE graphical interface. This is based Independently sourced clock in all clock dividers on the complete system’s requirements. It greatly speeds the Eight 16-bit clock dividers for the digital system design process. PSoC Creator allows you to build clocking systems with minimal input. You can specify desired clock Four 16-bit clock dividers for the analog system frequencies and accuracies, and the software locates or builds a Dedicated 16-bit divider for the bus clock clock that meets the required specifications. This is possible Dedicated 4-bit divider for the CPU clock because of the programmability inherent in PSoC. Automatic clock configuration in PSoC Creator Table 6-1. Oscillator Summary Source Fmin Tolerance at Fmin Fmax Tolerance at Fmax Startup Time IMO 3 MHz ±1% over voltage and temperature 62 MHz ±7% 13µs max MHzECO 4 MHz Crystal dependent 25 MHz Crystal dependent 5 ms typ, max is crystal dependent DSI 0 MHz Input dependent 33 MHz Input dependent Input dependent PLL 24 MHz Input dependent 67 MHz Input dependent 250 µs max Doubler 48 MHz Input dependent 48 MHz Input dependent 1 µs max ILO 1 kHz –50%, +100% 100 kHz –55%, +100% 15 ms max in lowest power mode kHzECO 32 kHz Crystal dependent 32 kHz Crystal dependent 500 ms typ, max is crystal dependent Figure 6-1. Clocking Subsystem External IO 3-62 MHz 4-25 MHz 1,33,100 kHz or DSI 32 kHz ECO IMO ECO ILO 0-33 MHz CPU Clock CPU Clock Divider 4 bit 48 MHz 24-67 MHz Master Doubler for PLL Mux USB Bus Clock Bus Clock Divider 16 bit s Digital Clock Digital Clock Analog Clock k Divider 16 bit Divider 16 bit Divider 16 bit e w s Digital Clock Digital Clock Analog Clock k Divider 16 bit Divider 16 bit Divider 16 bit e w 7 7 s Digital Clock Digital Clock Analog Clock k Divider 16 bit Divider 16 bit Divider 16 bit e w s Digital Clock Digital Clock Analog Clock k Divider 16 bit Divider 16 bit Divider 16 bit e w Document Number: 001-11729 Rev. AG Page 28 of 140

® PSoC 3: CY8C38 Family Datasheet 6.1.1 Internal Oscillators The 100-kHz clock (CLK100K) can be used as a low power master clock. It can also generate time intervals using the fast Figure 6-1 shows that there are two internal oscillators. They can timewheel. be routed directly or divided. The direct routes may not have a 50% duty cycle. Divided clocks have a 50% duty cycle. The fast timewheel is a 5-bit counter, clocked by the 100-kHz clock. It features programmable settings and automatically 6.1.1.1 Internal Main Oscillator resets when the terminal count is reached. An optional interrupt In most designs the IMO is the only clock source required, due can be generated each time the terminal count is reached. This to its ±1-percent accuracy. The IMO operates with no external enables flexible, periodic interrupts of the CPU at a higher rate components and outputs a stable clock. A factory trim for each than is allowed using the central timewheel. frequency range is stored in the device. With the factory trim, The 33-kHz clock (CLK33K) comes from a divide-by-3 operation tolerance varies from ±1 percent at 3 MHz, up to ±7 percent at on CLK100K. This output can be used as a reduced accuracy 62MHz. The IMO, in conjunction with the PLL, allows generation version of the 32.768-kHz ECO clock with no need for a crystal. of other clocks up to the device's maximum frequency (see PLL). The IMO provides clock outputs at 3, 6, 12, 24, 48, and 62 MHz. 6.1.2 External Oscillators 6.1.1.2 Clock Doubler Figure 6-1 shows that there are two external oscillators. They The clock doubler outputs a clock at twice the frequency of the can be routed directly or divided. The direct routes may not have input clock. The doubler works at input frequency of 24 MHz, a 50% duty cycle. Divided clocks have a 50% duty cycle. providing 48 MHz for the USB. It can be configured to use a clock 6.1.2.1 MHz External Crystal Oscillator from the IMO, MHzECO, or the DSI (external pin). The MHzECO provides high frequency, high precision clocking 6.1.1.3 PLL using an external crystal (see Figure6-2). It supports a wide The PLL allows low-frequency, high-accuracy clocks to be variety of crystal types, in the range of 4 to 25 MHz. When used multiplied to higher frequencies. This is a trade off between in conjunction with the PLL, it can generate other clocks up to the higher clock frequency and accuracy and, higher power device's maximum frequency (see PLL). The GPIO pins consumption and increased startup time. connecting to the external crystal and capacitors are fixed. MHzECO accuracy depends on the crystal chosen. The PLL block provides a mechanism for generating clock frequencies based upon a variety of input sources. The PLL Figure 6-2. MHzECO Block Diagram outputs clock frequencies in the range of 24 to 67 MHz. Its input and feedback dividers supply 4032 discrete ratios to create almost any desired clock frequency. The accuracy of the PLL XCLK_MHZ 4 - 25 MHz output depends on the accuracy of the PLL input source. The Crystal Osc most common PLL use is to multiply the IMO clock at 3 MHz, where it is most accurate, to generate the other clocks up to the device’s maximum frequency. The PLL achieves phase lock within 250 µs (verified by bit setting). It can be configured to use a clock from the IMO, MHzECO or DSI (external pin). The PLL clock source can be Xi Xo used until lock is complete and signaled with a lock bit. The lock (Pin P15[1]) (Pin P15[0]) signal can be routed through the DSI to generate an interrupt. 4 –25 MHz Disable the PLL before entering low-power modes. External crystal Components 6.1.1.4 Internal Low-Speed Oscillator Capacitors The ILO provides clock frequencies for low-power consumption, including the watchdog timer, and sleep timer. The ILO generates up to three different clocks: 1 kHz, 33 kHz, and 6.1.2.2 32.768-kHz ECO 100kHz. The 1-kHz clock (CLK1K) is typically used for a background ‘heartbeat’ timer. This clock inherently lends itself to The 32.768-kHz external crystal oscillator (32kHzECO) provides low-power supervisory operations such as the watchdog timer precision timing with minimal power consumption using an and long sleep intervals using the central timewheel (CTW). external 32.768-kHz watch crystal (see Figure6-3). The 32kHzECO also connects directly to the sleep timer and provides The central timewheel is a 1-kHz, free running, 13-bit counter the source for the RTC. The RTC uses a 1-second interrupt to clocked by the ILO. The central timewheel is always enabled, implement the RTC functionality in firmware. except in hibernate mode and when the CPU is stopped during debug on chip mode. It can be used to generate periodic The oscillator works in two distinct power modes. This allows interrupts for timing purposes or to wake the system from a users to trade off power consumption with noise immunity from low-power mode. Firmware can reset the central timewheel. neighboring circuits. The GPIO pins connected to the external Systems that require accurate timing should use the RTC crystal and capacitors are fixed. capability instead of the central timewheel. Document Number: 001-11729 Rev. AG Page 29 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 6-3. 32kHzECO Block Diagram The clock distribution system generates several types of clock trees. XCLK32K The master clock is used to select and supply the fastest clock 32 kHz in the system for general clock requirements and clock Crystal Osc synchronization of the PSoC device. Bus clock 16-bit divider uses the master clock to generate the bus clock used for data transfers. Bus clock is the source clock for the CPU clock divider. Xi Xo Eight fully programmable 16-bit clock dividers generate digital (Pin P15[3]) (Pin P15[2]) system clocks for general use in the digital system, as 32 kHz configured by the design’s requirements. Digital system clocks External crystal can generate custom clocks derived from any of the seven Components Capacitors clock sources for any purpose. Examples include baud rate generators, accurate PWM periods, and timer clocks, and many others. If more than eight digital clock dividers are required, the UDBs and fixed function timer/counter/PWMs can It is recommended that the external 32.768-kHz watch crystal also generate clocks. have a load capacitance (CL) of 6 pF or 12.5 pF. Check the crystal manufacturer's datasheet. The two external capacitors, Four 16-bit clock dividers generate clocks for the analog system CL1 and CL2, are typically of the same value, and their total components that require clocking, such as ADC and mixers. capacitance, CL1CL2 / (CL1 + CL2), including pin and trace The analog clock dividers include skew control to ensure that capacitance, should equal the crystal CL value. For more critical analog events do not occur simultaneously with digital information, refer to application note AN54439: PSoC 3 and switching events. This is done to reduce analog system noise. PSoC 5 External Oscillators. See also pin capacitance Each clock divider consists of an 8-input multiplexer, a 16-bit specifications in the “GPIO” section on page80. clock divider (divide by 2 and higher) that generates ~50 percent 6.1.2.3 Digital System Interconnect duty cycle clocks, master clock resynchronization logic, and deglitch logic. The outputs from each digital clock tree can be The DSI provides routing for clocks taken from external clock routed into the digital system interconnect and then brought back oscillators connected to I/O. The oscillators can also be into the clock system as an input, allowing clock chaining of up generated within the device in the digital system and UDBs. to 32 bits. While the primary DSI clock input provides access to all clocking resources, up to eight other DSI clocks (internally or externally 6.1.4 USB Clock Domain generated) may be routed directly to the eight digital clock The USB clock domain is unique in that it operates largely dividers. This is only possible if there are multiple precision clock asynchronously from the main clock network. The USB logic sources. contains a synchronous bus interface to the chip, while running on an asynchronous clock to process USB data. The USB logic 6.1.3 Clock Distribution requires a 48 MHz frequency. This frequency can be generated All seven clock sources are inputs to the central clock distribution from different sources, including DSI clock at 48 MHz or doubled system. The distribution system is designed to create multiple value of 24 MHz from internal oscillator, DSI signal, or crystal high precision clocks. These clocks are customized for the oscillator. design’s requirements and eliminate the common problems found with limited resolution prescalers attached to peripherals. Document Number: 001-11729 Rev. AG Page 30 of 140

® PSoC 3: CY8C38 Family Datasheet 6.2 Power System VDDIO pins must have capacitors connected as shown in Figure6-4. The two VCCD pins must be shorted together, with The power system consists of separate analog, digital, and I/O as short a trace as possible, and connected to a 1-µF supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It ±10-percent X5R capacitor. The power system also contains a also includes two internal 1.8-V regulators that provide the digital sleep regulator, an I2C regulator, and a hibernate regulator. (VCCD) and analog (VCCA) supplies for the internal core logic. The output pins of the regulators (VCCD and VCCA) and the Figure 6-4. PSoC Power System VDDIO2 1µF VDDD VDDIO0 0.1µF 0.1µF 2VDDIO I/O Supply VCCD VSSD VDDD I/O SI2uCpp ly VDDIO0 0.1µF Regulator Sleep Regulator Digital Domain VDDA VDDA Analog VCCA Digital 0.1µF VSSB Regulator Regulators 1µF . VSSA Analog Domain Hibernate Regulator 1 3 O O VDDI I/O Supply VCCD VSSD VDDD I/O Supply VDDI 0.1µF 0.1µF 0.1µF VDDIO1 VDDD VDDIO3 Notes The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-8 on page 12. It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias specifications. With some capacitors, the actual capacitance can decrease considerably when the DC bias (VDDX or VCCX in Figure 6-4) is a significant percentage of the rated working voltage. You can power the device in internally regulated mode, where the voltage applied to the VDDx pins is as high as 5.5 V, and the internal regulators provide the core voltages. In this mode, do not apply power to the VCCx pins, and do not tie the VDDx pins to the VCCx pins. You can also power the device in externally regulated mode, that is, by directly powering the VCCD and VCCA pins. In this configuration, the VDDD pins should be shorted to the VCCD pins and the VDDA pin should be shorted to the VCCA pin. The allowed supply range in this configuration is 1.71V to 1.89V. After power up in this configuration, the internal regulators are on by default, and should be disabled to reduce power consumption. Document Number: 001-11729 Rev. AG Page 31 of 140

® PSoC 3: CY8C38 Family Datasheet 6.2.1 Power Modes Active is the main processing mode. Its functionality is configurable. Each power controllable subsystem is enabled or PSoC 3 devices have four different power modes, as shown in disabled by using separate power configuration template Table6-2 and Table6-3. The power modes allow a design to registers. In alternate active mode, fewer subsystems are easily provide required functionality and processing power while enabled, reducing power. In sleep mode most resources are simultaneously minimizing power consumption and maximizing disabled regardless of the template settings. Sleep mode is battery life in low-power and portable devices. optimized to provide timed sleep intervals and Real Time Clock PSoC 3 power modes, in order of decreasing power functionality. The lowest power mode is hibernate, which retains consumption are: register and SRAM state, but no clocks, and allows wakeup only from I/O pins. Figure 6-5 on page 33 illustrates the allowable Active transitions between power modes. Sleep and hibernate modes Alternate Active should not be entered until all VDDIO supplies are at valid voltage levels. Sleep Hibernate Table 6-2. Power Modes Power Modes Description Entry Condition Wakeup Source Active Clocks Regulator Active Primary mode of operation, all Wakeup, reset, Any interrupt Any All regulators available. peripherals available manual register (programmable) Digital and analog (programmable) entry regulators can be disabled if external regulation used. Alternate Similar to Active mode, and is Manual register Any interrupt Any All regulators available. Active typically configured to have entry (programmable) Digital and analog fewer peripherals active to regulators can be disabled reduce power. One possible if external regulation used. configuration is to use the UDBs for processing, with the CPU turned off Sleep All subsystems automatically Manual register Comparator, ILO/kHzECO Both digital and analog disabled entry PICU, I2C, RTC, regulators buzzed. CTW, LVD Digital and analog regulators can be disabled if external regulation used. Hibernate All subsystems automatically Manual register PICU Only hibernate regulator disabled entry active. Lowest power consuming mode with all peripherals and internal regulators disabled, except hibernate regulator is enabled Configuration and memory contents retained Table 6-3. Power Modes Wakeup Time and Power Consumption Sleep Wakeup Current Code Digital Analog Clock Sources Reset Wakeup Sources Modes Time (typ) Execution Resources Resources Available Sources – 1.2 mA[12] Yes All All All – All Active Alternate – – User All All All – All Active defined <15 µs 1 µA No I2C Comparator ILO/kHzECO Comparator, XRES, LVD, Sleep PICU, I2C, RTC, WDR CTW, LVD Hibernate <100 µs 200 nA No None None None PICU XRES Note 12.Bus clock off. Execute from cache at 6 MHz. See Table 11-2 on page 72. Document Number: 001-11729 Rev. AG Page 32 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 6-5. Power Mode Transitions 6.2.1.5 Wakeup Events Wakeup events are configurable and can come from an interrupt or device reset. A wakeup event restores the system to active Active mode. Firmware enabled interrupt sources include internally generated interrupts, power supervisor, central timewheel, and I/O interrupts. Internal interrupt sources can come from a variety of peripherals, such as analog comparators and UDBs. The Manual central timewheel provides periodic interrupts to allow the Sleep Hibernate system to wake up, poll peripherals, or perform real-time functions. Reset event sources include the external reset I/O pin (XRES), WDT, and precision reset (PRES). 6.2.2 Boost Converter Alternate Applications that use a supply voltage of less than 1.71 V, such Active as solar panels or single cell battery supplies, may use the on-chip boost converter to generate a minimum of 1.8 V supply voltage. The boost converter may also be used in any system 6.2.1.1 Active Mode that requires a higher operating voltage than the supply provides Active mode is the primary operating mode of the device. When such as driving 5.0 V LCD glass in a 3.3 V system. With the in active mode, the active configuration template bits control addition of an inductor, Schottky diode, and capacitors, it which available resources are enabled or disabled. When a produces a selectable output voltage sourcing enough current to resource is disabled, the digital clocks are gated, analog bias operate the PSoC and other on-board components. currents are disabled, and leakage currents are reduced as The boost converter accepts an input voltage V from 0.5 V to BAT appropriate. User firmware can dynamically control subsystem 3.6 V, and can start up with V as low as 0.5 V. The converter BAT power by setting and clearing bits in the active configuration provides a user configurable output voltage of 1.8 to 5.0 V (V ) OUT template. The CPU can disable itself, in which case the CPU is in 100 mV increments. V is typically less than V ; if V is BAT OUT BAT automatically reenabled at the next wakeup event. greater than or equal to V , then V will be slightly less than OUT OUT When a wakeup event occurs, the global mode is always VBAT due to resistive losses in the boost converter. The block can returned to active, and the CPU is automatically enabled, deliver up to 50 mA (IBOOST) depending on configuration to both regardless of its template settings. Active mode is the default the PSoC device and external components. The sum of all global power mode upon boot. current sinks in the design including the PSoC device, PSoC I/O pin loads, and external component loads must be less than the 6.2.1.2 Alternate Active Mode I specified maximum current. BOOST Alternate Active mode is very similar to Active mode. In alternate Four pins are associated with the boost converter: VBAT, VSSB, active mode, fewer subsystems are enabled, to reduce power VBOOST, and IND. The boosted output voltage is sensed at the consumption. One possible configuration is to turn off the CPU VBOOST pin and must be connected directly to the chip’s supply and flash, and run peripherals at full speed. inputs; VDDA, VDDD, and VDDIO if used to power the PSoC device. 6.2.1.3 Sleep Mode The boost converter requires four components in addition to Sleep mode reduces power consumption when a resume time of those required in a non-boost design, as shown in Figure 6-6 on 15 µs is acceptable. The wake time is used to ensure that the page 34. A 22 µF capacitor (C ) is required close to the VBAT regulator outputs are stable enough to directly enter active BAT pin to provide local bulk storage of the battery voltage and mode. provide regulator stability. A diode between the battery and VBAT 6.2.1.4 Hibernate Mode pin should not be used for reverse polarity protection because the diodes forward voltage drop reduces the V voltage. In hibernate mode nearly all of the internal functions are BAT Between the VBAT and IND pins, an inductor of 4.7 µH, 10 µH, disabled. Internal voltages are reduced to the minimal level to or 22 µH is required. The inductor value can be optimized to keep vital systems alive. Configuration state is preserved in increase the boost converter efficiency based on input voltage, hibernate mode and SRAM memory is retained. GPIOs output voltage, temperature, and current. Inductor size is configured as digital outputs maintain their previous values and determined by following the design guidance in this chapter and external GPIO pin interrupt settings are preserved. The device electrical specifications. The inductor must be placed within 1 cm can only return from hibernate mode in response to an external of the VBAT and IND pins and have a minimum saturation I/O interrupt. The resume time from hibernate mode is less than current of 750mA. Between the IND and VBOOST pins, place a 100µs. Schottky diode within 1 cm of the pins. The Schottky diode shall To achieve an extremely low current, the hibernate regulator has have a forward current rating of at least 1.0 A and a reverse limited capacity. This limits the frequency of any signal present voltage of at least 20 V. Connect a 22-µF bulk capacitor on the input pins - no GPIO should toggle at a rate greater than (CBOOST) close to VBOOST to provide regulator output 10 kHz while in hibernate mode. If pins must be toggled at a high stability. It is important to sum the total capacitance connected to rate while in a low power mode, use sleep mode instead. the VBOOST pin and ensure the maximum CBOOST specification is not exceeded. All capacitors must be rated for a minimum of 10 V to minimize capacitive losses due to voltage de-rating. Document Number: 001-11729 Rev. AG Page 33 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 6-6. Application of Boost Converter powering PSoC device PSoC VDDA 0.1 µF 1.0 µF External Load VDDD 0.1 µF 1.0 µF VDDD 0.1 µF 1.0 µF VBOOST Schottky, 1A IND VDDIO0 0.1 µF 4.7 µH Boost VDDIO2 10 µH 0.1 µF Logic 22 µH VDDIO1 VBAT 0.1 µF 22 µF VDDIO3 VSSB 0.1 µF 0.5–3.6 V VSSA 22 µF VSSD All components and values are required The boost converter may also generate a supply that is not used the PSoC device, but with a change to the bulk capacitor directly by the PSoC device. An example of this use case is requirements. A parallel arrangement 22 µF, 1.0 µF, and 0.1 µF boosting a 1.8 V supply to 4.0 V to drive a white LED. If the boost capacitors are all required on the Vout supply and must be converter is not supplying the PSoC devices V , V , and placed within 1 cm of the VBOOST pin to ensure regulator DDA DDD V it must comply with the same design rules as supplying stability. DDIO Figure 6-7. Application of Boost Converter not powering PSoC device V OUT External PSoC Load VDDA VDDD 22 µF 1.0 µF 0.1 µF VDDD VDDA, VDDD, and VBOOST VDDIO connections Schottky, 1A per section 6.2 IND VDDIO0 Power System. 4.7 µH Boost VDDIO2 10 µH Logic 22 µH VDDIO1 VBAT 22 µF VDDIO3 VSSB 0.5–3.6 V VSSA VSSD All components and values are required The switching frequency is set to 400 kHz using an oscillator actively generates a regulated output voltage. In standby mode, integrated into the boost converter. The boost converter can be most boost functions are disabled, thus reducing power operated in two different modes: active and standby. Active consumption of the boost circuit. Only minimal power is provided, mode is the normal mode of operation where the boost regulator typically < 5 µA to power the PSoC device in Sleep mode. The Document Number: 001-11729 Rev. AG Page 34 of 140

® PSoC 3: CY8C38 Family Datasheet boost typically draws 250 µA in active mode and 25 µA in 3.Determine if the desired ambient temperature (T ) range fits A standby mode. The boost operating modes must be used in the ambient temperature operating range based on the T A conjunction with chip power modes to minimize total power range over V and V chart, Figure 11-8 on page 78. If BAT OUT consumption. Table6-4 lists the boost power modes available in the temperature range is not met, modify the operating condi- different chip power modes. tions and return to step 2, or use an external boost regulator. 4.Determine if the desired output current (I ) range fits the Table 6-4. Chip and Boost Power Modes Compatibility OUT output current operating range based on the I range over OUT Chip Power Modes Boost Power Modes VBAT and VOUT chart, Figure 11-9 on page 78. If the output current range is not met, modify the operating conditions and Chip-active or alternate Boost must be operated in its active return to step 2, or use an external boost regulator. active mode mode. 5.Find the allowed inductor values based on the L values Chip-sleep mode Boost can be operated in either active BOOST over V and V chart, Figure 11-10 on page 78. or standby mode. In boost standby BAT OUT mode, the chip must wake up periodi- 6.Based on the allowed inductor values, inductor dimensions, cally for boost active-mode refresh. inductor cost, boost efficiency, and VRIPPLE choose the optimum inductor value for the system. Boost efficiency and Chip-hibernate mode Boost can be operated in its active V typical values are provided in the Efficiency vs V RIPPLE BAT mode. However, it is recommended not and V vs V charts, Figure 11-11 on page 79 through RIPPLE BAT to use the boost in chip hibernate mode Figure 11-14 on page 79. In general, if high efficiency and low due to the higher current consumption V are most important, then the highest allowed inductor RIPPLE in boost active mode. value should be used. If low inductor cost or small inductor size are most important, then one of the smaller allowed 6.2.2.1 Boost Firmware Requirements inductor values should be used. If the allowed inductor(s) efficiency, V , cost or dimensions are not acceptable for To ensure boost inrush current is within specification at startup, RIPPLE the application than an external boost regulator should be the Enable Fast IMO During Startup value must be unchecked used. in the PSoC Creator IDE. The Enable Fast IMO During Startup option is found in PSoC Creator in the design wide resources 6.3 Reset (cydwr) file System tab. Un-checking this option configures the device to run at 12 MHz vs 48 MHz during startup while CY8C38 has multiple internal and external reset sources configuring the device. The slower clock speed results in available. The reset sources are: reduced current draw through the boost circuit. Power source monitoring – The analog and digital power 6.2.2.2 Boost Design Process voltages, VDDA, VDDD, VCCA, and VCCD are monitored in several different modes during power up, active mode, and Correct operation of the boost converter requires specific sleep mode (buzzing). If any of the voltages goes outside component values determined for each designs unique predetermined ranges then a reset is generated. The monitors operating conditions. The C capacitor, Inductor, Schottky BAT are programmable to generate an interrupt to the processor diode, and C capacitor components are required with the BOOST under certain conditions before reaching the reset thresholds. values specified in the electrical specifications, Table 11-7 on page 78. The only variable component value is the inductor External – The device can be reset from an external source by LBOOST which is primarily sized for correct operation of the boost pulling the reset pin (XRES) low. The XRES pin includes an across operating conditions and secondarily for efficiency. internal pull-up to VDDIO1. VDDD, VDDA, and VDDIO1 must Additional operating region constraints exist for VOUT, VBAT, IOUT, all have voltage applied before the part comes out of reset. and T . A Watchdog timer – A watchdog timer monitors the execution of The following steps must be followed to determine boost instructions by the processor. If the watchdog timer is not reset converter operating parameters and LBOOST value. by firmware within a certain period of time, the watchdog timer 1.Choose desired V , V , T , and I operating condition generates a reset. BAT OUT A OUT ranges for the application. Software – The device can be reset under program control. 2.Determine if V and V ranges fit the boost operating BAT OUT range based on the T range over V and V chart, A BAT OUT Figure 11-8 on page 78. If the operating ranges are not met, modify the operating conditions or use an external boost regulator. Document Number: 001-11729 Rev. AG Page 35 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 6-8. Resets ALVI, DLVI, AHVI – Analog/digital low voltage interrupt, analog high voltage interrupt VDDD VDDA Interrupt circuits are available to detect when VDDA and VDDD go outside a voltage range. For AHVI, VDDA is Power compared to a fixed trip level. For ALVI and DLVI, VDDA and Processor Voltage VDDD are compared to trip levels that are programmable, as Interrupt Level listed in Table6-5. ALVI and DLVI can also be configured to Monitors generate a device reset instead of an interrupt. Reset Pin Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High External Voltage Interrupt Reset System Reset Controller Reset Normal Voltage Interrupt Supply Available Trip Settings Range DLVI VDDD 1.71V–5.5V 1.70 V–5.45V in 250 mV Watchdog increments Timer ALVI VDDA 1.71V–5.5V 1.70 V–5.45V in 250 mV increments AHVI VDDA 1.71V–5.5V 5.75V Software Reset The monitors are disabled until after IPOR. During sleep mode Register these circuits are periodically activated (buzzed). If an interrupt occurs during buzzing then the system first enters its wakeup The term device reset indicates that the processor as well as sequence. The interrupt is then recognized and may be analog and digital peripherals and registers are reset. serviced. A reset status register shows some of the resets or power voltage The buzz frequency is adjustable, and should be set to be less monitoring interrupts. The program may examine this register to than the minimum time that any voltage is expected to be out detect and report certain exception conditions. This register is of range. For details on how to adjust the buzz frequency, see cleared after a power-on reset. For details see the Technical the TRM. Reference Manual. 6.3.1.2 Other Reset Sources 6.3.1 Reset Sources XRES – External reset PSoC 3 has either a single GPIO pin that is configured as an 6.3.1.1 Power Voltage Level Monitors external reset or a dedicated XRES pin. Either the dedicated IPOR – Initial power-on reset XRES pin or the GPIO pin, if configured, holds the part in reset while held active (low). The response to an XRES is the same At initial power on, IPOR monitors the power voltages VDDD, as to an IPOR reset. VDDA, VCCD and VCCA. The trip level is not precise. It is set to approximately 1 volt, which is below the lowest specified After XRES has been deasserted, at least 10 µs must elapse operating voltage but high enough for the internal circuits to be before it can be reasserted. reset and to hold their reset state. The monitor generates a The external reset is active low. It includes an internal pull-up reset pulse that is at least 150 ns wide. It may be much wider resistor. XRES is active during sleep and hibernate modes. if one or more of the voltages ramps up slowly. SRES – Software reset After boot, the IPOR circuit is disabled and voltage supervision A reset can be commanded under program control by setting is handed off to the precise low-voltage reset (PRES) circuit. a bit in the software reset register. This is done either directly by the program or indirectly by DMA access. The response to PRES – Precise low voltage reset a SRES is the same as after an IPOR reset. This circuit monitors the outputs of the analog and digital Another register bit exists to disable this function. internal regulators after power up. The regulator outputs are compared to a precise reference voltage. The response to a WRES – Watchdog timer reset PRES trip is identical to an IPOR reset. The watchdog reset detects when the software program is no longer being executed correctly. To indicate to the watchdog In normal operating mode, the program cannot disable the timer that it is running correctly, the program must periodically digital PRES circuit. The analog regulator can be disabled, reset the timer. If the timer is not reset before a user-specified which also disables the analog portion of the PRES. The PRES amount of time, then a reset is generated. circuit is disabled automatically during sleep and hibernate modes, with one exception: During sleep mode the regulators Note IPOR disables the watchdog function. The program must are periodically activated (buzzed) to provide supervisory enable the watchdog function at an appropriate point in the services and to reduce wakeup time. At these times the PRES code by setting a register bit. When this bit is set, it cannot be circuit is also buzzed to allow periodic voltage monitoring. cleared again except by an IPOR power on reset event. Document Number: 001-11729 Rev. AG Page 36 of 140

® PSoC 3: CY8C38 Family Datasheet 6.4 I/O System and Routing Slew rate controlled digital output drive mode PSoC I/Os are extremely flexible. Every GPIO has analog and Access port control and configuration registers on either port basis or pin basis digital I/O capability. All I/Os have a large number of drive modes, Separate port read (PS) and write (DR) data registers to avoid which are set at POR. PSoC also provides up to four individual read modify write errors I/O voltage domains through the VDDIO pins. Special functionality on a pin by pin basis There are two types of I/O pins on every device; those with USB Additional features only provided on the GPIO pins: provide a third type. Both GPIO and SIO provide similar digital functionality. The primary differences are their analog capability LCD segment drive on LCD equipped devices and drive strength. Devices that include USB also provide two CapSense[13] USBIO pins that support specific USB functionality as well as Analog input and output capability limited GPIO capability. Continuous 100 µA clamp current capability All I/O pins are available for use as digital inputs and outputs for Standard drive strength down to 1.7V both the CPU and digital peripherals. In addition, all I/O pins can Additional features only provided on SIO pins: generate an interrupt. The flexible and advanced capabilities of Higher drive strength than GPIO the PSoC I/O, combined with any signal to any pin routability, Hot swap capability (5V tolerance at any operating VDD) greatly simplify circuit design and board layout. All GPIO pins can Programmable and regulated high input and output drive be used for analog input, CapSense[13], and LCD segment drive, levels down to 1.2V while SIO pins are used for voltages in excess of VDDA and for No analog input, CapSense, or LCD capability programmable output voltages. Over voltage tolerance up to 5.5V Features supported by both GPIO and SIO: SIO can act as a general purpose analog comparator User programmable port reset state USBIO features: Separate I/O supplies and voltages for up to four groups of I/O Full speed USB 2.0 compliant I/O Digital peripherals use DSI to connect the pins Highest drive strength for general purpose use Input or output or both for CPU and DMA Input, output, or both for CPU and DMA Eight drive modes Input, output, or both for digital peripherals Every pin can be an interrupt source configured as rising Digital output (CMOS) drive mode edge, falling edge or both edges. If required, level sensitive Each pin can be an interrupt source configured as rising interrupts are supported through the DSI edge, falling edge, or both edges Dedicated port interrupt vector for each port Note 13.GPIOs with opamp outputs are not recommended for use with CapSense. Document Number: 001-11729 Rev. AG Page 37 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 6-9. GPIO Block Diagram Digital Input Path Naming Convention PRT[x]CTL ‘x’ = Port Number PRT[x]DBL_SYNC_IN ‘y’ = Pin Number PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Input Buffer Disable Interrupt Pin Interrupt Signal Logic PICU[x]INTSTAT Digital Output Path PRT[x]SLW PRT[x]SYNC_OUT VddioVddio PRT[x]DR 0 Digital System Output In 1 Vddio PRT[x]BYP PRT[x]DM2 Drive Slew PRT[x]DM1 Logic Cntl PIN PRT[x]DM0 Bidirectional Control PRT[x]BIE OE Analog 1 0 1 0 Capsense Global Control 1 CAPS[x]CFG1 Switches PRT[x]AG Analog Global PRT[x]AMUX Analog Mux LCD Display Data PRT[x]LCD_COM_SEG Logic & MUX PRT[x]LCD_EN LCD Bias Bus 5 Document Number: 001-11729 Rev. AG Page 38 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 6-10. SIO Input/Output Block Diagram Digital Input Path Naming Convention PRT[x]SIO_HYST_EN ‘x’ = Port Number PRT[x]SIO_DIFF Buffer ‘y’ = Pin Number Reference Level Thresholds PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Input Buffer Disable Interrupt Pin Interrupt Signal Logic PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG Driver PRT[x]SLW Vhigh PRT[x]SYNC_OUT PRT[x]DR 0 Digital System Output In 1 PRT[x]BYP PRT[x]DM2 Drive PRT[x]DM1 Logic Slew PIN Cntl PRT[x]DM0 Bidirectional Control PRT[x]BIE OE Figure 6-11. USBIO Block Diagram Digital Input Path Naming Convention ‘y’ = Pin Number USB Receiver Circuitry PRT[15]DBL_SYNC_IN PRT[15]PS[6,7] USBIO_CR1[0,1] Digital System Input PICU[15]INTTYPE[y] PICU[15]INTSTAT Interrupt Pin Interrupt Signal Logic PICU[15]INTSTAT Digital Output Path PRT[15]SYNC_OUT USBIO_CR1[5] USB or I/O D+ pin only USBIO_CR1[2] D+ 1.5 k Vddd VdddVddd USB SIE Control for USB Mode Vddd PRT[15]DR1[7,6] 0 Digital System Output 1 In Drive 5 k 1.5 k PRT[15]BYP Logic PIN PRT[15]DM0[6] D+ Open Drain PRT[15]DM0[7] D- Open Drain PRT[15]DM1[6] D+ 5 k PRT[15]DM1[7] D- 5 k Document Number: 001-11729 Rev. AG Page 39 of 140

® PSoC 3: CY8C38 Family Datasheet 6.4.1 Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table6-6. Three configuration bits are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure6-12 depicts a simplified pin view based on each of the eight drive modes. Table6-6 shows the I/O pin’s drive state based on the port data register value or digital array signal if bypass mode is selected. Note that the actual I/O pin voltage is determined by a combination of the selected drive mode and the load at the pin. For example, if a GPIO pin is configured for resistive pull-up mode and driven high while the pin is floating, the voltage measured at the pin is a high logic state. If the same GPIO pin is externally tied to ground then the voltage unmeasured at the pin is a low logic state. Figure 6-12. Drive Mode VDD VDD OInut Pin OInut Pin OInut Pin OInut Pin An An An An 0. High Impedance 1. High Impedance 2. Resistive Pull-Up 3. Resistive Pull-Down Analog Digital VDD VDD VDD OInut Pin OInut Pin OInut Pin OInut Pin An An An An 4. Open Drain, 5. Open Drain, 6. Strong Drive 7. Resistive Pull-Up Drives Low Drives High and Pull-Down The ‘Out’ connection is driven from either the Digital System (when the Digital Output terminal is connected) or the Data Register (when HW connection is disabled). The ‘In’ connection drives the Pin State register, and the Digital System if the Digital Input terminal is enabled and connected. The ‘An’ connection connects to the Analog System. Table 6-6. Drive Modes Diagram Drive Mode PRTxDM2 PRTxDM1 PRTxDM0 PRTxDR = 1 PRTxDR = 0 0 High impedance analog 0 0 0 High Z High Z 1 High Impedance digital 0 0 1 High Z High Z 2 Resistive pull-up[14] 0 1 0 Res High (5K) Strong Low 3 Resistive pull-down[14] 0 1 1 Strong High Res Low (5K) 4 Open drain, drives low 1 0 0 High Z Strong Low 5 Open drain, drive high 1 0 1 Strong High High Z 6 Strong drive 1 1 0 Strong High Strong Low 7 Resistive pull-up and pull-down[14] 1 1 1 Res High (5K) Res Low (5K) Note 14.Resistive pull-up and pull-down are not available with SIO in regulated output mode. Document Number: 001-11729 Rev. AG Page 40 of 140

® PSoC 3: CY8C38 Family Datasheet The USBIO pins (P15[7] and P15[6]), when enabled for I/O mode, have limited drive mode control. The drive mode is set using the PRT15.DM0[7, 6] register. A resistive pull option is also available at the USBIO pins, which can be enabled using the PRT15.DM1[7, 6] register. When enabled for USB mode, the drive mode control has no impact on the configuration of the USB pins. Unlike the GPIO and SIO configurations, the port wide configuration registers do not configure the USB drive mode bits. Table6-7 shows the drive mode configuration for the USBIO pins. Table 6-7. USBIO Drive Modes (P15[7] and P15[6]) PRT15.DM1[7,6] PRT15.DM0[7,6] PRT15.DR[7,6] = 1 PRT15.DR[7,6] = 0 Description Pull up enable Drive Mode enable 0 0 High Z Strong Low Open Drain, Strong Low 0 1 Strong High Strong Low Strong Outputs 1 0 Res High (5k) Strong Low Resistive Pull Up, Strong Low 1 1 Strong High Strong Low Strong Outputs High impedance analog 6.4.2 Pin Registers The default reset state with both the output driver and digital Registers to configure and interact with pins come in two forms input buffer turned off. This prevents any current from flowing that may be used interchangeably. in the I/O’s digital input buffer due to a floating voltage. This All I/O registers are available in the standard port form, where state is recommended for pins that are floating or that support each bit of the register corresponds to one of the port pins. This an analog voltage. High impedance analog pins do not provide register form is efficient for quickly reconfiguring multiple port digital input functionality. pins at the same time. To achieve the lowest chip current in sleep modes, all I/Os I/O registers are also available in pin form, which combines the must either be configured to the high impedance analog mode, eight most commonly used port register bits into a single register or have their pins driven to a power supply rail by the PSoC for each pin. This enables very fast configuration changes to device or by external circuitry. individual pins with a single register write. High impedance digital 6.4.3 Bidirectional Mode The input buffer is enabled for digital signal input. This is the High speed bidirectional capability allows pins to provide both standard high impedance (High Z) state recommended for the high impedance digital drive mode for input signals and a digital inputs. second user selected drive mode such as strong drive (set using Resistive pull-up or resistive pull-down PRT×DM[2:0] registers) for output signals on the same pin, based on the state of an auxiliary control bus signal. The Resistive pull-up or pull-down, respectively, provides a series bidirectional capability is useful for processor busses and resistance in one of the data states and strong drive in the communications interfaces such as the SPI Slave MISO pin that other. Pins can be used for digital input and output in these requires dynamic hardware control of the output buffer. modes. Interfacing to mechanical switches is a common application for these modes. Resistive pullup and pull-down The auxiliary control bus routes up to 16 UDB or digital peripheral are not available with SIO in regulated output mode. generated output enable signals to one or more pins. Open drain, drives high and open drain, drives low 6.4.4 Slew Rate Limited Mode Open drain modes provide high impedance in one of the data GPIO and SIO pins have fast and slow output slew rate options states and strong drive in the other. Pins can be used for digital for strong and open drain drive modes, not resistive drive modes. input and output in these modes. A common application for Because it results in reduced EMI, the slow edge rate option is these modes is driving the I2C bus signal lines. recommended for signals that are not speed critical, generally less than 1 MHz. The fast slew rate is for signals between 1 MHz Strong drive and 33 MHz. The slew rate is individually configurable for each Provides a strong CMOS output drive in either high or low pin, and is set by the PRT×SLW registers. state. This is the standard output mode for pins. Strong Drive mode pins must not be used as inputs under normal circumstances. This mode is often used to drive digital output signals or external FETs. Resistive pull-up and pull-down Similar to the resistive pull-up and resistive pull-down modes except the pin is always in series with a resistor. The high data state is pull-up while the low data state is pull-down. This mode is most often used when other signals that may cause shorts can drive the bus. Resistive pullup and pull-down are not available with SIO in regulated output mode. Document Number: 001-11729 Rev. AG Page 41 of 140

® PSoC 3: CY8C38 Family Datasheet 6.4.5 Pin Interrupts 6.4.9 CapSense All GPIO and SIO pins are able to generate interrupts to the This section applies only to GPIO pins. All GPIO pins may be system. All eight pins in each port interface to their own Port used to create CapSense buttons and sliders[15]. See the Interrupt Control Unit (PICU) and associated interrupt vector. “CapSense” section on page63 for more information. Each pin of the port is independently configurable to detect rising edge, falling edge, both edge interrupts, or to not generate an 6.4.10 LCD Segment Drive interrupt. This section applies only to GPIO pins. All GPIO pins may be Depending on the configured mode for each pin, each time an used to generate Segment and Common drive signals for direct interrupt event occurs on a pin, its corresponding status bit of the glass drive of LCD glass. See the “LCD Direct Drive” section on interrupt status register is set to ‘1’ and an interrupt request is page62 for details. sent to the interrupt controller. Each PICU has its own interrupt vector in the interrupt controller and the pin status register 6.4.11 Adjustable Output Level providing easy determination of the interrupt source down to the This section applies only to SIO pins. SIO port pins support the pin level. ability to provide a regulated high output level for interface to Port pin interrupts remain active in all sleep modes allowing the external signals that are lower in voltage than the SIO’s PSoC device to wake from an externally generated interrupt. respective VDDIO. SIO pins are individually configurable to While level sensitive interrupts are not directly supported; UDB output either the standard VDDIO level or the regulated output, provide this functionality to the system when needed. which is based on an internally generated reference. Typically a voltage DAC (VDAC) is used to generate the reference (see 6.4.6 Input Buffer Mode Figure 6-13). The “DAC” section on page64 has more details on VDAC use and reference routing to the SIO pins. Resistive GPIO and SIO input buffers can be configured at the port level pullup and pull-down drive modes are not available with SIO in for the default CMOS input thresholds or the optional LVTTL regulated output mode. input thresholds. All input buffers incorporate Schmitt triggers for input hysteresis. Additionally, individual pin input buffers can be 6.4.12 Adjustable Input Level disabled in any drive mode. This section applies only to SIO pins. SIO pins by default support 6.4.7 I/O Power Supplies the standard CMOS and LVTTL input levels but also support a differential mode with programmable levels. SIO pins are Up to four I/O pin power supplies are provided depending on the grouped into pairs. Each pair shares a reference generator block device and package. Each I/O supply must be less than or equal which, is used to set the digital input buffer reference level for to the voltage on the chip’s analog (VDDA) pin. This feature interface to external signals that differ in voltage from VDDIO. allows users to provide different I/O voltage levels for different The reference sets the pins voltage threshold for a high logic pins on the device. Refer to the specific device package pinout level (see Figure 6-13). Available input thresholds are: to determine VDDIO capability for a given port and pin. The SIO port pins support an additional regulated high output capability, 0.5 VDDIO as described in Adjustable Output Level. 0.4 VDDIO 6.4.8 Analog Connections 0.5 VREF These connections apply only to GPIO pins. All GPIO pins may be used as analog inputs or outputs. The analog voltage present VREF on the pin must not exceed the VDDIO supply voltage to which Typically a voltage DAC (VDAC) generates the VREF reference. the GPIO belongs. Each GPIO may connect to one of the analog “DAC” section on page64 has more details on VDAC use and global busses or to one of the analog mux buses to connect any reference routing to the SIO pins. pin to any internal analog resource such as ADC or comparators. In addition, select pins provide direct connections to specific analog features such as the high current DACs or uncommitted opamps. Note 15.GPIOs with opamp outputs are not recommended for use with CapSense. Document Number: 001-11729 Rev. AG Page 42 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 6-13. SIO Reference for Input and Output There are no current limitations for the SIO pins as they present a high impedance load to the external circuit where VDDIO < V < IN Input Path 5.5V. The GPIO pins must be limited to 100 µA using a current limiting Digital resistor. GPIO pins clamp the pin voltage to approximately one Input diode above the VDDIO supply where VDDIO < VIN < VDDA. Vinref In case of a GPIO pin configured for analog input/output, the analog voltage on the pin must not exceed the VDDIO supply voltage to which the GPIO belongs. A common application for this feature is connection to a bus such as I2C where different devices are running from different supply SIO_Ref Reference voltages. In the I2C case, the PSoC chip is configured into the Generator Open Drain, Drives Low mode for the SIO pin. This allows an PIN external pull-up to pull the I2C bus voltage above the PSoC pin supply. For example, the PSoC chip could operate at 1.8V, and Voutref an external device could run from 5V. Note that the SIO pin’s V Output Path IH Driver and VIL levels are determined by the associated VDDIO supply Vhigh pin. The SIO pin must be in one of the following modes: 0 (high impedance analog), 1 (high impedance digital), or 4 (open drain drives low). See Figure6-12 for details. Absolute maximum ratings for the device must be observed for all I/O pins. 6.4.16 Reset Configuration Digital Drive Output Logic While reset is active all I/Os are reset to and held in the High Impedance Analog state. After reset is released, the state can be reprogrammed on a port-by-port basis to pull-down or pull-up. To ensure correct reset operation, the port reset configuration data is stored in special nonvolatile registers. The stored reset data is automatically transferred to the port reset configuration registers at reset release. 6.4.13 SIO as Comparator 6.4.17 Low-Power Functionality This section applies only to SIO pins. The adjustable input level In all low-power modes the I/O pins retain their state until the part feature of the SIOs as explained in the Adjustable Input Level is awakened and changed or reset. To awaken the part, use a section can be used to construct a comparator. The threshold for pin interrupt, because the port interrupt logic continues to the comparator is provided by the SIO's reference generator. The function in all low-power modes. reference generator has the option to set the analog signal routed through the analog global line as threshold for the 6.4.18 Special Pin Functionality comparator. Note that a pair of SIO pins share the same threshold. The digital input path in Figure 6-10 on page 39 Some pins on the device include additional special functionality illustrates this functionality. In the figure, ‘Reference level’ is the in addition to their GPIO or SIO functionality. The specific special analog signal routed through the analog global. The hysteresis function pins are listed in Pinouts on page 6. The special features feature can also be enabled for the input buffer of the SIO, which are: increases noise immunity for the comparator. Digital 6.4.14 Hot Swap 4- to 25-MHz crystal oscillator 32.768-kHz crystal oscillator This section applies only to SIO pins. SIO pins support ‘hot swap’ Wake from sleep on I2C address match. Any pin can be used capability to plug into an application without loading the signals for I2C if wake from sleep is not required. that are connected to the SIO pins even when no power is JTAG interface pins applied to the PSoC device. This allows the unpowered PSoC to SWD interface pins maintain a high impedance load to the external device while also preventing the PSoC from being powered through a SIO pin’s SWV interface pins protection diode. External reset Analog Powering the device up or down while connected to an operational I2C bus may cause transient states on the SIO pins. Opamp inputs and outputs The overall I2C bus design should take this into account. High current IDAC outputs External reference inputs 6.4.15 Over Voltage Tolerance 6.4.19 JTAG Boundary Scan All I/O pins provide an over voltage tolerance feature at any The device supports standard JTAG boundary scan chains on all operating V . DD I/O pins for board level test. Document Number: 001-11729 Rev. AG Page 43 of 140

® PSoC 3: CY8C38 Family Datasheet 7. Digital Subsystem 7.1 Example Peripherals The flexibility of the CY8C38 family’s UDBs and analog blocks The digital programmable system creates application specific allow the user to create a wide range of components combinations of both standard and advanced digital peripherals (peripherals). The most common peripherals were built and and custom logic functions. These peripherals and logic are then characterized by Cypress and are shown in the PSoC Creator interconnected to each other and to any pin on the device, component catalog, however, users may also create their own providing a high level of design flexibility and IP security. custom components using PSoC Creator. Using PSoC Creator, The features of the digital programmable system are outlined users may also create their own components for reuse within here to provide an overview of capabilities and architecture. You their organization, for example sensor interfaces, proprietary do not need to interact directly with the programmable digital algorithms, and display interfaces. system at the hardware and register level. PSoC Creator The number of components available through PSoC Creator is provides a high level schematic capture graphical interface to too numerous to list in the data sheet, and the list is always automatically place and route resources similar to PLDs. growing. An example of a component available for use in The main components of the digital programmable system are: CY8C38 family, but, not explicitly called out in this data sheet is the UART component. UDB – These form the core functionality of the digital programmable system. UDBs are a collection of uncommitted 7.1.1 Example Digital Components logic (PLD) and structural logic (Datapath) optimized to create The following is a sample of the digital components available in all common embedded peripherals and customized PSoC Creator for the CY8C38 family. The exact amount of functionality that are application or design specific. hardware resources (UDBs, routing, RAM, flash) used by a Universal digital block array – UDB blocks are arrayed within component varies with the features selected in PSoC Creator for a matrix of programmable interconnect. The UDB array the component. structure is homogeneous and allows for flexible mapping of Communications digital functions onto the array. The array supports extensive and flexible routing interconnects between UDBs and the I2C Digital System Interconnect. UART SPI Digital system interconnect (DSI) – Digital signals from UDBs, fixed function peripherals, I/O pins, interrupts, DMA, and other Functions system core signals are attached to the digital system EMIF interconnect to implement full featured device connectivity. The PWMs DSI allows any digital function to any pin or other feature Timers routability when used with the universal digital block array. Counters Figure 7-1. CY8C38 Digital Programmable Architecture Logic NOT Digital Core System and Fixed Function Peripherals OR XOR O Port O Port AND I DSI Routing Interface I 7.1.2 Example Analog Components UDB UDB UDB UDB The following is a sample of the analog components available in PSoC Creator for the CY8C38 family. The exact amount of UDB UDB UDB UDB UDB Array UUDDBB UUDDBB UUDDBB UUDDBB UDB Array hbCayre rada wctooarmr efop rroe tnsheoenu ctr ocvemasrpi e(oSsn Cew/niCtth.T t hbelo cfekast,u rroeust isnegl,e RctAedM ,in f lPasSho)C u sed UDB UDB UDB UDB Amplifiers UDB UDB UDB UDB TIA DSI Routing Interface PGA ort ort opamp P P IO IO ADC Digital Core System and Fixed Function Peripherals Delta-sigma DACs Current Voltage PWM Comparators Mixers Document Number: 001-11729 Rev. AG Page 44 of 140

® PSoC 3: CY8C38 Family Datasheet 7.1.3 Example System Function Components 7.1.4.2 Component Catalog The following is a sample of the system function components The component catalog is a repository of reusable design available in PSoC Creator for the CY8C38 family. The exact elements that select device functionality and customize your amount of hardware resources (UDBs, DFB taps, SC/CT blocks, PSoC device. It is populated with an impressive selection of routing, RAM, flash) used by a component varies with the content; from simple primitives such as logic gates and device features selected in PSoC Creator for the component. registers, through the digital timers, counters and PWMs, plus analog components such as ADC, DACs, and filters, and CapSense communication protocols, such as I2C, USB, and CAN. See LCD drive Example Peripherals on page 44 for more details about available peripherals. All content is fully characterized and carefully LCD control documented in data sheets with code examples, AC/DC Filters specifications, and user code ready APIs. 7.1.4.3 Design Reuse 7.1.4 Designing with PSoC Creator The symbol editor gives you the ability to develop reusable 7.1.4.1 More Than a Typical IDE components that can significantly reduce future design time. Just A successful design tool allows for the rapid development and draw a symbol and associate that symbol with your proven deployment of both simple and complex designs. It reduces or design. PSoC Creator allows for the placement of the new eliminates any learning curve. It makes the integration of a new symbol anywhere in the component catalog along with the design into the production stream straightforward. content provided by Cypress. You can then reuse your content as many times as you want, and in any number of projects, PSoC Creator is that design tool. without ever having to revisit the details of the implementation. PSoC Creator is a full featured Integrated Development Environment (IDE) for hardware and software design. It is 7.1.4.4 Software Development optimized specifically for PSoC devices and combines a modern, Anchoring the tool is a modern, highly customizable user powerful software development platform with a sophisticated interface. It includes project management and integrated editors graphical design tool. This unique combination of tools makes for C and assembler source code, as well the design entry tools. PSoC Creator the most flexible embedded design platform Project build control leverages compiler technology from top available. commercial vendors such as ARM® Limited, Keil™, and Graphical design entry simplifies the task of configuring a CodeSourcery (GNU). Free versions of Keil C51 and GNU C particular part. You can select the required functionality from an Compiler (GCC) for ARM, with no restrictions on code size or end extensive catalog of components and place it in your design. All product distribution, are included with the tool distribution. components are parameterized and have an editor dialog that Upgrading to more optimizing compilers is a snap with support allows you to tailor functionality to your needs. for the professional Keil C51 product and ARM RealView™ PSoC Creator automatically configures clocks and routes the I/O compiler. to the selected pins and then generates APIs to give the 7.1.4.5 Nonintrusive Debugging application complete control over the hardware. Changing the PSoC device configuration is as simple as adding a new With JTAG (4-wire) and SWD (2-wire) debug connectivity component, setting its parameters, and rebuilding the project. available on all devices, the PSoC Creator debugger offers full control over the target device with minimum intrusion. At any stage of development you are free to change the Breakpoints and code execution commands are all readily hardware configuration and even the target processor. To available from toolbar buttons and an impressive lineup of retarget your application (hardware and software) to new windows—register, locals, watch, call stack, memory and devices, even from 8- to 32-bit families, just select the new peripherals—make for an unparalleled level of visibility into the device and rebuild. system. You also have the ability to change the C compiler and evaluate PSoC Creator contains all the tools necessary to complete a an alternative. Components are designed for portability and are design, and then to maintain and extend that design for years to validated against all devices, from all families, and against all come. All steps of the design flow are carefully integrated and supported tool chains. Switching compilers is as easy as editing optimized for ease-of-use and to maximize productivity. the from the project options and rebuilding the application with no errors from the generated APIs or boot code. Document Number: 001-11729 Rev. AG Page 45 of 140

® PSoC 3: CY8C38 Family Datasheet 7.2 Universal Digital Block Status and control module – The primary role of this block is to provide a way for CPU firmware to interact and synchronize The UDB represents an evolutionary step to the next generation with UDB operation. of PSoC embedded digital peripheral functionality. The architecture in first generation PSoC digital blocks provides Clock and reset module – This block provides the UDB clocks coarse programmability in which a few fixed functions with a and reset selection and control. small number of options are available. The new UDB architecture is the optimal balance between configuration 7.2.1 PLD Module granularity and efficient implementation. A cornerstone of this The primary purpose of the PLD blocks is to implement logic approach is to provide the ability to customize the devices digital expressions, state machines, sequencers, lookup tables, and operation to match application requirements. decoders. In the simplest use model, consider the PLD blocks as To achieve this, UDBs consist of a combination of uncommitted a standalone resource onto which general purpose RTL is logic (PLD), structured logic (Datapath), and a flexible routing synthesized and mapped. The more common and efficient use scheme to provide interconnect between these elements, I/O model is to create digital functions from a combination of PLD connections, and other peripherals. UDB functionality ranges and datapath blocks, where the PLD implements only the from simple self contained functions that are implemented in one random logic and state portion of the function while the datapath UDB, or even a portion of a UDB (unused resources are (ALU) implements the more structured elements. available for other functions), to more complex functions that Figure 7-3. PLD 12C4 Structure require multiple UDBs. Examples of basic functions are timers, counters, CRC generators, PWMs, dead band generators, and P P P P P P P P T T T T T T T T communications functions, such as UARTs, SPI, and I2C. Also, 0 1 2 3 4 5 6 7 IN0 TC TC TC TC TC TC TC TC the PLD blocks and connectivity provide full featured general IN1 TC TC TC TC TC TC TC TC purpose programmable logic within the limits of the available resources. IN2 TC TC TC TC TC TC TC TC IN3 TC TC TC TC TC TC TC TC Figure 7-2. UDB Block Diagram IN4 TC TC TC TC TC TC TC TC IN5 TC TC TC TC TC TC TC TC AND PLD IN6 TC TC TC TC TC TC TC TC Array Chaining IN7 TC TC TC TC TC TC TC TC PLD PLD IN8 TC TC TC TC TC TC TC TC Clock 12C4 12C4 IN9 TC TC TC TC TC TC TC TC and Reset (8 PTs) (8 PTs) IN10 TC TC TC TC TC TC TC TC Control IN11 TC TC TC TC TC TC TC TC Carry In Status and Control Datapath T T T T T T T T MC0 OUT0 Datapath T T T T T T T T MC1 OUT1 Chaining T T T T T T T T MC2 OUT2 T T T T T T T T MC3 OUT3 Carry Out OR Routing Channel Array The main component blocks of the UDB are: One 12C4 PLD block is shown in Figure7-3. This PLD has 12 inputs, which feed across eight product terms. Each product term PLD blocks – There are two small PLDs per UDB. These blocks (AND function) can be from 1 to 12 inputs wide, and in a given take inputs from the routing array and form registered or product term, the true (T) or complement (C) of each input can combinational sum-of-products logic. PLDs are used to be selected. The product terms are summed (OR function) to implement state machines, state bits, and combinational logic create the PLD outputs. A sum can be from 1 to 8 product terms equations. PLD configuration is automatically generated from wide. The 'C' in 12C4 indicates that the width of the OR gate (in graphical primitives. this case 8) is constant across all outputs (rather than variable as in a 22V10 device). This PLA like structure gives maximum Datapath module – This 8-bit wide datapath contains structured flexibility and insures that all inputs and outputs are permutable logic to implement a dynamically configurable ALU, a variety for ease of allocation by the software tools. There are two 12C4 of compare configurations and condition generation. This block PLDs in each UDB. also contains input/output FIFOs, which are the primary parallel data interface between the CPU/DMA system and the UDB. Document Number: 001-11729 Rev. AG Page 46 of 140

® PSoC 3: CY8C38 Family Datasheet 7.2.2 Datapath Module The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band generators and many others. Figure 7-4. Datapath Top Level PHUB System Bus R/W Access to All Registers F1 M FIFOs ProgIrnapmRuomt ufartoibnmlge 6MInupxuets Dynamic Configuration RA8 Word X 16 Bit Datapath Control Data ReDDFg001isters To/FroDDAAm0101 Conditions: 2 Compares, 2 Zero Detect, 2 Ones Detect Overflow Detect OMuutxTpeous/t6F romOPRrououtgptirunatgm tom able Previous Chaining Next Datapath Datapath A1 Accumulators A0 PI Parallel Input/Output (To/From Programmable Routing) PO ALU Shift Mask 7.2.2.1 Working Registers 7.2.2.2 Dynamic Configuration RAM The datapath contains six primary working registers, which are Dynamic configuration is the ability to change the datapath accessed by CPU firmware or DMA during normal operation. function and internal configuration on a cycle-by-cycle basis, under sequencer control. This is implemented using the 8-word Table 7-1. Working Datapath Registers × 16-bit configuration RAM, which stores eight unique 16-bit Name Function Description wide configurations. The address input to this RAM controls the sequence, and can be routed from any block connected to the A0 and A1 Accumulators These are sources and sinks for UDB routing matrix, most typically PLD logic, I/O pins, or from the ALU and also sources for the the outputs of this or other datapath blocks. compares. D0 and D1 Data Registers These are sources for the ALU ALU and sources for the compares. The ALU performs eight general purpose functions. They are: F0 and F1 FIFOs These are the primary interface Increment to the system bus. They can be a Decrement data source for the data registers Add and accumulators or they can capture data from the Subtract accumulators or ALU. Each FIFO Logical AND is four bytes deep. Logical OR Logical XOR Pass, used to pass a value through the ALU to the shift register, mask, or another UDB register. Document Number: 001-11729 Rev. AG Page 47 of 140

® PSoC 3: CY8C38 Family Datasheet Independent of the ALU operation, these functions are available: 7.2.2.7 Chaining Shift left The datapath can be configured to chain conditions and signals such as carries and shift data with neighboring datapaths to Shift right create higher precision arithmetic, shift, CRC/PRS functions. Nibble swap 7.2.2.8 Time Multiplexing Bitwise OR mask In applications that are over sampled, or do not need high clock rates, the single ALU block in the datapath can be efficiently 7.2.2.3 Conditionals shared with two sets of registers and condition generators. Carry and shift out data from the ALU are registered and can be Each datapath has two compares, with bit masking options. selected as inputs in subsequent cycles. This provides support Compare operands include the two accumulators and the two for 16-bit functions in one (8-bit) datapath. data registers in a variety of configurations. Other conditions include zero detect, all ones detect, and overflow. These 7.2.2.9 Datapath I/O conditions are the primary datapath outputs, a selection of which There are six inputs and six outputs that connect the datapath to can be driven out to the UDB routing matrix. Conditional the routing matrix. Inputs from the routing provide the computation can use the built in chaining to neighboring UDBs configuration for the datapath operation to perform in each cycle, to operate on wider data widths without the need to use routing and the serial data inputs. Inputs can be routed from other UDB resources. blocks, other device peripherals, device I/O pins, and so on. The 7.2.2.4 Variable MSB outputs to the routing can be selected from the generated conditions, and the serial data outputs. Outputs can be routed to The most significant bit of an arithmetic and shift function can be other UDB blocks, device peripherals, interrupt and DMA programmatically specified. This supports variable width CRC controller, I/O pins, and so on. and PRS functions, and in conjunction with ALU output masking, can implement arbitrary width timers, counters and shift blocks. 7.2.3 Status and Control Module 7.2.2.5 Built in CRC/PRS The primary purpose of this circuitry is to coordinate CPU The datapath has built-in support for single cycle CRC firmware interaction with internal UDB operation. computation and PRS generation of arbitrary width and arbitrary Figure 7-6. Status and Control Registers polynomial. CRC/PRS functions longer than 8 bits may be System Bus implemented in conjunction with PLD logic, or built in chaining may be use to extend the function into neighboring UDBs. 7.2.2.6 Input/Output FIFOs 8-bit Status Register 8-bit Control Register Each datapath contains two four-byte deep FIFOs, which can be (Read Only) (Write/Read) independently configured as an input buffer (system bus writes to the FIFO, datapath internal reads the FIFO), or an output buffer (datapath internal writes to the FIFO, the system bus reads from the FIFO). The FIFOs generate status that are selectable Routing Channel as datapath outputs and can therefore be driven to the routing, to interact with sequencers, interrupts, or DMA. The bits of the control register, which may be written to by the Figure 7-5. Example FIFO Configurations system bus, are used to drive into the routing matrix, and thus System Bus System Bus provide firmware with the opportunity to control the state of UDB processing. The status register is read-only and it allows internal UDB state to be read out onto the system bus directly from F0 F0 F1 internal routing. This allows firmware to monitor the state of UDB processing. Each bit of these registers has programmable connections to the routing matrix and routing connections are D0/D1 D0 D1 made depending on the requirements of the application. A0/A1/ALU A0/A1/ALU A0/A1/ALU A0 A1 7.2.3.1 Usage Examples As an example of control input, a bit in the control register can F1 F0 F1 be allocated as a function enable bit. There are multiple ways to enable a function. In one method the control bit output would be routed to the clock control block in one or more UDBs and serve as a clock enable for the selected UDB blocks. A status example System Bus System Bus is a case where a PLD or datapath block generated a condition, TX/RX Dual Capture Dual Buffer such as a “compare true” condition that is captured and latched by the status register and then read (and cleared) by CPU firmware. Document Number: 001-11729 Rev. AG Page 48 of 140

® PSoC 3: CY8C38 Family Datasheet 7.2.3.2 Clock Generation An example of this is the 8-bit timer in the upper left corner of the array. This function only requires one datapath in the UDB, and Each subcomponent block of a UDB including the two PLDs, the therefore the PLD resources may be allocated to another datapath, and Status and Control, has a clock selection and function. A function such as a Quadrature Decoder may require control block. This promotes a fine granularity with respect to more PLD logic than one UDB can supply and in this case can allocating clocking resources to UDB component blocks and utilize the unused PLD blocks in the 8-bit Timer UDB. allows unused UDB resources to be used by other functions for Programmable resources in the UDB array are generally maximum system efficiency. homogeneous so functions can be mapped to arbitrary 7.3 UDB Array Description boundaries in the array. Figure7-7 shows an example of a 16 UDB array. In addition to Figure 7-8. Function Mapping Example in a Bank of UDBs the array core, there are a DSI routing interfaces at the top and bottom of the array. Other interfaces that are not explicitly shown include the system interfaces for bus and clock distribution. The 8T-iBmiet r Quadrature Decoder cer 1P6W-BMit 16-Bit PYRS n UDB array includes multiple horizontal and vertical routing ue UDB UDB q UDB UDB channels each comprised of 96 wires. The wire connections to Se UDBs, at horizontal/vertical intersection and at the DSI interface are highly permutable providing efficient automatic routing in HV HV HV HV PSoC Creator. Additionally the routing allows wire by wire A B A B segmentation along the vertical and horizontal routing to further increase routing flexibility and capability. Figure 7-7. Digital System Interface Structure UDB UDB UDB 8-BitU DB Timer Logic 8-Bit SPI I2C Slave 12-Bit SPI System Connections UDB UDB UDB UDB HV HV HV HV B A B A HV HV HV HV B A B A UDB UDB UDB UDB Logic HV HV HV HV UDB UDB A B A B UDB UDB UART 12-Bit PWM UDB UDB UDB UDB 7.4 DSI Routing Interface Description UDB UDB UDB UDB The DSI routing interface is a continuation of the horizontal and vertical routing channels at the top and bottom of the UDB array HV HV HV HV core. It provides general purpose programmable routing B A B A between device peripherals, including UDBs, I/Os, analog peripherals, interrupts, DMA and fixed function peripherals. UDB UDB UDB UDB Figure7-9 illustrates the concept of the digital system interconnect, which connects the UDB array routing matrix with HV HV HV HV other device peripherals. Any digital core or fixed function A B A B peripheral that needs programmable routing is connected to this interface. Signals in this category include: System Connections Interrupt requests from all digital peripherals in the system. 7.3.1 UDB Array Programmable Resources DMA requests from all digital peripherals in the system. Figure7-8 shows an example of how functions are mapped into Digital peripheral data signals that need flexible routing to I/Os. a bank of 16 UDBs. The primary programmable resources of the UDB are two PLDs, one datapath and one status/control register. Digital peripheral data signals that need connections to UDBs. These resources are allocated independently, because they Connections to the interrupt and DMA controllers. have independently selectable clocks, and therefore unused blocks are allocated to other unrelated functions. Connection to I/O pins. Connection to analog system digital signals. Document Number: 001-11729 Rev. AG Page 49 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 7-9. Digital System Interconnect single synchronized (pipelined) and a data input signal has the option to be double synchronized. The synchronization clock is the master clock (see Figure6-1). Normally all inputs from pins Timer Interrupt DMA I/O Port Global Counters I2C Controller Controller Pins Clocks are synchronized as this is required if the CPU interacts with the signal or any signal derived from it. Asynchronous inputs have rare uses. An example of this is a feed through of combinational PLD logic from input pins to output pins. Figure 7-11. I/O Pin Synchronization Routing Digital System Routing/ FI DO UDB ARRAY DI Digital System Routing/ FI Figure 7-12. I/O Pin Output Connectivity 8 IO Data Output Connections from the UDB Array Digital System Interface Global I/O Port Delta SAR SC/CT EMIF Sigma DACS Comparators Clocks Pins ADC Blocks ADC Interrupt and DMA routing is very flexible in the CY8C38 programmable architecture. In addition to the numerous fixed function peripherals that can generate interrupt requests, any data signal in the UDB array routing can also be used to generate a request. A single peripheral may generate multiple DO DO DO DO DO DO DO DO independent interrupt requests simplifying system and firmware PIN 0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 design. Figure7-10 shows the structure of the IDMUX (Interrupt/DMA Multiplexer). Port i Figure 7-10. Interrupt and DMA Processing in the IDMUX Interrupt and DMA Processing in IDMUX There are four more DSI connections to a given I/O port to implement dynamic output enable control of pins. This Fixed Function IRQs connectivity gives a range of options, from fully ganged 8-bits 0 controlled by one signal, to up to four individually controlled pins. 1 The output enable signal is useful for creating tri-state Interrupt IRQs Controller bidirectional pins and buses. 2 UDB Array Figure 7-13. I/O Pin Output Enable Connectivity Edge 3 Detect DRQs 4 IO Control Signal Connections from DMA termout (IRQs) UDB Array Digital System Interface 0 Fixed Function DRQs DMA 1 Controller Edge 2 Detect 7.4.1 I/O Port Routing There are a total of 20 DSI routes to a typical 8-bit I/O port, 16 for data and four for drive strength control. OE OE OE OE OE OE OE OE When an I/O pin is connected to the routing, there are two PIN 0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 primary connections available, an input and an output. In conjunction with drive strength control, this can implement a bidirectional I/O pin. A data output signal has the option to be Port i Document Number: 001-11729 Rev. AG Page 50 of 140

® PSoC 3: CY8C38 Family Datasheet 7.5 CAN The CAN peripheral is a fully functional controller area network (CAN) supporting communication baud rates up to 1Mbps. The CAN controller implements the CAN2.0A and CAN2.0B specifications as defined in the Bosch specification and conforms to the ISO-11898-1 standard. The CAN protocol was originally designed for automotive applications with a focus on a high level of fault detection. This ensures high communication reliability at a low cost. Because of its success in automotive applications, CAN is used as a standard communication protocol for motion oriented machine control networks (CANOpen) and factory automation applications (DeviceNet). The CAN controller features allow the efficient implementation of higher level protocols without affecting the performance of the microcontroller CPU. Full configuration support is provided in PSoC Creator. Figure 7-14. CAN Bus System Implementation CAN Node 1 CAN Node 2 CAN Node n PSoC CAN Drivers CAN Controller En Tx Rx CAN Transceiver CAN_H CAN_L CAN_H CAN_L CAN_H CAN_L CAN Bus 7.5.1 CAN Features Receive path CAN2.0A/B protocol implementation – ISO 11898 compliant 16 receive buffers each with its own message filter Standard and extended frames with up to 8 bytes of data per Econvhearnsc tehde hIDar, dIDwEar,e a mnde sRsTaRge filter implementation that frame Message filter capabilities DeviceNet addressing support Remote Transmission Request (RTR) support Mmuelstispaleg ere acreraivye buffers linkable to build a larger receive Programmable bit rate up to 1 Mbps Automatic transmission request (RTR) response handler Listen Only mode Lost received message notification SW readable error counter and indicator Transmit path Sleep mode: Wake the device from sleep with activity on the Eight transmit buffers Rx pin Programmable transmit priority Round robin Supports two or three wire interface to external transceiver (Tx, Fixed priority Rx, and Enable). The three-wire interface is compatible with Message transmissions abort capability the Philips PHY; the PHY is not included on-chip. The three wires can be routed to any I/O 7.5.2 Software Tools Support Enhanced interrupt controller CAN Controller configuration integrated into PSoC Creator: CAN receive and transmit buffers status CAN Configuration walkthrough with bit timing analyzer CAN controller error status including BusOff Receive filter setup Document Number: 001-11729 Rev. AG Page 51 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 7-15. CAN Controller Block Diagram TxMessage0 TxReq TxAbort Tx Buffer TxMessage1 Bit Timing Status TxReq TxReq TxAbort Pending Priority Tx TxMessage6 Arbiter Tx CRC TxReq CAN Generator TxInterrupt TxAbort Framer Request (if enabled) TxMessage7 TxReq TxAbort Error Status  Error Active  Error Passive RTR RxMessages  Bus Off 0-15 Tx Error Counter Rx Error Counter Rx Buffer RxMessage0 Acceptance Code 0 Acceptance Mask 0 Status RxMessage RxMessage1 Acceptance Code 1 Acceptance Mask 1 Rx Available Rx RxMessage CAN CRC Check Handler Framer RxMessage14 Acceptance Code 14 Acceptance Mask 14 RxInterrupt Request RxMessage15 Acceptance Code 15 Acceptance Mask 15 (if enabled) WakeUp Error Detection Request CRC Form ErrInterrupt ACK Request Bit Stuffing (if enabled) Bit Error Overload Arbitration Document Number: 001-11729 Rev. AG Page 52 of 140

® PSoC 3: CY8C38 Family Datasheet 7.6 USB 7.7 Timers, Counters, and PWMs PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0 The timer/counter/PWM peripheral is a 16-bit dedicated transceiver supporting all four USB transfer types: control, peripheral providing three of the most common embedded interrupt, bulk, and isochronous. PSoC Creator provides full peripheral features. As almost all embedded systems use some configuration support. USB interfaces to hosts through two combination of timers, counters, and PWMs. Four of them have dedicated USBIO pins, which are detailed in the “I/O System and been included on this PSoC device family. Additional and more Routing” section on page37. advanced functionality timers, counters, and PWMs can also be instantiated in UDBs as required. PSoC Creator allows you to USB includes the following features: choose the timer, counter, and PWM features that they require. Eight unidirectional data endpoints The tool set utilizes the most optimal resources available. One bidirectional control endpoint 0 (EP0) The timer/counter/PWM peripheral can select from multiple clock sources, with input and output signals connected through the Shared 512-byte buffer for the eight data endpoints DSI routing. DSI routing allows input and output connections to any device pin and any internal digital signal accessible through Dedicated 8-byte buffer for EP0 the DSI. Each of the four instances has a compare output, Three memory modes terminal count output (optional complementary compare output), Manual memory management with no DMA access and programmable interrupt request line. The Timer/Counter/PWMs are configurable as free running, one shot, Manual memory management with manual DMA access or Enable input controlled. The peripheral has timer reset and Automatic memory management with automatic DMA capture inputs, and a kill input for control of the comparator access outputs. The peripheral supports full 16-bit capture. Internal 3.3-V regulator for transceiver Timer/Counter/PWM features include: Internal 48-MHz main oscillator mode that auto locks to USB 16-bit Timer/Counter/PWM (down count only) bus clock, requiring no external crystal for USB (USB equipped Selectable clock source parts only) PWM comparator (configurable for LT, LTE, EQ, GTE, GT) Interrupts on bus and each endpoint event, with device wakeup Period reload on start, reset, and terminal count USB reset, suspend, and resume operations Interrupt on terminal count, compare true, or capture Bus-powered and self-powered modes Dynamic counter reads Figure 7-16. USB Timer capture mode Count while enable signal is asserted mode Free run mode 512 X 8 Arbiter SRAM One Shot mode (stop at end of period) External 22  Complementary PWM outputs with deadband us D+ Resistors PWM output kill B S I E m (Serial Interface USB Figure 7-17. Timer/Counter/PWM e I/O st Engine) y S D– Interrupts Clock IRQ Reset Timer / Counter / 48 MHz Enable TC / Compare! PWM 16-bit IMO Capture Compare Kill Document Number: 001-11729 Rev. AG Page 53 of 140

® PSoC 3: CY8C38 Family Datasheet 7.8 I2C functionality is required, I2C pin connections are limited to one of PSoC includes a single fixed-function I2C peripheral. Additional two specific pairs of SIO pins. See descriptions of SCL and SDA I2C interfaces can be instantiated using Universal Digital Blocks pins in Pin Descriptions on page 12. (UDBs) in PSoC Creator, as required. I2C features include: The I2C peripheral provides a synchronous two-wire interface Slave and master, transmitter, and receiver operation designed to interface the PSoC device with a two-wire I2C serial Byte processing for low CPU overhead communication bus. It is compatible[16] with I2C Standard-mode, Interrupt or polling CPU interface Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus Support for bus speeds up to 1 Mbps I/O may be implemented with GPIO or SIO in open-drain modes. 7 or 10-bit addressing (10-bit addressing requires firmware support) To eliminate the need for excessive CPU intervention and overhead, I2C specific support is provided for status detection SMBus operation (through firmware support - SMBus and generation of framing bits. I2C operates as a slave, a master, supported in hardware in UDBs) or multimaster (Slave and Master)[17]. In slave mode, the unit 7-bit hardware address compare always listens for a start condition to begin sending or receiving Wake from low-power modes on address match data. Master mode supplies the ability to generate the Start and Stop conditions and initiate transactions. Multimaster mode Glitch filtering (active and alternate-active modes only) provides clock synchronization and arbitration to allow multiple Data transfers follow the format shown in Figure7-18. After the masters on the same bus. If Master mode is enabled and Slave START condition (S), a slave address is sent. This address is 7 mode is not enabled, the block does not generate interrupts on bits long followed by an eighth bit which is a data direction bit externally generated Start conditions. I2C interfaces through DSI (R/W) - a 'zero' indicates a transmission (WRITE), a 'one' routing and allows direct connections to any GPIO or SIO pins. indicates a request for data (READ). A data transfer is always I2C provides hardware address detect of a 7-bit address without terminated by a STOP condition (P) generated by the master. CPU intervention. Additionally the device can wake from low-power modes on a 7-bit hardware address match. If wakeup Figure 7-18. I2C Complete Transfer Timing SDA SCL 1 - 7 8 9 1 - 7 8 9 1 - 7 8 9 START STOP ADDRESS R/W ACK DATA ACK DATA ACK Condition Condition 7.8.1 External Electrical Connections Figure 7-19. Connection of Devices to the I2C Bus As Figure 7-19 shows, the I2C bus requires external pull-up resistors (R ). These resistors are primarily determined by the P supply voltage, bus speed, and bus capacitance. For detailed information on how to calculate the optimum pull-up resistor value for your design, we recommend using the UM10204 I2C-bus specification and user manual Rev 6, or newer, available from the NXP website at www.nxp.com. Notes 16.The I2C peripheral is non-compliant with the NXP I2C specification in the following areas: analog glitch filter, I/O VOL/IOL, I/O hysteresis. The I2C Block has a digital glitch filter (not available in sleep mode). The Fast-mode minimum fall-time specification can be met by setting the I/Os to slow speed mode. See the I/O Electrical Specifications in “Inputs and Outputs” section on page80 for details. 17.Fixed-block I2C does not support undefined bus conditions, nor does it support Repeated Start in Slave mode. These conditions should be avoided, or the UDB-based I2C component should be used instead. Document Number: 001-11729 Rev. AG Page 54 of 140

® PSoC 3: CY8C38 Family Datasheet For most designs, the default values in Table7-2 will provide Equation parameters: excellent performance without any calculations. The default V = Nominal supply voltage for I2C bus values were chosen to use standard resistor values between the DD minimum and maximum limits. The values in Table7-2 work for VOL = Maximum output low voltage of bus devices. designs with 1.8 V to 5.0V VDD, less than 200-pF bus capaci- IOL= Low-level output current from I2C specification tance (C ), up to 25 µA of total input leakage (I ), up to 0.4V B IL T = Rise Time of bus from I2C specification output voltage level (V ), and a max V of 0.7 * V . Standard R OL IH DD Mode and Fast Mode can use either GPIO or SIO PSoC pins. C = Capacitance of each bus line including pins and PCB traces B Fast Mode Plus requires use of SIO pins to meet the V spec OL V = Minimum high-level input voltage of all bus devices at 20 mA. Calculation of custom pull-up resistor values is IH required; if your design does not meet the default assumptions, VNH = Minimum high-level input noise margin from I2C specifi- you use series resistors (RS) to limit injected noise, or you need cation to maximize the resistor value for low power consumption. I = Total input leakage current of all devices on the bus IH Table 7-2. Recommended default Pull-up Resistor Values The supply voltage (V ) limits the minimum pull-up resistor DD value due to bus devices maximum low output voltage (V ) R Units OL P specifications. Lower pull-up resistance increases current Standard Mode – 100 kbps 4.7 k, 5% Ω through the pins and can, therefore, exceed the spec conditions of V . Equation 1 is derived using Ohm's law to determine the Fast Mode – 400 kbps 1.74 k, 1% Ω OL minimum resistance that will still meet the V specification at OL Fast Mode Plus – 1 Mbps 620, 5% Ω 3mA for standard and fast modes, and 20 mA for fast mode plus at the given V . Calculation of the ideal pull-up resistor value involves finding a DD value between the limits set by three equations detailed in the Equation 2 determines the maximum pull-up resistance due to NXP I2C specification. These equations are: bus capacitance. Total bus capacitance is comprised of all pin, wire, and trace capacitance on the bus. The higher the bus Equation 1: capacitance, the lower the pull-up resistance required to meet the specified bus speeds rise time due to RC delays. Choosing R = V max–V maxI min a pull-up resistance higher than allowed can result in failing PMIN DD OL OL timing requirements resulting in communication errors. Most Equation 2: designs with five or less I2C devices and up to 20 centimeters of bus trace length have less than 100 pF of bus capacitance. R = T max0.8473C max A secondary effect that limits the maximum pull-up resistor value PMAX R B is total bus leakage calculated in Equation 3. The primary source Equation 3: of leakage is I/O pins connected to the bus. If leakage is too high, the pull-ups will have difficulty maintaining an acceptable V IH R = V min–V min+V minI max level causing communication errors. Most designs with five or PMAX DD IH NH IH less I2C devices on the bus have less than 10 µA of total leakage current. Document Number: 001-11729 Rev. AG Page 55 of 140

® PSoC 3: CY8C38 Family Datasheet 7.9 Digital Filter Block The typical use model is for data to be supplied to the DFB over the system bus from another on-chip system data source such Some devices in the CY8C38 family of devices have a dedicated as an ADC. The data typically passes through main memory or HW accelerator block used for digital filtering. The DFB has a is directly transferred from another chip resource through DMA. dedicated multiplier and accumulator that calculates a 24-bit by The DFB processes this data and passes the result to another 24-bit multiply accumulate in one bus clock cycle. This enables on chip resource such as a DAC or main memory through DMA the mapping of a direct form FIR filter that approaches a on the system bus. computation rate of one FIR tap for each clock cycle. The MCU can implement any of the functions performed by this block, but Data movement in or out of the DFB is typically controlled by the at a slower rate that consumes MCU bandwidth. system DMA controller but can be moved directly by the MCU. The heart of the DFB is a datapath (DP), which is the numerical 8. Analog Subsystem calculation unit of the DFB. The DP is a 24-bit fixed-point numerical processor containing a 48-bit multiply and accumulate The analog programmable system creates application specific function (MAC), a multi-function ALU, sample and coefficient combinations of both standard and advanced analog signal data RAMs as well as data routing, shifting, holding and rounding processing blocks. These blocks are then interconnected to functions. each other and also to any pin on the device, providing a high In the MAC, two 24-bit values can be multiplied and the result level of design flexibility and IP security. The features of the added to the 48-bit accumulator in each bus clock cycle. The analog subsystem are outlined here to provide an overview of MAC is the only portion of the DP that is wider than 24 bits. All capabilities and architecture. results from the MAC are passed on to the ALU as 24-bit values Flexible, configurable analog routing architecture provided by representing the high-order 24 bits in the accumulator shifted by analog globals, analog mux bus, and analog local buses. one (bits 46:23). The MAC assumes an implied binary point after the most significant bit. High resolution delta-sigma ADC. The DP also contains an optimized ALU that supports add, Up to four 8-bit DACs that provide either voltage or current subtract, comparison, threshold, absolute value, squelch, output. saturation, and other functions. The DP unit is controlled by seven control fields totaling 18 bits coming from the DFB Four comparators with optional connection to configurable LUT Controller. For more information see the TRM. outputs. The PSoC Creator interface provides a wizard to implement FIR Up to four configurable switched capacitor/continuous time and IIR digital filters with coefficients for LPF, BPF, HPF, Notch (SC/CT) blocks for functions that include opamp, unity gain and arbitrary shape filters. 64 pairs of data and coefficients are buffer, programmable gain amplifier, transimpedance amplifier, stored. This enables a 64 tap FIR filter or up to 4 16 tap filters of and mixer. either FIR or IIR formulation. Up to four opamps for internal use and connection to GPIO that Figure 7-20. DFB Application Diagram (pwr/gnd not shown) can be used as high current output buffers. CapSense subsystem to enable capacitive touch sensing. BUSCLK read_data Data Precision reference for generating an accurate analog voltage Source for internal analog blocks. write_data (PHUB) System Bus addr Digital Digital Filter Routing Block Data Dest (PHUB) DMA Request DMA CTRL Document Number: 001-11729 Rev. AG Page 56 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 8-1. Analog Subsystem Block Diagram DAC DAC DelSig ADC RPerefecriseinocne A DAC DAC A N N A A LO SC/CT Block SC/CT Block LO GPIO G G GPIO Port R OpAmp SC/CT Block SC/CT Block OpAmp R Port O O U U TI OpAmp Comparators OpAmp TI N CMP CMP CMP CMP N G G CapSense Subsystem Analog Config & Status Interface PHUB CPU Registers DSI Clock Decimator Array Distribution The PSoC Creator software program provides a user friendly 8.1.1 Features interface to configure the analog connections between the GPIO Flexible, configurable analog routing architecture and various analog resources and connections from one analog resource to another. PSoC Creator also provides component 16 analog globals (AG) and two analog mux buses libraries that allow you to configure the various analog blocks to (AMUXBUS) to connect GPIOs and the analog blocks perform application specific functions (PGA, transimpedance amplifier, voltage DAC, current DAC, and so on). The tool also Each GPIO is connected to one analog global and one analog generates API interface libraries that allow you to write firmware mux bus that allows the communication between the analog peripheral Eight analog local buses (abus) to route signals between the and CPU/Memory. different analog blocks 8.1 Analog Routing Multiplexers and switches for input and output selection of the The CY8C38 family of devices has a flexible analog routing analog blocks architecture that provides the capability to connect GPIOs and 8.1.2 Functional Description different analog blocks, and also route signals between different analog blocks. One of the strong points of this flexible routing Analog globals (AGs) and analog mux buses (AMUXBUS) architecture is that it allows dynamic routing of input and output provide analog connectivity between GPIOs and the various connections to the different analog blocks. analog blocks. There are 16 AGs in the CY8C38 family. The analog routing architecture is divided into four quadrants as For information on how to make pin selections for optimal analog shown in Figure8-2. Each quadrant has four analog globals routing, refer to the application note, AN58304 - PSoC® 3 and (AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is PSoC® 5 - Pin Selection for Analog Designs. connected to the corresponding AG through an analog switch. The analog mux bus is a shared routing resource that connects to every GPIO through an analog switch. There are two AMUXBUS routes in CY8C38, one in the left half (AMUXBUSL) and one in the right half (AMUXBUSR), as shown in Figure 8-2 on page 58. Document Number: 001-11729 Rev. AG Page 57 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 8-2. CY8C38 Analog Interconnect V V V V d s c s d s c s a* a* a* d* Vddio0*swP0[3]inn*GPIOswP0[2]inp*GPIOP0[1]*GPIOP0[0]*GPIOP4[1]GPIOP4[0]GPIOP12[3]SIOP12[2]SIO AMUXBUSL AMUXBUSRP15[3]*GPIOP15[2]*GPIOP12[1]*SIOP12[0]*SIOP3[7]GPIOP3[6]GPIO Vddio3* AGL[4] AGR[4] AGL[5] AGR[5] AGL[6] AGR[6] USL AGL[7] AGR[7] GP0P[I4O*] swAMUXBinpAGL[4]AGL[5]AGL[6]AGL[7] EExxVVrreeffLL1 opswamfopl0 opsawmfopl2 01234Ex5V6re7fL20123 3210 76543210 ospwafmolp3 sowpfaomlp1 sswwiinnpn GGP3PP[II5OO] GP0P[I5O*] swinn swinp GP3P[I4O] GGP0PP[II6OO] * i0 ab(u1f._0v2r4eVf_)int swout swin ionu0t0 LPF oiunt11 swin swout ab(u1f._0v2r4eVf_)int ExVrefR swinn GPP33P[[I32O]] P0[7]* i2 + comp0 comp1 + i3 GPIO - - P3[1] GGGPP44PPP[[III32OOO]] VrdVecbfrdbd(emcg1aufmd_bfv.p/_vuap02(rdv0f_0_e2ram_ev._f42fr_vur1eVe5xcr f(s2ve)61m_n f.(eV0[ 1p1n2.):2140VV] )) cmprefbufl_1_cmpvrefcmp1_vref bg_vda_swabusl0 +-orCeuftcOoCmMpA2PPASRENATScoOmEpR3oreuft+- cmp1_vref refbufr_cmp rreecffbb(mu1uff_.p_0vv0r2ree_4ff2v1V r ((1e)1.f.20 V2)4V) i1 **PPGGGP11PP3P55[XXI0[[O01TT]]] in refbufl refbufr in GPP44P[[I45O]] refsel[1:0] vssa Vscin0 sVcin1 Vssa refsel[1:0] AGR[7]AGR[6]AGR[5]AGR[4]XBUSR GGP4PP[II6OO] ss((cc1102..00__22bb44ggVVrree))ff VoVurinetf SC/CT VVorieunft s(c1s3(.c01_12.b0_4g2bVr4ge)Vrf e)f AMU *Vccd PV4c[c7d]* oVsucre2tf Vsocreu3ft **VVdssddd * Vssd ABUSL0 ABUSR0 ABUSL1 ABUSR1 ABUSL2 ABUSR2 ABUSL3 ABUSR3 * Vddd GPIO vi00DAC0VIDACDAC1vi11 *UPS1B5[ 7IO] P6[0] USB IO GP6P[I1O] vi22DAC2 DAC3vi33 *PG1P5IO[6] GPIO dac_vref (0.256V) P5[7] P6[2] vcmsel[1:0] +DSM0 DSM GPIO GPIO dsm0_vcm_vref1v s(0s.d8V) vssa - P5[6] P6[3] dsm0_vcm_vref2 (0.7V) vcm refs GPIO GPIO qtz_ref P5[5] P15[4] dsdmsm0_0q_tzq_tzv_rverfe1f 2(1 (.102.24VV)) vref_vss_ext GPIO PG1P5I[O5] VVddddaa//34 ExVrefL ExVrefR PS5I[O4] GPIO P12[7] P2[0] AMUXBUSL01234567 0123 3210 76543210 AMUXBUSR SIO GPIO ANALOG ANALOG ANALOG ANALOG P12[6] P2[1] GLOBALS BUS BUS GLOBALS GPIO GPIO *P1[7] P2[2] GPIO GPIO *P1[6] P2[3]* GPIO VPd2d[i4o]2**MUXBUSLAGL[0]AGL[1]AGL[2]AGL[3] : ATDSC VVssB Eref LPF AGL[3] AGR[3] AGR[3]AGR[2]AGR[1]AGR[0]AMUXBUSR A AGL[2] AGR[2] AGL[1] AGR[1] AGL[0] AGR[0] AMUXBUSL AMUXBUSR * * * * * SCwMoinutcnxh eG cGtrirooounupp GPIO*P2[5]GPIO*P2[6]GPIO*P2[7]SIOP12[4]SIOP12[5]GPIOP6[4]GPIOP6[5]GPIOP6[6]GPIOP6[7] GPIOP5[0]GPIOP5[1]GPIOP5[2]GPIOP5[3]GPIOP1[0]GPIOP1[1]GPIOP1[2]GPIOP1[3]GPIO*P1[4]GPIO*P1[5] Vddio1 Switch Resistance * * * * * Notes: SLmaraglel (( ~~827000 OOhhmmss )) Ind Vssb Vbat Vboost Vssd XRES * DLCenDo tseigsn painlss a orne anlol tp sahcokwagne.s Rev #60 10-Feb-2012 To preserve detail of this figure, this figure is best viewed with a PDF display program or printed on a 11" × 17" paper. Document Number: 001-11729 Rev. AG Page 58 of 140

® PSoC 3: CY8C38 Family Datasheet Analog local buses (abus) are routing resources located within block diagram is shown in Figure8-4. The signal from the input the analog subsystem and are used to route signals between muxes is delivered to the delta-sigma modulator either directly or different analog blocks. There are eight abus routes in CY8C38, through the input buffer. The delta-sigma modulator performs the four in the left half (abusl [0:3]) and four in the right half (abusr actual analog to digital conversion. The modulator over-samples [0:3]) as shown in Figure8-2. Using the abus saves the analog the input and generates a serial data stream output. This high globals and analog mux buses from being used for speed data stream is not useful for most applications without interconnecting the analog blocks. some type of post processing, and so is passed to the decimator through the Analog Interface block. The decimator converts the Multiplexers and switches exist on the various buses to direct high speed serial data stream into parallel ADC results. The signals into and out of the analog blocks. A multiplexer can have modulator/decimator frequency response is [(sin x)/x]4. only one connection on at a time, whereas a switch can have multiple connections on simultaneously. In Figure8-2, Figure 8-4. Delta-sigma ADC Block Diagram multiplexers are indicated by grayed ovals and switches are indicated by transparent ovals. Positive 8.2 Delta-sigma ADC Input Mux Delta Input 12 to 20 Bit The CY8C38 device contains one delta-sigma ADC. This ADC (Analog Routing) Buffer Sigma Decimator Result Modulator offers differential input, high resolution and excellent linearity, Negative EOC making it a good ADC choice for both audio signal processing Input Mux and measurement applications. The converter's nominal operation is 16 bits at 48 ksps. The ADC can be configured to SOC output 20-bit resolution at data rates of up to 187 sps. At a fixed Resolution and sample rate are controlled by the Decimator. clock rate, resolution can be traded for faster data rates as Data is pipelined in the decimator; the output is a function of the shown in Table8-1 and Figure8-3. last four samples. When the input multiplexer is switched, the output data is not valid until after the fourth sample after the Table 8-1. Delta-sigma ADC Performance switch. Maximum Sample Rate Bits (sps) SINAD (dB) 8.2.2 Operational Modes 20 187 – The ADC can be configured by the user to operate in one of four modes: Single Sample, Multi Sample, Continuous, or Multi 16 48 k 84 Sample (Turbo). All four modes are started by either a write to 12 192 k 66 the start bit in a control register or an assertion of the Start of Conversion (SoC) signal. When the conversion is complete, a 8 384 k 43 status bit is set and the output signal End of Conversion (EoC) asserts high and remains high until the value is read by either the DMA controller or the CPU. Figure 8-3. Delta-sigma ADC Sample Rates, Range = ±1.024V 8.2.2.1 Single Sample 1000000 In Single Sample mode, the ADC performs one sample conversion on a trigger. In this mode, the ADC stays in standby 100000 state waiting for the SoC signal to be asserted. When SoC is signaled the ADC performs four successive conversions. The ps 10000 first three conversions prime the decimator. The ADC result is Rate, s 1000 vEaolCid asingdn aalv aisi lagbelnee araftteerd t.h eTo f oduertthe ccto tnhvee resniodn o, fa tc ownhvicehrs tiiomne, tthhee e mple system may poll a control register for status or configure the Sa 100 external EoC signal to generate an interrupt or invoke a DMA request. When the transfer is done the ADC reenters the standby 10 state where it stays until another SoC event. 8.2.2.2 Continuous 1 6 8 10 12 14 16 18 20 22 Continuous sample mode is used to take multiple successive Resolution, bits samples of a single input signal. Multiplexing multiple inputs Continuous Multi-Sample Multi-SampleTurbo should not be done with this mode. There is a latency of three conversion times before the first conversion result is available. This is the time required to prime the decimator. After the first 8.2.1 Functional Description result, successive conversions are available at the selected sample rate. The ADC connects and configures three basic components, input buffer, delta-sigma modulator, and decimator. The basic Document Number: 001-11729 Rev. AG Page 59 of 140

® PSoC 3: CY8C38 Family Datasheet 8.2.2.3 Multi Sample 8.2.4 End of Conversion Output Multi sample mode is similar to continuous mode except that the The EoC signal goes high at the end of each ADC conversion. ADC is reset between samples. This mode is useful when the This signal may be used to trigger either an interrupt or DMA input is switched between multiple signals. The decimator is request. re-primed between each sample so that previous samples do not affect the current conversion. Upon completion of a sample, the 8.3 Comparators next sample is automatically initiated. The results can be The CY8C38 family of devices contains four comparators in a transferred using either firmware polling, interrupt, or DMA. device. Comparators have these features: 8.2.2.4 Multi Sample (Turbo) Input offset factory trimmed to less than 5 mV The multi sample (turbo) mode operates identical to the Rail-to-rail common mode input range (VSSA to VDDA) Multi-sample mode for resolutions of 8 to 16 bits. For resolutions Speed and power can be traded off by using one of three of 17 to 20 bits, the performance is about four times faster than modes: fast, slow, or ultra low-power the multi sample mode, because the ADC is only reset once at the end of conversion. Comparator outputs can be routed to lookup tables to perform simple logic functions and then can also be routed to digital More information on output formats is provided in the Technical blocks Reference Manual. The positive input of the comparators may be optionally passed 8.2.3 Start of Conversion Input through a low pass filter. Two filters are provided The SoC signal is used to start an ADC conversion. A digital Comparator inputs can be connections to GPIO, DAC outputs clock or UDB output can be used to drive this input. It can be and SC block outputs used when the sampling period must be longer than the ADC conversion time or when the ADC must be synchronized to other 8.3.1 Input and Output Interface hardware. This signal is optional and does not need to be The positive and negative inputs to the comparators come from connected if ADC is running in a continuous mode. the analog global buses, the analog mux line, the analog local bus and precision reference through multiplexers. The output from each comparator could be routed to any of the two input LUTs. The output of that LUT is routed to the UDB DSI. Figure 8-5. Analog Comparator ANAIF From + Analog comp0 + From _ Routing comp1 Analog _ Routing + From comp3 Analog From + _ Routing Analog c_omp2 Routing 4 4 4 4 4 4 4 4 LUT0 LUT1 LUT2 LUT3 UDBs Document Number: 001-11729 Rev. AG Page 60 of 140

® PSoC 3: CY8C38 Family Datasheet 8.3.2 LUT Figure 8-7. Opamp Configurations The CY8C38 family of devices contains four LUTs. The LUT is a a) Voltage Follower two input, one output lookup table that is driven by any one or two of the comparators in the chip. The output of any LUT is routed to the digital system interface of the UDB array. From the digital system interface of the UDB array, these signals can be Opamp Vout to Pin connected to UDBs, DMA controller, I/O, or the interrupt Vin controller. The LUT control word written to a register sets the logic function on the output. The available LUT functions and the associated b) External Uncommitted control word is shown in Table8-2. Opamp Table 8-2. LUT Function vs. Program Word and Inputs Opamp Vout to GPIO Control Word Output (A and B are LUT inputs) 0000b FALSE (‘0’) 0001b A AND B Vp to GPIO 0010b A AND (NOT B) Vn to GPIO 0011b A 0100b (NOT A) AND B c) Internal Uncommitted 0101b B Opamp 0110b A XOR B 0111b A OR B Vn 1000b A NOR B To Internal Signals Opamp Vout to Pin 1001b A XNOR B 1010b NOT B Vp 1011b A OR (NOT B) GPIO Pin 1100b NOT A The opamp has three speed modes, slow, medium, and fast. The 1101b (NOT A) OR B slow mode consumes the least amount of quiescent power and 1110b A NAND B the fast mode consumes the most power. The inputs are able to 1111b TRUE (‘1’) swing rail-to-rail. The output swing is capable of rail-to-rail operation at low current output, within 50 mV of the rails. When 8.4 Opamps driving high current loads (about 25 mA) the output voltage may The CY8C38 family of devices contain up to four general only get within 500 mV of the rails. purpose opamps in a device. 8.5 Programmable SC/CT Blocks Figure 8-6. Opamp The CY8C38 family of devices contains up to four switched capacitor/continuous time (SC/CT) blocks in a device. Each GPIO switched capacitor/continuous time block is built around a single Analog rail-to-rail high bandwidth opamp. Global Bus Switched capacitor is a circuit design technique that uses Analog Opamp GPIO capacitors plus switches instead of resistors to create analog Global Bus VREF functions. These circuits work by moving charge between Analog capacitors by opening and closing different switches. Internal Bus Nonoverlapping in phase clock signals control the switches, so = Analog Switch that not all switches are ON simultaneously. GPIO The PSoC Creator tool offers a user friendly interface, which The opamp is uncommitted and can be configured as a gain allows you to easily program the SC/CT blocks. Switch control stage or voltage follower, or output buffer on external or internal and clock phase control configuration is done by PSoC Creator signals. so users only need to determine the application use parameters See Figure8-7. In any configuration, the input and output signals such as gain, amplifier polarity, VREF connection, and so on. can all be connected to the internal global signals and monitored The same opamps and block interfaces are also connectable to with an ADC, or comparator. The configurations are an array of resistors which allows the construction of a variety of implemented with switches between the signals and GPIO pins. continuous time functions. Document Number: 001-11729 Rev. AG Page 61 of 140

® PSoC 3: CY8C38 Family Datasheet The opamp and resistor array is programmable to perform The PGA is used in applications where the input signal may not various analog functions including be large enough to achieve the desired resolution in the ADC, or dynamic range of another SC/CT block such as a mixer. The gain Naked operational amplifier – Continuous mode is adjustable at runtime, including changing the gain of the PGA Unity-gain buffer – Continuous mode prior to each ADC sample. PGA – Continuous mode 8.5.4 TIA Transimpedance amplifier (TIA) – Continuous mode The Transimpedance Amplifier (TIA) converts an internal or Up/down mixer – Continuous mode external current to an output voltage. The TIA uses an internal Sample and hold mixer (NRZ S/H) – Switched cap mode feedback resistor in a continuous time configuration to convert input current to output voltage. For an input current I , the output First order analog to digital modulator – Switched cap mode in voltage is V - I x R , where V is the value placed on the REF in fb REF non inverting input. The feedback resistor Rfb is programmable 8.5.1 Naked Opamp between 20 K and 1M through a configuration register. The Naked Opamp presents both inputs and the output for Table8-4 shows the possible values of Rfb and associated connection to internal or external signals. The opamp has a unity configuration settings. gain bandwidth greater than 6.0 MHz and output drive current up to 650 µA. This is sufficient for buffering internal signals (such as Table 8-4. Feedback Resistor Settings DAC outputs) and driving external loads greater than 7.5 kohms. Configuration Word Nominal R (K) fb 8.5.2 Unity Gain 000b 20 The Unity Gain buffer is a Naked Opamp with the output directly 001b 30 connected to the inverting input for a gain of 1.00. It has a –3 dB 010b 40 bandwidth greater than 6.0 MHz. 011b 60 8.5.3 PGA 100b 120 The PGA amplifies an external or internal signal. The PGA can 101b 250 be configured to operate in inverting mode or noninverting mode. The PGA function may be configured for both positive and 110b 500 negative gains as high as 50 and 49 respectively. The gain is 111b 1000 adjusted by changing the values of R1 and R2 as illustrated in Figure8-8. The schematic in Figure8-8 shows the configuration and possible resistor settings for the PGA. The gain is switched Figure 8-9. Continuous Time TIA Schematic from inverting and non inverting by changing the shared select value of the both the input muxes. The bandwidth for each gain Rfb case is listed in Table8-3. Table 8-3. Bandwidth Gain Bandwidth Iin 1 6.0 MHz Vout Vref 24 340 kHz 48 220 kHz 50 215 kHz The TIA configuration is used for applications where an external sensor's output is current as a function of some type of stimulus Figure 8-8. PGA Resistor Settings such as temperature, light, magnetic flux etc. In a common application, the voltage DAC output can be connected to the V TIA input to allow calibration of the external sensor bias R1 R2 REF Vin 0 current by adjusting the voltage DAC output voltage. V 1 8.6 LCD Direct Drive ref 20 k or 40 k 20 k to 980 k The PSoC LCD driver system is a highly configurable peripheral S designed to allow PSoC to directly drive a broad range of LCD glass. All voltages are generated on chip, eliminating the need Vref 0 for external components. With a high multiplex ratio of up to 1/16, the CY8C38 family LCD driver system can drive a maximum of Vin 1 736 segments. The PSoC LCD driver module was also designed with the conservative power budget of portable devices in mind, enabling different LCD drive modes and power down modes to conserve power. Document Number: 001-11729 Rev. AG Page 62 of 140

® PSoC 3: CY8C38 Family Datasheet PSoC Creator provides an LCD segment drive component. The 8.6.1 LCD Segment Pin Driver component wizard provides easy and flexible configuration of Each GPIO pin contains an LCD driver circuit. The LCD driver LCD resources. You can specify pins for segments and buffers the appropriate output of the LCD DAC to directly drive commons along with other options. The software configures the the glass of the LCD. A register setting determines whether the device to meet the required specifications. This is possible pin is a common or segment. The pin’s LCD driver then selects because of the programmability inherent to PSoC devices. one of the six bias voltages to drive the I/O pin, as appropriate Key features of the PSoC LCD segment system are: for the display data. LCD panel direct driving 8.6.2 Display Data Flow Type A (standard) and Type B (low-power) waveform support The LCD segment driver system reads display data and generates the proper output voltages to the LCD glass to Wide operating voltage range support (2V to 5V) for LCD produce the desired image. Display data resides in a memory panels buffer in the system SRAM. Each time you need to change the Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels common and segment driver voltages, the next set of pixel data moves from the memory buffer into the Port Data Registers Internal bias voltage generation through internal resistor ladder through the DMA. Up to 62 total common and segment outputs 8.6.3 UDB and LCD Segment Control Up to 1/16 multiplex for a maximum of 16 backplane/common A UDB is configured to generate the global LCD control signals outputs and clocking. This set of signals is routed to each LCD pin driver through a set of dedicated LCD global routing channels. In Up to 62 front plane/segment outputs for direct drive addition to generating the global LCD control signals, the UDB Drives up to 736 total segments (16 backplane × 46 front plane) also produces a DMA request to initiate the transfer of the next frame of LCD data. Up to 64 levels of software controlled contrast 8.6.4 LCD DAC Ability to move display data from memory buffer to LCD driver through DMA (without CPU intervention) The LCD DAC generates the contrast control and bias voltage for the LCD system. The LCD DAC produces up to five LCD drive Adjustable LCD refresh rate from 10 Hz to 150 Hz voltages plus ground, based on the selected bias ratio. The bias Ability to invert LCD display for negative image voltages are driven out to GPIO pins on a dedicated LCD bias bus, as required. Three LCD driver drive modes, allowing power optimization 8.7 CapSense Figure 8-10. LCD System The CapSense system provides a versatile and efficient means for measuring capacitance in applications such as touch sense Global LCD buttons, sliders, proximity detection, etc. The CapSense system DAC Clock uses a configuration of system resources, including a few hardware functions primarily targeted for CapSense. Specific resource usage is detailed in the CapSense component in PSoC Creator. UDB PIN A capacitive sensing method using a Delta-sigma Modulator LCD Driver (CSD) is used. It provides capacitance sensing using a switched Block capacitor technique with a delta-sigma modulator to convert the sensing current to a digital code. Display DMA RAM 8.8 Temp Sensor Die temperature is used to establish programming parameters for writing flash. Die temperature is measured using a dedicated sensor based on a forward biased transistor. The temperature PHUB sensor has its own auxiliary ADC. Document Number: 001-11729 Rev. AG Page 63 of 140

® PSoC 3: CY8C38 Family Datasheet 8.9 DAC High and low speed / power modes The CY8C38 parts contain up to four Digital to Analog 8 Msps conversion rate for current output Convertors (DACs). Each DAC is 8-bit and can be configured for either voltage or current output. The DACs support CapSense, 1 Msps conversion rate for voltage output power supply regulation, and waveform generation. Each DAC Monotonic in nature has the following features: Data and strobe inputs can be provided by the CPU or DMA, Adjustable voltage or current output in 255 steps or routed directly from the DSI Programmable step size (range selection) Dedicated low-resistance output pin for high-current mode Eight bits of calibration to correct ± 25 percent of gain error Source and sink option for current output Figure 8-11. DAC Block Diagram I Range  source  1x, 8x, 64x Vout Reference  Scaler Iout R Source 3R I Range     sink  1x, 8x, 64x 8.9.1 Current DAC Continuous time up and down mixing works for applications with input signals and local oscillator frequencies up to 1 MHz. The current DAC (IDAC) can be configured for the ranges 0 to 31.875µA, 0 to 255 µA, and 0 to 2.04 mA. The IDAC can be Figure 8-12. Mixer Configuration configured to source or sink current. C2 = 1.7 pF 8.9.2 Voltage DAC C1 = 850 fF For the voltage DAC (VDAC), the current DAC output is routed through resistors. The two ranges available for the VDAC are 0 to 1.02V and 0 to 4.08V. In voltage mode any load connected Rmix 0 20 k or 40 k to the output of a DAC should be purely capacitive (the output of the VDAC is not buffered). sc_clk Rmix 0 20 k or 40 k 8.10 Up/Down Mixer Vin Vout In continuous time mode, the SC/CT block components are used 0 to build an up or down mixer. Any mixing application contains an Vref 1 input signal frequency and a local oscillator frequency. The sc_clk polarity of the clock, Fclk, switches the amplifier between inverting or noninverting gain. The output is the product of the input and the switching function from the local oscillator, with frequency components at the local oscillator plus and minus the 8.11 Sample and Hold signal frequency (Fclk + Fin and Fclk – Fin) and reduced-level The main application for a sample and hold, is to hold a value frequency components at odd integer multiples of the local stable while an ADC is performing a conversion. Some oscillator frequency. The local oscillator frequency is provided by applications require multiple signals to be sampled the selected clock source for the mixer. simultaneously, such as for power calculations (V and I). Document Number: 001-11729 Rev. AG Page 64 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 8-13. Sample and Hold Topology device. It does not require special interfaces, debugging pods, (1 and 2 are opposite phases of a clock) simulators, or emulators. Only the standard programming connections are required to fully support debug.   The PSoC Creator IDE software provides fully integrated 1 C C 1 Vi 1 2 Vref programming and debug support for PSoC devices. The low cost n MiniProg3 programmer and debugger is designed to provide full 2 1 2 Vout pwriothg rthaem PmSinogC a Cndre daetbour gID sEu.p PpoSrot Cof JPTSAoGC, dSeWviDce, sa nind c SoWnjuVn ction 2 interfaces are fully compatible with industry standard third party tools. All DOC circuits are disabled by default and can only be enabled 1 in firmware. If not enabled, the only way to reenable them is to erase the entire device, clear flash protection, and reprogram the  1 2 1 device with new firmware that enables DOC. Disabling DOC V features, robust flash protection, and hiding custom analog and ref digital functionality inside the PSoC device provide a level of V security not possible with multichip application solutions. 2 C3 C4 2 ref Additionally, all device interfaces can be permanently disabled (Device Security) for applications concerned about phishing attacks due to a maliciously reprogrammed device. Permanently 8.11.1 Down Mixer disabling interfaces is not recommended in most applications The SC/CT block can be used as a mixer to down convert an because you cannot access the device later. Because all input signal. This circuit is a high bandwidth passive sample programming, debug, and test interfaces are disabled when network that can sample input signals up to 14 MHz. This device security is enabled, PSoCs with Device Security enabled sampled value is then held using the opamp with a maximum may not be returned for failure analysis. clock rate of 4 MHz. The output frequency is at the difference between the input frequency and the highest integer multiple of Table 9-1. Debug Configurations the Local Oscillator that is less than the input. Debug and Trace Configuration GPIO Pins Used 8.11.2 First Order Modulator – SC Mode All debug and trace disabled 0 A first order modulator is constructed by placing the SC/CT block in an integrator mode and using a comparator to provide a 1-bit JTAG 4 or 5 feedback to the input. Depending on this bit, a reference voltage SWD 2 is either subtracted or added to the input signal. The block output is the output of the comparator and not the integrator in the SWV 1 modulator case. The signal is downshifted and buffered and then SWD + SWV 3 processed by a decimator to make a delta-sigma converter or a counter to make an incremental converter. The accuracy of the sampled data from the first-order modulator is determined from 9.1 JTAG Interface several factors. The IEEE 1149.1 compliant JTAG interface exists on four or five The main application for this modulator is for a low-frequency pins (the nTRST pin is optional). The JTAG interface is used for ADC with high accuracy. Applications include strain gauges, programming the flash memory, debugging, I/O scan chains, and thermocouples, precision voltage, and current measurement. JTAG device chaining. 9. Programming, Debug Interfaces, PSoC 3 has certain timing requirements to be met for entering programming mode through the JTAG interface. Due to these Resources timing requirements, not all standard JTAG programmers, or standard JTAG file formats such as SVF or STAPL, can support PSoC devices include extensive support for programming, PSoC 3 programming. The list of programmers that support testing, debugging, and tracing both hardware and firmware. PSoC 3 programming is available at Three interfaces are available: JTAG, SWD, and SWV. JTAG and http://www.cypress.com/go/programming. SWD support all programming and debug features of the device. JTAG also supports standard JTAG scan chains for board level The JTAG clock frequency can be up to 14MHz, or 1/3 of the test and chaining multiple JTAG devices to a single JTAG CPU clock frequency for 8 and 16-bit transfers, or 1/5 of the CPU connection. clock frequency for 32-bit transfers. By default, the JTAG pins are enabled on new devices but the JTAG interface can be disabled, For more information on PSoC 3 Programming, refer to the PSoC® 3 Device Programming Specifications. allowing these pins to be used as GPIO instead. Complete Debug on Chip (DoC) functionality enables full device debugging in the final system using the standard production Document Number: 001-11729 Rev. AG Page 65 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 9-1. JTAG Interface Connections between PSoC 3 and Programmer V DD Host Programmer PSoC 3 VDD V , V , V , V , V , V 1, 2, 3, 4 DDD DDA DDIO0 DDIO1 DDIO2 DDIO3 TCK TCK (P1[1] TMS  5 TMS (P1[0])  5 TDO TDI (P1[4]) TDI TDO (P1[3]) nTRST 6 nTRST (P1[5]) 6 XRES XRES or P1[2] 4, 7 GND V , V SSD SSA GND 1 The voltage levels of Host Programmer and the PSoC 3 voltage domains involved in Programming should be same. The Port 1 JTAG pins, XRES pin (XRES_N or P1[2]) are powered by V . So, V of PSoC 3 should be at same voltage DDIO1 DDIO1 level as host V . Rest of PSoC 3 voltage domains (V , V , V , V , V ) need not be at the same voltage level as DD DDD DDA DDIO0 DDIO2 DDIO3 host Programmer. 2 Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3. 3 For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external interface circuitry to toggle power which will depend on the programming setup. The power supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other supplies. 4 For JTAG Programming, Device reset can also be done without connecting to the XRES pin or Power cycle mode by using the TMS,TCK,TDI, TDO pins of PSoC 3, and writing to a specific register. But this requires that the DPS setting in NVL is not equal to “Debug Ports Disabled”. 5 By default, PSoC 3 is configured for 4-wire JTAG mode unless user changes the DPS setting. So the TMS pin is unidirectional. But if the DPS setting is changed to non-JTAG mode, the TMS pin in JTAG is bi-directional as the SWD Protocol has to be used for acquiring the PSoC 3 device initially. After switching from SWD to JTAG mode, the TMS pin will be uni-directional. In such a case, unidirectional buffer should not be used on TMS line. 6 nTRST JTAG pin (P1[5]) cannot be used to reset the JTAG TAP controlller during first time programming of PSoC 3 as the default setting is 4-wire JTAG (nTRST disabled). Use the TMS, TCK pins to do a reset of JTAG TAP controller. 7 If XRES pin is used by host, P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES pin). For devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48-pin devices, but use dedicated XRES pin for rest of devices. Document Number: 001-11729 Rev. AG Page 66 of 140

® PSoC 3: CY8C38 Family Datasheet 9.2 Serial Wire Debug Interface (JTAG or USB) receives a predetermined acquire sequence of 1s and 0s. If the NVL latches are set for SWD (see Section5.5), The SWD interface is the preferred alternative to the JTAG this sequence need not be applied to the JTAG pin pair. The interface. It requires only two pins instead of the four or five acquire sequence must always be applied to the USB pin pair. needed by JTAG. SWD provides all of the programming and debugging features of JTAG at the same speed. SWD does not SWD is used for debugging or for programming the flash provide access to scan chains or device chaining. The SWD memory. clock frequency can be up to 1/3 of the CPU clock frequency. The SWD interface can be enabled from the JTAG interface or SWD uses two pins, either two of the JTAG pins (TMS and TCK) disabled, allowing its pins to be used as GPIO. Unlike JTAG, the or the USBIO D+ and D– pins. The USBIO pins are useful for in SWD interface can always be reacquired on any device during system programming of USB solutions that would otherwise the key window. It can then be used to reenable the JTAG require a separate programming connector. One pin is used for interface, if desired. When using SWD or JTAG pins as standard the data clock and the other is used for data input and output. GPIO, make sure that the GPIO functionality and PCB circuits do not interfere with SWD or JTAG use. SWD can be enabled on only one of the pin pairs at a time. This only happens if, within 8 μs (key window) after reset, that pin pair Figure 9-2. SWD Interface Connections between PSoC 3 and Programmer V DD Host Programmer PSoC 3 VDD VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3 1, 2, 3 SWDCK SWDCK (P1[1] or P15[7]) SWDIO SWDIO (P1[0] or P15[6]) XRES XRES or P1[2]  3, 4 GND V , V SSD SSA GND 1 The voltage levels of the Host Programmer and the PSoC 3 voltage domains involved in Programming should be the same. XRES pin (XRES_N or P1[2]) is powered by V . The USB SWD pins are DDIO1 powered by V . So for Programming using the USB SWD pins with XRES pin, the V , V of DDD DDD DDIO1  PSoC 3 should be at the same voltage level as Host V . Rest of PSoC 3 voltage domains (V , V ,   DD DDA DDIO0 V , V ) need not be at the same voltage level as host Programmer. The Port 1 SWD pins are DDIO2 DDIO3 powered by V . So V of PSoC 3 should be at same voltage level as host V for Port 1 SWD DDIO1 DDIO1 DD programming. Rest of PSoC 3 voltage domains (V ,  V , V , V , V ) need not be at the same DDD DDA DDIO0 DDIO2 DDIO3 voltage level as host Programmer. 2 Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3. 3 For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external interface circuitry to toggle power which will depend on the programming setup. The power supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other supplies. 4 P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES pin). For devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48- pin devices, but use dedicated XRES pin for rest of devices. Document Number: 001-11729 Rev. AG Page 67 of 140

® PSoC 3: CY8C38 Family Datasheet 9.3 Debug Features erase. Individual flash blocks can be erased, programmed, and verified, if block security settings permit. Using the JTAG or SWD interface, the CY8C38 supports the following debug features: 9.7 Device Security Halt and single-step the CPU PSoC 3 offers an advanced security feature called device View and change CPU and peripheral registers, and RAM security, which permanently disables all test, programming, and debug ports, protecting your application from external access. addresses The device security is activated by programming a 32-bit key Eight program address breakpoints (0×50536F43) to a Write Once Latch (WOL). One memory access breakpoint—break on reading or writing The Write Once Latch is a type of nonvolatile latch (NVL). The any memory address and data value cell itself is an NVL with additional logic wrapped around it. Each Break on a sequence of breakpoints (non recursive) WOL device contains four bytes (32 bits) of data. The wrapper Debugging at the full speed of the CPU outputs a ‘1’ if a super-majority (28 of 32) of its bits match a pre-determined pattern (0×50536F43); it outputs a ‘0’ if this Compatible with PSoC Creator and MiniProg3 programmer and majority is not reached. When the output is 1, the Write Once NV debugger latch locks the part out of Debug and Test modes; it also Standard JTAG programming and debugging interfaces make permanently gates off the ability to erase or alter the contents of CY8C38 compatible with other popular third-party tools (for the latch. Matching all bits is intentionally not required, so that example, ARM / Keil) single (or few) bit failures do not deassert the WOL output. The state of the NVL bits after wafer processing is truly random with 9.4 Trace Features no tendency toward 1 or 0. The CY8C38 supports the following trace features when using The WOL only locks the part after the correct 32-bit key JTAG or SWD: (0×50536F43) is loaded into the NVL's volatile memory, Trace the 8051 program counter (PC), accumulator register programmed into the NVL's nonvolatile cells, and the part is (ACC), and one SFR / 8051 core RAM register reset. The output of the WOL is only sampled on reset and used to disable the access. This precaution prevents anyone from Trace depth up to 1000 instructions if all registers are traced, reading, erasing, or altering the contents of the internal memory. or 2000 instructions if only the PC is traced (on devices that include trace memory) The user can write the key into the WOL to lock out external access only if no flash protection is set (see “Flash Security” on Program address trigger to start tracing page23). However, after setting the values in the WOL, a user Trace windowing, that is, only trace when the PC is within a still has access to the part until it is reset. Therefore, a user can given range write the key into the WOL, program the flash protection data, Two modes for handling trace buffer full: continuous (overwriting and then reset the part to lock it. the oldest trace data) or break when trace buffer is full If the device is protected with a WOL setting, Cypress cannot 9.5 Single Wire Viewer Interface perform failure analysis and, therefore, cannot accept RMAs from customers. The WOL can be read out through the SWD port The SWV interface is closely associated with SWD but can also to electrically identify protected parts. The user can write the key be used independently. SWV data is output on the JTAG in WOL to lock out external access only if no flash protection is interface’s TDO pin. If using SWV, you must configure the device set. For more information on how to take full advantage of the for SWD, not JTAG. SWV is not supported with the JTAG security features in PSoC see the PSoC 3 TRM. interface. Disclaimer SWV is ideal for application debug where it is helpful for the Note the following details of the flash code protection features on firmware to output data similar to 'printf' debugging on PCs. The Cypress devices. SWV is ideal for data monitoring, because it requires only a single pin and can output data in standard UART format or Cypress products meet the specifications contained in their Manchester encoded format. For example, it can be used to tune particular Cypress data sheets. Cypress believes that its family a PID control loop in which the output and graphing of the three of products is one of the most secure families of its kind on the error terms greatly simplifies coefficient tuning. market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code The following features are supported in SWV: protection features. Any of these methods, to our knowledge, 32 virtual channels, each 32 bits long would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of Simple, efficient packing and serializing protocol their code. Code protection does not mean that we are Supports standard UART format (N81) guaranteeing the product as “unbreakable.” 9.6 Programming Features Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly The JTAG and SWD interfaces provide full programming evolving. We at Cypress are committed to continuously support. The entire device can be erased, programmed, and improving the code protection features of our products. verified. You can increase flash protection levels to protect firmware IP. Flash protection can only be reset after a full device Document Number: 001-11729 Rev. AG Page 68 of 140

® PSoC 3: CY8C38 Family Datasheet 9.8 CSP Package Bootloader For more information on this bootloader, see the following Cypress application notes: A factory-installed bootloader program is included in all devices with CSP packages. The bootloader is compatible with PSoC AN89611 – PSoC® 3 AND PSoC 5LP - Getting Started With Creator 3.0 bootloadable project files and has the following Chip Scale Packages (CSP) features: AN73854 – PSoC 3 and PSoC 5 LP Introduction to Bootloaders I2C-based AN60317 – PSoC 3 and PSoC 5 LP I2C Bootloader SCLK and SDAT available at P1[6] and P1[7], respectively Note that a PSOC Creator bootloadable project must be External pull-up resistors required associated with .hex and .elf files for a bootloader project that is configured for the target device. Bootloader .hex and .elf files I2C slave, address 4, data rate = 100 kbps can be found at www.cypress.com/go/PSoC3datasheet. Single application The factory-installed bootloader can be overwritten using JTAG or SWD programming. Wait two seconds for bootload command Other bootloader options are as set by the PSoC Creator 3.0 Bootloader Component default Occupies the bottom 9K of flash Document Number: 001-11729 Rev. AG Page 69 of 140

® PSoC 3: CY8C38 Family Datasheet 10. Development Support Application Notes: PSoC application notes discuss a particular application of PSoC in depth; examples include brushless DC The CY8C38 family has a rich set of documentation, motor control and on-chip filtering. Application notes often development tools, and online resources to assist you during include example projects in addition to the application note your development process. Visit document. psoc.cypress.com/getting-started to find out more. Technical Reference Manual: The Technical Reference Manual (TRM) contains all the technical detail you need to use a PSoC 10.1 Documentation device, including a complete description of all PSoC registers. A suite of documentation, supports the CY8C38 family to ensure that you can find answers to your questions quickly. This section 10.2 Online contains a list of some of the key documents. In addition to print documentation, the Cypress PSoC forums Software User Guide: A step-by-step guide for using PSoC connect you with fellow PSoC users and experts in PSoC from Creator. The software user guide shows you how the PSoC around the world, 24 hours a day, 7 days a week. Creator build process works in detail, how to use source control 10.3 Tools with PSoC Creator, and much more. Component data sheets: The flexibility of PSoC allows the With industry standard cores, programming, and debugging creation of new peripherals (components) long after the device interfaces, the CY8C38 family is part of a development tool has gone into production. Component data sheets provide all of ecosystem. Visit us at www.cypress.com/go/psoccreator for the the information needed to select and use a particular component, latest information on the revolutionary, easy to use PSoC Creator including a functional description, API documentation, example IDE, supported third party compilers, programmers, debuggers, code, and AC/DC specifications. and development kits. Document Number: 001-11729 Rev. AG Page 70 of 140

® PSoC 3: CY8C38 Family Datasheet 11. Electrical Specifications Specifications are valid for –40°C  T  85°C and T  100°C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, see the component data sheets for full AC/DC specifications of individual functions. See the “Example Peripherals” section on page44 for further explanation of PSoC Creator components. 11.1 Absolute Maximum Ratings Table 11-1. Absolute Maximum Ratings DC Specifications[18] Parameter Description Conditions Min Typ Max Units V Analog supply voltage relative to –0.5 – 6 V DDA V SSA V Digital supply voltage relative to –0.5 – 6 V DDD V SSD V I/O supply voltage relative to V –0.5 – 6 V DDIO SSD V Direct analog core voltage input –0.5 – 1.95 V CCA V Direct digital core voltage input –0.5 – 1.95 V CCD V Analog ground voltage V – 0.5 – V + V SSA SSD SSD 0.5 V [19] DC input voltage on GPIO Includes signals sourced by V V – 0.5 – V + V GPIO DDA SSD DDIO and routed internal to the pin 0.5 V DC input voltage on SIO Output disabled V – 0.5 – 7 V SIO SSD Output enabled V – 0.5 – 6 V SSD V Voltage at boost converter input 0.5 – 5.5 V IND V Boost converter supply V – 0.5 – 5.5 V BAT SSD I Current per V supply pin – – 100 mA VDDIO DDIO I GPIO current –30 – 41 mA GPIO I SIO current –49 – 28 mA SIO I USBIO current –56 – 59 mA USBIO V ADC external reference inputs Pins P0[3], P3[2] – – 2 V EXTREF LU Latch up current[20] –140 – 140 mA Electrostatic discharge voltage, V tied to V 2200 – – V SSA SSD ESDHBM Human body model V not tied to V 750 – – V SSA SSD Electrostatic discharge voltage, 500 – – V ESD CDM Charge device model Notes 18.Usage above the absolute maximum conditions listed in Table11-1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification. 19.The VDDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin VDDIO  VDDA. 20.Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test. Document Number: 001-11729 Rev. AG Page 71 of 140

® PSoC 3: CY8C38 Family Datasheet 11.2 Device Level Specifications Specifications are valid for –40°C  T  85°C and T  100°C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter Description Conditions Min Typ[25] Max Units Analog supply voltage and input to analog core V Analog core regulator enabled 1.8 – 5.5 V DDA regulator Analog supply voltage, analog regulator V Analog core regulator disabled 1.71 1.8 1.89 V DDA bypassed 1.8 – V [21] V Digital supply voltage relative to V Digital core regulator enabled DDA V DDD SSD – – V + 0.1[27] DDA Digital supply voltage, digital regulator V Digital core regulator disabled 1.71 1.8 1.89 V DDD bypassed 1.71 – V [21] V [22] I/O supply voltage relative to V DDA V DDIO SSIO – – V + 0.1[27] DDA Direct analog core voltage input (Analog V Analog core regulator disabled 1.71 1.8 1.89 V CCA regulator bypass) Direct digital core voltage input (Digital V Digital core regulator disabled 1.71 1.8 1.89 V CCD regulator bypass) Active Mode V = 2.7 V – 5.5 T = –40 °C – 1.2 2.9 Only IMO and CPU clock enabled. CPU DDX V; T = 25 °C – 1.2 3.1 executing simple loop from instruction buffer. FCPU = 6 MHz[26] T = 85 °C – 4.9 7.7 V = 2.7 V – 5.5 T = –40 °C – 1.3 2.9 DDX V; T = 25 °C – 1.6 3.2 FCPU = 3 MHz[26] T = 85 °C – 4.8 7.5 V = 2.7 V – 5.5 T = –40 °C – 2.1 3.7 DDX V; T = 25 °C – 2.3 3.9 F = 6 MHz CPU T = 85 °C – 5.6 8.5 I [23, 24] VDDX = 2.7 V – T = –40 °C – 3.5 5.2 DD 5.5V; T = 25 °C – 3.8 5.5 mA IMO enabled, bus clock and CPU clock FCPU = 12 MHz[26] T = 85 °C – 7.1 9.8 enabled. CPU executing program from flash. V = 2.7V– T = –40 °C – 6.3 8.1 DDX 5.5V; T = 25 °C – 6.6 8.3 FCPU = 24 MHz[26] T = 85 °C – 10 13 V = 2.7 V – 5.5 T = –40 °C – 11.5 13.5 DDX V; T = 25 °C – 12 14 FCPU = 48 MHz[26] T = 85 °C – 15.5 18.5 V = 2.7 V – 5.5 T = –40 °C – 16 18 DDX V; T = 25 °C – 16 18 FCPU = 62 MHz T = 85 °C – 19.5 23 Notes 21.The power supplies can be brought up in any sequence however once stable VDDA must be greater than or equal to all other supplies. 22.The VDDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin VDDIO  VDDA. 23.Total current for all power domains: digital (IDDD), analog (IDDA), and I/Os (IDDIO0, 1, 2, 3). Boost not included. All I/Os floating. 24.The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in PSoC Creator, the integrated design environment. To estimate total current, find the CPU current at the frequency of interest and add peripheral currents for your particular system from the device datasheet and component datasheets. 25.VDDX = 3.3 V. 26.Based on device specifications (not production tested). 27.Guaranteed by design, not production tested. Document Number: 001-11729 Rev. AG Page 72 of 140

® PSoC 3: CY8C38 Family Datasheet Table 11-2. DC Specifications (continued) Parameter Description Conditions Min Typ[25] Max Units Sleep Mode[28] CPU = OFF V = V = T = –40 °C – 1.1 2.3 µA DD DDIO RTC = ON (= ECO32K ON, in low-power 4.5V-5.5V T = 25 °C – 1.1 2.2 mode) Sleep timer = ON (= ILO ON at 1 kHz)[29] T = 85 °C – 15 30 WDT = OFF VDD = VDDIO = T = –40 °C – 1 2.2 I2C Wake = OFF 2.7V–3.6V T = 25 °C – 1 2.1 Comparator = OFF T = 85 °C – 12 28 POR = ON Boost = OFF VDD = VDDIO = T = 25 °C – 2.2 4.2 SIO pins in single ended input, unregulated 1.71V–1.95V[30] output mode Comparator = ON V = V = T = 25 °C – 2.2 2.7 DD DDIO CPU = OFF 2.7V–3.6V[31] RTC = OFF Sleep timer = OFF WDT = OFF I2C Wake = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode I2C Wake = ON V = V = T = 25 °C – 2.2 2.8 DD DDIO CPU = OFF 2.7V–3.6V[31] RTC = OFF Sleep timer = OFF WDT = OFF Comparator = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode Hibernate Mode[28] Hibernate mode current V = V = T = –40 °C – 0.2 1.5 µA DD DDIO All regulators and oscillators off 4.5V-5.5V T = 25 °C – 0.5 1.5 SRAM retention T = 85 °C – 4.1 5.3 GPIO interrupts are active Boost = OFF VDD = VDDIO = T = –40 °C – 0.2 1.5 SIO pins in single ended input, unregulated 2.7V–3.6V T = 25 °C – 0.2 1.5 output T = 85 °C – 3.2 4.2 mode V = V = T = –40 °C – 0.2 1.5 DD DDIO 1.71V–1.95V[30] T = 25 °C – 0.3 1.5 T = 85 °C – 3.3 4.3 I Analog current consumption while device is V  3.6V – 0.3 0.6 mA DDAR DDA reset[32] V  3.6V – 1.4 3.3 mA DDA I Digital current consumption while device is V  3.6V – 1.1 3.1 mA DDDR DDD reset[32] V  3.6V – 0.7 3.1 mA DDD Notes 28.If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV. 29.Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off. 30.Externally regulated mode. 31.Based on device characterization (not production tested). 32.Based on device characterization (not production tested). USBIO pins tied to ground (VSSD). Document Number: 001-11729 Rev. AG Page 73 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-1. Active Mode Current vs F , V = 3.3 V, Figure 11-2. Active Mode Current vs Temperature and F , CPU DD CPU Temperature = 25 °C V = 3.3 V DD Figure 11-3. Active Mode Current vs V and Temperature, DD F = 24 MHz CPU Document Number: 001-11729 Rev. AG Page 74 of 140

® PSoC 3: CY8C38 Family Datasheet Table 11-3. AC Specifications[33] Parameter Description Conditions Min Typ Max Units F CPU frequency 1.71V  V  5.5V DC – 67.01 MHz CPU DDD F Bus frequency 1.71V  V  5.5V DC – 67.01 MHz BUSCLK DDD Svdd V ramp rate – – 0.066 V/µs DD T Time from V /V /V /V – – 10 µs IO_INIT DDD DDA CCD CCA IPOR to I/O ports set to their reset states T Time from V /V /V /V V /V = regulated from – – 40 µs STARTUP DDD DDA CCD CCA CCA DDA  PRES to CPU executing code at V /V , no PLL used, fast IMO DDA DDD reset vector boot mode (48 MHz typ.) V /V = regulated from – – 74 µs CCA CCD V /V , no PLL used, slow DDA DDD IMO boot mode (12 MHz typ.) T Wakeup from sleep mode – – – 15 µs SLEEP Application of non-LVD interrupt to beginning of execution of next CPU instruction T Wakeup from hibernate mode – – – 100 µs HIBERNATE Application of external interrupt to beginning of execution of next CPU instruction Figure 11-4. F vs. V CPU DD 5.5 V Valid Operating Region ge3.3 V a olt V d d V 1.71 V Valid Operating Region with SMP 0.5 V 0 V DC 1 MHz 10 MHz 67 MHz CPU Frequency Note 33.Based on device characterization (Not production tested). Document Number: 001-11729 Rev. AG Page 75 of 140

® PSoC 3: CY8C38 Family Datasheet 11.3 Power Regulators Specifications are valid for –40°C  T  85°C and T  100°C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description Conditions Min Typ Max Units V Input voltage 1.8 – 5.5 V DDD V Output voltage – 1.80 – V CCD Regulator output capacitor ±10%, X5R ceramic or better. The two 0.9 1 1.1 µF V pins must be shorted together, with CCD as short a trace as possible, see Power System on page 31 Figure 11-5. Regulators V vs V Figure 11-6. Digital Regulator PSRR vs Frequency and V CC DD DD 11.3.2 Analog Core Regulator Table 11-5. Analog Core Regulator DC Specifications Parameter Description Conditions Min Typ Max Units V Input voltage 1.8 – 5.5 V DDA V Output voltage – 1.80 – V CCA Regulator output capacitor ±10%, X5R ceramic or better 0.9 1 1.1 µF Figure 11-7. Analog Regulator PSRR vs Frequency and V DD Document Number: 001-11729 Rev. AG Page 76 of 140

® PSoC 3: CY8C38 Family Datasheet 11.3.3 Inductive Boost Regulator Unless otherwise specified, operating conditions are: V = 0.5 V–3.6 V, V = 1.8 V–5.0 V, I = 0 mA–50 mA, BAT OUT OUT L = 4.7 µH–22 µH, C = 22 µF || 3 × 1.0 µF || 3 × 0.1 µF, C = 22 µF, I = 1.0 A. Unless otherwise specified, all charts BOOST BOOST BAT F and graphs show typical values. Table 11-6. Inductive Boost Regulator DC Specifications Parameter Description Conditions Min Typ Max Units VOUT Boost output voltage[34] vsel = 1.8 V in register BOOST_CR0 1.71 1.8 1.89 V vsel = 1.9 V in register BOOST_CR0 1.81 1.90 2.00 V vsel = 2.0 V in register BOOST_CR0 1.90 2.00 2.10 V vsel = 2.4 V in register BOOST_CR0 2.16 2.40 2.64 V vsel = 2.7 V in register BOOST_CR0 2.43 2.70 2.97 V vsel = 3.0 V in register BOOST_CR0 2.70 3.00 3.30 V vsel = 3.3 V in register BOOST_CR0 2.97 3.30 3.63 V vsel = 3.6 V in register BOOST_CR0 3.24 3.60 3.96 V vsel = 5.0 V in register BOOST_CR0 4.50 5.00 5.50 V VBAT Input voltage to boost[35] IOUT = 0 mA–5 mA vsel = 1.8 V–2.0 V, 0.5 – 0.8 V T = 0 °C–70 °C A I = 0 mA–15 mA vsel = 1.8 V–5.0 V[36], 1.6 – 3.6 V OUT T = –10 °C–85 °C A I = 0 mA–25 mA vsel = 1.8 V–2.7 V, 0.8 – 1.6 V OUT T = –10 °C–85 °C A I = 0 mA–50 mA vsel = 1.8 V–3.3 V[36], 1.8 – 2.5 V OUT T = –40 °C–85 °C A vsel = 1.8 V–3.3 V[36], 1.3 – 2.5 V T = –10 °C–85 °C A vsel = 2.5 V–5.0 V[36], 2.5 – 3.6 V T = –10 °C–85 °C A I Output current T = 0 °C–70 °C V = 0.5 V–0.8 V 0 – 5 mA OUT A BAT T = –10 °C–85 °C V = 1.6 V–3.6 V 0 – 15 mA A BAT V = 0.8 V–1.6 V 0 – 25 mA BAT V = 1.3 V–2.5 V 0 – 50 mA BAT V = 2.5 V–3.6 V 0 – 50 mA BAT T = –40 °C–85 °C V = 1.8 V–2.5 V 0 – 50 mA A BAT I Inductor peak current – – 700 mA LPK I Quiescent current Boost active mode – 250 – µA Q Boost sleep mode, I < 1 µA – 25 – µA OUT Reg Load regulation – – 10 % LOAD Reg Line regulation – – 10 % LINE Notes 34.Listed vsel options are characterized. Additional vsel options are valid and guaranteed by design. 35.The boost will start at all valid VBAT conditions including down to VBAT = 0.5 V. 36.If VBAT is greater than or equal to VOUT boost setting, then VOUT will be less than VBAT due to resistive losses in the boost circuit. Document Number: 001-11729 Rev. AG Page 77 of 140

® PSoC 3: CY8C38 Family Datasheet Table 11-7. Recommended External Components for Boost Circuit Parameter Description Conditions Min Typ Max Units L Boost inductor 4.7 µH nominal 3.7 4.7 5.7 µH BOOST 10 µH nominal 8.0 10.0 12.0 µH 22 µH nominal 17.0 22.0 27.0 µH C Total capacitance sum of 17.0 26.0 31.0 µF BOOST V , V , V [37] DDD DDA DDIO C Battery filter capacitor 17.0 22.0 27.0 µF BAT I Schottky diode average 1.0 – – A F forward current V Schottky reverse voltage 20.0 – – V R Figure 11-8. T range over V and V Figure 11-9. I range over V and V A BAT OUT OUT BAT OUT (cid:8)(cid:3)(cid:23) (cid:8)(cid:3)(cid:23) (cid:14)(cid:6)(cid:2)(cid:11)(cid:10)(cid:5)(cid:4)(cid:11)(cid:15)(cid:13) (cid:2)(cid:14)(cid:9)(cid:4)(cid:11)(cid:30)(cid:25) (cid:14)(cid:9)(cid:2)(cid:11)(cid:10)(cid:5)(cid:4)(cid:11)(cid:12)(cid:13) (cid:6)(cid:3)(cid:4) (cid:6)(cid:3)(cid:4) (cid:2)(cid:14)(cid:4)(cid:2)(cid:11)(cid:30)(cid:25) (cid:14)(cid:16)(cid:2)(cid:14)(cid:16)(cid:11)(cid:10)(cid:2)(cid:11)(cid:5)(cid:10)(cid:4)(cid:5)(cid:11)(cid:12)(cid:4)(cid:13)(cid:11)(cid:17)(cid:13) (cid:24)(cid:27)(cid:11)(cid:24)(cid:20)(cid:25)(cid:26) (cid:9)(cid:9)(cid:3)(cid:3)(cid:23)(cid:5) (cid:24)(cid:27)(cid:11)(cid:24)(cid:20)(cid:25)(cid:26) (cid:9)(cid:3)(cid:23) (cid:2)(cid:14)(cid:9)(cid:4)(cid:11)(cid:30)(cid:25) (cid:9)(cid:3)(cid:8) (cid:9)(cid:3)(cid:8) (cid:2)(cid:14)(cid:6)(cid:4)(cid:11)(cid:30)(cid:25) (cid:2)(cid:3)(cid:5) (cid:18)(cid:19)(cid:11)(cid:20)(cid:19)(cid:19)(cid:21)(cid:22) (cid:2)(cid:3)(cid:5) (cid:18)(cid:19)(cid:11)(cid:20)(cid:19)(cid:19)(cid:21)(cid:22) (cid:2)(cid:3)(cid:4) (cid:2)(cid:10)(cid:7)(cid:2)(cid:11)(cid:12)(cid:13) (cid:2)(cid:3)(cid:4) (cid:2)(cid:14)(cid:4)(cid:11)(cid:30)(cid:25) (cid:2) (cid:2) (cid:9)(cid:3)(cid:2) (cid:9)(cid:3)(cid:5) (cid:6)(cid:3)(cid:2) (cid:6)(cid:3)(cid:7) (cid:8)(cid:3)(cid:8) (cid:4)(cid:3)(cid:2) (cid:9)(cid:3)(cid:2) (cid:9)(cid:3)(cid:5) (cid:6)(cid:3)(cid:2) (cid:6)(cid:3)(cid:4)(cid:6)(cid:3)(cid:7) (cid:8)(cid:3)(cid:8) (cid:4)(cid:3)(cid:2) (cid:24)(cid:28)(cid:29)(cid:26)(cid:27)(cid:11)(cid:24) (cid:24)(cid:28)(cid:29)(cid:26)(cid:27)(cid:11)(cid:24) Figure 11-10. L values over V and V BOOST BAT OUT (cid:8)(cid:3)(cid:23) (cid:16)(cid:3)(cid:7)(cid:11)(cid:31) ! "#(cid:11)(cid:6)(cid:4)(cid:11)(cid:30)(cid:25)$(cid:11)(cid:16)(cid:3)(cid:7)(cid:11)(cid:31) (cid:27)(cid:11)(cid:9)(cid:2)(cid:11)(cid:31) (cid:11) (cid:28)(cid:29)(cid:26) (cid:9)(cid:2)(cid:11)(cid:31) ! "#(cid:11)(cid:4)(cid:2)(cid:11)(cid:30)(cid:25)$(cid:11)(cid:16)(cid:3)(cid:7)(cid:11)(cid:31) (cid:11) (cid:28)(cid:29)(cid:26) (cid:6)(cid:3)(cid:4) (cid:24) (cid:16)(cid:3)(cid:7)(cid:11)(cid:31) (cid:16)(cid:3)(cid:7)(cid:11)(cid:31) (cid:24)(cid:27)(cid:11)(cid:20)(cid:25)(cid:26) (cid:9)(cid:3)(cid:23) (cid:9)(cid:6)(cid:2)(cid:6)(cid:11)(cid:11)(cid:31)(cid:31) (cid:9)(cid:2)(cid:11)(cid:31) (cid:9)(cid:3)(cid:8) (cid:16)(cid:3)(cid:7)(cid:11)(cid:31) (cid:9)(cid:2)(cid:11)(cid:31) (cid:2)(cid:3)(cid:5) (cid:18)(cid:19)(cid:11)(cid:20)(cid:19)(cid:19)(cid:21)(cid:22) (cid:2)(cid:3)(cid:4) (cid:9)(cid:2)(cid:11)(cid:31) (cid:2) (cid:9)(cid:3)(cid:2) (cid:9)(cid:3)(cid:5) (cid:6)(cid:3)(cid:2) (cid:6)(cid:3)(cid:4) (cid:6)(cid:3)(cid:7) (cid:8)(cid:3)(cid:8) (cid:4)(cid:3)(cid:2) (cid:24) (cid:27)(cid:11)(cid:24) (cid:28)(cid:29)(cid:26) Note 37.Based on device characterization (Not production tested). Document Number: 001-11729 Rev. AG Page 78 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-11. Efficiency vs V , L = 4.7 µH [38] Figure 11-12. Efficiency vs V , L = 10 µH [38] BAT BOOST BAT BOOST 100% 100% 95% Vout = 1.8 V 95% 90% Vout = 2.4 V 90% 85% Vout = 3.3 V 85% % Efficiency 778050%%% Vout = 5.0 V % Efficiency 778050%%% VVoouutt == 12..84 VV 6655%% 6655%% VVoouutt == 33.33 VV 60% 60% Vout = 5.0 V 55% 55% 50% 50% 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 VBAT, V VBAT, V Figure 11-13. Efficiency vs V , L = 22 µH [38] Figure 11-14. V vs V [38] BAT BOOST RIPPLE BAT 100% 300 95% 250 90% 85% 200 % Efficiency 778050%%% VVoouutt == 12..84 VV V, mVRIPPLE110500 LLbboooosstt == 41.07 uuHH 6655%% Vout = 3.3 V Lboost = 22 uH 60% 50 55% 0 50% 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 VBAT, V VBAT, V Note 38.Typical example. Actual values may vary depending on external component selection, PCB layout, and other design parameters. Document Number: 001-11729 Rev. AG Page 79 of 140

® PSoC 3: CY8C38 Family Datasheet 11.4 Inputs and Outputs Specifications are valid for –40°C  T  85°C and T  100°C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. Unless otherwise specified, all charts and graphs show typical values. When the power supplies ramp up, there are low-impedance connections between each GPIO pin and its V supply. This causes DDIO the pin voltages to track V until both V and V reach the IPOR voltage, which can be as high as 1.45V. At that point, the DDIO DDIO DDA low-impedance connections no longer exist and the pins change to their normal NVL settings. 11.4.1 GPIO Table 11-9. GPIO DC Specifications Parameter Description Conditions Min Typ Max Units V Input voltage high threshold CMOS Input, PRT[×]CTL = 0 0.7  V – – V IH DDIO V Input voltage low threshold CMOS Input, PRT[×]CTL = 0 – – 0.3 V V IL DDIO V Input voltage high threshold LVTTL Input, PRT[×]CTL = 1, 0.7 × V – – V IH DDIO V < 2.7V DDIO V Input voltage high threshold LVTTL Input, PRT[×]CTL = 1, 2.0 – – V IH V  2.7V DDIO V Input voltage low threshold LVTTL Input, PRT[×]CTL = 1, – – 0.3 × V V IL DDIO V < 2.7V DDIO V Input voltage low threshold LVTTL Input, PRT[×]CTL = 1, – – 0.8 V IL V  2.7V DDIO V Output voltage high I = 4 mA at 3.3 V V – 0.6 – – V OH OH DDIO DDIO I = 1 mA at 1.8 V V – 0.5 – – V OH DDIO DDIO V Output voltage low I = 8 mA at 3.3 V – – 0.6 V OL OL DDIO I = 4 mA at 1.8 V – – 0.6 V OL DDIO I = 3 mA at 3.3 V – – 0.4 V OL DDIO Rpullup Pull-up resistor 3.5 5.6 8.5 k Rpulldown Pull-down resistor 3.5 5.6 8.5 k I Input leakage current (absolute value)[39] 25 °C, V = 3.0 V – – 2 nA IL DDIO C Input capacitance[39] GPIOs not shared with opamp – 4 7 pF IN outputs, MHz ECO or kHzECO GPIOs shared with MHz ECO – 5 7 pF or kHzECO[40] GPIOs shared with opamp – – 18 pF outputs V Input voltage hysteresis (Schmitt-Trigger)[39] – 40 – mV H Idiode Current through protection diode to V and – – 100 µA DDIO V SSIO Rglobal Resistance pin to analog global bus 25 °C, V = 3.0 V – 320 –  DDIO Rmux Resistance pin to analog mux bus 25°C, V = 3.0 V – 220 –  DDIO Notes 39.Based on device characterization (Not production tested). 40.For information on designing with PSoC oscillators, refer to the application note, AN54439 - PSoC® 3 and PSoC 5 External Oscillator. Document Number: 001-11729 Rev. AG Page 80 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-15. GPIO Output High Voltage and Current Figure 11-16. GPIO Output Low Voltage and Current Table 11-10. GPIO AC Specifications Parameter Description Conditions Min Typ Max Units TriseF Rise time in Fast Strong Mode[41] 3.3V V Cload = 25 pF – – 6 ns DDIO TfallF Fall time in Fast Strong Mode[41] 3.3V V Cload = 25 pF – – 6 ns DDIO TriseS Rise time in Slow Strong Mode[41] 3.3V V Cload = 25 pF – – 60 ns DDIO TfallS Fall time in Slow Strong Mode[41] 3.3V V Cload = 25 pF – – 60 ns DDIO GPIO output operating frequency 2.7V < V < 5.5V, fast strong drive mode 90/10% V into 25 pF – – 33 MHz DDIO DDIO Fgpioout 1.71V < V < 2.7V, fast strong drive mode 90/10% V into 25 pF – – 20 MHz DDIO DDIO 3.3V < V < 5.5V, slow strong drive mode 90/10% V into 25 pF – – 7 MHz DDIO DDIO 1.71V < V < 3.3V, slow strong drive mode 90/10% V into 25 pF – – 3.5 MHz DDIO DDIO GPIO input operating frequency Fgpioin 1.71V < V < 5.5V 90/10% V – – 33 MHz DDIO DDIO Note 41.Based on device characterization (Not production tested). Document Number: 001-11729 Rev. AG Page 81 of 140

® PSoC 3: CY8C38 Family Datasheet 11.4.2 SIO Table 11-11. SIO DC Specifications Parameter Description Conditions Min Typ Max Units Vinmax Maximum input voltage All allowed values of V and – – 5.5 V DDIO V , see Section11.1 DDD Vinref Input voltage reference 0.5 – 0.52 V V DDIO (Differential input mode) Output voltage reference (Regulated output mode) Voutref V > 3.7 1 – V – 1 V DDIO DDIO V < 3.7 1 – V – 0.5 V DDIO DDIO Input voltage high threshold GPIO mode CMOS input 0.7  V – – V V DDIO IH Differential input mode[42] Hysteresis disabled SIO_ref + 0.2 – – V Input voltage low threshold V GPIO mode CMOS input – – 0.3 V V IL DDIO Differential input mode[42] Hysteresis disabled – – SIO_ref – 0.2 V Output voltage high Unregulated mode I = 4 mA, V = 3.3V V – 0.4 – – V OH DDIO DDIO V OH Regulated mode[42] I = 1 mA SIO_ref – 0.65 – SIO_ref + 0.2 V OH Regulated mode[42] I = 0.1 mA SIO_ref – 0.3 – SIO_ref + 0.2 V OH V Output voltage low V = 3.30 V, I = 25 mA – – 0.8 V OL DDIO OL V = 3.30 V, I = 20 mA – – 0.4 V DDIO OL V = 1.80 V, I = 4 mA – – 0.4 V DDIO OL Rpullup Pull-up resistor 3.5 5.6 8.5 k Rpulldown Pull-down resistor 3.5 5.6 8.5 k I Input leakage current IL (Absolute value)[43] V < Vddsio 25°C, Vddsio = 3.0 V, V = 3.0 V – – 14 nA IH IH V > Vddsio 25°C, Vddsio = 0 V, V = 3.0 V – – 10 µA IH IH C Input Capacitance[43] – – 7 pF IN Input voltage hysteresis Single ended mode (GPIO – 40 – mV V (Schmitt-Trigger)[43] mode) H Differential mode – 35 – mV Current through protection diode – – 100 µA Idiode to V SSIO Notes 42.See Figure 6-10 on page 39 and Figure 6-13 on page 43 for more information on SIO reference. 43.Based on device characterization (Not production tested). Document Number: 001-11729 Rev. AG Page 82 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-17. SIO Output High Voltage and Current, Figure 11-18. SIO Output Low Voltage and Current, Unregulated Mode Unregulated Mode Figure 11-19. SIO Output High Voltage and Current, Regulat- ed Mode Table 11-12. SIO AC Specifications Parameter Description Conditions Min Typ Max Units TriseF Rise time in fast strong mode Cload = 25 pF, V = 3.3V – – 12 ns DDIO (90/10%)[44] TfallF Fall time in fast strong mode Cload = 25 pF, V = 3.3V – – 12 ns DDIO (90/10%)[44] TriseS Rise time in slow strong mode Cload = 25 pF, V = 3.0 V – – 75 ns DDIO (90/10%)[44] TfallS Fall time in slow strong mode Cload = 25 pF, V = 3.0 V – – 60 ns DDIO (90/10%)[44] Note 44.Based on device characterization (Not production tested). Document Number: 001-11729 Rev. AG Page 83 of 140

® PSoC 3: CY8C38 Family Datasheet Table 11-12. SIO AC Specifications (continued) Parameter Description Conditions Min Typ Max Units SIO output operating frequency 2.7V < V < 5.5V, Unregulated 90/10% V into 25 pF – – 33 MHz DDIO DDIO output (GPIO) mode, fast strong drive mode 1.71V < V < 2.7V, 90/10% V into 25 pF – – 16 MHz DDIO DDIO Unregulated output (GPIO) mode, fast strong drive mode 3.3V < V < 5.5V, Unregulated 90/10% V into 25 pF – – 5 MHz DDIO DDIO output (GPIO) mode, slow strong drive mode 1.71V < V < 3.3V, Unregu- 90/10% V into 25 pF – – 4 MHz Fsioout DDIO DDIO lated output (GPIO) mode, slow strong drive mode 2.7V < V < 5.5V, Regulated Output continuously switching – – 20 MHz DDIO output mode, fast strong drive into 25 pF mode 1.71V < V < 2.7V, Regulated Output continuously switching – – 10 MHz DDIO output mode, fast strong drive into 25 pF mode 1.71V < V < 5.5V, Regulated Output continuously switching – – 2.5 MHz DDIO output mode, slow strong drive into 25 pF mode SIO input operating frequency Fsioin 1.71V < V < 5.5V 90/10% V – – 33 MHz DDIO DDIO Figure 11-20. SIO Output Rise and Fall Times, Fast Strong Figure 11-21. SIO Output Rise and Fall Times, Slow Strong Mode, V = 3.3 V, 25 pF Load Mode, V = 3.3 V, 25 pF Load DDIO DDIO Document Number: 001-11729 Rev. AG Page 84 of 140

® PSoC 3: CY8C38 Family Datasheet Table 11-13. SIO Comparator Specifications[45] Parameter Description Conditions Min Typ Max Units Vos Offset voltage V = 2 V – – 68 mV DDIO V = 2.7 V – – 72 DDIO V = 5.5 V – – 82 DDIO TCVos Offset voltage drift with temp – – 250 μV/°C CMRR Common mode rejection ratio V = 2 V 30 – – dB DDIO V = 2.7 V 35 – – DDIO V = 5.5 V 40 – – DDIO Tresp Response time – – 30 ns 11.4.3 USBIO For operation in GPIO mode, the standard range for V applies, see Device Level Specifications on page 72. DDD Table 11-14. USBIO DC Specifications Parameter Description Conditions Min Typ Max Units Rusbi USB D+ pull-up resistance With idle bus 0.900 – 1.575 k Rusba USB D+ pull-up resistance While receiving traffic 1.425 – 3.090 k Vohusb Static output high 15 k ±5% to Vss, internal pull-up 2.8 – 3.6 V enabled Volusb Static output low 15 k ±5% to Vss, internal pull-up – – 0.3 V enabled Vihgpio Input voltage high, GPIO mode V 3V 2 – – V DDD Vilgpio Input voltage low, GPIO mode V 3V – – 0.8 V DDD Vohgpio Output voltage high, GPIO mode I = 4 mA, V  3V 2.4 – – V OH DDD Volgpio Output voltage low, GPIO mode I = 4 mA, V  3V – – 0.3 V OL DDD Vdi Differential input sensitivity |(D+) – (D–)| – – 0.2 V Vcm Differential input common mode – 0.8 – 2.5 V range Vse Single ended receiver threshold – 0.8 – 2 V Rps2 PS/2 pull-up resistance In PS/2 mode, with PS/2 pull-up 3 – 7 k enabled External USB series resistor In series with each USB pin 21.78 22 22.22  Rext (–1%) (+1%) Zo USB driver output impedance Including Rext 28 – 44  C USB transceiver input capacitance – – – 20 pF IN I [45] Input leakage current (absolute value) 25°C, V = 3.0 V – – 2 nA IL DDD Note 45.Based on device characterization (Not production tested). Document Number: 001-11729 Rev. AG Page 85 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-22. USBIO Output High Voltage and Current, GPIO Figure 11-23. USBIO Output Low Voltage and Current, GPIO Mode Mode Table 11-15. USBIO AC Specifications Parameter Description Conditions Min Typ Max Units Tdrate Full-speed data rate average bit rate 12 – 0.25% 12 12 + 0.25% MHz Tjr1 Receiver data jitter tolerance to next –8 – 8 ns transition Tjr2 Receiver data jitter tolerance to pair –5 – 5 ns transition Tdj1 Driver differential jitter to next transition –3.5 – 3.5 ns Tdj2 Driver differential jitter to pair transition –4 – 4 ns Tfdeop Source jitter for differential transition to –2 – 5 ns SE0 transition Tfeopt Source SE0 interval of EOP 160 – 175 ns Tfeopr Receiver SE0 interval of EOP 82 – – ns Tfst Width of SE0 interval during differential – – 14 ns transition Fgpio_out GPIO mode output operating frequency 3V  V  5.5V – – 20 MHz DDD V = 1.71V – – 6 MHz DDD Tr_gpio Rise time, GPIO mode, 10%/90% V V > 3V, 25 pF load – – 12 ns DDD DDD V = 1.71V, 25 pF load – – 40 ns DDD Tf_gpio Fall time, GPIO mode, 90%/10% V V > 3V, 25 pF load – – 12 ns DDD DDD V = 1.71V, 25 pF load – – 40 ns DDD Document Number: 001-11729 Rev. AG Page 86 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-24. USBIO Output Rise and Fall Times, GPIO Mode, V = 3.3 V, 25 pF Load DDD Table 11-16. USB Driver AC Specifications Parameter Description Conditions Min Typ Max Units Tr Transition rise time – – 20 ns Tf Transition fall time – – 20 ns TR Rise/fall time matching V , V , see USB 90% – 111% USB_5 USB_3.3 DC Specifications on page 111 Vcrs Output signal crossover voltage 1.3 – 2 V Document Number: 001-11729 Rev. AG Page 87 of 140

® PSoC 3: CY8C38 Family Datasheet 11.4.4 XRES Table 11-17. XRES DC Specifications Parameter Description Conditions Min Typ Max Units V Input voltage high threshold 0.7  V – – V IH DDIO V Input voltage low threshold – – 0.3 V V IL DDIO Rpullup Pull-up resistor 3.5 5.6 8.5 k C Input capacitance[46] – 3 – pF IN V Input voltage hysteresis – 100 – mV H (Schmitt-Trigger)[46] Idiode Current through protection diode to V – – 100 µA DDIO and V SSIO Table 11-18. XRES AC Specifications Parameter Description Conditions Min Typ Max Units T Reset pulse width 1 – – µs RESET 11.5 Analog Peripherals Specifications are valid for –40°C  T  85°C and T  100°C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.5.1 Opamp Table 11-19. Opamp DC Specifications Parameter Description Conditions Min Typ Max Units V Input voltage range V – V V I SSA DDA V Input offset voltage – – 2.5 mV OS Operating temperature –40°C – – 2 mV to 70°C TCV Input offset voltage drift with Power mode = high – – ±30 µV/ °C OS temperature Ge1 Gain error, unity gain buffer Rload = 1 k – – ±0.1 % mode C Input capacitance Routing from pin – – 18 pF IN V Output voltage range 1 mA, source or sink, power V + 0.05 – V – 0.05 V O SSA DDA mode = high I Output current capability, V + 500 mV Vout  V 25 – – mA OUT SSA DDA source or sink –500 mV, V > 2.7V DDA V + 500 mV  Vout  V 16 – – mA SSA DDA –500 mV, 1.7 V = V  2.7V DDA I Quiescent current Power mode = min – 250 400 uA DD Power mode = low – 250 400 uA Power mode = med – 330 950 uA Power mode = high – 1000 2500 uA CMRR Common mode rejection ratio 80 – – dB PSRR Power supply rejection ratio V  2.7 V 85 – – dB DDA V < 2.7 V 70 – – dB DDA I Input bias current[46] 25 °C – 10 – pA IB Note 46.Based on device characterization (Not production tested). Document Number: 001-11729 Rev. AG Page 88 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-25. Opamp Voffset Histogram, 3388 samples/847 Figure 11-26. Opamp Voffset vs Temperature, V = 5V DDA parts, 25 °C, V = 5 V DDA Figure 11-27. Opamp Voffset vs Vcommon and Figure 11-28. Opamp Output Voltage vs Load Current and VDDA, 25 °C Temperature, High Power Mode, 25 °C, VDDA = 2.7 V Figure 11-29. Opamp Operating Current vs V and Power DDA Mode Document Number: 001-11729 Rev. AG Page 89 of 140

® PSoC 3: CY8C38 Family Datasheet . Table 11-20. Opamp AC Specifications Parameter Description Conditions Min Typ Max Units GBW Gain-bandwidth product Power mode = minimum, 15pF load 1 – – MHz Power mode = low, 15pF load 2 – – MHz Power mode = medium, 200pF load 1 – – MHz Power mode = high, 200pF load 3 – – MHz SR Slew rate, 20% - 80% Power mode = low, 15pF load 1.1 – – V/µs Power mode = medium, 200pF load 0.9 – – V/µs Power mode = high, 200pF load 3 – – V/µs e Input noise density Power mode = high, V = 5 V, – 45 – nV/sqrtHz n DDA at 100 kHz Figure 11-30. Opamp Noise vs Frequency, Power Mode = Figure 11-31. Opamp Step Response, Rising High, V = 5V DDA Figure 11-32. Opamp Step Response, Falling Document Number: 001-11729 Rev. AG Page 90 of 140

® PSoC 3: CY8C38 Family Datasheet 11.5.2 Delta-sigma ADC Unless otherwise specified, operating conditions are: Operation in continuous sample mode fclk = 3.072 MHz for resolution = 16 to 20 bits; fclk = 6.144 MHz for resolution = 8 to 15 bits Reference = 1.024 V internal reference bypassed on P3.2 or P0.3 Unless otherwise specified, all charts and graphs show typical values Table 11-21. 20-bit Delta-sigma ADC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution 8 – 20 bits No. of Number of channels, single ended – – – GPIO Differential pair is formed using a No. of Number of channels, differential – – – pair of GPIOs. GPIO/2 Monotonic Yes – – – – Buffered, buffer gain = 1, Range = Ge Gain error – – ±0.2 % ±1.024V, 16-bit mode, 25 °C Buffered, buffer gain = 1, Range = ppm/° Gd Gain drift – – 50 ±1.024V, 16-bit mode C Buffered, 16-bit mode, full voltage – – ±0.2 mV range Vos Input offset voltage Buffered, 16-bit mode, – – ±0.1 mV V = 1.8 V ±5%, 25 °C DDA Temperature coefficient, input offset Buffer gain = 1, 16-bit, TCVos – – 1 µV/°C voltage Range = ±1.024 V Input voltage range, single ended[47] V – V V SSA DDA Input voltage range, differential unbuf- fered[47] VSSA – VDDA V Input voltage range, differential, buffered[47] VSSA – VDDA – 1 V PSRRb Power supply rejection ratio, buffered[47] Buffer gain = 1, 16-bit, 90 – – dB Range = ±1.024V CMRRb Common mode rejection ratio, buffered[47] Buffer gain = 1, 16 bit, 85 – – dB Range = ±1.024 V INL20 Integral non linearity[47] Range = ±1.024V, unbuffered – – ±32 LSB DNL20 Differential non linearity[47] Range = ±1.024V, unbuffered – – ±1 LSB INL16 Integral non linearity[47] Range = ±1.024V, unbuffered – – ±2 LSB DNL16 Differential non linearity[47] Range = ±1.024V, unbuffered – – ±1 LSB INL12 Integral non linearity[47] Range = ±1.024V, unbuffered – – ±1 LSB DNL12 Differential non linearity[47] Range = ±1.024V, unbuffered – – ±1 LSB INL8 Integral non linearity[47] Range = ±1.024V, unbuffered – – ±1 LSB DNL8 Differential non linearity[47] Range = ±1.024V, unbuffered – – ±1 LSB Rin_Buff ADC input resistance Input buffer used 10 – – M Rin_ADC16 ADC input resistance Input buffer bypassed, 16-bit, Range – 74[48] – k = ±1.024V Rin_ADC12 ADC input resistance Input buffer bypassed, 12 bit, Range – 148[48] – k = ±1.024V Rin_ExtRef ADC external reference input resistance – 70[48, 49] – k Notes 47.Based on device characterization (not production tested). 48.By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual. 49.Recommend an external reference device with an output impedance <100 Ω, for example, the LM185/285/385 family. A 1-µF capacitor is recommended. For more information, see AN61290 - PSoC® 3 and PSoC 5LP Hardware Design Considerations. Document Number: 001-11729 Rev. AG Page 91 of 140

® PSoC 3: CY8C38 Family Datasheet Table 11-21. 20-bit Delta-sigma ADC DC Specifications (continued) Parameter Description Conditions Min Typ Max Units ADC external reference input voltage, see Vextref also internal reference in Voltage Pins P0[3], P3[2] 0.9 – 1.3 V Reference on page 95 Current Consumption I I + I current consumption, 20 bit[50] 187 sps, unbuffered – – 1.5 mA DD_20 DDA DDD I I + I current consumption, 16 bit[50] 48 ksps, unbuffered – – 1.5 mA DD_16 DDA DDD I I + I current consumption, 12 bit[50] 192 ksps, unbuffered – – 1.95 mA DD_12 DDA DDD I Buffer current consumption[50] – – 2.5 mA BUFF Table 11-22. Delta-sigma ADC AC Specifications Parameter Description Conditions Min Typ Max Units Startup time – – 4 Samples THD Total harmonic distortion[50] Buffer gain = 1, 16 bit, – – 0.0032 % Range = ±1.024V 20-Bit Resolution Mode SR20 Sample rate[50] Range = ±1.024V, unbuffered 7.8 – 187 sps BW20 Input bandwidth at max sample rate[50] Range = ±1.024V, unbuffered – 40 – Hz 16-Bit Resolution Mode SR16 Sample rate[50] Range = ±1.024V, unbuffered 2 – 48 ksps BW16 Input bandwidth at max sample rate[50] Range = ±1.024V, unbuffered – 11 – kHz SINAD16int Signal to noise ratio, 16-bit, internal Range = ±1.024V, unbuffered 81 – – dB reference[50] SINAD16ext Signal to noise ratio, 16-bit, external Range = ±1.024V, unbuffered 84 – – dB reference[50] 12-Bit Resolution Mode SR12 Sample rate, continuous, high power[50] Range = ±1.024V, unbuffered 4 – 192 ksps BW12 Input bandwidth at max sample rate[50] Range = ±1.024V, unbuffered – 44 – kHz SINAD12int Signal to noise ratio, 12-bit, internal Range = ±1.024V, unbuffered 66 – – dB reference[50] 8-Bit Resolution Mode SR8 Sample rate, continuous, high power[50] Range = ±1.024V, unbuffered 8 – 384 ksps BW8 Input bandwidth at max sample rate[50] Range = ±1.024V, unbuffered – 88 – kHz SINAD8int Signal to noise ratio, 8-bit, internal Range = ±1.024V, unbuffered 43 – – dB reference[50] Note 50.Based on device characterization (Not production tested). Document Number: 001-11729 Rev. AG Page 92 of 140

® PSoC 3: CY8C38 Family Datasheet Table 11-23. Delta-sigma ADC Sample Rates, Range = ±1.024V Continuous Multi-Sample Multi-Sample Turbo Resolution, Bits Min Max Min Max Min Max 8 8000 384000 1911 91701 1829 87771 9 6400 307200 1543 74024 1489 71441 10 5566 267130 1348 64673 1307 62693 11 4741 227555 1154 55351 1123 53894 12 4000 192000 978 46900 956 45850 13 3283 157538 806 38641 791 37925 14 2783 133565 685 32855 674 32336 15 2371 113777 585 28054 577 27675 16 2000 48000 495 11861 489 11725 17 500 12000 124 2965 282 6766 18 125 3000 31 741 105 2513 19 16 375 4 93 15 357 20 8 187.5 2 46 8 183 Figure 11-33. Delta-sigma ADC IDD vs sps, Range = ±1.024 V, Figure 11-34. Delta-sigma ADC Noise Histogram, 1000 Continuous Sample Mode, Input Buffer Bypassed Samples, 20-Bit, 187 sps, Ext Ref, V = V /2, Range = IN REF ±1.024V Figure 11-35. Delta-sigma ADC Noise Histogram, 1000 Figure 11-36. Delta-sigma ADC Noise Histogram, 1000 Samples, 16-bit, 48 ksps, Ext Ref, V = V /2, Range = Samples, 16-bit, 48 ksps, Int Ref, V = V /2, Range = IN REF IN REF ±1.024V ±1.024V Document Number: 001-11729 Rev. AG Page 93 of 140

® PSoC 3: CY8C38 Family Datasheet Table 11-24. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 16-bit, Internal Reference, Single Ended Sample rate, Input Voltage Range sps 0 to V 0 to V x 2 V to V 0 to V x 6 REF REF SSA DDA REF 2000 1.21 1.02 1.14 0.99 3000 1.28 1.15 1.25 1.22 6000 1.36 1.22 1.38 1.22 12000 1.44 1.33 1.43 1.40 24000 1.67 1.50 1.43 1.53 48000 1.91 1.60 1.85 1.67 Table 11-25. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 16-bit, Internal Reference, Differential Sample rate, Input Voltage Range sps ±V ±VREF/2 ±VREF/4 ±VREF/8 ±VREF / 16 REF 2000 0.56 0.65 0.74 1.02 1.77 4000 0.58 0.72 0.81 1.10 1.98 8000 0.53 0.72 0.82 1.12 2.18 15625 0.58 0.72 0.85 1.13 2.20 32000 0.60 0.76 INVALID OPERATING REGION 43750 0.58 0.75 48000 0.59 Table 11-26. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 20-bit, External Reference, Single Ended Sample rate, Input Voltage Range sps 0 to V 0 to V x 2 V to V 0 to V x 6 REF REF SSA DDA REF 8 1.28 1.24 6.02 0.97 23 1.33 1.28 6.09 0.98 45 1.77 1.26 6.28 0.96 90 1.65 0.91 6.84 0.95 187 1.87 1.06 7.97 1.01 Table 11-27. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 20-bit, External Reference, Differential Sample rate, sps Input Voltage Range ±V ±VREF/2 ±VREF/4 ±VREF/8 ±VREF/16 REF 8 0.70 0.84 1.02 1.40 2.65 11.3 0.69 0.86 0.96 1.40 2.69 22.5 0.73 0.82 1.25 1.77 2.67 45 0.76 0.94 1.02 1.76 2.75 61 0.75 1.01 1.13 1.65 2.98 170 0.75 0.98 INVALID OPERATING REGION 187 0.73 Document Number: 001-11729 Rev. AG Page 94 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-37. Delta-sigma ADC DNL vs Output Code, 16-bit, Figure 11-38. Delta-sigma ADC INL vs Output Code, 16-bit, 48 ksps, 25 °C V = 3.3 V 48 ksps, 25 °C V = 3.3 V DDA DDA 11.5.3 Voltage Reference Table 11-28. Voltage Reference Specifications See also ADC external reference specifications in Section11.5.2. Parameter Description Conditions Min Typ Max Units V [51] Precision reference voltage Initial trimming, 25 °C 1.023 1.024 1.025 V REF (–0.1%) (+0.1%) After typical PCB assembly, Typical (non-optimized) board –40 °C – ±0.5 – % post reflow layout and 250 °C solder reflow. 25 °C – ±0.2 – % Device may be calibrated after assembly to improve performance 85 °C – ±0.2 – % Temperature drift[52] Box method – – 30 ppm/°C Long term drift – 100 – ppm/khr Thermal cycling drift – 100 – ppm (stability)[52, 53] Figure 11-39. Voltage Reference vs. Temperature and V Figure 11-40. Voltage Reference Long-Term Drift CCA Notes 51.VREF is measured after packaging, and thus accounts for substrate and die attach stresses 52.Based on device characterization (Not production tested). 53.After eight full cycles between –40 °C and 100 °C. Document Number: 001-11729 Rev. AG Page 95 of 140

® PSoC 3: CY8C38 Family Datasheet 11.5.4 Analog Globals Table 11-29. Analog Globals Specifications Parameter Description Conditions Min Typ Max Units Rppag Resistance pin-to-pin through P2[4], V = 3 V – 1472 2200  DDA AGL0, DSM INP, AGL1, P2[5][54] Rppmuxbus Resistance pin-to-pin through P2[3], V = 3 V – 706 1100  DDA amuxbusL, P2[4][54] 11.5.5 Comparator Table 11-30. Comparator DC Specifications Parameter Description Conditions Min Typ Max Units Input offset voltage in fast mode Factory trim, V > 2.7 V, – 10 mV DDA V  0.5 V IN Input offset voltage in slow mode Factory trim, Vin  0.5 V – 9 mV V Input offset voltage in fast mode[55] Custom trim – – 4 mV OS Input offset voltage in slow mode[55] Custom trim – – 4 mV Input offset voltage in ultra V ≤ 4.6 V – ±12 – mV DDA low-power mode V Hysteresis Hysteresis enable mode – 10 32 mV HYST V Input common mode voltage High current / fast mode V – V V ICM SSA DDA Low current / slow mode V – V V SSA DDA Ultra low-power mode V – V – V SSA DDA V ≤ 4.6 V 1.15 DDA CMRR Common mode rejection ratio – 50 – dB I High current mode/fast mode[56] – – 400 µA CMP Low current mode/slow mode[56] – – 100 µA Ultra low-power mode[56] V ≤ 4.6 V – 6 – µA DDA Table 11-31. Comparator AC Specifications Parameter Description Conditions Min Typ Max Units Response time, high current 50 mV overdrive, measured – 75 110 ns mode[56] pin-to-pin Response time, low current 50 mV overdrive, measured – 155 200 ns TRESP mode[56] pin-to-pin Response time, ultra low-power 50 mV overdrive, measured – 55 – µs mode[56] pin-to-pin, V ≤ 4.6 V DDA Notes 54.The resistance of the analog global and analog mux bus is high if VDDA 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog mux bus under these conditions is not recommended. 55.The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM. 56.Based on device characterization (Not production tested). Document Number: 001-11729 Rev. AG Page 96 of 140

® PSoC 3: CY8C38 Family Datasheet 11.5.6 Current Digital-to-analog Converter (IDAC) All specifications are based on use of the low-resistance IDAC output pins (see Pin Descriptions on page 12 for details). See the IDAC component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-32. IDAC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution – – 8 bits I Output current at code = 255 Range = 2.04 mA, code = 255, – 2.04 – mA OUT VDDA  2.7 V, Rload = 600  Range = 2.04 mA, high speed – 2.04 – mA mode, code = 255, V  2.7 V, DDA Rload = 300  Range = 255 µA, code = 255, Rload – 255 – µA = 600  Range = 31.875 µA, code = 255, – 31.875 – µA Rload = 600  Monotonicity – – Yes Ezs Zero scale error – 0 ±1 LSB Eg Gain error Range = 2.04 mA, 25 °C – – ±2.5 % Range = 255 µA, 25 ° C – – ±2.5 % Range = 31.875 µA, 25 ° C – – ±3.5 % TC_Eg Temperature coefficient of gain Range = 2.04 mA – – 0.04 % / °C error Range = 255 µA – – 0.04 % / °C Range = 31.875 µA – – 0.05 % / °C INL Integral nonlinearity Sink mode, range = 255 µA, Codes – ±0.9 ±1 LSB 8 – 255, Rload = 2.4 k, Cload = 15pF Source mode, range = 255 µA, – ±1.2 ±1.6 LSB Codes 8 – 255, Rload = 2.4 k, Cload = 15 pF DNL Differential nonlinearity Sink mode, range = 255 µA, Rload – ±0.3 ±1 LSB = 2.4 k, Cload = 15 pF Source mode, range = 255 µA, – ±0.3 ±1 LSB Rload = 2.4 k, Cload = 15 pF Vcompliance Dropout voltage, source or sink Voltage headroom at max current, 1 – – V mode Rload to V or Rload to V , DDA SSA Vdiff from V DDA Document Number: 001-11729 Rev. AG Page 97 of 140

® PSoC 3: CY8C38 Family Datasheet Table 11-32. IDAC DC Specifications (continued) Parameter Description Conditions Min Typ Max Units I Operating current, code = 0 Low speed mode, source mode, – 44 100 µA DD range = 31.875µA Low speed mode, source mode, – 33 100 µA range = 255µA, Low speed mode, source mode, – 33 100 µA range = 2.04mA Low speed mode, sink mode, – 36 100 µA range = 31.875µA Low speed mode, sink mode, – 33 100 µA range = 255µA Low speed mode, sink mode, – 33 100 µA range = 2.04mA High speed mode, source mode, – 310 500 µA range = 31.875µA High speed mode, source mode, – 305 500 µA range = 255µA High speed mode, source mode, – 305 500 µA range = 2.04mA High speed mode, sink mode, – 310 500 µA range = 31.875µA High speed mode, sink mode, – 300 500 µA range = 255µA High speed mode, sink mode, – 300 500 µA range = 2.04 mA Figure 11-41. IDAC INL vs Input Code, Range = 255 µA, Figure 11-42. IDAC INL vs Input Code, Range = 255 µA, Sink Source Mode Mode Document Number: 001-11729 Rev. AG Page 98 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-43. IDAC DNL vs Input Code, Range = 255 µA, Figure 11-44. IDAC DNL vs Input Code, Range = 255 µA, Sink Source Mode Mode Figure 11-45. IDAC INL vs Temperature, Range = 255 µA, High Figure 11-46. IDAC DNL vs Temperature, Range = 255 µA, speed mode High speed mode Figure 11-47. IDAC Full Scale Error vs Temperature, Range Figure 11-48. IDAC Full Scale Error vs Temperature, Range = 255 µA, Source Mode = 255 µA, Sink Mode Document Number: 001-11729 Rev. AG Page 99 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-49. IDAC Operating Current vs Temperature, Figure 11-50. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Source Mode Range = 255 µA, Code = 0, Sink Mode Table 11-33. IDAC AC Specifications Parameter Description Conditions Min Typ Max Units F Update rate – – 8 Msps DAC T Settling time to 0.5 LSB Range = 31.875 µA or 255 µA, full – – 125 ns SETTLE scale transition, High speed mode, 600 15-pF load Current noise Range = 255µA, source mode, – 340 – pA/sqrtHz High speed mode, V = 5V, DDA 10kHz Figure 11-51. IDAC Step Response, Codes 0x40 - 0xC0, Figure 11-52. IDAC Glitch Response, Codes 0x7F - 0x80, 255 µA Mode, Source Mode, High speed mode, V = 5 V 255 µA Mode, Source Mode, High speed mode, V = 5 V DDA DDA Document Number: 001-11729 Rev. AG Page 100 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-53. IDAC PSRR vs Frequency Figure 11-54. IDAC Current Noise, 255µA Mode, Source Mode, High speed mode, V = 5 V DDA 60 50 40 B d R, 30 R S PP 2200 10 0 0.1 1 10 100 1000 10000 Frequency, kHz 255 (cid:2)A, code 0x7F 255 (cid:2)A, code 0xFF 11.5.7 Voltage Digital to Analog Converter (VDAC) See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-34. VDAC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution – 8 – bits V Output voltage range, code = 255 1 V scale – 1.02 – V OUT 4 V scale, V = 5 V – 4.08 – V DDA INL1 Integral nonlinearity 1 V scale – ±2.1 ±2.5 LSB INL4 Integral nonlinearity[57] 4 V scale – ±2.1 ±2.5 LSB DNL1 Differential nonlinearity 1 V scale – ±0.3 ±1 LSB DNL4 Differential nonlinearity[57] 4 V scale – ±0.3 ±1 LSB Rout Output resistance 1 V scale – 4 – k 4 V scale – 16 – k Monotonicity – – Yes – V Zero scale error – 0 ±0.9 LSB OS Eg Gain error 1 V scale, – – ±2.5 % 4 V scale – – ±2.5 % TC_Eg Temperature coefficient, gain error 1 V scale, – – 0.03 %FSR / °C 4 V scale – – 0.03 %FSR / °C I Operating current Low speed mode – – 100 µA DD High speed mode – – 500 µA Note 57.Based on device characterization (Not production tested). Document Number: 001-11729 Rev. AG Page 101 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-55. VDAC INL vs Input Code, 1 V Mode Figure 11-56. VDAC DNL vs Input Code, 1 V Mode Figure 11-57. VDAC INL vs Temperature, 1 V Mode Figure 11-58. VDAC DNL vs Temperature, 1 V Mode Figure 11-59. VDAC Full Scale Error vs Temperature, 1 V Figure 11-60. VDAC Full Scale Error vs Temperature, 4 V Mode Mode Document Number: 001-11729 Rev. AG Page 102 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-61. VDAC Operating Current vs Temperature, 1V Figure 11-62. VDAC Operating Current vs Temperature, 1 V Mode, Low speed mode Mode, High speed mode Table 11-35. VDAC AC Specifications Parameter Description Conditions Min Typ Max Units F Update rate 1 V scale – – 1000 ksps DAC 4 V scale – – 250 ksps TsettleP Settling time to 0.1%, step 25% to 1 V scale, Cload = 15 pF – 0.45 1 µs 75% 4 V scale, Cload = 15 pF – 0.8 3.2 µs TsettleN Settling time to 0.1%, step 75% to 1 V scale, Cload = 15 pF – 0.45 1 µs 25% 4 V scale, Cload = 15 pF – 0.7 3 µs Voltage noise Range = 1V, High speed mode, – 750 – nV/sqrtHz V = 5V, 10kHz DDA Figure 11-63. VDAC Step Response, Codes 0x40 - 0xC0, 1V Figure 11-64. VDAC Glitch Response, Codes 0x7F - 0x80, 1V Mode, High speed mode, V = 5 V Mode, High speed mode, V = 5 V DDA DDA Document Number: 001-11729 Rev. AG Page 103 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-65. VDAC PSRR vs Frequency Figure 11-66. VDAC Voltage Noise, 1V Mode, High speed mode, V = 5V DDA 50 40 B d 30 R, R S 20 PP 10 0 0.1 1 10 100 1000 Frequency, kHz 4 V, code 0x7F 4 V, code 0xFF 11.5.8 Mixer The mixer is created using a SC/CT analog block; see the Mixer component data sheet in PSoC Creator for full electrical specifications and APIs. Table 11-36. Mixer DC Specifications Parameter Description Conditions Min Typ Max Units V Input offset voltage – – 15 mV OS Quiescent current – 0.9 2 mA G Gain – 0 – dB Table 11-37. Mixer AC Specifications Parameter Description Conditions Min Typ Max Units f Local oscillator frequency Down mixer mode – – 4 MHz LO f Input signal frequency Down mixer mode – – 14 MHz in f Local oscillator frequency Up mixer mode – – 1 MHz LO f Input signal frequency Up mixer mode – – 1 MHz in SR Slew rate 3 – – V/µs Document Number: 001-11729 Rev. AG Page 104 of 140

® PSoC 3: CY8C38 Family Datasheet 11.5.9 Transimpedance Amplifier The TIA is created using a SC/CT analog block; see the TIA component data sheet in PSoC Creator for full electrical specifications and APIs. Table 11-38. Transimpedance Amplifier (TIA) DC Specifications Parameter Description Conditions Min Typ Max Units V Input offset voltage – – 10 mV IOFF Rconv Conversion resistance[58] R = 20K; 40 pF load –25 – +35 % R = 30K; 40 pF load –25 – +35 % R = 40K; 40 pF load –25 – +35 % R = 80K; 40 pF load –25 – +35 % R = 120K; 40 pF load –25 – +35 % R = 250K; 40 pF load –25 – +35 % R= 500K; 40 pF load –25 – +35 % R = 1M; 40 pF load –25 – +35 % Quiescent current – 1.1 2 mA Table 11-39. Transimpedance Amplifier (TIA) AC Specifications Parameter Description Conditions Min Typ Max Units BW Input bandwidth (–3 dB) R = 20K; –40 pF load 1500 – – kHz R = 120K; –40 pF load 240 – – kHz R = 1M; –40 pF load 25 – – kHz Note 58.Conversion resistance values are not calibrated. Calibrated values and details about calibration are provided in PSoC Creator component data sheets. External precision resistors can also be used. Document Number: 001-11729 Rev. AG Page 105 of 140

® PSoC 3: CY8C38 Family Datasheet 11.5.10 Programmable Gain Amplifier The PGA is created using a SC/CT analog block; see the PGA component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, operating conditions are: Operating temperature = 25 °C for typical values Unless otherwise specified, all charts and graphs show typical values Table 11-40. PGA DC Specifications Parameter Description Conditions Min Typ Max Units Vin Input voltage range Power mode = minimum Vssa – V V DDA Vos Input offset voltage Power mode = high, – – 10 mV gain = 1 TCVos Input offset voltage drift Power mode = high, – – ±30 µV/°C with temperature gain = 1 Ge1 Gain error, gain = 1 – – ±0.15 % Ge16 Gain error, gain = 16 – – ±2.5 % Ge50 Gain error, gain = 50 – – ±5 % Vonl DC output nonlinearity Gain = 1 – – ±0.01 % of FSR Cin Input capacitance – – 7 pF Voh Output voltage swing Power mode = high, V – 0.15 – – V DDA gain = 1, Rload = 100 k to V / 2 DDA Vol Output voltage swing Power mode = high, – – V + 0.15 V SSA gain = 1, Rload = 100 k to V / 2 DDA Vsrc Output voltage under load Iload = 250 µA, V  – – 300 mV DDA 2.7V, power mode = high Idd Operating current Power mode = high – 1.5 1.65 mA PSRR Power supply rejection 48 – – dB ratio Figure 11-67. PGA Voffset Histogram, 4096 samples/ 1024 parts Document Number: 001-11729 Rev. AG Page 106 of 140

® PSoC 3: CY8C38 Family Datasheet Table 11-41. PGA AC Specifications Parameter Description Conditions Min Typ Max Units BW1 –3 dB bandwidth Power mode = high, 6.7 8 – MHz gain = 1, input = 100 mV peak-to-peak SR1 Slew rate Power mode = high, 3 – – V/µs gain = 1, 20% to 80% e Input noise density Power mode = high, – 43 – nV/sqrtHz n V = 5 V, at 100 kHz DDA Figure 11-68. Bandwidth vs. Temperature, at Different Gain Figure 11-69. Noise vs. Frequency, V = 5V, DDA Settings, Power Mode = High Power Mode = High 10 z H 1 M , W B 0.1 -40 -20 0 20 40 60 80 Temperature, °C Gain = 1 Gain = 24 Gain = 48 11.5.11 Temperature Sensor Table 11-42. Temperature Sensor Specifications Parameter Description Conditions Min Typ Max Units Temp sensor accuracy Range: –40 °C to +85 °C – ±5 – °C 11.5.12 LCD Direct Drive Table 11-43. LCD Direct Drive DC Specifications Parameter Description Conditions Min Typ Max Units I LCD system operating current Device sleep mode with wakeup at – 38 – A CC 400-Hz rate to refresh LCDs, bus clock = 3 MHz, V = V = 3V, DDIO DDA 4 commons, 16 segments, 1/4 duty cycle, 50Hz frame rate, no glass connected I Current per segment driver Strong drive mode – 260 – µA CC_SEG V LCD bias range (V refers to the V  3V and V  V 2 – 5 V BIAS BIAS DDA DDA BIAS main output voltage(V0) of LCD DAC) LCD bias step size V  3V and V  V – 9.1 × V – mV DDA DDA BIAS DDA LCD capacitance per Drivers may be combined – 500 5000 pF segment/common driver Long term segment offset – – 20 mV I Output drive current per segment V = 5.5V, strong drive mode 355 – 710 µA OUT DDIO driver) Document Number: 001-11729 Rev. AG Page 107 of 140

® PSoC 3: CY8C38 Family Datasheet Table 11-44. LCD Direct Drive AC Specifications Parameter Description Conditions Min Typ Max Units f LCD frame rate 10 50 150 Hz LCD 11.6 Digital Peripherals Specifications are valid for –40°C  T  85°C and T  100°C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.6.1 Timer The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for more information, see the Timer component data sheet in PSoC Creator. Table 11-45. Timer DC Specifications Parameter Description Conditions Min Typ Max Units Block current consumption 16-bit timer, at listed input clock – – – µA frequency 3 MHz – 15 – µA 12 MHz – 60 – µA 48 MHz – 260 – µA 67 MHz – 350 – µA Table 11-46. Timer AC Specifications Parameter Description Conditions Min Typ Max Units Operating frequency DC – 67.01 MHz Capture pulse width (Internal) 15 – – ns Capture pulse width (external) 30 – – ns Timer resolution 15 – – ns Enable pulse width 15 – – ns Enable pulse width (external) 30 – – ns Reset pulse width 15 – – ns Reset pulse width (external) 30 – – ns Document Number: 001-11729 Rev. AG Page 108 of 140

® PSoC 3: CY8C38 Family Datasheet 11.6.2 Counter The following specifications apply to the Timer/Counter/PWM peripheral, in counter mode. Counters can also be implemented in UDBs; for more information, see the Counter component data sheet in PSoC Creator. Table 11-47. Counter DC Specifications Parameter Description Conditions Min Typ Max Units Block current consumption 16-bit counter, at listed input clock – – – µA frequency 3 MHz – 15 – µA 12 MHz – 60 – µA 48 MHz – 260 – µA 67 MHz – 350 – µA Table 11-48. Counter AC Specifications Parameter Description Conditions Min Typ Max Units Operating frequency DC – 67.01 MHz Capture pulse 15 – – ns Resolution 15 – – ns Pulse width 15 – – ns Pulse width (external) 30 ns Enable pulse width 15 – – ns Enable pulse width (external) 30 – – ns Reset pulse width 15 – – ns Reset pulse width (external) 30 – – ns 11.6.3 Pulse Width Modulation The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented in UDBs; for more information, see the PWM component data sheet in PSoC Creator. Table 11-49. PWM DC Specifications Parameter Description Conditions Min Typ Max Units Block current consumption 16-bit PWM, at listed input clock – – – µA frequency 3 MHz – 15 – µA 12 MHz – 60 – µA 48 MHz – 260 – µA 67 MHz – 350 – µA Table 11-50. Pulse Width Modulation (PWM) AC Specifications Parameter Description Conditions Min Typ Max Units Operating frequency DC – 67.01 MHz Pulse width 15 – – ns Pulse width (external) 30 – – ns Kill pulse width 15 – – ns Kill pulse width (external) 30 – – ns Enable pulse width 15 – – ns Enable pulse width (external) 30 – – ns Reset pulse width 15 – – ns Reset pulse width (external) 30 – – ns Document Number: 001-11729 Rev. AG Page 109 of 140

® PSoC 3: CY8C38 Family Datasheet 11.6.4 I2C Table 11-51. Fixed I2C DC Specifications Parameter Description Conditions Min Typ Max Units Block current consumption Enabled, configured for 100 kbps – – 250 µA – Enabled, configured for 400 kbps – – 260 µA – Wake from sleep mode – – 30 µA Table 11-52. Fixed I2C AC Specifications Parameter Description Conditions Min Typ Max Units Bit rate – – 1 Mbps 11.6.5 Controller Area Network Table 11-53. CAN DC Specifications[59] Parameter Description Conditions Min Typ Max Units I Block current consumption – – 200 µA DD Table 11-54. CAN AC Specifications[59] Parameter Description Conditions Min Typ Max Units Bit rate Minimum 8 MHz clock – – 1 Mbit 11.6.6 Digital Filter Block Table 11-55. DFB DC Specifications Parameter Description Conditions Min Typ Max Units DFB operating current 64-tap FIR at F DFB 500 kHz (6.7 ksps) – 0.16 0.27 mA 1 MHz (13.4 ksps) – 0.33 0.53 mA 10 MHz (134 ksps) – 3.3 5.3 mA 48 MHz (644 ksps) – 15.7 25.5 mA 67 MHz (900 ksps) – 21.8 35.6 mA Table 11-56. DFB AC Specifications Parameter Description Conditions Min Typ Max Units F DFB operating frequency DC – 67.01 MHz DFB Note 59.Refer to ISO 11898 specification for details. Document Number: 001-11729 Rev. AG Page 110 of 140

® PSoC 3: CY8C38 Family Datasheet 11.6.7 USB Table 11-57. USB DC Specifications Parameter Description Conditions Min Typ Max Units V Device supply (V ) for USB USB configured, USB regulator 4.35 – 5.25 V USB_5 DDD operation enabled V USB configured, USB regulator 3.15 – 3.6 V USB_3.3 bypassed V USB configured, USB regulator 2.85 – 3.6 V USB_3 bypassed[60] I Device supply current in device V = 5 V, F = 1.5 MHz – 10 – mA USB_Configured DDD CPU active mode, bus clock and IMO = V = 3.3 V, F = 1.5 MHz – 8 – mA 24 MHz DDD CPU I Device supply current in device V = 5 V, connected to USB – 0.5 – mA USB_Suspended DDD sleep mode host, PICU configured to wake on USB resume signal V = 5 V, disconnected from – 0.3 – mA DDD USB host V = 3.3 V, connected to USB – 0.5 – mA DDD host, PICU configured to wake on USB resume signal V = 3.3 V, disconnected from – 0.3 – mA DDD USB host 11.6.8 Universal Digital Blocks (UDBs) PSoC Creator provides a library of prebuilt and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. See the component data sheets in PSoC Creator for full AC/DC specifications, APIs, and example code. Table 11-58. UDB AC Specifications Parameter Description Conditions Min Typ Max Units Datapath Performance F Maximum frequency of 16-bit timer in – – 67.01 MHz MAX_TIMER a UDB pair F Maximum frequency of 16-bit adder in – – 67.01 MHz MAX_ADDER a UDB pair F Maximum frequency of 16-bit – – 67.01 MHz MAX_CRC CRC/PRS in a UDB pair PLD Performance F Maximum frequency of a two-pass – – 67.01 MHz MAX_PLD PLD function in a UDB pair Clock to Output Performance t Propagation delay for clock in to data 25 °C, V  2.7 V – 20 25 ns CLK_OUT DDD out, see Figure11-70. t Propagation delay for clock in to data Worst-case placement, routing, – – 55 ns CLK_OUT out, see Figure11-70. and pin selection Note 60.Rise/fall time matching (TR) not guaranteed, see USB Driver AC Specifications on page 87. Document Number: 001-11729 Rev. AG Page 111 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-70. Clock to Output Performance 11.7 Memory Specifications are valid for –40 °C  T  85 °C and T  100 °C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.7.1 Flash Table 11-59. Flash DC Specifications Parameter Description Conditions Min Typ Max Units Erase and program voltage V pin 1.71 – 5.5 V DDD Table 11-60. Flash AC Specifications Parameter Description Conditions Min Typ Max Units T Row write time (erase + program) – 15 20 ms WRITE T Row erase time – 10 13 ms ERASE Row program time – 5 7 ms T Bulk erase time (16 KB to 64 KB) – – 35 ms BULK Sector erase time (8 KB to 16 KB) – – 15 ms T Total device programming time No overhead[61] – 1.5 2 seconds PROG Flash data retention time, retention Average ambient temp. 20 – – years period measured from last erase T  55°C, 100 K erase/program A cycle cycles Average ambient temp. 10 – – T  85 °C, 10K erase/program A cycles Note 61.See PSoC® 3 Device Programming Specifications for a description of a low-overhead method of programming PSoC 3 flash. Document Number: 001-11729 Rev. AG Page 112 of 140

® PSoC 3: CY8C38 Family Datasheet 11.7.2 EEPROM Table 11-61. EEPROM DC Specifications Parameter Description Conditions Min Typ Max Units Erase and program voltage 1.71 – 5.5 V Table 11-62. EEPROM AC Specifications Parameter Description Conditions Min Typ Max Units T Single row erase/write cycle time – 10 20 ms WRITE EEPROM data retention time, Average ambient temp, T  25 °C, 20 – – years A retention period measured from last 1M erase/program cycles erase cycle Average ambient temp, T  55 °C, 20 – – A 100K erase/program cycles Average ambient temp. T 85 °C, 10 – – A 10K erase/program cycles 11.7.3 Nonvolatile Latches (NVL)) Table 11-63. NVL DC Specifications Parameter Description Conditions Min Typ Max Units Erase and program voltage V pin 1.71 – 5.5 V DDD Table 11-64. NVL AC Specifications Parameter Description Conditions Min Typ Max Units NVL endurance Programmed at 25 °C 1K – – program/erase cycles Programmed at 0 °C to 70 °C 100 – – program/erase cycles NVL data retention time Average ambient temp. T ≤ 55 °C 20 – – years A Average ambient temp. T ≤ 85 °C 10 – – years A 11.7.4 SRAM Table 11-65. SRAM DC Specifications Parameter Description Conditions Min Typ Max Units V SRAM retention voltage 1.2 – – V SRAM Table 11-66. SRAM AC Specifications Parameter Description Conditions Min Typ Max Units F SRAM operating frequency DC – 67.01 MHz SRAM Document Number: 001-11729 Rev. AG Page 113 of 140

® PSoC 3: CY8C38 Family Datasheet 11.7.5 External Memory Interface Figure 11-71. Asynchronous Write and Read Cycle Timing, No Wait States Tbus_clock Bus Clock EM_Addr EM_CE EM_WE EM_OE Twr_setup Trd_setup Trd_hold EM_Data Write Cycle Read Cycle Minimum of 4 bus clock cycles between successive EMIF accesses Table 11-67. Asynchronous Write and Read Timing Specifications[62] Parameter Description Conditions Min Typ Max Units Fbus_clock Bus clock frequency[63] – – 33 MHz Tbus_clock Bus clock period[64] 30.3 – – ns Twr_Setup Time from EM_data valid to rising edge Tbus_clock – 10 – – ns of EM_WE and EM_CE Trd_setup Time that EM_data must be valid before 5 – – ns rising edge of EM_OE Trd_hold Time that EM_data must be valid after 5 – – ns rising edge of EM_OE Notes 62.Based on device characterization (Not production tested). 63.EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page80. 64.EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency. Document Number: 001-11729 Rev. AG Page 114 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 11-72. Synchronous Write and Read Cycle Timing, No Wait States Tbus_clock Bus Clock EM_Clock EM_Addr EM_CE EM_ADSC EM_WE EM_OE Twr_setup Trd_setup Trd_hold EM_Data Write Cycle Read Cycle Minimum of 4 bus clock cycles between successive EMIF accesses Table 11-68. Synchronous Write and Read Timing Specifications[65] Parameter Description Conditions Min Typ Max Units Fbus_clock Bus clock frequency[66] – – 33 MHz Tbus_clock Bus clock period[67] 30.3 – – ns Twr_Setup Time from EM_data valid to rising edge of Tbus_clock – 10 – – ns EM_Clock Trd_setup Time that EM_data must be valid before 5 – – ns rising edge of EM_OE Trd_hold Time that EM_data must be valid after 5 – – ns rising edge of EM_OE Notes 65.Based on device characterization (Not production tested). 66.EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page80. 67.EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency. Document Number: 001-11729 Rev. AG Page 115 of 140

® PSoC 3: CY8C38 Family Datasheet 11.8 PSoC System Resources Specifications are valid for –40 °C  T  85 °C and T  100 °C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.8.1 POR with Brown Out For brown out detect in regulated mode, V and V must be  2.0 V. Brown out detect is not available in externally regulated DDD DDA mode. Table 11-69. Precise Low-Voltage Reset (PRES) with Brown Out DC Specifications Parameter Description Conditions Min Typ Max Units PRESR Rising trip voltage Factory trim 1.64 – 1.68 V PRESF Falling trip voltage 1.62 – 1.66 V Table 11-70. Power On Reset (POR) with Brown Out AC Specifications Parameter Description Conditions Min Typ Max Units PRES_TR Response time – – 0.5 µs V /V droop rate Sleep mode – 5 – V/sec DDD DDA 11.8.2 Voltage Monitors Table 11-71. Voltage Monitors DC Specifications Parameter Description Conditions Min Typ Max Units LVI Trip voltage LVI_A/D_SEL[3:0] = 0000b 1.68 1.73 1.77 V LVI_A/D_SEL[3:0] = 0001b 1.89 1.95 2.01 V LVI_A/D_SEL[3:0] = 0010b 2.14 2.20 2.27 V LVI_A/D_SEL[3:0] = 0011b 2.38 2.45 2.53 V LVI_A/D_SEL[3:0] = 0100b 2.62 2.71 2.79 V LVI_A/D_SEL[3:0] = 0101b 2.87 2.95 3.04 V LVI_A/D_SEL[3:0] = 0110b 3.11 3.21 3.31 V LVI_A/D_SEL[3:0] = 0111b 3.35 3.46 3.56 V LVI_A/D_SEL[3:0] = 1000b 3.59 3.70 3.81 V LVI_A/D_SEL[3:0] = 1001b 3.84 3.95 4.07 V LVI_A/D_SEL[3:0] = 1010b 4.08 4.20 4.33 V LVI_A/D_SEL[3:0] = 1011b 4.32 4.45 4.59 V LVI_A/D_SEL[3:0] = 1100b 4.56 4.70 4.84 V LVI_A/D_SEL[3:0] = 1101b 4.83 4.98 5.13 V LVI_A/D_SEL[3:0] = 1110b 5.05 5.21 5.37 V LVI_A/D_SEL[3:0] = 1111b 5.30 5.47 5.63 V HVI Trip voltage 5.57 5.75 5.92 V Table 11-72. Voltage Monitors AC Specifications Parameter Description Conditions Min Typ Max Units Response time[68] – – 1 µs Note 68.Based on device characterization (Not production tested). Document Number: 001-11729 Rev. AG Page 116 of 140

® PSoC 3: CY8C38 Family Datasheet 11.8.3 Interrupt Controller Table 11-73. Interrupt Controller AC Specifications Parameter Description Conditions Min Typ Max Units Delay from interrupt signal input to ISR Includes worse case completion of – – 25 Tcy CPU code execution from ISR code longest instruction DIV with 6 cycles 11.8.4 JTAG Interface Figure 11-73. JTAG Interface Timing (1/f_TCK) TCK T_TDI_setup T_TDI_hold TDI T_TDO_valid T_TDO_hold TDO T_TMS_setup T_TMS_hold TMS Table 11-74. JTAG Interface AC Specifications[69] Parameter Description Conditions Min Typ Max Units f_TCK TCK frequency 3.3V  V  5V – – 14[70] MHz DDD 1.71V  V < 3.3V – – 7[70] MHz DDD T_TDI_setup TDI setup before TCK high (T/10) – 5 – – ns T_TMS_setup TMS setup before TCK high T/4 – – T_TDI_hold TDI, TMS hold after TCK high T = 1/f_TCK max T/4 – – T_TDO_valid TCK low to TDO valid T = 1/f_TCK max – – 2T/5 T_TDO_hold TDO hold after TCK high T = 1/f_TCK max T/4 – – Notes 69.Based on device characterization (Not production tested). 70.f_TCK must also be no more than 1/3 CPU clock frequency. Document Number: 001-11729 Rev. AG Page 117 of 140

® PSoC 3: CY8C38 Family Datasheet 11.8.5 SWD Interface Figure 11-74. SWD Interface Timing (1/f_SWDCK) SWDCK T_SWDI_setup T_SWDI_hold SWDIO (PSoC input) T_SWDO_valid T_SWDO_hold SWDIO (PSoC output) Table 11-75. SWD Interface AC Specifications[71] Parameter Description Conditions Min Typ Max Units f_SWDCK SWDCLK frequency 3.3V  V  5V – – 14[72] MHz DDD 1.71V  V < 3.3V – – 7[72] MHz DDD 1.71V  V < 3.3V, – – 5.5[72] MHz DDD SWD over USBIO pins T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max T/4 – – T_SWDI_hold SWDIO input hold after SWDCK high T = 1/f_SWDCK max T/4 – – T_SWDO_valid SWDCK high to SWDIO output T = 1/f_SWDCK max – – 2T/5 11.8.6 SWV Interface Table 11-76. SWV Interface AC Specifications[71] Parameter Description Conditions Min Typ Max Units SWV mode SWV bit rate – – 33 Mbit Notes 71.Based on device characterization (Not production tested). 72.f_SWDCK must also be no more than 1/3 CPU clock frequency. Document Number: 001-11729 Rev. AG Page 118 of 140

® PSoC 3: CY8C38 Family Datasheet 11.9 Clocking Specifications are valid for –40°C  T  85°C and T  100°C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. Unless otherwise specified, all charts and graphs show typical values. 11.9.1 Internal Main Oscillator Table 11-77. IMO DC Specifications[73] Parameter Description Conditions Min Typ Max Units Supply current 62.6 MHz – – 600 µA 48 MHz – – 500 µA 24 MHz – USB mode With oscillator locking to USB bus – – 500 µA 24 MHz – non USB mode – – 300 µA 12 MHz – – 200 µA 6 MHz – – 180 µA 3 MHz – – 150 µA Figure 11-75. IMO Current vs. Frequency Note 73.Based on device characterization (Not production tested). Document Number: 001-11729 Rev. AG Page 119 of 140

® PSoC 3: CY8C38 Family Datasheet Table 11-78. IMO AC Specifications Parameter Description Conditions Min Typ Max Units IMO frequency stability (with factory trim) 62.6 MHz –7 – 7 % 48 MHz –5 – 5 % 24 MHz – Non USB mode –4 – 4 % 24 MHz – USB mode With oscillator locking to USB bus –0.25 – 0.25 % 12 MHz –3 – 3 % F [74] IMO 6 MHz –2 – 2 % 3 MHz 0 °C to 70 °C –1 – 1 % –40 °C to 85 °C –1.5 – 1.5 % 3 MHz frequency stability after typical Typical (non-optimized) board – ±2 – % PCB assembly post-reflow. layout and 250 °C solder reflow. Device may be calibrated after assembly to improve performance. Startup time[75] From enable (during normal system – – 13 µs operation) Jitter (peak to peak)[75] Jp–p F = 24 MHz – 0.9 – ns F = 3 MHz – 1.6 – ns Jitter (long term)[75] Jperiod F = 24 MHz – 0.9 – ns F = 3 MHz – 12 – ns Figure 11-76. IMO Frequency Variation vs. Temperature Figure 11-77. IMO Frequency Variation vs. V CC Notes 74.FIMO is measured after packaging, and thus accounts for substrate and die attach stresses. 75.Based on device characterization (Not production tested). Document Number: 001-11729 Rev. AG Page 120 of 140

® PSoC 3: CY8C38 Family Datasheet 11.9.2 Internal Low-Speed Oscillator Table 11-79. ILO DC Specifications Parameter Description Conditions Min Typ Max Units Operating current[76] F = 1 kHz – – 1.7 µA OUT I F = 33 kHz – – 2.6 µA CC OUT F = 100 kHz – – 2.6 µA OUT Leakage current[76] Power down mode – – 15 nA Table 11-80. ILO AC Specifications[77] Parameter Description Conditions Min Typ Max Units Startup time, all frequencies Turbo mode – – 2 ms F ILO frequencies ILO 100 kHz 45 100 200 kHz 1 kHz 0.5 1 2 kHz Figure 11-78. ILO Frequency Variation vs. Temperature Figure 11-79. ILO Frequency Variation vs. V DD 11.9.3 MHz External Crystal Oscillator For more information on crystal or ceramic resonator selection for the MHzECO, refer to application note AN54439: PSoC 3 and PSoC 5 External Oscillators. . Table 11-81. MHzECO DC Specifications Parameter Description Conditions Min Typ Max Units I Operating current[77] 13.56 MHz crystal – 3.8 – mA CC Table 11-82. MHzECO AC Specifications Parameter Description Conditions Min Typ Max Units F Crystal frequency range 4 – 25 MHz Note 76.This value is calculated, not measured. 77.Based on device characterization (Not production tested). Document Number: 001-11729 Rev. AG Page 121 of 140

® PSoC 3: CY8C38 Family Datasheet 11.9.4 kHz External Crystal Oscillator Table 11-83. kHzECO DC Specifications[78] Parameter Description Conditions Min Typ Max Units I Operating current Low-power mode; CL = 6pF – 0.25 1.0 µA CC DL Drive level – – 1 µW Table 11-84. kHzECO AC Specifications Parameter Description Conditions Min Typ Max Units F Frequency – 32.768 – kHz T Startup time High power mode – 1 – s ON 11.9.5 External Clock Reference Table 11-85. External Clock Reference AC Specifications[78] Parameter Description Conditions Min Typ Max Units External frequency range 0 – 33 MHz Input duty cycle range Measured at V /2 30 50 70 % DDIO Input edge rate V to V 0.51 – – V/ns IL IH 11.9.6 Phase-Locked Loop Table 11-86. PLL DC Specifications Parameter Description Conditions Min Typ Max Units I PLL operating current In = 3 MHz, Out = 67 MHz – 400 – µA DD In = 3 MHz, Out = 24 MHz – 200 – µA Table 11-87. PLL AC Specifications Parameter Description Conditions Min Typ Max Units Fpllin PLL input frequency[79] 1 – 48 MHz PLL intermediate frequency[80] Output of prescaler 1 – 3 MHz Fpllout PLL output frequency[79] 24 – 67 MHz Lock time at startup – – 250 µs Jperiod-rms Jitter (rms)[78] – – 250 ps Notes 78.Based on device characterization (Not production tested). 79.This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL. 80.PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16. Document Number: 001-11729 Rev. AG Page 122 of 140

® PSoC 3: CY8C38 Family Datasheet 12. Ordering Information In addition to the features listed in Table12-1, every CY8C38 device includes: a precision on-chip voltage reference, precision oscillators, flash, ECC, DMA, a fixed function I2C, 4 KB trace RAM, JTAG/SWD programming and debug, external memory interface, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C38 derivatives incorporate device and flash security in user-selectable security levels; see the TRM for details. Table 12-1. CY8C38 Family with Single Cycle 8051 MCU Core Analog Digital I/O[83] e Part Number CPU Speed (MHz) Flash (KB) SRAM (KB) EEPROM (KB) LCD Segment Driv ADC DAC Comparator SC/CT[81]Analog Blocks Opamps DFB CapSense [82]UDBs 16-bit Timer/PWM FS USB CAN 2.0b Total I/O GPIO SIO USBIO Package JTAG ID[84] 32 KB Flash CY8C3865AXI-019 67 32 4 1 ✔ 20-bit Del-Sig 4 4 4 4 ✔ ✔ 20 4 ✔ – 72 62 8 2 100-pin TQFP 0×1E013069 CY8C3865LTI-014 67 32 4 1 ✔ 20-bit Del-Sig 4 4 4 4 ✔ ✔ 20 4 ✔ – 48 38 8 2 68-pin QFN 0×1E00E069 CY8C3865AXI-204 67 32 8 1 ✔ 20-bit Del-Sig 2 0 0 0 – ✔ 16 4 ✔ – 72 62 8 2 100-pin TQFP 0x1E0CC069 CY8C3865LTI-205 67 32 8 1 ✔ 20-bit Del-Sig 2 0 0 0 – ✔ 16 4 ✔ – 48 38 8 2 68-pin QFN 0x1E0CD069 64 KB Flash CY8C3866LTI-067 67 64 8 2 ✔ 20-bit Del-Sig 4 4 4 2 ✔ ✔ 24 4 ✔ – 31 25 4 2 48-pin QFN 0×1E043069 CY8C3866PVI-021 67 64 8 2 ✔ 20-bit Del-Sig 4 4 4 2 ✔ ✔ 24 4 ✔ – 31 25 4 2 48-pin SSOP 0×1E015069 CY8C3866AXI-035 67 64 8 2 ✔ 20-bit Del-Sig 4 4 4 4 ✔ ✔ 24 4 – ✔ 70 62 8 0 100-pin TQFP 0x1E023069 CY8C3866AXI-039 67 64 8 2 ✔ 20-bit Del-Sig 4 4 4 4 ✔ ✔ 24 4 ✔ – 72 62 8 2 100-pin TQFP 0×1E027069 CY8C3866LTI-030 67 64 8 2 ✔ 20-bit Del-Sig 4 4 4 4 ✔ ✔ 24 4 ✔ – 48 38 8 2 68-pin QFN 0×1E01E069 ✔ ✔ ✔ ✔ ✔ CY8C3866LTI-068 67 64 8 2 20-bit Del-Sig 4 4 4 2 24 4 31 25 4 2 48-pin QFN 0×1E044069 CY8C3866AXI-040 67 64 8 2 ✔ 20-bit Del-Sig 4 4 4 4 ✔ ✔ 24 4 ✔ ✔ 72 62 8 2 100-pin TQFP 0×1E028069 CY8C3866PVI-070 67 64 8 2 ✔ 20-bit Del-Sig 4 4 4 2 ✔ ✔ 24 4 – ✔ 29 25 4 0 48-pin SSOP 0×1E046069 CY8C3866AXI-206 67 64 8 2 ✔ 20-bit Del-Sig 2 2 0 2 ✔ ✔ 20 4 ✔ – 72 62 8 2 100-pin TQFP 0x1E0CE069 CY8C3866LTI-207 67 64 8 2 ✔ 20-bit Del-Sig 2 2 0 2 ✔ ✔ 20 4 ✔ – 48 38 8 2 68-pin QFN 0x1E0CF069 CY8C3866AXI-208 67 64 8 2 ✔ 20-bit Del-Sig 2 2 2 2 ✔ ✔ 24 4 ✔ ✔ 72 62 8 2 100-pin TQFP 0x1E0D0069 CY8C3866LTI-209 67 64 8 2 ✔ 20-bit Del-Sig 2 2 2 2 ✔ ✔ 24 4 ✔ ✔ 48 38 8 2 68-pin QFN 0x1E0D1069 CY8C3866FNI-210 67 64 8 2 ✔ 20-bit Del-Sig 4 4 4 4 ✔ ✔ 24 4 ✔ ✔ 48 38 8 2 72 WLCSP 0x1E0D2069 Notes 81.Analog blocks support a variety of functionality including TIA, PGA, and mixers. See the Example Peripherals on page 44 for more information on how analog blocks can be used. 82.UDBs support a variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See the Example Peripherals on page 44 for more information on how UDBs can be used. 83.The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See the I/O System and Routing on page 37 for details on the functionality of each of these types of I/O. 84.The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID. Document Number: 001-11729 Rev. AG Page 123 of 140

® PSoC 3: CY8C38 Family Datasheet 12.1 Part Numbering Conventions PSoC 3 devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9, A, B, …, Z) unless stated otherwise. CY8Cabcdefg-xxx a: Architecture ef: Package code 3: PSoC 3 Two character alphanumeric 5: PSoC 5 AX: TQFP b: Family group within architecture LT: QFN 4: CY8C34 family PV: SSOP 6: CY8C36 family FN: CSP 8: CY8C38 family g: Temperature range c: Speed grade C: commercial 4: 48 MHz I: industrial 6: 67 MHz A: automotive xxx: Peripheral set d: Flash capacity 4: 16 KB Three character numeric 5: 32 KB No meaning is associated with these three characters. 6: 64 KB Examples CY8C 3 8 6 6 P V I - x x x Cypress Prefix 3: PSoC 3 Architecture 8: CY8C38 Family Family Group within Architecture 6: 67 MHz Speed Grade 6: 64 KB Flash Capacity PV: SSOP Package Code I: Industrial Temperature Range Peripheral Set Tape and reel versions of these devices are available and are marked with a "T" at the end of the part number. All devices in the PSoC 3 CY8C38 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages. A high-level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package Material Declaration data sheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of life” requirements. Document Number: 001-11729 Rev. AG Page 124 of 140

® PSoC 3: CY8C38 Family Datasheet 13. Packaging Table 13-1. Package Characteristics Parameter Description Conditions Min Typ Max Units T Operating ambient temperature –40 25.00 85 °C A T Operating junction temperature –40 – 100 °C J TJA Package JA (48-pin SSOP) – 49 – °C/Watt T Package  (48-pin QFN) – 14 – °C/Watt JA JA T Package  (68-pin QFN) – 15 – °C/Watt JA JA T Package  (100-pin TQFP) – 34 – °C/Watt JA JA T Package  (48-pin SSOP) – 24 – °C/Watt JC JC T Package  (48-pin QFN) – 15 – °C/Watt JC JC T Package  (68-pin QFN) – 13 – °C/Watt JC JC T Package  (100-pin TQFP) – 10 – °C/Watt JC JC T Package  (72-pin CSP) – 18 – °C/Watt JA JA T Package  (72-pin CSP) – 0.13 – °C/Watt JC JC Table 13-2. Solder Reflow Peak Temperature Maximum Peak Maximum Time at Peak Package Temperature Temperature 48-pin SSOP 260 °C 30 seconds 48-pin QFN 260 °C 30 seconds 68-pin QFN 260 °C 30 seconds 100-pin TQFP 260 °C 30 seconds 72-pin CSP 260 °C 30 seconds Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 48-pin SSOP MSL 3 48-pin QFN MSL 3 68-pin QFN MSL 3 100-pin TQFP MSL 3 72-pin CSP MSL 1 Document Number: 001-11729 Rev. AG Page 125 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 13-1. 48-pin (300 mil) SSOP Package Outline 51-85061 *F Figure 13-2. 48-pin QFN Package Outline 001-45616 *F Document Number: 001-11729 Rev. AG Page 126 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 13-3. 68-pin QFN 8×8 with 0.4 mm Pitch Package Outline (Sawn Version) 001-09618 *E Figure 13-4. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline 51-85048 *J Document Number: 001-11729 Rev. AG Page 127 of 140

® PSoC 3: CY8C38 Family Datasheet Figure 13-5. WLCSP Package (4.25 × 4.98 × 0.60 mm) TOP VIEW SIDE VIEW BOTTOM VIEW 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A A B B C C D D E E F F G G H H J J NOTES: 1. JEDEC Publication 95; Design Guide 4.18 2. ALL DIMENSIONS ARE IN MILLIMETERS 001-82897 ** Document Number: 001-11729 Rev. AG Page 128 of 140

® PSoC 3: CY8C38 Family Datasheet 14. Acronyms Table 14-1. Acronyms Used in this Document (continued) Table 14-1. Acronyms Used in this Document Acronym Description FIR finite impulse response, see also IIR Acronym Description FPB flash patch and breakpoint abus analog local bus FS full-speed ADC analog-to-digital converter GPIO general-purpose input/output, applies to a PSoC AG analog global pin AHB AMBA (advanced microcontroller bus archi- HVI high-voltage interrupt, see also LVI, LVD tecture) high-performance bus, an ARM data transfer bus IC integrated circuit ALU arithmetic logic unit IDAC current DAC, see also DAC, VDAC AMUXBUS analog multiplexer bus IDE integrated development environment API application programming interface I2C, or IIC Inter-Integrated Circuit, a communications protocol APSR application program status register ARM® advanced RISC machine, a CPU architecture IIR infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO ATM automatic thump mode IMO internal main oscillator, see also ILO BW bandwidth INL integral nonlinearity, see also DNL CAN Controller Area Network, a communications protocol I/O input/output, see also GPIO, DIO, SIO, USBIO CMRR common-mode rejection ratio IPOR initial power-on reset CPU central processing unit IPSR interrupt program status register CRC cyclic redundancy check, an error-checking IRQ interrupt request protocol ITM instrumentation trace macrocell DAC digital-to-analog converter, see also IDAC, VDAC LCD liquid crystal display DFB digital filter block LIN Local Interconnect Network, a communications DIO digital input/output, GPIO with only digital protocol. capabilities, no analog. See GPIO. LR link register DMA direct memory access, see also TD LUT lookup table DNL differential nonlinearity, see also INL LVD low-voltage detect, see also LVI DNU do not use LVI low-voltage interrupt, see also HVI DR port write data registers LVTTL low-voltage transistor-transistor logic DSI digital system interconnect MAC multiply-accumulate DWT data watchpoint and trace MCU microcontroller unit ECC error correcting code MISO master-in slave-out ECO external crystal oscillator NC no connect EEPROM electrically erasable programmable read-only NMI nonmaskable interrupt memory NRZ non-return-to-zero EMI electromagnetic interference NVIC nested vectored interrupt controller EMIF external memory interface NVL nonvolatile latch, see also WOL EOC end of conversion opamp operational amplifier EOF end of frame PAL programmable array logic, see also PLD EPSR execution program status register PC program counter ESD electrostatic discharge PCB printed circuit board ETM embedded trace macrocell PGA programmable gain amplifier Document Number: 001-11729 Rev. AG Page 129 of 140

® PSoC 3: CY8C38 Family Datasheet Table 14-1. Acronyms Used in this Document (continued) Table 14-1. Acronyms Used in this Document (continued) Acronym Description Acronym Description PHUB peripheral hub SOF start of frame PHY physical layer SPI Serial Peripheral Interface, a communications protocol PICU port interrupt control unit SR slew rate PLA programmable logic array SRAM static random access memory PLD programmable logic device, see also PAL SRES software reset PLL phase-locked loop SWD serial wire debug, a test protocol PMDD package material declaration data sheet SWV single-wire viewer POR power-on reset TD transaction descriptor, see also DMA PRES precise low-voltage reset THD total harmonic distortion PRS pseudo random sequence TIA transimpedance amplifier PS port read data register PSoC® Programmable System-on-Chip™ TRM technical reference manual TTL transistor-transistor logic PSRR power supply rejection ratio TX transmit PWM pulse-width modulator UART Universal Asynchronous Transmitter Receiver, a RAM random-access memory communications protocol RISC reduced-instruction-set computing UDB universal digital block RMS root-mean-square USB Universal Serial Bus RTC real-time clock USBIO USB input/output, PSoC pins used to connect to RTL register transfer language a USB port RTR remote transmission request VDAC voltage DAC, see also DAC, IDAC RX receive WDT watchdog timer SAR successive approximation register WOL write once latch, see also NVL SC/CT switched capacitor/continuous time WRES watchdog timer reset SCL I2C serial clock XRES external reset I/O pin SDA I2C serial data XTAL crystal S/H sample and hold 15. Reference Documents SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced PSoC® 3, PSoC® 5 Architecture TRM features. See GPIO. PSoC® 3 Registers TRM SOC start of conversion Document Number: 001-11729 Rev. AG Page 130 of 140

® PSoC 3: CY8C38 Family Datasheet 16. Document Conventions 16.1 Units of Measure Table 16-1. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohours kHz kilohertz k kilohms ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz M megaohms Msps megasamples per second µA microamperes µF microfarads µH microhenrys µs microseconds µV microvolts µW microwatts mA milliamperes ms milliseconds mV millivolts nA nanoamperes ns nanoseconds nV nanovolts  ohms pF picofarads ppm parts per million ps picoseconds s seconds sps samples per second sqrtHz square root of hertz V volts Document Number: 001-11729 Rev. AG Page 131 of 140

® PSoC 3: CY8C38 Family Datasheet 17. Revision History Description Title: PSoC® 3: CY8C38 Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-11729 Submission Orig. of Revision ECN Description of Change Date Change ** 571504 See ECN HMT New data sheet for new device Part Number family. *A 754416 See ECN HMT Prepare Preliminary for PR1. *B 2253366 See ECN DSG Prepare Preliminary2 for PR3--total rewrite. *C 2350209 See ECN DSG Minor change: Added “Confidential” watermark. Corrected typo on 68QFN pinout: pin 13 XREF to XRES. *D 2481747 See ECN SFV Changed part numbers and data sheet title. *E 2521877 See ECN DSG Prelim3 release–extensive spec, writing, and formatting changes *F 2660161 02/16/09 GDK Reorganized content to be consistent with the TRM. Added Xdata Space Access SFRs and DAC sections. Updated Boost Converter section and Conversion Signals section. Classified Ordering Information according to CPU speed; added information on security features and ROHS compliance Added a section on XRES Specifications under Electrical Specification. Updated Analog Subsystem and CY8C35/55 Architecture block diagrams. Updated Electrical Specifications. Renamed CyDesigner as PSoC Creator *G 2712468 05/29/09 MKEA Updates to Electrical Specifications. Added Analog Routing section Updates to Ordering Information table *H 2758970 09/02/09 MKEA Updated Part Numbering Conventions. Added Section 11.7.5 (EMIF Figures and Tables). Updated GPIO and SIO AC specifications. Updated XRES Pin Description and Xdata Address Map specifications. Updated DFB and Comparator specifications. Updated PHUB features section and RTC in sleep mode. Updated IDAC and VDAC DC and Analog Global specifications Updated USBIO AC and Delta Sigma ADC specifications. Updated PPOR and Voltage Monitors DC specifications. Updated Drive Mode diagram Added 48-QFN Information. Updated other electrical specifications *I 2824546 12/09/09 MKEA Updated I2C section to reflect 1 Mbps. Updated Table 11-6 and 11- 7 (Boost AC and DC specs); also added Shottky Diode specs. Changed current for sleep/hibernate mode to include SIO; Added footnote to analog global specs. Updated Figures 1-1, 6-2, 7-14, and 8-1. Updated Table 6-2 and Table 6-3 (Hibernate and Sleep rows) and Power Modes section. Updated GPIO and SIO AC specifications. Updated Gain error in IDAC and VDAC specifications. Updated description of V spec in Table 11-1 and removed GPIO Clamp DDA Current parameter. Updated number of UDBs on page 1. Moved FILO from ILO DC to AC table. Added PCB Layout and PCB Schematic diagrams. Updated Fgpioout spec (Table 11-9). Added duty cycle frequency in PLL AC spec table. Added note for Sleep and Hibernate modes and Active Mode specs in Table 11-2. Linked URL in Section 10.3 to PSoC Creator site. Updated Ja and Jc values in Table 13-1. Updated Single Sample Mode and Fast FIR Mode sections. Updated Input Resistance specification in Del-Sig ADC table. Added Tio_init parameter. Updated PGA and UGB AC Specs. Removed SPC ADC. Updated Boost Converter section. Added section 'SIO as Comparator'; updated Hysteresis spec (differential mode) in Table 11-10. Updated V condition and deleted Vstart parameter in Table 11-6. BAT Added 'Bytes' column for Tables 4-1 to 4-5. *J 2873322 02/04/10 MKEA Changed maximum value of PPOR_TR to '1'. Updated V specification. BIAS Updated PCB Schematic. Updated Figure 8-1 and Figure 6-3. Updated Interrupt Vector table, Updated Sales links. Updated JTAG and SWD specifi- cations. Removed Jp-p and Jperiod from ECO AC Spec table. Added note on sleep timer in Table 11-2. Updated ILO AC and DC specifications. Added Resolution parameter in VDAC and IDAC tables. Updated I typical and OUT maximum values. Changed Temperature Sensor range to –40 °C to +85 °C. Removed Latchup specification from Table 11-1. Document Number: 001-11729 Rev. AG Page 132 of 140

® PSoC 3: CY8C38 Family Datasheet Description Title: PSoC® 3: CY8C38 Family Datasheet Programmable System-on-Chip (PSoC®) (continued) Document Number: 001-11729 Submission Orig. of Revision ECN Description of Change Date Change *K 2903576 04/01/2010 MKEA Updated Vb pin in PCB Schematic. Updated Tstartup parameter in AC Specifications table. Added Load regulation and Line regulation parameters to Inductive Boost Regulator DC Specifications table. Updated I parameter in LCD Direct Drive DC Specs table. CC In page 1, updated internal oscillator range under Precision programmable clocking to start from 3 MHz. Updated I parameter in LCD Direct Drive DC Specs table. OUT Updated Table 6-2 and Table 6-3. Added bullets on CapSense in page 1; added CapSense column in Section 12. Removed some references to footnote [1]. Changed INC_Rn cycles from 3 to 2 (Table 4-1). Added footnote in PLL AC Specification table. Added PLL intermediate frequency row with footnote in PLL AC Specs table. Added UDBs subsection under 11.6 Digital Peripherals. Updated Figure 2-6 (PCB Layout). Updated Pin Descriptions section and modified Figures 6-6, 6-8, 6-9. Updated LVD in Tables 6-2 and 6-3; modified Low-power modes bullet in page 1. Added note to Figures 2-5 and 6-2; Updated Figure 6-2 to add capacitors for V and V pins. DDA DDD Updated boost converter section (6.2.2). Updated Tstartup values in Table 11-3. Removed IPOR rows from Table 11-68. Updated 6.3.1.1, Power Voltage Level Monitors. Updated section 5.2 and Table 11-2 to correct suggestion of execution from flash. Updated V specs in Table 11-21. REF Updated IDAC uncompensated gain error in Table 11-25. Updated Delay from Interrupt signal input to ISR code execution from ISR code in Table11-72. Removed other line in table. Added sentence to last paragraph of section 6.1.1.3. Updated T , high and low-power modes, in Table 11-24. RESP Updated f_TCK values in Table 11-73 and f_SWDCK values in Table 11-74. Updated SNR condition in Table 11-20. Corrected unit of measurement in Table 11-21. Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3. Added 1.71V <= V < 3.3V, SWD over USBIO pins value to Table 11-74. DDD Removed mention of hibernate reset (HRES) from page 1 features, Table 6-3, Section 6.2.1.4, Section 6.3, and Section 6.3.1.1. Changed PPOR/PRES to TBDs in Section 6.3.1.1, Section 6.4.1.6 (changed PPOR to reset), Table 11-3 (changed PPOR to PRES), Table 11-68 (changed title, values TBD), and Table 11-69 (changed PPOR_TR to PRES_TR). Added sentence saying that LVD circuits can generate a reset to Section 6.3.1.1. Changed I values on page 1, page 5, and Table 11-2. DD Changed resume time value in Section 6.2.1.3. Changed ESD HBM value in Table 11-1. Changed SNR in 16-bit resolution mode value and sample rate row in Table 11-20. Removed V = 1.65V rows and changed BWag value in Table 11-22. DDA Changed V values and changed CMRR value in Table 11-23. IOFF Changed INL max value in Table 11-27. Added max value to the Quiescent current specs in Tables 11-29 and 11-31. Changed occurrences of “Block” to “Row” and deleted the “ECC not included” footnote in Table 11-57. Changed max response time value in Tables 11-69 and 11-71. Changed the Startup time in Table 11-79. Added condition to intermediate frequency row in Table 11-85. Added row to Table 11-69. Document Number: 001-11729 Rev. AG Added brown out note to Section 11.8.1. Page 133 of 140

® PSoC 3: CY8C38 Family Datasheet Description Title: PSoC® 3: CY8C38 Family Datasheet Programmable System-on-Chip (PSoC®) (continued) Document Number: 001-11729 Submission Orig. of Revision ECN Description of Change Date Change *L 2938381 05/27/10 MKEA Replaced V with V in USBIO diagram and specification tables, added DDIO DDD text in USBIO section of Electrical Specifications. Added Table 13-2 (Package MSL) Modified Tstorag condition and changed max spec to 100 Added bullet (Pass) under ALU (section 7.2.2.2) Added figures for kHzECO and MHzECO in the External Oscillator section Updated Figure 6-1(Clocking Subsystem diagram) Removed CPUCLK_DIV in table 5-2, Deleted Clock Divider SFR subsection Updated PSoC Creator Framework image Updated SIO DC Specifications (V and V parameters) IH IL Updated bullets in Clocking System and Clocking Distribution sections Updated Figure 8-2 Updated PCB Layout and Schematic, updated as per MTRB review comments Updated Table 6-3 (power changed to current) In 32kHZ EC DC Specifications table, changed I Max to 0.25 CC In IMO DC Specifications table, updated Supply Current values Updated GPIO DC Specs table *M 2958674 06/22/10 SHEA Minor ECN to post data sheet to external website *N 2989685 08/04/10 MKEA INL max is changed from 16 to 32 in Table 11-20, 20-bit Delta-sigma ADC AC Specifications. Added to Table 6-6 a footnote and references to same. Added sentences to the resistive pullup and pull-down description bullets. Added sentence to Section 6.4.11, Adjustable Output Level. Updated section 5.5 External Memory Interface Updated Table 11-73 JTAG Interface AC Specifications Updated Table 11-74 SWD Interface AC Specifications Updated style changes as per the new template. *O 3078568 11/04/10 MKEA Added 48-SSOP pin and package details. Removed PLL output duty cycle spec. Updated “Current Digital-to-analog Converter (IDAC)” on page97 Updated “Voltage Digital to Analog Converter (VDAC)” on page101 Updated Table11-2, “DC Specifications,” on page72 Updated Table11-28, “Voltage Reference Specifications,” on page95 Document Number: 001-11729 Rev. AG Page 134 of 140

® PSoC 3: CY8C38 Family Datasheet Description Title: PSoC® 3: CY8C38 Family Datasheet Programmable System-on-Chip (PSoC®) (continued) Document Number: 001-11729 Submission Orig. of Revision ECN Description of Change Date Change *P 3107314 12/10/2010 MKEA Updated delta-sigma tables and graphs. Formatted table 11.2. Updated interrupt controller table Updated transimpedance amplifier section Updated SIO DC specs table Updated Voltage Monitors DC Specifications table Updated LCD Direct Drive DC specs table Replaced the Discrete Time Mixer and Continuous Time Mixer tables with Mixer DC and AC specs tables Updated ESD value. HBM Updated IDAC and VDAC sections Removed ESO parts from ordering information Changed USBIO pins from NC to DNU and removed redundant USBIO pin description notes Updated POR with brown out DC and AC specs Updated PGA AC specs Updated 32 kHz External Crystal DC Specifications Updated opamp AC specs Updated XRES IO specs Updated Inductive boost regulator section Delta sigma ADC spec updates Updated comparator section Removed buzz mode from Power Mode Transition diagram Updated opamp DC and AC spec tables Updated PGA DC table *Q 3179219 22/02/2011 MKEA Updated conditions for flash data retention time Updated 100-pin TQFP package spec. Updated EEPROM AC specifications. *R 3200146 03/28/2011 MKEA Removed Preliminary status from the data sheet. Updated JTAG ID Deleted Cin_G1, ADC input capacitance from Delta-Sigma ADC DC spec table Updated JTAG Interface AC Specifications and SWD Interface Specifications tables Updated USBIO DC specs Added 0.01 to max speed Updated Features on page 1 Added Section 5.5, Nonvolatile Latches Updated Flash AC specs Added CAN DC specs Updated delta-sigma graphs, noise histogram figures and RMS Noise spec tables Add reference to application note AN58304 in section 8.1 Updated 100-pin TQFP package spec Added oscillator, I/O, VDAC, regulator graphs Updated JTAG/SWD timing diagrams Updated GPIO and SIO AC specs Updated POR with Brown Out AC spec table Updated IDAC graphs Added DMA timing diagram, interrupt timing and interrupt vector, I2C timing diagrams Updated opamp graphs and PGA graphs Added full chip performance graphs Changed MHzECO range. Added “Solder Reflow Peak Temperature” table. Document Number: 001-11729 Rev. AG Page 135 of 140

® PSoC 3: CY8C38 Family Datasheet Description Title: PSoC® 3: CY8C38 Family Datasheet Programmable System-on-Chip (PSoC®) (continued) Document Number: 001-11729 Submission Orig. of Revision ECN Description of Change Date Change *S 3259185 05/17/2011 MKEA Added JTAG and SWD interface connection diagrams Updated T and T values in Table 13-1 JA JC Changed typ and max values for the TCVos parameter in Opamp DC specifications table. Updated Clocking subsystem diagram. Changed Vssd to V in the PSoC Power System diagram SSB Updated Ordering information. *T 3464258 12/14/2011 MKEA Updated Analog Global specs Updated IDAC range Updated TIA section Modified VDDIO description in Section 3 Added note on Sleep and Hibernate modes in the Power Modes section Updated Boost Converter section Updated conditions for Inductive boost AC specs Added VDAC/IDAC noise graphs and specs Added pin capacitance specs for ECO pins Removed C from 32 kHz External Crystal DC Specs table. L Added reference to AN54439 in Section 6.1.2.2 Deleted T_SWDO_hold row from the SWD Interface AC Specifications table Removed Pin 46 connections in "Example Schematic for 100-pin TQFP Part with Power Connections” Updated Active Mode IDD description in Table 11-2. Added I and I specs in Table 11-2. DDDR DDAR Replaced “total device program time” with T in Flash AC specs table PROG Added I , I and I specs in Absolute Maximum Ratings GPIO SIO USBIO Added conditions to I spec in 32 kHz External Crystal DC Specs table. CC Updated TCV value OS Removed Boost Efficiency vs V graph OUT Updated boost graphs Updated min value of GPIO input edge rate Removed 3.4 Mbps in UDBs from I2C section Updated USBIO Block diagram; added USBIO drive mode description Updated Analog Interconnect diagram Changed max IMO startup time to 12 µs Added note for I spec in USBIO DC specs table IL Updated GPIO Block diagram Updated voltage reference specs Added text explaining power supply ramp up in Section 11-4. Document Number: 001-11729 Rev. AG Page 136 of 140

® PSoC 3: CY8C38 Family Datasheet Description Title: PSoC® 3: CY8C38 Family Datasheet Programmable System-on-Chip (PSoC®) (continued) Document Number: 001-11729 Submission Orig. of Revision ECN Description of Change Date Change *U 3645908 06/14/2012 MKEA Section 2: Changed text and added figures describing Vddio source and sink. Corrected example PCB layout figure. Sections 3, 6.2: Added text about usage in externally regulated mode. Section 5.2 and elsewhere: Added text describing flash cache, and updated related text. Section 6.1, 11.91: Changed IMO startup time specification. Section 6.1.1.4: Removed text stating that FTW is a wakeup source. Section 6.2.1.4: Added paragraph clarifying limiting the frequency of IO input signals to achieve low hibernate current. Section 6.3: Changed reset status register description text. Sections 6.3.1.1, 6.3.1.2: Added text on XRES and PRES re-arm times Sections 6.3.1.1, 11.8.1: Revised description of IPOR and clarified PRES term. Added text on adjustability of buzz frequency. Section 6.4.14, 11.4: Deleted and updated text regarding SIO performance under certain power ramp conditions. Section 6.4.15: Changed text describing SIO modes for overvoltage tolerance. Section 7.8: Changed “compliant with I2C” to “compatible with I2C”. Section 7.9: Updated DFB description text. Sections 8.9, 11.5.6, 11.5.7: Changed DAC high and low speed/power mode descriptions and conditions. Section 9.1: Added a statement about support for JTAG programmers and file formats. Section 9.3: Deleted the text “debug operations are possible while the device is reset”. Section 11.1: Added specification for ESDHBM for when Vssa and Vssd are separate. Changed footnote to state that all GPIO input voltages must be less than Vddio. Changed supply ramp rate specification. Section 11.2.1: Added chip Idd specs for active and low-power modes, for multiple voltage, temperature and usage conditions. Section 11.3.3: Removed from boost mention of 22 µH inductors, and related graphs. Section 11.5.1: Changed load capacitor conditions in opamp specifications. Clarified description of opamp Iout specification. Section 11.5.3: Updated Vref temperature drift specifications. Added graphs and footnote. Section 11.5.4: Changed analog global specification descriptions and values. Section 11.5.5: Changed comparator specifications and conditions. Section 11.8.2: Voltage monitors response time specification is based on characterization. Section 13: Updated 48-QFN and 100-TQFP package drawings. Throughout document: updated terminology for “master” and “system” clock. *V 3648803 06/18/2012 WKA/MKEA Updated the description of changes for previous (*U) revision. No technical changes. EROS update. Document Number: 001-11729 Rev. AG Page 137 of 140

® PSoC 3: CY8C38 Family Datasheet Description Title: PSoC® 3: CY8C38 Family Datasheet Programmable System-on-Chip (PSoC®) (continued) Document Number: 001-11729 Submission Orig. of Revision ECN Description of Change Date Change *W 3732521 09/03/2012 MKEA Replaced I and I specs in Table11-2, “DC Specifications,” on DDDR DDAR page72 that were dropped out in *U revision. Updated V Max value from 10 to 15 in Table11-36, “Mixer DC Specifications,” OS on page104. Updated Table11-21, “20-bit Delta-sigma ADC DC Specifications,” on page91, I Max value from 1.25 to 1.5 mA DD_20 I Max value from 1.2 to 1.5 mA DD_16 I Max value from 1.4 to 1.95 mA DD_12 Replaced PSoC® 3 Programming AN62391 with TRM in footnote #61 and “Programming, Debug Interfaces, Resources” section on page65. Removed Figure 11-8 (Efficiency vs Vout) Updated Table11-19, “Opamp DC Specifications,” on page88, I Quiescent DD current row values from 200 and 270 to 250 and 400 respectively. Updated conditions for Storage Temperature in Table11-1, “Absolute Maximum Ratings DC Specifications[18],” on page71 Updated conditions and min values for NVL data retention time in Table11-64, “NVL AC Specifications,” on page113 Updated Table11-79, “ILO DC Specifications,” on page121. Removed the following pruned parts from the “Ordering Information” section on page123. CY8C3865PVI-060 CY8C3865LTI-062 CY8C3865PVI-063 CY8C3866AXI-035 Updated PSoC 3 boost circuit value throughout the document. Removed 100 kHz sub row in Table11-55, “DFB DC Specifications,” on page110. Updated package diagram 51-85061 to *F revision. *X 3922905 03/25/2013 MKEA Updated I parameters under Table11-21, “20-bit Delta-sigma ADC DC DD_XX Specifications,” on page91. Updated Temperature Drift spec in Voltage Reference Specifications. Added CY8C3865AXI-204, CY8C3865LTI-205, CY8C3866AXI-206, CY8C3866LTI-207, CY8C3866AXI-208, and CY8C3866LTI-209 part numbers in Ordering Information. Updated I2C section and GPIO and SIO DC specification tables. Corrected Hibernate max limit. Changed INL max value from ±1.5 to ±1.6 in IDAC DC Specifications. Updated ECCEN default setting in Fields and Factory Default Settings. *Y 4064707 07/18/2013 MKEA Added USB test ID in Features. Updated schematic in Section2.. Added paragraph for device reset warning in Section5.4. Added NVL bit for DEBUG_EN in Section5.5. Updated UDB PLD array diagram in Section7.2.1. Changed Tstartup specs in Section11.2.1. Changed GPIO rise and fall time specs in Section11.4. Added Opamp IIB spec in Section11.5.1. Changed Del-sig Vos spec in Section11.5.2. Added VREF spec condition: pre-assembly and added "box method" to VREF temperature drift spec conditions in Section11.5.3. Added IMO spec condition: pre-assembly in Section11.9.1. Added Appendix for CSP package (preliminary). *Z 4118845 09/10/2013 MKEA Removed T spec. and added note clarifying the maximum storage temper- STG ature range in Table11-1. Updated Vos spec conditions and TCVos in Table11-21. Updated F spec (3 MHz). IMO Updated 100-TQFP package diagram. Document Number: 001-11729 Rev. AG Page 138 of 140

® PSoC 3: CY8C38 Family Datasheet Description Title: PSoC® 3: CY8C38 Family Datasheet Programmable System-on-Chip (PSoC®) (continued) Document Number: 001-11729 Submission Orig. of Revision ECN Description of Change Date Change AA 4188568 11/14/2013 MKEA Added SIO Comparator Specifications. Corrected typo in the V parameter in the Voltage Reference Specifications. REF Added CSP information in Packaging and Ordering Information sections. Updated delta-sigma V spec conditions. OS AB 4385782 05/21/2014 MKEA Updated General Description and Features. Added More Information and PSoC Creator sections. Updated 100-pin TQFP package diagram. Corrected number of I/O pins for CY8C3866FNI-210. AC 4708125 03/31/2015 MKEA Added INL4 and DNL4 specs in VDAC DC Specifications. Updated Figure 6-11. Added second note after Figure 6-4. Added a reference to Fig 6-1 in Section6.1.1 and Section6.1.2. Updated Section6.2.2. Added Section7.8.1. Updated Boost specifications. AD 4807497 06/23/2015 MKEA Added reference to code examples in More Information. Updated typ value of TWRITE from 2 to 10 in EEPROM AC specs table. Changed “Device supply for USB operation" to "Device supply (VDDD) for USB operation" in USB DC Specifications. Clarified power supply sequencing and margin for VDDA and VDDD. Updated Serial Wire Debug Interface with limitations of debugging on Port 15. Updated Section 11.7.5. Updated Delta-sigma ADC DC Specifications AE 4932879 09/24/2015 MKEA Changed the Regulator Output Capacitor min and max from "-" to 0.9 and 1.1, respectively. Added reference to AN54439 in Section 11.9.3. Added MHz ECO DC specs table. Removed references to IPOR rearm issues in Section 6.3.1.1. Table 6-1: Changed DSI Fmax to 33 MHz Figure 6-1: Changed External I/O or DSI to 0-33 MHz. Table 11-10: Changed Fgpioin Max to 33 MHz Table 11-12: Changed Fsioin Max to 33 MHz. AF 5322536 06/27/2016 MKEA Updated More Information. Corrected typos in External Electrical Connections. Added links to CAD Libraries in Section 2. AG 5715438 04/27/2017 MKEA/ Updated 48-pin QFN package outline. GNKK Updated the Cypress logo and copyright information. Document Number: 001-11729 Rev. AG Page 139 of 140

® PSoC 3: CY8C38 Family Datasheet 18. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions ARM® Cortex® Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Forums | WICED IOT Forums | Projects | Video | Blogs | Interface cypress.com/interface Training | Components Internet of Things cypress.com/iot Technical Support Memory cypress.com/memory cypress.com/support Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless © Cypress Semiconductor Corporation, 2006-2017. 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