® PSoC 3: CY8C32 Family Data Sheet ® Programmable System-on-Chip (PSoC ) General Description With its unique array of configurable blocks, PSoC® 3 is a true ystem level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C32 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C32 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C32 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, and multimaster inter-integrated circuit (I2C). In addition to communication interfaces, the CY8C32 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C32 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates. Features (cid:132)Single cycle 8051 CPU core (cid:135)Full-speed (FS) USB 2.0 12 Mbps using internal oscillator[2] (cid:135)DC to 50 MHz operation (cid:135)Up to four 16-bit configurable timer, counter, and PWM blocks (cid:135)Multiply and divide instructions (cid:135)Library of standard peripherals (cid:135)Flash program memory, up to 64 KB, 100,000 write cycles, • 8-, 16-, 24-, and 32-bit timers, counters, and PWMs 20 years retention, and multiple security features • Serial peripheral interface (SPI), universal asynchronous (cid:135)Up to 8-KB flash error correcting code (ECC) or configuration transmitter receiver (UART), and I2C storage • Many others available in catalog (cid:135)Up to 8 KB SRAM (cid:135)Library of advanced peripherals • Cyclic redundancy check (CRC) (cid:135)Up to 2 KB electrically erasable programmable read-only memory (EEPROM), 1 M cycles, and 20 years retention • Pseudo random sequence (PRS) generator • Local interconnect network (LIN) bus 2.0 (cid:135)24-channel direct memory access (DMA) with multilayer AHB[1] bus access • Quadrature decoder • Programmable chained descriptors and priorities (cid:132)Analog peripherals (1.71V ≤ VDDA ≤ 5.5V) • High bandwidth 32-bit transfer support (cid:135)1.024V ±0.9-percent internal voltage reference across –40°C (cid:132)Low voltage, ultra low-power to +85°C (14 ppm/°C) (cid:135)Wide operating voltage range: 0.5V to 5.5V (cid:135)Configurable delta-sigma ADC with 8- to12-bit resolution • Programmable gain stage: ×0.25 to ×16 (cid:135)High efficiency boost regulator from 0.5-V through 1.8-V to • 12-bit mode, 192-ksps, 66-dB signal to noise and distortion 5.0-V output ratio (SINAD), ±1-bit INL/DNL (cid:135)0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 50 MHz (cid:135)Low-power modes including: (cid:135)One 8-bit, 8-Msps IDAC or 1-Msps VDAC • 1-µA sleep mode with real-time clock (RTC) and (cid:135)Two comparators with 95 ns response time low-voltage detect(LVD) interrupt (cid:135)CapSense support • 200-nA hibernate mode with RAM retention (cid:132)Programming, debug, and trace (cid:132)Versatile I/O system (cid:135)JTAG (4-wire), serial wire debug (SWD) (2-wire), and single (cid:135)28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO), wire viewer (SWV) interfaces twoUSBIOs[2]) (cid:135)Eight address and one data breakpoint (cid:135)Any GPIO to any digital or analog peripheral routability (cid:135)4-KB instruction trace buffer (cid:135)LCD direct drive from any GPIO, up to 46×16 segments[2] (cid:135)Bootloader programming supportable through I2C, SPI, (cid:135)CapSense® support from any GPIO[3] UART, USB, and other interfaces (cid:135)1.2-V to 5.5-V I/O interface voltages, up to four domains (cid:132)Precision, programmable clocking (cid:135)Maskable, independent IRQ on any pin or port (cid:135)3- to 24-MHz internal oscillator over full temperature and voltage range (cid:135)Schmitt-trigger transistor-transistor logic (TTL) inputs (cid:135)All GPIO configurable as open drain high/low, (cid:135)4- to 25-MHz crystal oscillator for crystal PPM accuracy pull-up/pull-down, High Z, or strong output (cid:135)Internal PLL clock generation up to 50 MHz (cid:135)Configurable GPIO pin state at power-on reset (POR) (cid:135)32.768-kHz watch crystal oscillator (cid:135)25 mA sink on SIO (cid:135)Low-power internal oscillator at 1, 33, and 100 kHz (cid:132)Digital peripherals (cid:132)Temperature and packaging (cid:135)16 to 24 programmable PLD based universal digital (cid:135)–40°C to +85°C degrees industrial temperature blocks(UDB) (cid:135)48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP package options Notes 1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus 2. This feature on select devices only. See Ordering Information on page 108 for details. 3. GPIOs with opamp outputs are not recommended for use with CapSense. CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-56955 Rev. *K Revised May 20, 2011

® PSoC 3: CY8C32 Family Data Sheet Contents 1. Architectural Overview .....................................................3 8.5 CapSense .................................................................57 2. Pinouts ...............................................................................5 8.6 Temp Sensor ............................................................57 8.7 DAC ..........................................................................58 3. Pin Descriptions ..............................................................10 9. Programming, Debug Interfaces, Resources ................59 4. CPU ...................................................................................11 9.1 JTAG Interface .........................................................59 4.1 8051 CPU .................................................................11 9.2 Serial Wire Debug Interface .....................................61 4.2 Addressing Modes ....................................................11 9.3 Debug Features ........................................................62 4.3 Instruction Set ..........................................................12 9.4 Trace Features .........................................................62 4.4 DMA and PHUB .......................................................16 9.5 Single Wire Viewer Interface ....................................62 4.5 Interrupt Controller ...................................................18 9.6 Programming Features .............................................62 5. Memory .............................................................................22 9.7 Device Security ........................................................62 5.1 Static RAM ...............................................................22 10. Development Support ...................................................63 5.2 Flash Program Memory ............................................22 10.1 Documentation .......................................................63 5.3 Flash Security ...........................................................22 10.2 Online .....................................................................63 5.4 EEPROM ..................................................................22 10.3 Tools .......................................................................63 5.5 Nonvolatile Latches (NVLs) ......................................23 5.6 External Memory Interface .......................................24 11. Electrical Specifications ...............................................64 5.7 Memory Map ............................................................24 11.1 Absolute Maximum Ratings ....................................64 11.2 Device Level Specifications ....................................65 6. System Integration ..........................................................26 11.3 Power Regulators ...................................................69 6.1 Clocking System .......................................................26 11.1 Inputs and Outputs .................................................73 6.2 Power System ..........................................................29 11.2 Analog Peripherals .................................................81 6.3 Reset ........................................................................33 11.3 Digital Peripherals ..................................................93 6.4 I/O System and Routing ...........................................34 11.4 Memory ..................................................................96 7. Digital Subsystem ...........................................................40 11.5 PSoC System Resources .....................................102 7.1 Example Peripherals ................................................41 11.6 Clocking ................................................................104 7.2 Universal Digital Block ..............................................44 12. Ordering Information ...................................................108 7.3 UDB Array Description .............................................47 12.1 Part Numbering Conventions ...............................109 7.4 DSI Routing Interface Description ............................47 7.5 USB ..........................................................................49 13. Packaging .....................................................................110 7.6 Timers, Counters, and PWMs ..................................49 14. Acronyms .....................................................................113 7.7 I2C ............................................................................49 15. Reference Documents .................................................114 8. Analog Subsystem ..........................................................51 16. Document Conventions ..............................................115 8.1 Analog Routing .........................................................52 16.1 Units of Measure ..................................................115 8.2 Delta-sigma ADC ......................................................54 17. Revision History ..........................................................116 8.3 Comparators .............................................................55 8.4 LCD Direct Drive ......................................................57 18. Sales, Solutions, and Legal Information .................120 Document Number: 001-56955 Rev. *K Page 2 of 120

® PSoC 3: CY8C32 Family Data Sheet 1. Architectural Overview Introducing the CY8C32 family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C32 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure 1-1. Simplified Block Diagram Analog Interconnect Digital Interconnect S Os System Wide Digital System IO PI Resources Universal Digital Block Array (24 x UDB) I2C 3(2(4O.7O-p63p8t3it oi MoKnnHaHal)zzl) GPIOsG OIXMtsaOcl Clock Tree Usage Example for UDB 8IT2-iCmB SietUUUU lraDDDDvBBBBeQuadratu8r-eB DiUUUUte SDDDDcPBBBBoIder Sequencer1L2o-gBUUUiUciDDDtD SBBBB1PP6IW-BMit 18T6-i-mBBieUUUUti rtDDDD PBBBBRLSogic UUUUDDDDBBBB UUUUDDDDBBBB CPTo4iWum xnMetre r FMSSa2l asU.v0teSer/B UPHSGPIOBY 22 Ω UART 12-Bit PWM s RTC Timer System Bus Memory System CPU System Program & G P WDT 8051 or Debug IO Waankde EEPROM SRAM Cortex M3 CInotnetrrroulpletr Program s CPU GPIOs EMIF FLASH PHUB BDoeTubrnaudcgae r&y ILO DMA Scan Clocking System G Analog System P SIOs PoweSry Mstaenmagement LCDD Driivreect IOs ADC POR and LVD Sleep Power Del Sig 1.71 to5.5V 1.8V LDO TemSpeenrsaoturre DAC ADC C2M xP + GPIO - s SMP CapSense 0.5 to 5.5V (Optional) Figure1-1 illustrates the major components of the CY8C32 PSoC’s digital subsystem provides half of its unique family. They are: configurability. It connects a digital signal from any peripheral to any pin through the Digital System Interconnect (DSI). It also (cid:132)8051 CPU subsystem provides functional flexibility through an array of small, fast, (cid:132)Nonvolatile subsystem low-power UDBs. PSoC Creator provides a library of prebuilt and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, (cid:132)Programming, debug, and test subsystem timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. You can also easily create a digital circuit using (cid:132)Inputs and outputs boolean primitives by means of graphical design entry. Each (cid:132)Clocking UDB contains programmable array logic (PAL)/programmable logic device (PLD) functionality, together with a small state (cid:132)Power machine engine to support a wide variety of peripherals. (cid:132)Digital subsystem (cid:132)Analog subsystem Document Number: 001-56955 Rev. *K Page 3 of 120

® PSoC 3: CY8C32 Family Data Sheet In addition to the flexibility of the UDB array, PSoC also provides exchange data without CPU involvement. This allows the CPU configurable digital blocks targeted at specific functions. For the to run slower (saving power) or use those CPU cycles to improve CY8C32 family these blocks can include four 16-bit timers, the performance of firmware algorithms. The single cycle 8051 counters, and PWM blocks; I2C slave, master, and multimaster; CPU runs ten times faster than a standard 8051 processor. The and FS USB. processor speed itself is configurable, allowing you to tune active power consumption for specific applications. For more details on the peripherals see the “Example Peripherals” section on page41 of this datasheet. For PSoC’s nonvolatile subsystem consists of flash, byte-writeable information on UDBs, DSI, and other digital blocks, see the EEPROM, and nonvolatile configuration options. It provides up “Digital Subsystem” section on page40 of this datasheet. to 64 KB of on-chip flash. The CPU can reprogram individual blocks of flash, enabling bootloaders. You can enable an ECC PSoC’s analog subsystem is the second half of its unique for high reliability applications. A powerful and flexible protection configurability. All analog performance is based on a highly model secures the user's sensitive information, allowing accurate absolute voltage reference with less than 0.9-percent selective memory block locking for read and write protection. Up error over temperature and voltage. The configurable analog to 2 KB of byte-writeable EEPROM is available on-chip to store subsystem includes: application data. Additionally, selected configuration options (cid:132)Analog muxes such as boot speed and pin drive mode are stored in nonvolatile memory. This allows settings to activate immediately after POR. (cid:132)Comparators The three types of PSoC I/O are extremely flexible. All I/Os have (cid:132)Voltage references many drive modes that are set at POR. PSoC also provides up to four I/O voltage domains through the V pins. Every GPIO (cid:132)ADC DDIO has analog I/O, LCD drive[4], CapSense[5], flexible interrupt (cid:132)DAC generation, slew rate control, and digital I/O capability. The SIOs on PSoC allow Voh to be set independently of V when used All GPIO pins can route analog signals into and out of the device DDIO as outputs. When SIOs are in input mode they are high using the internal analog bus. This allows the device to interface impedance. This is true even when the device is not powered or up to 62 discrete analog signals. The heart of the analog when the pin voltage goes above the supply voltage. This makes subsystem is a fast, accurate, configurable delta-sigma ADC the SIO ideally suited for use on an I2C bus where the PSoC may with these features: not be powered when other devices on the bus are. The SIO pins (cid:132)Less than 100 µV offset also have high current sink capability for applications such as LED drives. The programmable input threshold feature of the (cid:132)A gain error of 0.2 percent SIO can be used to make the SIO function as a general purpose (cid:132)INL less than ±1 LSB analog comparator. For devices with FS USB the USB physical interface is also provided (USBIO). When not using USB these (cid:132)DNL less than ±1 LSB pins may also be used for limited digital functionality and device programming. All of the features of the PSoC I/Os are covered (cid:132)SINAD better than 66 dB in detail in the “I/O System and Routing” section on page34 of This converter addresses a wide variety of precision analog this datasheet. applications, including some of the most demanding sensors. The PSoC device incorporates flexible internal clock generators, A high-speed voltage or current DAC supports 8-bit output designed for high stability and factory trimmed for high accuracy. signals at an update rate of 8 Msps in current DAC (IDAC) and The Internal Main Oscillator (IMO) is the master clock base for 1 Msps in voltage DAC (VDAC). It can be routed out of any GPIO the system, and has 1-percent accuracy at 3 MHz. The IMO can pin. You can create higher resolution voltage PWM DAC outputs be configured to run from 3 MHz up to 24 MHz. Multiple clock using the UDB array. This can be used to create a pulse width derivatives can be generated from the main clock frequency to modulated (PWM) DAC of up to 10 bits, at up to 48 kHz. The meet application needs. The device provides a PLL to generate digital DACs in each UDB support PWM, PRS, or delta-sigma system clock frequencies up to 50 MHz from the IMO, external algorithms with programmable widths. crystal, or external reference clock. It also contains a separate, In addition to the ADC and DAC, the analog subsystem provides very low-power Internal Low-Speed Oscillator (ILO) for the sleep multiple comparators. and watchdog timers. A 32.768-kHz external watch crystal is also supported for use in RTC applications. The clocks, together See the “Analog Subsystem” section on page51 of this with programmable clock dividers, provide the flexibility to datasheet for more details. integrate most timing requirements. PSoC’s 8051 CPU subsystem is built around a single cycle The CY8C32 family supports a wide supply operating range from pipelined 8051 8-bit processor running at up to 50 MHz. The 1.71 V to 5.5V. This allows operation from regulated supplies CPU subsystem includes a programmable nested vector such as 1.8 ± 5 percent, 2.5V ±10 percent, 3.3V ± 10 percent, interrupt controller, DMA controller, and RAM. PSoC’s nested or 5.0 V ± 10 percent, or directly from a wide range of battery vector interrupt controller provides low latency by allowing the types. In addition, it provides an integrated high efficiency CPU to vector directly to the first address of the interrupt service synchronous boost converter that can power the device from routine, bypassing the jump instruction required by other supply voltages as low as 0.5V. architectures. The DMA controller enables peripherals to Notes 4. This feature on select devices only. See Ordering Information on page 108 for details. 5. GPIOs with opamp outputs are not recommended for use with CapSense. Document Number: 001-56955 Rev. *K Page 4 of 120

® PSoC 3: CY8C32 Family Data Sheet This enables the device to be powered directly from a single you can implement a full debugging interface with just three pins. battery or solar cell. In addition, you can use the boost converter Using these standard interfaces enables you to debug or to generate other voltages required by the device, such as a program the PSoC with a variety of hardware solutions from 3.3-V supply for LCD glass drive. The boost’s output is available Cypress or third party vendors. PSoC supports on-chip break on the V pin, allowing other devices in the application to points and 4-KBinstruction and data race memory for debug. BOOST be powered from the PSoC. Details of the programming, test, and debugging interfaces are discussed in the “Programming, Debug Interfaces, Resources” PSoC supports a wide range of low-power modes. These include section on page59 of this datasheet. a 200-nA hibernate mode with RAM retention and a 1-µA sleep mode with RTC. In the second mode the optional 32.768-kHz 2. Pinouts watch crystal runs continuously and maintains an accurate RTC. Power to all major functional blocks, including the programmable The Vddio pin that supplies a particular set of pins is indicated digital and analog peripherals, can be controlled independently by the black lines drawn on the pinout diagrams in Figure2-1 by firmware. This allows low-power background processing through Figure2-4. Using the Vddio pins, a single PSoC can when some peripherals are not in use. This, in turn, provides a support multiple interface voltage levels, eliminating the need for total device current of only 1.2 mA when the CPU is running at off-chip level shifters. Each Vddio may sink up to 100 mA total to 6MHz, or 0.8 mA running at 3 MHz. its associated I/O pins. On the 68 pin and 100 pin devices each The details of the PSoC power modes are covered in the “Power set of Vddio associated pins may sink up to 100 mA. The 48-pin System” section on page29 of this datasheet. device may sink up to 100 mA total for all Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all Vddio1 plus Vddio3 PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for associated I/O pins. programming, debug, and test. The 1-wire SWV may also be used for “printf” style debugging. By combining SWD and SWV, Figure 2-1. 48-pin SSOP Part Pinout (SIO) P12[2] 1 48 Vdda (SIO) P12[3] 2 47 Vssa (GPIO) P0[0] 3 Lines show 46 Vcca Vddio to I/O (GPIO) P0[1] 4 45 P15[3] (GPIO, kHz XTAL: Xi) supply (GPIO) P0[2] 5 association 44 P15[2] (GPIO, kHz XTAL: Xo) (Extref0, GPIO) P0[3] 6 43 P12[1] (SIO, I2C1: SDA) Vddio0 7 42 P12[0] (SIO, I2C1: SCL) (GPIO) P0[4] 8 41 Vddio3 (GPIO) P0[5] 9 40 P15[1] (GPIO, MHz XTAL: Xi) (IDAC0, GPIO) P0[6] 10 39 P15[0] (GPIO, MHz XTAL: Xo) (GPIO) P0[7] 11 38 Vccd Vccd 12 SSOP 37 Vssd Vssd 13 36 Vddd [6] Vddd 14 35 P15[7] (USBIO, D-, SWDCK) [6] (GPIO) P2[3] 15 34 P15[6] (USBIO, D+, SWDIO) (GPIO) P2[4] 16 33 P1[7] (GPIO) Vddio2 17 32 P1[6] (GPIO) (GPIO) P2[5] 18 31 Vddio1 (GPIO) P2[6] 19 30 P1[5] (GPIO, nTRST) (GPIO) P2[7] 20 29 P1[4] (GPIO, TDI) Vssb 21 28 P1[3] (GPIO, TDO, SWV) Ind 22 27 P1[2] (GPIO, configurable XRES) Vboost 23 26 P1[1] (GPIO, TCK, SWDCK) Vbat 24 25 P1[0] (GPIO, TMS, SWDIO) Note 6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. Document Number: 001-56955 Rev. *K Page 5 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 2-2. 48-pin QFN Part Pinout[8] 0) C A D O) O)O) O)O, IO)O) PI PIPI PIPIPIPI G GG GGGG P2[5] (Vddio2P2[4] (P2[3] (VdddVssdVccdP0[7] (P0[6] (P0[5] (P0[4] (Vddio0 (GPIO) P2[6] 14847 46454443 42414039383736 P0[3] (Extref0, GPIO) (GPIO) P2[7] 2 Lines show 35 P0[2] (GPIO) Vssb 3 Vddio to I/O 34 P0[1] (GPIO) Ind 4 supply 33 P0[0] (GPIO) association Vboost 5 32 P12[3] (SIO) Vbat 6 QFN 31 P12[2] (SIO) (GPIO, TMS, SWDIO) P1[0] 7 (Top View) 30 Vdda (GPIO, TCK, SWDCK) P1[1] 8 29 Vssa (GPIO, Configurable XRES) P1[2] 9 28 Vcca (GPIO, TDO, SWV) P1[3] 10 27 P15[3] (GPIO, kHz XTAL: Xi) (GPIO, TDI) P1[4] 11 26 P15[2] (GPIO, kHz XTAL: Xo) (GPIO, nTRST) P1[5] 121314 1516 171819202122232425 P12[1] (SIO, I2C1: SDA) Vddio1 (GPIO) P1[6](GPIO) P1[7]USBIO, D+, SWDIO) P15[6]USBIO, D-, SWDCK) P15[7]VdddVssdVccdPIO, MHz XTAL: Xo) P15[0] GPIO, MHz XTAL: Xi) P15[1]Vddio3(SIO, I2C1: SCL) P12[0] (( G ( 7] 7] ( [ [ Notes 7. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. 8. PPins are Do Not Use (DNU) on devices without USB. The pin must be left floating. Document Number: 001-56955 Rev. *K Page 6 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 2-3. 68-pin QFN Part Pinout[10] 0) C A D PIO) PIO)PIO) PIO)PIO)PIO) GPOI)GPIO) PIO) PIO, I PIO)PIO) 2[5] (G ddio2 2[4] (G2[3] (G 2[2] (G2[1] (G2[0] (G 15[5] (15[4] (ddd ssdccd 0[7] (G 0[6] (G 0[5] (G0[4] (Gddio0 P V PP PPP PPV VV P P PPV 87 65 4 32109 876 54 32 66 66 6 66665 555 55 55 (GPIO) P2[6] 1 51 P0[3] (GPIO, Extref0) (GPIO) P2[7] 2 50 P0[2] (GPIO) (I2C0: SCL, SIO) P12[4] 3 49 P0[1] (GPIO) Lines show Vddio (I2C0: SDA, SIO) P12[5] 4 48 P0[0] (GPIO) to I/O supply Vssb 5 association 47 P12[3] (SIO) Ind 6 46 P12[2] (SIO) Vboost 7 45 Vssd Vbat 8 44 Vdda QFN Vssd 9 43 Vssa XRES 10 (Top View) 42 Vcca (TMS, SWDIO, GPIO) P1[0] 11 41 P15[3] (GPIO, kHz XTAL: Xi) (TCK, SWDCK, GPIO) P1[1] 12 40 P15[2] (GPIO, kHz XTAL: Xo) (configurable XRES, GPIO) P1[2] 13 39 P12[1] (SIO, I2C1: SDA) (TDO, SWV, GPIO) P1[3] 14 38 P12[0] (SIO, 12C1: SCL) (TDI, GPIO) P1[4] 15 37 P3[7] (GPIO) (nTRST, GPIO) P1[5] 16 36 P3[6] (GPIO) Vddio1 17 35 Vddio3 89 012 3 4567 890 123 4 11 222 2 2222 223 333 3 P1[6] P1[7]12[6]12[7] 15[6]15[7] Vddd VssdVccd15[0] 15[1]P3[0]P3[1]P3[2] P3[3] P3[4] P3[5] (GPIO) (GPIO) (SIO) P(SIO) P (USBIO, D+, SWDIO) P(USBIO, D-, SWDCK) P (MHz XTAL: Xo, GPIO) P (MHz XTAL: Xi, GPIO) P(GPIO) (GPIO) (Extref1, GPIO) (GPIO) (GPIO) (GPIO) Notes 9. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. 10.The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. Document Number: 001-56955 Rev. *K Page 7 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 2-4. 100-pin TQFP Part Pinout 0) C A D PIO) PIO)PIO) PIO)PIO)GPIO) GPIO)PIO)PIO) PIO)PIO) PIO)PIO) PIO)PIO)PIO)PIO) PIO) PIO, I PIO)PIO) ddio2 2[4] (G 2[3] (G2[2] (G 2[1] (G2[0] (G15[5] ( 15[4] (6[3] (G6[2] (G 6[1] (G6[0] (G ddd ssd ccd4[7] (G4[6] (G 4[5] (G4[4] (G4[3] (G4[2] (G 0[7] (G 0[6] (G 0[5] (G0[4] (G V P PP PPP PPP PP V V VPP PPPP P P PP (GPIO) P2[5] 1 10099 9897 96 9594939291 908988 8786 858483 8281 80 7978 777675 Vddio0 (GPIO) P2[6] 2 74 P0[3] (GPIO,Extref0) (GPIO) P2[7] 3 73 P0[2] (GPIO) Lines show Vddio (I2C0: SCL, SIO) P12[4] 4 72 P0[1] (GPIO) to I/O supply (I2C0: SDA, SIO) P12[5] 5 association 71 P0[0] (GPIO) (GPIO) P6[4] 6 70 P4[1] (GPIO) (GPIO) P6[5] 7 69 P4[0] (GPIO) (GPIO) P6[6] 8 68 P12[3] (SIO) (GPIO) P6[7] 9 67 P12[2] (SIO) Vssb 10 66 Vssd Ind 11 65 Vdda Vboost 12 64 Vssa Vbat 13 TQFP 63 Vcca Vssd 14 62 NC XRES 15 61 NC (GPIO) P5[0] 16 60 NC (GPIO) P5[1] 17 59 NC (GPIO) P5[2] 18 58 NC (GPIO) P5[3] 19 57 NC (TMS, SWDIO, GPIO) P1[0] 20 56 P15[3] (GPIO, kHz XTAL: Xi) (TCK, SWDCK, GPIO) P1[1] 21 55 P15[2] (GPIO, kHz XTAL: Xo) (configurable XRES, GPIO) P1[2] 22 54 P12[1] (SIO, I2C1: SDA) (TDO, SWV, GPIO) P1[3] 23 53 P12[0] (SIO, I2C1: SCL) (TDI, GPIO) P1[4] 24 52 P3[7] (GPIO) (nTRST, GPIO) P1[5] 25 51 P3[6] (GPIO) 67 890 1 2345 678 901 2 345 6 78 90 22 223 3 3333 333 344 4 444 4 44 45 Vddio1 (GPIO) P1[6](GPIO) P1[7](SIO) P12[6] (SIO) P12[7](GPIO) P5[4] (GPIO) P5[5] (GPIO) P5[6](GPIO) P5[7]1](USBIO, D+, SWDIO) P15[6] (USBIO, D-, SWDCK) P15[7]1]VdddVssdVccd NC NC (MHz XTAL: Xo, GPIO) P15[0] (MHz XTAL: Xi, GPIO) P15[1] (GPIO) P3[0](GPIO) P3[1](Extref1, GPIO) P3[2](GPIO) P3[3](GPIO) P3[4] (GPIO) P3[5]Vddio3 1 1 [ [ Figure2-5 and Figure2-6 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog performance on a two layer board. (cid:132)The two pins labeled Vddd must be connected together. (cid:132)The two pins labeled Vccd must be connected together, with capacitance added, as shown in Figure2-5 and Power System on page 29. The trace between the two Vccd pins should be as short as possible. (cid:132)The two pins labeled Vssd must be connected together. For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board Layout Considerations for PSoC® 3 and PSoC 5. Note 11.Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. Document Number: 001-56955 Rev. *K Page 8 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 2-5. Example Schematic for 100-pin TQFP Part with Power Connections Vddd Vddd C1 C2 Vddd 1 uF 0.1 uF Vccd 0C.61 uF Vddd Vssd VdddVssd Vssd Vssd 100999897969594939291908988878685848382818079787776 UC2Y8C55xx 1234 PPPP2221[[[2567[]]]4], SIOVddio2P2[4]P2[3]P2[2]P2[1]P2[0]P15[5]P15[4]P6[3]P6[2]P6[1]P6[0]VdddVssdVccdP4[7]P4[6]P4[5]P4[4]P4[3]P4[2]IDAC2, P0[7]OIDAC0, P0[6]A0OA2-, P0[5]-O,OA2+, P0[4] AOR0EAoF0u+0tV,,, dPPPd000io[[[1320]]] 77774523 Vddd0C.18 uF Vdda1C 1u7F 5 P12[5], SIO OA2out, P0[0] 71 6 P6[4] P4[1] 70 Vssd Vssd 11111119780123456 VIVVVXPPPPnb5666Rbssdssa[[[[oE0756bdtoS]]]]st SSIIOO,, PPVPVVV11d422cssNNNd[[[css023CCCaaad]]] 66666666663467801259 VVVVVssdcssscdsadaad 1C 9uFVssd VVdssdaa0C.110 uF 17 P5[1] NC 59 18 P5[2] NC 58 1290 PP51[[30]], SWIO, TMS kHzXin, P15N[3C] 5576 Vssa 21 P1[1], SWDIO, TCK kHzXout, P15[2] 55 22222345 PPPP1111[[[[2345]]]],,, STnTDWRIVVddio1S, TP1[6]TDP1[7]OP12[6], SIOP12[7], SIOP5[4]P5[5]P5[6]P5[7]USB D+, P15[6]USB D-, P15[7]VdddVssdVccdNCNCP15[0], MHzXoutP15[1], MHzXinP3[0], IDAC1P3[1], IDAC3P3[2], OA3-, REF1P3[3], OA3+P3[4], OA1-P3[5], OA1+OOVddio3AASS13IIooOOuu,, tt,,PP PP113322[[[[6701]]]] 55553412 Vddd 26272829303132333435363738394041424344454647484950 Vddd P32 C11 C12 0.1 uF 0.1 uF Vddd Vssd Vccd 10 Cu1F3, 6.3 V 0C.114 uF Vssd Vssd C16 C15 0.1 uF 1 uF Vssa Vssa Vssd Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6 on page 10. Document Number: 001-56955 Rev. *K Page 9 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance Vssa Vddd Vssd Vdda Vssa Vssd Plane Plane 3. Pin Descriptions nTRST Optional JTAG test reset programming and debug port IDAC0 connection to reset the JTAG connection. Low resistance output pin for high current DAC (IDAC). SIO Extref0, Extref1 Special I/O provides interfaces to the CPU, digital peripherals External reference input to the analog system. and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state GPIO when the device is unpowered. General purpose I/O pin provides interfaces to the CPU, digital SWDCK peripherals, analog peripherals, interrupts, LCD segment drive, and CapSense. Serial wire debug clock programming and debug port connection. I2C0: SCL, I2C1: SCL SWDIO I2C SCL line providing wake from sleep on an address match. Any I/O pin can be used for I2C SCL if wake from sleep is not Serial wire debug input and output programming and debug port required. connection. I2C0: SDA, I2C1: SDA SWV. I2C SDA line providing wake from sleep on an address match. Single wire viewer debug output. Any I/O pin can be used for I2C SDA if wake from sleep is not TCK required. JTAG test clock programming and debug port connection. Ind TDI Inductor connection to boost pump. JTAG test data in programming and debug port connection. kHz XTAL: Xo, kHz XTAL: Xi TDO 32.768-kHz crystal oscillator pin. JTAG test data out programming and debug port connection. MHz XTAL: Xo, MHz XTAL: Xi TMS 4- to 25- MHz crystal oscillator pin. JTAG test mode select programming and debug port connection. Document Number: 001-56955 Rev. *K Page 10 of 120

® PSoC 3: CY8C32 Family Data Sheet USBIO, D+ 4. CPU Provides D+ connection directly to a USB 2.0 bus. May be used 4.1 8051 CPU as a digital I/O pin. Pins are Do Not Use (DNU) on devices without USB. The CY8C32 devices use a single cycle 8051 CPU, which is fully compatible with the original MCS-51 instruction set. The USBIO, D– CY8C32 family uses a pipelined RISC architecture, which Provides D– connection directly to a USB 2.0 bus. May be used executes most instructions in 1 to 2 cycles to provide peak as a digital I/O pin. Pins are No Connect (NC) on devices without performance of up to 24 MIPS with an average of 2 cycles per USB. instruction. The single cycle 8051 CPU runs ten times faster than a standard 8051 processor. Vboost The 8051 CPU subsystem includes these features: Power sense connection to boost pump. (cid:132)Single cycle 8051 CPU Vbat (cid:132)Up to 64 KB of flash memory, up to 2 KB of EEPROM, and up Battery supply to boost pump. to 8 KB of SRAM Vcca (cid:132)Programmable nested vector interrupt controller Output of analog core regulator and input to analog core. (cid:132)Direct memory access (DMA) controller Requires a 1-µF capacitor to V . Regulator output not for SSA external use. (cid:132)Peripheral HUB (PHUB) Vccd (cid:132)External memory interface (EMIF) Output of digital core regulator and input to digital core. The two 4.2 Addressing Modes V pins must be shorted together, with the trace between CCD them as short as possible, and a 1-µF capacitor to V ; see The following addressing modes are supported by the 8051: SSD Power System on page 29. Regulator output not for external use. (cid:132)Direct Addressing: The operand is specified by a direct 8-bit Vdda address field. Only the internal RAM and the SFRs can be accessed using this mode. Supply for all analog peripherals and analog core regulator. Vdda must be the highest voltage present on the device. All (cid:132)Indirect Addressing: The instruction specifies the register which other supply pins must be less than or equal to V . contains the address of the operand. The registers R0 or R1 DDA are used to specify the 8-bit address, while the data pointer Vddd (DPTR) register is used to specify the 16-bit address. Supply for all digital peripherals and digital core regulator. VDDA (cid:132)Register Addressing: Certain instructions access one of the must be less than or equal to VDDA. registers (R0 to R7) in the specified register bank. These instructions are more efficient because there is no need for an Vssa address field. Ground for all analog peripherals. (cid:132)Register Specific Instructions: Some instructions are specific Vssb to certain registers. For example, some instructions always act on the accumulator. In this case, there is no need to specify the Ground connection for boost pump. operand. Vssd (cid:132)Immediate Constants: Some instructions carry the value of the Ground for all digital logic and I/O pins. constants directly instead of an address. Vddio0, Vddio1, Vddio2, Vddio3 (cid:132)Indexed Addressing: This type of addressing can be used only for a read of the program memory. This mode uses the data Supply for I/O pins. See pinouts for specific I/O pin to Vddio pointer as the base and the accumulator value as an offset to mapping. Each Vddio must be tied to a valid operating voltage read a program memory. (1.71V to 5.5V), and must be less than or equal to Vdda. If the I/O pins associated with Vddio0, Vddio2 or Vddio3 are not used (cid:132)Bit Addressing: In this mode, the operand is one of 256 bits. then that Vddio should be tied to ground (Vssd or Vssa). XRES (and configurable XRES) External reset pin. Active low with internal pull-up. Pin P1[2] may be configured to be a XRES pin; see “Nonvolatile Latches (NVLs)” on page23. Document Number: 001-56955 Rev. *K Page 11 of 120

® PSoC 3: CY8C32 Family Data Sheet 4.3 Instruction Set 4.3.1 Instruction Set Summary The 8051 instruction set is highly optimized for 8-bit handling and 4.3.1.1 Arithmetic Instructions Boolean operations. The types of instructions supported include: Arithmetic instructions support the direct, indirect, register, (cid:132)Arithmetic instructions immediate constant, and register-specific instructions. Arithmetic modes are used for addition, subtraction, (cid:132)Logical instructions multiplication, division, increment, and decrement operations. Table4-1 Table 4-1 on page 12lists the different arithmetic (cid:132)Data transfer instructions instructions. (cid:132)Boolean instructions (cid:132)Program branching instructions Table 4-1. Arithmetic Instructions Mnemonic Description Bytes Cycles ADD A,Rn Add register to accumulator 1 1 ADD A,Direct Add direct byte to accumulator 2 2 ADD A,@Ri Add indirect RAM to accumulator 1 2 ADD A,#data Add immediate data to accumulator 2 2 ADDCA,Rn Add register to accumulator with carry 1 1 ADDCA,Direct Add direct byte to accumulator with carry 2 2 ADDCA,@Ri Add indirect RAM to accumulator with carry 1 2 ADDCA,#data Add immediate data to accumulator with carry 2 2 SUBBA,Rn Subtract register from accumulator with borrow 1 1 SUBBA,Direct Subtract direct byte from accumulator with borrow 2 2 SUBBA,@Ri Subtract indirect RAM from accumulator with borrow 1 2 SUBBA,#data Subtract immediate data from accumulator with borrow 2 2 INC A Increment accumulator 1 1 INC Rn Increment register 1 2 INC Direct Increment direct byte 2 3 INC @Ri Increment indirect RAM 1 3 DEC A Decrement accumulator 1 1 DEC Rn Decrement register 1 2 DEC Direct Decrement direct byte 2 3 DEC @Ri Decrement indirect RAM 1 3 INC DPTR Increment data pointer 1 1 MUL Multiply accumulator and B 1 2 DIV Divide accumulator by B 1 6 DAA Decimal adjust accumulator 1 3 Document Number: 001-56955 Rev. *K Page 12 of 120

® PSoC 3: CY8C32 Family Data Sheet 4.3.1.2 Logical Instructions The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. Table4-2Table 4-2 on page 13 shows the list of logical instructions and their description. Table 4-2. Logical Instructions Mnemonic Description Bytes Cycles ANL A,Rn AND register to accumulator 1 1 ANL A,Direct AND direct byte to accumulator 2 2 ANL A,@Ri AND indirect RAM to accumulator 1 2 ANL A,#data AND immediate data to accumulator 2 2 ANL Direct, A AND accumulator to direct byte 2 3 ANL Direct, #data AND immediate data to direct byte 3 3 ORL A,Rn OR register to accumulator 1 1 ORL A,Direct OR direct byte to accumulator 2 2 ORL A,@Ri OR indirect RAM to accumulator 1 2 ORL A,#data OR immediate data to accumulator 2 2 ORL Direct, A OR accumulator to direct byte 2 3 ORL Direct, #data OR immediate data to direct byte 3 3 XRL A,Rn XOR register to accumulator 1 1 XRL A,Direct XOR direct byte to accumulator 2 2 XRL A,@Ri XOR indirect RAM to accumulator 1 2 XRL A,#data XOR immediate data to accumulator 2 2 XRL Direct, A XOR accumulator to direct byte 2 3 XRL Direct, #data XOR immediate data to direct byte 3 3 CLR A Clear accumulator 1 1 CPL A Complement accumulator 1 1 RL A Rotate accumulator left 1 1 RLC A Rotate accumulator left through carry 1 1 RR A Rotate accumulator right 1 1 RRC A Rotate accumulator right though carry 1 1 SWAPA Swap nibbles within accumulator 1 1 Document Number: 001-56955 Rev. *K Page 13 of 120

® PSoC 3: CY8C32 Family Data Sheet 4.3.1.3 Data Transfer Instructions addressing mode. Table4-3 lists the various data transfer instructions available. The data transfer instructions are of three types: the core RAM, xdata RAM, and the lookup tables. The core RAM transfer 4.3.1.4 Boolean Instructions includes transfer between any two core RAM locations or SFRs. The 8051 core has a separate bit-addressable memory location. These instructions can use direct, indirect, register, and It has 128 bits of bit addressable RAM and a set of SFRs that are immediate addressing. The xdata RAM transfer includes only the bit addressable. The instruction set includes the whole menu of transfer between the accumulator and the xdata RAM location. bit operations such as move, set, clear, toggle, OR, and AND It can use only indirect addressing. The lookup tables involve instructions and the conditional jump instructions. Table 4-4 on nothing but the read of program memory using the Indexed page 15Table4-4 lists the available Boolean instructions. Table 4-3. Data Transfer Instructions Mnemonic Description Bytes Cycles MOV A,Rn Move register to accumulator 1 1 MOV A,Direct Move direct byte to accumulator 2 2 MOV A,@Ri Move indirect RAM to accumulator 1 2 MOV A,#data Move immediate data to accumulator 2 2 MOV Rn,A Move accumulator to register 1 1 MOV Rn,Direct Move direct byte to register 2 3 MOV Rn, #data Move immediate data to register 2 2 MOV Direct, A Move accumulator to direct byte 2 2 MOV Direct, Rn Move register to direct byte 2 2 MOV Direct, Direct Move direct byte to direct byte 3 3 MOV Direct, @Ri Move indirect RAM to direct byte 2 3 MOV Direct, #data Move immediate data to direct byte 3 3 MOV @Ri, A Move accumulator to indirect RAM 1 2 MOV @Ri, Direct Move direct byte to indirect RAM 2 3 MOV @Ri, #data Move immediate data to indirect RAM 2 2 MOV DPTR, #data16 Load data pointer with 16-bit constant 3 3 MOVC A, @A+DPTR Move code byte relative to DPTR to accumulator 1 5 MOVC A, @A + PC Move code byte relative to PC to accumulator 1 4 MOVX A,@Ri Move external RAM (8-bit) to accumulator 1 4 MOVX A, @DPTR Move external RAM (16-bit) to accumulator 1 3 MOVX @Ri, A Move accumulator to external RAM (8-bit) 1 5 MOVX @DPTR, A Move accumulator to external RAM (16-bit) 1 4 PUSH Direct Push direct byte onto stack 2 3 POP Direct Pop direct byte from stack 2 2 XCH A, Rn Exchange register with accumulator 1 2 XCH A, Direct Exchange direct byte with accumulator 2 3 XCH A, @Ri Exchange indirect RAM with accumulator 1 3 XCHD A, @Ri Exchange low order indirect digit RAM with accumulator 1 3 Document Number: 001-56955 Rev. *K Page 14 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 4-4. Boolean Instructions Mnemonic Description Bytes Cycles CLR C Clear carry 1 1 CLR bit Clear direct bit 2 3 SETB C Set carry 1 1 SETB bit Set direct bit 2 3 CPL C Complement carry 1 1 CPL bit Complement direct bit 2 3 ANL C, bit AND direct bit to carry 2 2 ANL C, /bit AND complement of direct bit to carry 2 2 ORL C, bit OR direct bit to carry 2 2 ORL C, /bit OR complement of direct bit to carry 2 2 MOV C, bit Move direct bit to carry 2 2 MOV bit, C Move carry to direct bit 2 3 JC rel Jump if carry is set 2 3 JNC rel Jump if no carry is set 2 3 JB bit, rel Jump if direct bit is set 3 5 JNB bit, rel Jump if direct bit is not set 3 5 JBC bit, rel Jump if direct bit is set and clear bit 3 5 Document Number: 001-56955 Rev. *K Page 15 of 120

® PSoC 3: CY8C32 Family Data Sheet 4.3.1.5 Program Branching Instructions The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. Table4-5 shows the list of jump instructions. Table 4-5. Jump Instructions Mnemonic Description Bytes Cycles ACALL addr11 Absolute subroutine call 2 4 LCALL addr16 Long subroutine call 3 4 RET Return from subroutine 1 4 RETI Return from interrupt 1 4 AJMP addr11 Absolute jump 2 3 LJMP addr16 Long jump 3 4 SJMP rel Short jump (relative address) 2 3 JMP @A + DPTR Jump indirect relative to DPTR 1 5 JZ rel Jump if accumulator is zero 2 4 JNZ rel Jump if accumulator is nonzero 2 4 CJNE A,Direct, rel Compare direct byte to accumulator and jump if not equal 3 5 CJNE A, #data, rel Compare immediate data to accumulator and jump if not equal 3 4 CJNE Rn, #data, rel Compare immediate data to register and jump if not equal 3 4 CJNE @Ri, #data, rel Compare immediate data to indirect RAM and jump if not equal 3 5 DJNZ Rn,rel Decrement register and jump if not zero 2 4 DJNZ Direct, rel Decrement direct byte and jump if not zero 3 5 NOP No operation 1 1 4.4 DMA and PHUB (cid:132)Simultaneous CPU and DMA access to peripherals located on different spokes The PHUB and the DMA controller are responsible for data transfer between the CPU and peripherals, and also data (cid:132)Simultaneous DMA source and destination burst transactions transfers between peripherals. The PHUB and DMA also control on different spokes device configuration during boot. The PHUB consists of: (cid:132)Supports 8, 16, 24, and 32-bit addressing and data (cid:132)A central hub that includes the DMA controller, arbiter, and router Table 4-6. PHUB Spokes and Peripherals (cid:132)Multiple spokes that radiate outward from the hub to most PHUB Spokes Peripherals peripherals 0 SRAM There are two PHUB masters: the CPU and the DMA controller. 1 IOs, PICU, EMIF Both masters may initiate transactions on the bus. The DMA 2 PHUB local configuration, Power manager, channels can handle peripheral communication without CPU Clocks, IC, SWV, EEPROM, Flash intervention. The arbiter in the central hub determines which programming interface DMA channel is the highest priority if there are multiple requests. 3 Analog interface and trim, Decimator 4.4.1 PHUB Features 4 USB, USB, I2C, Timers, Counters, and PWMs (cid:132)CPU and DMA controller are both bus masters to the PHUB 5 Reserved (cid:132)Eight Multi-layer AHB Bus parallel access paths (spokes) for 6 UDBs group 1 peripheral access 7 UDBs group 2 Document Number: 001-56955 Rev. *K Page 16 of 120

® PSoC 3: CY8C32 Family Data Sheet 4.4.2 DMA Features shown in Table4-7 after the CPU and DMA priority levels 0 and 1 have satisfied their requirements. (cid:132)24 DMA channels Table 4-7. Priority Levels (cid:132)Each channel has one or more transaction descriptors (TDs) to configure channel behavior. Up to 128 total TDs can be Priority Level % Bus Bandwidth defined 0 100.0 (cid:132)TDs can be dynamically updated 1 100.0 (cid:132)Eight levels of priority per channel 2 50.0 (cid:132)Any digitally routable signal, the CPU, or another DMA channel, 3 25.0 can trigger a transaction 4 12.5 (cid:132)Each channel can generate up to two interrupts per transfer 5 6.2 (cid:132)Transactions can be stalled or canceled 6 3.1 (cid:132)Supports transaction size of infinite or 1 to 64k bytes 7 1.5 (cid:132)TDs may be nested and/or chained for complex transactions 4.4.3 Priority Levels When the fairness algorithm is disabled, DMA access is granted based solely on the priority level; no bus bandwidth guarantees The CPU always has higher priority than the DMA controller are made. when their accesses require the same bus resources. Due to the system architecture, the CPU can never starve the DMA. DMA 4.4.4 Transaction Modes Supported channels of higher priority (lower priority number) may interrupt The flexible configuration of each DMA channel and the ability to current DMA transfers. In the case of an interrupt, the current chain multiple channels allow the creation of both simple and transfer is allowed to complete its current transaction. To ensure complex use cases. General use cases include, but are not latency limits when multiple DMA accesses are requested limited to: simultaneously, a fairness algorithm guarantees an interleaved minimum percentage of bus bandwidth for priority levels 2 4.4.4.1 Simple DMA through 7. Priority levels 0 and 1 do not take part in the fairness In a simple DMA case, a single TD transfers data between a algorithm and may use 100 percent of the bus bandwidth. If a tie source and sink (peripherals or memory location). The basic occurs on two DMA requests of the same priority level, a simple timing diagrams of DMA read and write cycles are shown in round robin method is used to evenly share the allocated Figure 4-1. For more description on other transfer modes, refer bandwidth. The round robin allocation can be disabled for each to the Technical Reference Manual. DMA channel, allowing it to always be at the head of the line. Priority levels 2 to 7 are guaranteed the minimum bus bandwidth Figure 4-1. DMA Timing Diagram ADDRESS Phase DATA Phase ADDRESS Phase DATA Phase CLK CLK ADDR 16/32 A B ADDR 16/32 A B WRITE WRITE DATA DATA (A) DATA DATA (A) READY READY Basic DMA Read Transfer without wait states Basic DMA Write Transfer without wait states 4.4.4.2 Auto Repeat DMA data previously received in the other buffer. In its simplest form, this is done by chaining two TDs together so that each TD calls Auto repeat DMA is typically used when a static pattern is the opposite TD when complete. repetitively read from system memory and written to a peripheral. This is done with a single TD that chains to itself. 4.4.4.4 Circular DMA 4.4.4.3 Ping Pong DMA Circular DMA is similar to ping pong DMA except it contains more than two buffers. In this case there are multiple TDs; after the last A ping pong DMA case uses double buffering to allow one buffer TD is complete it chains back to the first TD. to be filled by one client while another client is consuming the Document Number: 001-56955 Rev. *K Page 17 of 120

® PSoC 3: CY8C32 Family Data Sheet 4.4.4.5 Scatter Gather DMA 4.5 Interrupt Controller In the case of scatter gather DMA, there are multiple The interrupt controller provides a mechanism for hardware noncontiguous sources or destinations that are required to resources to change program execution to a new address, effectively carry out an overall DMA transaction. For example, a independent of the current task being executed by the main packet may need to be transmitted off of the device and the code. The interrupt controller provides enhanced features not packet elements, including the header, payload, and trailer, exist found on original 8051 interrupt controllers: in various noncontiguous locations in memory. Scatter gather DMA allows the segments to be concatenated together by using (cid:132)Thirty two interrupt vectors multiple TDs in a chain. The chain gathers the data from the (cid:132)Jumps directly to ISR anywhere in code space with dynamic multiple locations. A similar concept applies for the reception of vector addresses data onto the device. Certain parts of the received data may need to be scattered to various locations in memory for software (cid:132)Multiple sources for each vector processing convenience. Each TD in the chain specifies the (cid:132)Flexible interrupt to vector matching location for each discrete element in the chain. (cid:132)Each interrupt vector is independently enabled or disabled 4.4.4.6 Packet Queuing DMA Packet queuing DMA is similar to scatter gather DMA but (cid:132)Each interrupt can be dynamically assigned one of eight specifically refers to packet protocols. With these protocols, priorities there may be separate configuration, data, and status phases (cid:132)Eight level nestable interrupts associated with sending or receiving a packet. (cid:132)Multiple I/O interrupt vectors For instance, to transmit a packet, a memory mapped configuration register can be written inside a peripheral, (cid:132)Software can send interrupts specifying the overall length of the ensuing data phase. The CPU can set up this configuration information anywhere in system (cid:132)Software can clear pending interrupts memory and copy it with a simple TD to the peripheral. After the When an interrupt is pending, the current instruction is configuration phase, a data phase TD (or a series of data phase completed and the program counter is pushed onto the stack. TDs) can begin (potentially using scatter gather). When the data Code execution then jumps to the program address provided by phase TD(s) finish, a status phase TD can be invoked that reads the vector. After the ISR is completed, a RETI instruction is some memory mapped status information from the peripheral executed and returns execution to the instruction following the and copies it to a location in system memory specified by the previously interrupted instruction. To do this the RETI instruction CPU for later inspection. Multiple sets of configuration, data, and pops the program counter from the stack. status phase “subchains” can be strung together to create larger If the same priority level is assigned to two or more interrupts, chains that transmit multiple packets in this way. A similar the interrupt with the lower vector number is executed first. Each concept exists in the opposite direction to receive the packets. interrupt vector may choose from three interrupt sources: Fixed 4.4.4.7 Nested DMA Function, DMA, and UDB. The fixed function interrupts are direct connections to the most common interrupt sources and provide One TD may modify another TD, as the TD configuration space the lowest resource cost connection. The DMA interrupt sources is memory mapped similar to any other peripheral. For example, provide direct connections to the two DMA interrupt sources a first TD loads a second TD’s configuration and then calls the provided per DMA channel. The third interrupt source for vectors second TD. The second TD moves data as required by the is from the UDB digital routing array. This allows any digital signal application. When complete, the second TD calls the first TD, available to the UDB array to be used as an interrupt source. which again updates the second TD’s configuration. This Fixed function interrupts and all interrupt sources may be routed process repeats as often as necessary. to any interrupt vector using the UDB interrupt source connections. Figure 4-2 on page 19 represents typical flow of events when an interrupt triggered. Figure 4-3 on page 20 shows the interrupt structure and priority polling. Document Number: 001-56955 Rev. *K Page 18 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 4-2. Interrupt Processing Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 S CLK Arrival of new Interrupt INT_INPUT S Pend bit is set on next system clock active edge POST and PEND bits cleared after IRQ is sleared PEND S Interrupt is posted to ascertain the priority POST S IRQ cleared after receiving IRA Interrupt request sent to core for processing IRQ S S ACTIVE_INT_(N#U10M) NA 0x0010 numbTerh eis apcotsivtee din ttoe rcrourpet S 0x0000 S The active interrupt ISR INT_VECT_ADDR NA address is posted to core NA S IRA S IRC S Int. State Interrupt generation and posting to CPU CPU Response Clear Completing current instruction and branching to vector address Complete ISR and return TIME Notes 1: Interrupt triggered asynchronous to the clock 2: The PEND bit is set on next active clock edge to indicate the interrupt arrival 3: POST bit is set following the PEND bit 4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks) 5: ISR address is posted to CPU core for branching 6: CPU acknowledges the interrupt request 7: ISR address is read by CPU for branching 8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core 10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles) 11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status The total interrupt latency (ISR execution) = POST + PEND + IRQ + IRA + Completing current instruction and branching = 1+1+1+2+7 cycles = 12 cycles Document Number: 001-56955 Rev. *K Page 19 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 4-3. Interrupt Structure Interrupts form Fixed Interrupt Polling logic function blocks, DMA and UDBs Highest Priority Interrupt Enable/ Disable, PEND and Interrupts 0 to 30 POST logic from UDBs 0 Interrupts 0 to 30 from Fixed 1 Function Blocks IRQ 0 to 30 ACTIVE_INT_NUM Individual Enable Disable P I3n0te frrroumpt sD 0M tAo rtooIus nsottieenulrgerrc culeotp sg3t i1c bits Interrupt 2 ind8Ptef eorLcirroeor uravdiplteely tlr s olling se [15:0] INT_VECT_ADDR to 29 quen c e IRA IRC 30 Global Enable Lowest Priority disable bit Document Number: 001-56955 Rev. *K Page 20 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 4-8. Interrupt Vector Table # Fixed Function DMA UDB 0 LVD phub_termout0[0] udb_intr[0] 1 ECC phub_termout0[1] udb_intr[1] 2 Reserved phub_termout0[2] udb_intr[2] 3 Sleep (Pwr Mgr) phub_termout0[3] udb_intr[3] 4 PICU[0] phub_termout0[4] udb_intr[4] 5 PICU[1] phub_termout0[5] udb_intr[5] 6 PICU[2] phub_termout0[6] udb_intr[6] 7 PICU[3] phub_termout0[7] udb_intr[7] 8 PICU[4] phub_termout0[8] udb_intr[8] 9 PICU[5] phub_termout0[9] udb_intr[9] 10 PICU[6] phub_termout0[10] udb_intr[10] 11 PICU[12] phub_termout0[11] udb_intr[11] 12 PICU[15] phub_termout0[12] udb_intr[12] 13 Comparators phub_termout0[13] udb_intr[13] Combined 14 Reserved phub_termout0[14] udb_intr[14] 15 I2C phub_termout0[15] udb_intr[15] 16 Reserved phub_termout1[0] udb_intr[16] 17 Timer/Counter0 phub_termout1[1] udb_intr[17] 18 Timer/Counter1 phub_termout1[2] udb_intr[18] 19 Timer/Counter2 phub_termout1[3] udb_intr[19] 20 Timer/Counter3 phub_termout1[4] udb_intr[20] 21 USB SOF Int phub_termout1[5] udb_intr[21] 22 USB Arb Int phub_termout1[6] udb_intr[22] 23 USB Bus Int phub_termout1[7] udb_intr[23] 24 USB Endpoint[0] phub_termout1[8] udb_intr[24] 25 USB Endpoint Data phub_termout1[9] udb_intr[25] 26 Reserved phub_termout1[10] udb_intr[26] 27 LCD phub_termout1[11] udb_intr[27] 28 Reserved phub_termout1[12] udb_intr[28] 29 Decimator Int phub_termout1[13] udb_intr[29] 30 PHUB Error Int phub_termout1[14] udb_intr[30] 31 EEPROM Fault Int phub_termout1[15] udb_intr[31] Document Number: 001-56955 Rev. *K Page 21 of 120

® PSoC 3: CY8C32 Family Data Sheet 5. Memory security is needed in your application. The PSoC device also offers an advanced security feature called Device Security which 5.1 Static RAM permanently disables all test, programming, and debug ports, protecting your application from external access (see the CY8C32 Static RAM (SRAM) is used for temporary data storage. “Device Security” section on page62). For more information Up to 8 KB of SRAM is provided and can be accessed by the about how to take full advantage of the security features in 8051 or the DMA controller. See Memory Map on page 24. PSoC, see the PSoC 3 TRM. Simultaneous access of SRAM by the 8051 and the DMA controller is possible if different 4-KB blocks are accessed. Table 5-1. Flash Protection 5.2 Flash Program Memory Protection Allowed Not Allowed Setting Flash memory in PSoC devices provides nonvolatile storage for Unprotected External read and write – user firmware, user configuration data, bulk data storage, and + internal read and write optional ECC data. The main flash memory area contains up to 64 KB of user program space. Factory External write + internal External read Up to an additional 8 KB of flash space is available for Error Upgrade read and write Correcting Codes (ECC). If ECC is not used this space can store Field Upgrade Internal read and write External read and device configuration data and bulk user data. User code may not write be run out of the ECC flash memory section. ECC can correct one bit error and detect two bit errors per 8 bytes of firmware Full Protection Internal read External read and memory; an interrupt can be generated when an error is write + internal write detected. Disclaimer Flash is read in units of rows; each row is 9 bytes wide with 8 Note the following details of the flash code protection features on bytes of data and 1 byte of ECC data. When a row is read, the Cypress devices. data bytes are copied into an 8-byte instruction buffer. The CPU Cypress products meet the specifications contained in their fetches its instructions from this buffer, for improved CPU particular Cypress datasheets. Cypress believes that its family of performance. products is one of the most secure families of its kind on the Flash programming is performed through a special interface and market today, regardless of how they are used. There may be preempts code execution out of flash. The flash programming methods, unknown to Cypress, that can breach the code interface performs flash erasing, programming and setting code protection features. Any of these methods, to our knowledge, protection levels. Flash in-system serial programming (ISSP), would be dishonest and possibly illegal. Neither Cypress nor any typically used for production programming, is possible through other semiconductor manufacturer can guarantee the security of both the SWD and JTAG interfaces. In-system programming, their code. Code protection does not mean that we are typically used for bootloaders, is also possible using serial guaranteeing the product as “unbreakable.” interfaces such as I2C, USB, UART, and SPI, or any Cypress is willing to work with the customer who is concerned communications protocol. about the integrity of their code. Code protection is constantly 5.3 Flash Security evolving. We at Cypress are committed to continuously improving the code protection features of our products. All PSoC devices include a flexible flash-protection model that prevents access and visibility to on-chip flash memory. This 5.4 EEPROM prevents duplication or reverse engineering of proprietary code. PSoC EEPROM memory is a byte-addressable nonvolatile Flash memory is organized in blocks, where each block contains memory. The CY8C32 has up to 2 KB of EEPROM memory to 256 bytes of program or data and 32 bytes of ECC or store user data. Reads from EEPROM are random access at the configuration data. A total of up to 256 blocks is provided on byte level. Reads are done directly; writes are done by sending 64-KB flash devices. write commands to an EEPROM programming interface. CPU The device offers the ability to assign one of four protection code execution can continue from flash during EEPROM writes. levels to each row of flash. Table5-1 lists the protection modes EEPROM is erasable and writeable at the row level. The available. Flash protection levels can only be changed by EEPROM is divided into 128 rows of 16 bytes each. performing a complete flash erase. The Full Protection and Field The CPU can not execute out of EEPROM. There is no ECC Upgrade settings disable external access (through a debugging hardware associated with EEPROM. If ECC is required it must tool such as PSoC Creator, for example). If your application be handled in firmware. requires code update through a boot loader, then use the Field Upgrade setting. Use the Unprotected setting only when no Document Number: 001-56955 Rev. *K Page 22 of 120

® PSoC 3: CY8C32 Family Data Sheet 5.5 Nonvolatile Latches (NVLs) PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown in Table5-2. Table 5-2. Device Configuration NVL Register Map Register Address 7 6 5 4 3 2 1 0 0x00 PRT3RDM[1:0] PRT2RDM[1:0] PRT1RDM[1:0] PRT0RDM[1:0] 0x01 PRT12RDM[1:0] PRT6RDM[1:0] PRT5RDM[1:0] PRT4RDM[1:0] 0x02 XRESMEN PRT15RDM[1:0] 0x03 DIG_PHS_DLY[3:0] ECCEN DPS[1:0] The details for individual fields and their factory default settings are shown in Table5-3:. Table 5-3. Fields and Factory Default Settings Field Description Settings PRTxRDM[1:0] Controls reset drive mode of the corresponding IO port. 00b (default) - high impedance analog See “Reset Configuration” on page40. All pins of the port 01b - high impedance digital are set to the same mode. 10b - resistive pull up 11b - resistive pull down XRESMEN Controls whether pin P1[2] is used as a GPIO or as an 0 (default for 68-pin and 100-pin parts) - GPIO external reset. See “Pin Descriptions” on page10, XRES 1 (default for 48-pin parts) - external reset description. DPS{1:0] Controls the usage of various P1 pins as a debug port. 00b - 5-wire JTAG See “Programming, Debug Interfaces, Resources” on 01b (default) - 4-wire JTAG page59. 10b - SWD 11b - debug ports disabled ECCEN Controls whether ECC flash is used for ECC or for general 0 (default) - ECC disabled configuration and data storage. See “Flash Program 1 - ECC enabled Memory” on page22. DIG_PHS_DLY[3:0] Selects the digital clock phase delay. See the TRM for details. Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase / write cycles is limited – see “Nonvolatile Latches (NVL))” on page97. Document Number: 001-56955 Rev. *K Page 23 of 120

® PSoC 3: CY8C32 Family Data Sheet 5.6 External Memory Interface Figure5-1 is the EMIF block diagram. The EMIF supports synchronous and asynchronous memories. The CY8C32 CY8C32 provides an external memory interface (EMIF) for supports only one type of external memory device at a time. connecting to external memory devices. The connection allows read and write accesses to external memories. The EMIF External memory can be accessed via the 8051 xdata space; up operates in conjunction with UDBs, I/O ports, and other to 24 address bits can be used. See “xdata Space” section on hardware to generate external memory address and control page26. The memory can be 8 or 16 bits wide. signals. At 33 MHz, each memory access cycle takes four bus clock cycles. Figure 5-1. EMIF Block Diagram Address Signals IO External_MEM_ADDR[23:0] PORTs Data, Address, and Control Signals IO IF Data Signals IO External_MEM_DATA[15:0] PORTs Control Signals IO Control PHUB PORTs Data, Address, DSI Dynamic Output and Control Control Signals UDB DSI to Port Other EM Control Control Data, Signals Signals Address, and Control Signals EMIF 5.7 Memory Map 5.7.2 Internal Data Space The CY8C32 8051 memory map is very similar to the MCS-51 The CY8C32 8051 internal data space is 384 bytes, compressed memory map. within a 256-byte space. This space consists of 256 bytes of RAM (in addition to the SRAM mentioned in Static RAM on page 5.7.1 Code Space 22) and a 128-byte space for Special Function Registers (SFRs). The CY8C32 8051 code space is 64 KB. Only main flash exists See Figure5-2. The lowest 32 bytes are used for 4 banks of registers R0-R7. The next 16 bytes are bit-addressable. in this space. See the “Flash Program Memory” section on page22. Document Number: 001-56955 Rev. *K Page 24 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 5-2. 8051 Internal Data Space In addition to the register or bit address modes used with the lower 48 bytes, the lower 128 bytes can be accessed with direct 0x00 or indirect addressing. With direct addressing mode, the upper 4 Banks, R0-R7 Each 0x1F 128 bytes map to the SFRs. With indirect addressing mode, the upper 128 bytes map to RAM. Stack operations use indirect 0x20 Bit-Addressable Area addressing; the 8051 stack space is 256 bytes. See the 0x2F “Addressing Modes” section on page11 0x30 Lower Core RAM Shared with Stack Space (direct and indirect addressing) 0x7F 0x80 Upper Core RAM Shared SFR with Stack Space Special Function Registers (indirect addressing) (direct addressing) 0xFF 5.7.3 SFRs The special function register (SFR) space provides access to frequently accessed registers. The memory map for the SFR memory space is shown in Table5-4. Table 5-4. SFR Map Address 0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F 0×F8 SFRPRT15DR SFRPRT15PS SFRPRT15SEL – – – – – 0×F0 B – SFRPRT12SEL – – – – – 0×E8 SFRPRT12DR SFRPRT12PS MXAX – – – – – 0×E0 ACC – – – – – – – 0×D8 SFRPRT6DR SFRPRT6PS SFRPRT6SEL – – – – – 0×D0 PSW – – – – – – – 0×C8 SFRPRT5DR SFRPRT5PS SFRPRT5SEL – – – – – 0×C0 SFRPRT4DR SFRPRT4PS SFRPRT4SEL – – – – – 0×B8 – – – – – – – – 0×B0 SFRPRT3DR SFRPRT3PS SFRPRT3SEL – – – – – 0×A8 IE – – – – – – – 0×A0 P2AX – SFRPRT1SEL – – – – – 0×98 SFRPRT2DR SFRPRT2PS SFRPRT2SEL – – – – – 0×90 SFRPRT1DR SFRPRT1PS – DPX0 DPX1 – – 0×88 – SFRPRT0PS SFRPRT0SEL – – – – – 0×80 SFRPRT0DR SP DPL0 DPH0 DPL1 DPH1 DPS – The CY8C32 family provides the standard set of registers found (cid:132)JMP @A+DPTR on industry standard 8051 devices. In addition, the CY8C32 (cid:132)INC DPTR devices add SFRs to provide direct access to the I/O ports on the (cid:132)MOV DPTR, #data16 device. The following sections describe the SFRs added to the CY8C32 family. The extended data pointer SFRs, DPX0, DPX1, MXAX, and P2AX, hold the most significant parts of memory addresses XData Space Access SFRs during access to the xdata space. These SFRs are used only The 8051 core features dual DPTR registers for faster data with the MOVX instructions. transfer operations. The data pointer select SFR, DPS, selects During a MOVX instruction using the DPTR0/DPTR1 register, which data pointer register, DPTR0 or DPTR1, is used for the the most significant byte of the address is always equal to the following instructions: contents of DPX0/DPX1. (cid:132)MOVX @DPTR, A During a MOVX instruction using the R0 or R1 register, the most (cid:132)MOVX A, @DPTR significant byte of the address is always equal to the contents of MXAX, and the next most significant byte is always equal to the (cid:132)MOVC A, @A+DPTR contents of P2AX. Document Number: 001-56955 Rev. *K Page 25 of 120

® PSoC 3: CY8C32 Family Data Sheet I/O Port SFRs Table 5-5. XDATA Data Address Map (continued) The I/O ports provide digital input sensing, output drive, pin Address Range Purpose interrupts, connectivity for analog inputs and outputs, LCD, and 0×01 0000 – 0×01 FFFF Digital Interconnect configuration access to peripherals through the DSI. Full information on I/O ports is found in I/O System and Routing on page 34. 0×05 0220 – 0×05 02F0 Debug controller I/O ports are linked to the CPU through the PHUB and are also 0×08 0000 – 0×08 1FFF Flash ECC bytes available in the SFRs. Using the SFRs allows faster access to a 0×80 0000 – 0×FF FFFF External Memory Interface limited set of I/O port registers, while using the PHUB allows boot configuration and access to all I/O port registers. Each SFR supported I/O port provides three SFRs: 6. System Integration (cid:132)SFRPRTxDR sets the output data state of the port (where x is port number and includes ports 0 – 6, 12 and 15). 6.1 Clocking System (cid:132)The SFRPRTxSEL selects whether the PHUB PRTxDR The clocking system generates, divides, and distributes clocks register or the SFRPRTxDR controls each pin’s output buffer throughout the PSoC system. For the majority of systems, no within the port. If a SFRPRTxSEL[y] bit is high, the external crystal is required. The IMO and PLL together can corresponding SFRPRTxDR[y] bit sets the output state for that generate up to a 50 MHz clock, accurate to ±1 percent over pin. If a SFRPRTxSEL[y] bit is low, the corresponding voltage and temperature. Additional internal and external clock PRTxDR[y] bit sets the output state of the pin (where y varies sources allow each design to optimize accuracy, power, and from 0 to 7). cost. All of the system clock sources can be used to generate other clock frequencies in the 16-bit clock dividers and UDBs for (cid:132)The SFRPRTxPS is a read only register that contains pin state anything the user wants, for example a UART baud rate values of the port pins. generator. 5.7.3.1 xdata Space Clock generation and distribution is automatically configured through the PSoC Creator IDE graphical interface. This is based The 8051 xdata space is 24-bit, or 16 MB in size. The majority of on the complete system’s requirements. It greatly speeds the this space is not “external”—it is used by on-chip components. design process. PSoC Creator allows you to build clocking See Table5-5. External, that is, off-chip, memory can be systems with minimal input. You can specify desired clock accessed using the EMIF. See External Memory Interface on frequencies and accuracies, and the software locates or builds a page 24. clock that meets the required specifications. This is possible Table 5-5. XDATA Data Address Map because of the programmability inherent PSoC. Address Range Purpose Key features of the clocking system include: 0×00 0000 – 0×00 1FFF SRAM (cid:132)Seven general purpose clock sources 0×00 4000 – 0×00 42FF Clocking, PLLs, and oscillators (cid:135)3- to 24-MHz IMO, ±1 percent at 3 MHz 0×00 4300 – 0×00 43FF Power management (cid:135)4- to 25-MHz external crystal oscillator (MHzECO) 0×00 4400 – 0×00 44FF Interrupt controller (cid:135)Clock doubler provides a doubled clock frequency output for the USB block, see USB Clock Domain on page 29 0×00 4500 – 0×00 45FF Ports interrupt control (cid:135)DSI signal from an external I/O pin or other logic 0×00 4700 – 0×00 47FF Flash programming interface (cid:135)24- to 50- MHz fractional PLL sourced from IMO, MHzECO, or DSI 0×00 4900 – 0×00 49FF I2C controller (cid:135)1-kHz, 33-kHz, 100-kHz ILO for watchdog timer (WDT) and 0×00 4E00 – 0×00 4EFF Decimator sleep timer 0×00 4F00 – 0×00 4FFF Fixed timer/counter/PWMs (cid:135)32.768-kHz external crystal oscillator (kHzECO) for RTC (cid:132)IMO has a USB mode that auto locks to the USB bus clock 0×00 5000 – 0×00 51FF I/O ports control requiring no external crystal for USB. (USB equipped parts only) 0×00 5400 – 0×00 54FF External Memory Interface (EMIF) (cid:132)Independently sourced clock in all clock dividers control registers (cid:132)Eight 16-bit clock dividers for the digital system 0×00 5800 – 0×00 5FFF Analog Subsystem interface (cid:132)Four 16-bit clock dividers for the analog system 0×00 6000 – 0×00 60FF USB controller (cid:132)Dedicated 16-bit divider for the bus clock 0×00 6400 – 0×00 6FFF UDB configuration (cid:132)Dedicated 4-bit divider for the CPU clock 0×00 7000 – 0×00 7FFF PHUB configuration (cid:132)Automatic clock configuration in PSoC Creator 0×00 8000 – 0×00 8FFF EEPROM Document Number: 001-56955 Rev. *K Page 26 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 6-1. Oscillator Summary Source Fmin Tolerance at Fmin Fmax Tolerance at Fmax Startup Time IMO 3 MHz ±1% over voltage and temperature 24 MHz ±4% 10 µs max MHzECO 4 MHz Crystal dependent 25 MHz Crystal dependent 5 ms typ, max is crystal dependent DSI 0 MHz Input dependent 50 MHz Input dependent Input dependent PLL 24 MHz Input dependent 50 MHz Input dependent 250 µs max Doubler 48 MHz Input dependent 48 MHz Input dependent 1 µs max ILO 1 kHz –50%, +100% 100 kHz –55%, +100% 15 ms max in lowest power mode kHzECO 32 kHz Crystal dependent 32 kHz Crystal dependent 500 ms typ, max is crystal dependent Figure 6-1. Clocking Subsystem External IO 3-24 MHz 4-25 MHz 1,33,100 kHz or DSI 32 kHz ECO IMO ECO ILO 0-50 MHz CPU Clock CPU Clock Divider 4 bit 48 MHz 24-50 MHz System Doubler for PLL Clock Mux USB Bus Clock Bus Clock Divider 16 bit s Digital Clock Digital Clock Analog Clock k Divider 16 bit Divider 16 bit Divider 16 bit e w s Digital Clock Digital Clock Analog Clock k Divider 16 bit Divider 16 bit Divider 16 bit e w 7 7 s Digital Clock Digital Clock Analog Clock k Divider 16 bit Divider 16 bit Divider 16 bit e w s Digital Clock Digital Clock Analog Clock k Divider 16 bit Divider 16 bit Divider 16 bit e w 6.1.1 Internal Oscillators 6.1.1.2 Clock Doubler 6.1.1.1 Internal Main Oscillator The clock doubler outputs a clock at twice the frequency of the input clock. The doubler works at input frequency of 24 MHz, In most designs the IMO is the only clock source required, due providing 48 MHz for the USB. It can be configured to use a clock to its ±1-percent accuracy. The IMO operates with no external from the IMO, MHzECO, or the DSI (external pin). components and outputs a stable clock. A factory trim for each frequency range is stored in the device. With the factory trim, 6.1.1.3 Phase-locked Loop tolerance varies from ±1 percent at 3 MHz, up to ±4-percent at The PLL allows low-frequency, high-accuracy clocks to be 24 MHz. The IMO, in conjunction with the PLL, allows generation multiplied to higher frequencies. This is a tradeoff between of CPU and system clocks up to the device's maximum higher clock frequency and accuracy and, higher power frequency (see Phase-locked Loop) consumption and increased startup time. The IMO provides clock outputs at 3, 6, 12, and 24 MHz. The PLL block provides a mechanism for generating clock frequencies based upon a variety of input sources. The PLL Document Number: 001-56955 Rev. *K Page 27 of 120

® PSoC 3: CY8C32 Family Data Sheet outputs clock frequencies in the range of 24 to 50 MHz. Its input Figure 6-2. MHzECO Block Diagram and feedback dividers supply 4032 discrete ratios to create almost any desired system clock frequency. The accuracy of the PLL output depends on the accuracy of the PLL input source. XCLK_MHZ The most common PLL use is to multiply the IMO clock at 3 MHz, 4 - 25 MHz where it is most accurate to generate the CPU and system clocks Crystal Osc up to the device’s maximum frequency. The PLL achieves phase lock within 250 µs (verified by bit setting). It can be configured to use a clock from the IMO, MHzECO or DSI (external pin). The PLL clock source can be used until lock is complete and signaled with a lock bit. The lock signal can be routed through the DSI to generate an interrupt. Xi Xo (Pin P15[1]) (Pin P15[0]) Disable the PLL before entering low-power modes. 6.1.1.4 Internal Low-Speed Oscillator 4 – 25 MHz External crystal The ILO provides clock frequencies for low-power consumption, Components including the watchdog timer, and sleep timer. The ILO Capacitors generates up to three different clocks: 1 kHz, 33 kHz, and 100kHz. The 1 kHz clock (CLK1K) is typically used for a background ‘heartbeat’ timer. This clock inherently lends itself to low-power 6.1.2.2 32.768-kHz ECO supervisory operations such as the watchdog timer and long sleep intervals using the central timewheel (CTW). The 32.768-kHz External Crystal Oscillator (32kHzECO) provides precision timing with minimal power consumption using The central timewheel is a 1 kHz, free running, 13-bit counter an external 32.768-kHz watch crystal (see Figure6-3). The clocked by the ILO. The central timewheel is always enabled, 32kHzECO also connects directly to the sleep timer and provides except in hibernate mode and when the CPU is stopped during the source for the RTC. The RTC uses a 1-second interrupt to debug on chip mode. It can be used to generate periodic implement the RTC functionality in firmware. interrupts for timing purposes or to wake the system from a low-power mode. Firmware can reset the central timewheel. The oscillator works in two distinct power modes. This allows Systems that require accurate timing should use the RTC users to trade off power consumption with noise immunity from capability instead of the central timewheel. neighboring circuits. The GPIO pins connected to the external crystal and capacitors are fixed. The 100-kHz clock (CLK100K) works as a low-power system clock to run the CPU. It can also generate time intervals such as Figure 6-3. 32kHzECO Block Diagram fast sleep intervals using the fast timewheel. The fast timewheel is a 100-kHz, 5-bit counter clocked by the ILO that can also be used to wake the system. The fast timewheel XCLK32K 32 kHz settings are programmable, and the counter automatically resets Crystal Osc when the terminal count is reached. This enables flexible, periodic wakeups of the CPU at a higher rate than is allowed using the central timewheel. The fast timewheel can generate an optional interrupt each time the terminal count is reached. The 33-kHz clock (CLK33K) comes from a divide-by-3 operation on CLK100K. This output can be used as a reduced accuracy Xi Xo version of the 32.768-kHz ECO clock with no need for a crystal. (Pin P15[3]) (Pin P15[2]) 6.1.2 External Oscillators 32 kHz External crystal 6.1.2.1 MHz External Crystal Oscillator Components Capacitors The MHzECO provides high frequency, high precision clocking using an external crystal (see Figure6-2). It supports a wide variety of crystal types, in the range of 4 to 25 MHz. When used in conjunction with the PLL, it can generate CPU and system clocks up to the device's maximum frequency (see 6.1.2.3 Digital System Interconnect “Phase-locked Loop” section on page27). The GPIO pins The DSI provides routing for clocks taken from external clock connecting to the external crystal and capacitors are fixed. oscillators connected to I/O. The oscillators can also be MHzECO accuracy depends on the crystal chosen. generated within the device in the digital system and Universal Digital Blocks. While the primary DSI clock input provides access to all clocking resources, up to eight other DSI clocks (internally or externally generated) may be routed directly to the eight digital clock Document Number: 001-56955 Rev. *K Page 28 of 120

® PSoC 3: CY8C32 Family Data Sheet dividers. This is only possible if there are multiple precision clock Each clock divider consists of an 8-input multiplexer, a 16-bit sources. clock divider (divide by 2 and higher) that generates ~50 percent duty cycle clocks, system clock resynchronization logic, and 6.1.3 Clock Distribution deglitch logic. The outputs from each digital clock tree can be All seven clock sources are inputs to the central clock distribution routed into the digital system interconnect and then brought back system. The distribution system is designed to create multiple into the clock system as an input, allowing clock chaining of up high precision clocks. These clocks are customized for the to 32 bits. design’s requirements and eliminate the common problems 6.1.4 USB Clock Domain found with limited resolution prescalers attached to peripherals. The clock distribution system generates several types of clock The USB clock domain is unique in that it operates largely trees. asynchronously from the main clock network. The USB logic contains a synchronous bus interface to the chip, while running (cid:132)The system clock is used to select and supply the fastest clock on an asynchronous clock to process USB data. The USB logic in the system for general system clock requirements and clock requires a 48 MHz frequency. This frequency can be generated synchronization of the PSoC device. from different sources, including DSI clock at 48 MHz or doubled (cid:132)Bus Clock 16-bit divider uses the system clock to generate the value of 24 MHz from internal oscillator, DSI signal, or crystal system's bus clock used for data transfers. Bus clock is the oscillator. source clock for the CPU clock divider. 6.2 Power System (cid:132)Eight fully programmable 16-bit clock dividers generate digital The power system consists of separate analog, digital, and I/O system clocks for general use in the digital system, as supply pins, labeled Vdda, Vddd, and Vddiox, respectively. It configured by the design’s requirements. Digital system clocks also includes two internal 1.8V regulators that provide the digital can generate custom clocks derived from any of the seven (Vccd) and analog (Vcca) supplies for the internal core logic. The clock sources for any purpose. Examples include baud rate output pins of the regulators (Vccd and Vcca) and the Vddio pins generators, accurate PWM periods, and timer clocks, and must have capacitors connected as shown in Figure6-4. The many others. If more than eight digital clock dividers are two Vccd pins must be shorted together, with as short a trace as required, the Universal Digital Blocks (UDBs) and fixed function possible, and connected to a 1-µF ±10-percent X5R capacitor. Timer/Counter/PWMs can also generate clocks. The power system also contains a sleep regulator, an I2C (cid:132)Four 16-bit clock dividers generate clocks for the analog system regulator, and a hibernate regulator. components that require clocking, such as ADC. The analog clock dividers include skew control to ensure that critical analog events do not occur simultaneously with digital switching events. This is done to reduce analog system noise. Document Number: 001-56955 Rev. *K Page 29 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 6-4. PSoC Power System Vddio2 1µF Vddd Vddio0 0.1µF 0.1µF dio2 I/O Supply Vccd Vssd Vddd I/O Supply Vddio0 Vd 0.1µF I2C Regulator Sleep Regulator Digital Domain Vdda Vdda Analog Vcca Digital 0.1µF Vssb Regulator Regulators 1µF . Vssa Analog Domain Hibernate Regulator 1 3 o o Vddi I/O Supply Vccd Vssd Vddd I/O Supply Vddi 0.1µF 0.1µF 0.1µF Vddio1 Vddd Vddio3 Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure2-6. Document Number: 001-56955 Rev. *K Page 30 of 120

® PSoC 3: CY8C32 Family Data Sheet 6.2.1 Power Modes Active is the main processing mode. Its functionality is configurable. Each power controllable subsystem is enabled or PSoC 3 devices have four different power modes, as shown in disabled by using separate power configuration template Table6-2 and Table6-3. The power modes allow a design to registers. In alternate active mode, fewer subsystems are easily provide required functionality and processing power while enabled, reducing power. In sleep mode most resources are simultaneously minimizing power consumption and maximizing disabled regardless of the template settings. Sleep mode is battery life in low-power and portable devices. optimized to provide timed sleep intervals and RTC functionality. PSoC 3 power modes, in order of decreasing power The lowest power mode is hibernate, which retains register and consumption are: SRAM state, but no clocks, and allows wakeup only from I/O pins. Figure6-5 illustrates the allowable transitions between (cid:132)Active power modes. (cid:132)Alternate Active (cid:132)Sleep (cid:132)Hibernate Table 6-2. Power Modes Power Modes Description Entry Condition Wakeup Source Active Clocks Regulator Active Primary mode of operation, all Wakeup, reset, Any interrupt Any All regulators available. peripherals available (program- manual register (programmable) Digital and analog mable) entry regulators can be disabled if external regulation used. Alternate Similar to Active mode, and is Manual register Any interrupt Any All regulators available. Active typically configured to have entry (programmable) Digital and analog fewer peripherals active to regulators can be disabled reduce power. One possible if external regulation used. configuration is to use the UDBs for processing, with the CPU turned off Sleep All subsystems automatically Manual register Comparator, ILO/kHzECO Both digital and analog disabled entry PICU, I2C, RTC, regulators buzzed. CTW, LVD Digital and analog regulators can be disabled if external regulation used. Hibernate All subsystems automatically Manual register PICU Only hibernate regulator disabled entry active. Lowest power consuming mode with all peripherals and internal regulators disabled, except hibernate regulator is enabled Configuration and memory contents retained Table 6-3. Power Modes Wakeup Time and Power Consumption Sleep Wakeup Current Code Digital Analog Clock Sources Reset Wakeup Sources Modes Time (typ) Execution Resources Resources Available Sources Active – 1.2 mA[12] Yes All All All – All Alternate – – User All All All – All Active defined <15 µs 1 µA No I2C Comparator ILO/kHzECO Comparator, XRES, LVD, Sleep PICU, I2C, RTC, WDR CTW, LVD Hibernate <100 µs 200 nA No None None None PICU XRES Note 12.Bus clock off. Execute from CPU instruction buffer at 6 MHz. See Table 11-2 on page 65. Document Number: 001-56955 Rev. *K Page 31 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 6-5. Power Mode Transitions 6.2.1.5 Wakeup Events Wakeup events are configurable and can come from an interrupt Active or device reset. A wakeup event restores the system to active mode. Firmware enabled interrupt sources include internally generated interrupts, power supervisor, central timewheel, and I/O interrupts. Internal interrupt sources can come from a variety of peripherals, such as analog comparators and UDBs. The Manual central timewheel provides periodic interrupts to allow the Sleep Hibernate system to wake up, poll peripherals, or perform real-time functions. Reset event sources include the external reset I/O pin (XRES), WDT, and Precision Reset (PRES). Buzz 6.2.2 Boost Converter Applications that use a supply voltage of less than 1.71V, such Alternate as solar or single cell battery supplies, may use the on-chip boost Active converter. The boost converter may also be used in any system that requires a higher operating voltage than the supply provides. For instance, this includes driving 5.0 V LCD glass in a 3.3V 6.2.1.1 Active Mode system. The boost converter accepts an input voltage as low as Active mode is the primary operating mode of the device. When 0.5V. With one low cost inductor it produces a selectable output in active mode, the active configuration template bits control voltage sourcing enough current to operate the PSoC and other which available resources are enabled or disabled. When a on-board components. resource is disabled, the digital clocks are gated, analog bias The boost converter accepts an input voltage from 0.5V to 5.5V currents are disabled, and leakage currents are reduced as (V ), and can start up with V as low as 0.5V. The converter BAT BAT appropriate. User firmware can dynamically control subsystem provides a user configurable output voltage of 1.8 to 5.0 V power by setting and clearing bits in the active configuration (V ). V is typically less than V ; if V is greater BOOST BAT BOOST BAT template. The CPU can disable itself, in which case the CPU is than or equal to V , then V will be the same as V . BOOST BOOST BAT automatically reenabled at the next wakeup event. The block can deliver up to 50 mA (I ) depending on BOOST When a wakeup event occurs, the global mode is always configuration. returned to active, and the CPU is automatically enabled, Four pins are associated with the boost converter: V , V , BAT SSB regardless of its template settings. Active mode is the default V , and Ind. The boosted output voltage is sensed at the BOOST global power mode upon boot. V pin and must be connected directly to the chip’s supply BOOST inputs. An inductor is connected between the V and Ind pins. 6.2.1.2 Alternate Active Mode BAT You can optimize the inductor value to increase the boost Alternate Active mode is very similar to Active mode. In alternate converter efficiency based on input voltage, output voltage, active mode, fewer subsystems are enabled, to reduce power current and switching frequency. The External Schottky diode consumption. One possible configuration is to turn off the CPU shown in Figure6-6 is required only in cases when and flash, and run peripherals at full speed. V >3.6V. BOOST 6.2.1.3 Sleep Mode Figure 6-6. Application for Boost Converter Sleep mode reduces power consumption when a resume time of 15 µs is acceptable. The wake time is used to ensure that the regulator outputs are stable enough to directly enter active Vboost VddaVdddVddio mode. Optional Schottky Diode 6.2.1.4 Hibernate Mode Only required Vboost >3 .6 V Ind In hibernate mode nearly all of the internal functions are disabled. Internal voltages are reduced to the minimal level to 22 µF0.1 µF keep vital systems alive. Configuration state is preserved in P S oC 10 µH SMP hibernate mode and SRAM memory is retained. GPIOs configured as digital outputs maintain their previous values and external GPIO pin interrupt settings are preserved. The device can only return from hibernate mode in response to an external Vbat 22 µF I/O interrupt. The resume time from hibernate mode is less than Vssa 100µs. Vssb Vssd Document Number: 001-56955 Rev. *K Page 32 of 120

® PSoC 3: CY8C32 Family Data Sheet The switching frequency can be set to 100 kHz, 400 kHz, 2 MHz, by firmware within a certain period of time, the watchdog timer or 32 kHz to optimize efficiency and component cost. The generates a reset. 100kHz, 400 kHz, and 2 MHz switching frequencies are (cid:132)Software – The device can be reset under program control. generated using oscillators internal to the boost converter block. When the 32-kHz switching frequency is selected, the clock is Figure 6-7. Resets derived from a 32 kHz external crystal oscillator. The 32-kHz Vddd Vdda external clock is primarily intended for boost standby mode. At 2 MHz the Vboost output is limited to 2 × Vbat, and at 400 kHz Vboost is limited to 4 × Vbat. Power Processor Voltage The boost converter can be operated in two different modes: Interrupt Level active and standby. Active mode is the normal mode of operation Monitors where the boost regulator actively generates a regulated output Reset voltage. In standby mode, most boost functions are disabled, Pin thus reducing power consumption of the boost circuit. The External converter can be configured to provide low-power, low-current Reset Reset System Controller Reset regulation in the standby mode. The external 32 kHz crystal can be used to generate inductor boost pulses on the rising and falling edge of the clock when the output voltage is less than the programmed value. This is called automatic thump mode (ATM). Watchdog Timer The boost typically draws 200 µA in active mode and 12 µA in standby mode. The boost operating modes must be used in conjunction with chip power modes to minimize the total chip power consumption. Table6-4 lists the boost power modes Software available in different chip power modes. Reset Register Table 6-4. Chip and Boost Power Modes Compatibility Chip Power Modes Boost Power Modes The term device reset indicates that the processor as well as Chip – Active mode Boost can be operated in either active analog and digital peripherals and registers are reset. or standby mode. A reset status register holds the source of the most recent reset Chip – Sleep mode Boost can be operated in either active or power voltage monitoring interrupt. The program may or standby mode. However, it is recom- examine this register to detect and report exception conditions. mended to operate boost in standby This register is cleared after a power-on reset. mode for low-power consumption 6.3.1 Reset Sources Chip – Hibernate mode Boost can only be operated in active 6.3.1.1 Power Voltage Level Monitors mode. However, it is recommended not to use boost in chip hibernate mode (cid:132)IPOR – Initial Power-on Reset due to high current consumption in At initial power-on, IPOR monitors the power voltages V boost active mode DDD and V , both directly at the pins and at the outputs of the DDA If the boost converter is not used in a given application, tie the corresponding internal regulators. The trip level is not precise. V , V , and V pins to ground and leave the Ind pin It is set to approximately 1 volt, which is below the lowest BAT SSB BOOST unconnected. specified operating voltage but high enough for the internal circuits to be reset and to hold their reset state. The monitor 6.3 Reset generates a reset pulse that is at least 100 ns wide. It may be CY8C32 has multiple internal and external reset sources much wider if one or more of the voltages ramps up slowly. available. The reset sources are: To save power the IPOR circuit is disabled when the internal (cid:132)Power source monitoring – The analog and digital power digital supply is stable. Voltage supervision is then handed off voltages, V , V , V , and V are monitored in to the precise low voltage reset (PRES) circuit. When the DDA DDD CCA CCD several different modes during power up, active mode, and voltage is high enough for PRES to release, the IMO starts. sleep mode (buzzing). If any of the voltages goes outside (cid:132)PRES – Precise Low Voltage Reset predetermined ranges then a reset is generated. The monitors This circuit monitors the outputs of the analog and digital are programmable to generate an interrupt to the processor internal regulators after power up. The regulator outputs are under certain conditions before reaching the reset thresholds. compared to a precise reference voltage. The response to a (cid:132)External – The device can be reset from an external source by PRES trip is identical to an IPOR reset. pulling the reset pin (XRES) low. The XRES pin includes an In normal operating mode, the program cannot disable the internal pull-up to V . V , V , and V must all DDIO1 DDD DDA DDIO1 digital PRES circuit. The analog regulator can be disabled, have voltage applied before the part comes out of reset. which also disables the analog portion of the PRES. The PRES (cid:132)Watchdog timer – A watchdog timer monitors the execution of circuit is disabled automatically during sleep and hibernate instructions by the processor. If the watchdog timer is not reset modes, with one exception: During sleep mode the regulators are periodically activated (buzzed) to provide supervisory Document Number: 001-56955 Rev. *K Page 33 of 120

® PSoC 3: CY8C32 Family Data Sheet services and to reduce wakeup time. At these times the PRES 6.4 I/O System and Routing circuit is also buzzed to allow periodic voltage monitoring. PSoC I/Os are extremely flexible. Every GPIO has analog and (cid:132)ALVI, DLVI, AHVI – Analog/Digital Low Voltage Interrupt, digital I/O capability. All I/Os have a large number of drive modes, Analog High Voltage Interrupt which are set at POR. PSoC also provides up to four individual I/O voltage domains through the V pins. Interrupt circuits are available to detect when V and V DDIO DDA DDD go outside a voltage range. For AHVI, V is compared to a There are two types of I/O pins on every device; those with USB DDA fixed trip level. For ALVI and DLVI, V and V are provide a third type. Both GPIO and Special I/O (SIO) provide DDA DDD compared to trip levels that are programmable, as listed in similar digital functionality. The primary differences are their Table6-5. ALVI and DLVI can also be configured to generate analog capability and drive strength. Devices that include USB a device reset instead of an interrupt. also provide two USBIO pins that support specific USB functionality as well as limited GPIO capability. Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High All I/O pins are available for use as digital inputs and outputs for Voltage Interrupt both the CPU and digital peripherals. In addition, all I/O pins can generate an interrupt. The flexible and advanced capabilities of Normal Interrupt Supply Voltage Available Trip Accuracy the PSoC I/O, combined with any signal to any pin routability, Settings Range greatly simplify circuit design and board layout. All GPIO pins can be used for analog input, CapSense, and LCD segment drive, DLVI V 1.71V – 1.70 V – 5.45V ±2% DDD while SIO pins are used for voltages in excess of V and for 5.5V in 250 mV DDA programmable output voltages. increments ALVI V 1.71V – 1.70 V – 5.45V ±2% (cid:132)Features supported by both GPIO and SIO: DDA 5.5V in 250 mV (cid:135)User programmable port reset state increments (cid:135)Separate I/O supplies and voltages for up to four groups of I/O AHVI VDDA 1.71V – 5.75V ±2% (cid:135)Digital peripherals use DSI to connect the pins 5.5V (cid:135)Input or output or both for CPU and DMA (cid:135)Eight drive modes The monitors are disabled until after IPOR. During sleep mode these circuits are periodically activated (buzzed). If an interrupt (cid:135)Every pin can be an interrupt source configured as rising edge, falling edge or both edges. If required, level sensitive occurs during buzzing then the system first enters its wake up interrupts are supported through the DSI sequence. The interrupt is then recognized and may be (cid:135)Dedicated port interrupt vector for each port serviced. (cid:135)Slew rate controlled digital output drive mode 6.3.1.2 Other Reset Sources (cid:135)Access port control and configuration registers on either port basis or pin basis (cid:132)XRES – External Reset (cid:135)Separate port read (PS) and write (DR) data registers to avoid PSoC 3 has either a single GPIO pin that is configured as an read modify write errors external reset or a dedicated XRES pin. Either the dedicated (cid:135)Special functionality on a pin by pin basis XRES pin or the GPIO pin, if configured, holds the part in reset (cid:132)Additional features only provided on the GPIO pins: while held active (low). The response to an XRES is the same as to an IPOR reset. (cid:135)LCD segment drive on LCD equipped devices (cid:135)CapSense The external reset is active low. It includes an internal pull-up (cid:135)Analog input and output capability resistor. XRES is active during sleep and hibernate modes. (cid:135)Continuous 100 µA clamp current capability (cid:132)SRES – Software Reset (cid:135)Standard drive strength down to 1.7V A reset can be commanded under program control by setting (cid:132)Additional features only provided on SIO pins: a bit in the software reset register. This is done either directly (cid:135)Higher drive strength than GPIO by the program or indirectly by DMA access. The response to (cid:135)Hot swap capability (5V tolerance at any operating VDD) a SRES is the same as after an IPOR reset. (cid:135)Programmable and regulated high input and output drive Another register bit exists to disable this function. levels down to 1.2V (cid:135)No analog input, CapSense, or LCD capability (cid:132)WRES – Watchdog Timer Reset (cid:135)Over voltage tolerance up to 5.5V The watchdog reset detects when the software program is no (cid:135)SIO can act as a general purpose analog comparator longer being executed correctly. To indicate to the watchdog (cid:132)USBIO features: timer that it is running correctly, the program must periodically reset the timer. If the timer is not reset before a user-specified (cid:135)Full speed USB 2.0 compliant I/O amount of time, then a reset is generated. (cid:135)Highest drive strength for general purpose use (cid:135)Input, output, or both for CPU and DMA Note IPOR disables the watchdog function. The program must (cid:135)Input, output, or both for digital peripherals enable the watchdog function at an appropriate point in the code by setting a register bit. When this bit is set, it cannot be (cid:135)Digital output (CMOS) drive mode cleared again except by an IPOR power-on reset event. (cid:135)Each pin can be an interrupt source configured as rising edge, falling edge, or both edges Document Number: 001-56955 Rev. *K Page 34 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 6-8. GPIO Block Diagram Digital Input Path Naming Convention PRT[x]CTL ‘x’ = Port Number PRT[x]DBL_SYNC_IN ‘y’ = Pin Number PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Input Buffer Disable Interrupt Pin Interrupt Signal Logic PICU[x]INTSTAT Digital Output Path PRT[x]SLW PRT[x]SYNC_OUT VddioVddio PRT[x]DR 0 Digital System Output In 1 Vddio PRT[x]BYP PRT[x]DM2 Drive Slew PRT[x]DM1 Logic Cntl PIN PRT[x]DM0 Bidirectional Control PRT[x]BIE OE Analog 1 0 1 0 Capsense Global Control 1 CAPS[x]CFG1 Switches PRT[x]AG Analog Global Enable PRT[x]AMUX Analog Mux Enable LCD Display Data PRT[x]LCD_COM_SEG Logic & MUX PRT[x]LCD_EN LCD Bias Bus 5 Document Number: 001-56955 Rev. *K Page 35 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 6-9. SIO Input/Output Block Diagram Digital Input Path Naming Convention PRT[x]SIO_HYST_EN ‘x’ = Port Number PRT[x]SIO_DIFF Buffer ‘y’ = Pin Number Reference Level Thresholds PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Input Buffer Disable Interrupt Pin Interrupt Signal Logic PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG Driver PRT[x]SLW Vhigh PRT[x]SYNC_OUT PRT[x]DR 0 Digital System Output In 1 PRT[x]BYP PRT[x]DM2 Drive PRT[x]DM1 Logic Slew PIN Cntl PRT[x]DM0 Bidirectional Control PRT[x]BIE OE Figure 6-10. USBIO Block Diagram Digital Input Path Naming Convention ‘x’ = Port Number ‘y’ = Pin Number USB Receiver Circuitry PRT[x]DBL_SYNC_IN USBIO_CR1[0,1] Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Interrupt Pin Interrupt Signal Logic PICU[x]INTSTAT Digital Output Path PRT[x]SYNC_OUT D+ pin only USBIO_CR1[7] USB or I/O USB SIE Control for USB Mode Vddd VdddVddd Vddd USBIO_CR1[4,5] 0 Digital System Output In 1 Drive 5 k 1.5 k PRT[x]BYP Logic PIN USBIO_CR1[2] D+ 1.5 k USBIO_CR1[3] D+D- 5 k USBIO_CR1[6] Open Drain Document Number: 001-56955 Rev. *K Page 36 of 120

® PSoC 3: CY8C32 Family Data Sheet 6.4.1 Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table6-6. Three configuration bits are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure6-11 depicts a simplified pin view based on each of the eight drive modes. Table6-6 shows the I/O pin’s drive state based on the port data register value or digital array signal if bypass mode is selected. Note that the actual I/O pin voltage is determined by a combination of the selected drive mode and the load at the pin. For example, if a GPIO pin is configured for resistive pull-up mode and driven high while the pin is floating, the voltage measured at the pin is a high logic state. If the same GPIO pin is externally tied to ground then the voltage unmeasured at the pin is a low logic state. Figure 6-11. Drive Mode Vddio Vddio PDSR Pin PDSR Pin PDSR Pin PDSR Pin 0. High Impedance 1. High Impedance 2. Resistive 3. Resistive Analog Digital Pull-Up Pull-Down Vddio Vddio Vddio PDSR Pin PDSR Pin PDSR Pin PDSR Pin 4. Open Drain, 5. Open Drain, 6. Strong Drive 7. Resistive Drives Low Drives High Pull-Up and Pull-Down Table 6-6. Drive Modes Diagram Drive Mode PRTxDM2 PRTxDM1 PRTxDM0 PRTxDR = 1 PRTxDR = 0 0 High impedence analog 0 0 0 High Z High Z 1 High Impedance digital 0 0 1 High Z High Z 2 Resistive pull-up[13] 0 1 0 Res High (5K) Strong Low 3 Resistive pull-down[13] 0 1 1 Strong High Res Low (5K) 4 Open drain, drives low 1 0 0 High Z Strong Low 5 Open drain, drive high 1 0 1 Strong High High Z 6 Strong drive 1 1 0 Strong High Strong Low 7 Resistive pull-up and pull-down[13] 1 1 1 Res High (5K) Res Low (5K) Note 13.Resistive pull-up and pull-down are not available with SIO in regulated output mode. Document Number: 001-56955 Rev. *K Page 37 of 120

® PSoC 3: CY8C32 Family Data Sheet (cid:132)High Impedance Analog 6.4.3 Bidirectional Mode The default reset state with both the output driver and digital High-speed bidirectional capability allows pins to provide both input buffer turned off. This prevents any current from flowing the high impedance digital drive mode for input signals and a in the I/O’s digital input buffer due to a floating voltage. This second user selected drive mode such as strong drive (set using state is recommended for pins that are floating or that support PRT×DM[2:0] registers) for output signals on the same pin, an analog voltage. High impedance analog pins do not provide based on the state of an auxiliary control bus signal. The digital input functionality. bidirectional capability is useful for processor busses and communications interfaces such as the SPI Slave MISO pin that To achieve the lowest chip current in sleep modes, all I/Os requires dynamic hardware control of the output buffer. must either be configured to the high impedance analog mode, or have their pins driven to a power supply rail by the PSoC The auxiliary control bus routes up to 16 UDB or digital peripheral device or by external circuitry. generated output enable signals to one or more pins. (cid:132)High Impedance Digital 6.4.4 Slew Rate Limited Mode The input buffer is enabled for digital signal input. This is the GPIO and SIO pins have fast and slow output slew rate options standard high impedance (HiZ) state recommended for digital for strong and open drain drive modes, not resistive drive modes. inputs. Because it results in reduced EMI, the slow edge rate option is recommended for signals that are not speed critical, generally (cid:132)Resistive pull-up or resistive pull-down less than 1 MHz. The fast slew rate is for signals between 1 MHz Resistive pull-up or pull-down, respectively, provides a series and 33 MHz. The slew rate is individually configurable for each resistance in one of the data states and strong drive in the pin, and is set by the PRT×SLW registers. other. Pins can be used for digital input and output in these modes. Interfacing to mechanical switches is a common 6.4.5 Pin Interrupts application for these modes. Resistive pull-up and pull-down All GPIO and SIO pins are able to generate interrupts to the are not available with SIO in regulated output mode. system. All eight pins in each port interface to their own Port (cid:132)Open Drain, Drives High and Open Drain, Drives Low Interrupt Control Unit (PICU) and associated interrupt vector. Each pin of the port is independently configurable to detect rising Open drain modes provide high impedance in one of the data edge, falling edge, both edge interrupts, or to not generate an states and strong drive in the other. Pins can be used for digital interrupt. input and output in these modes. A common application for these modes is driving the I2C bus signal lines. Depending on the configured mode for each pin, each time an interrupt event occurs on a pin, its corresponding status bit of the (cid:132)Strong Drive interrupt status register is set to “1” and an interrupt request is Provides a strong CMOS output drive in either high or low sent to the interrupt controller. Each PICU has its own interrupt state. This is the standard output mode for pins. Strong Drive vector in the interrupt controller and the pin status register mode pins must not be used as inputs under normal providing easy determination of the interrupt source down to the circumstances. This mode is often used to drive digital output pin level. signals or external FETs. Port pin interrupts remain active in all sleep modes allowing the PSoC device to wake from an externally generated interrupt. (cid:132)Resistive pull-up and pull-down While level sensitive interrupts are not directly supported; Similar to the resistive pull-up and resistive pull-down modes Universal Digital Blocks (UDB) provide this functionality to the except the pin is always in series with a resistor. The high data system when needed. state is pull-up while the low data state is pull-down. This mode is most often used when other signals that may cause shorts 6.4.6 Input Buffer Mode can drive the bus. Resistive pull-up and pull-down are not available with SIO in regulated output mode. GPIO and SIO input buffers can be configured at the port level for the default CMOS input thresholds or the optional LVTTL 6.4.2 Pin Registers input thresholds. All input buffers incorporate Schmitt triggers for input hysteresis. Additionally, individual pin input buffers can be Registers to configure and interact with pins come in two forms disabled in any drive mode. that may be used interchangeably. All I/O registers are available in the standard port form, where 6.4.7 I/O Power Supplies each bit of the register corresponds to one of the port pins. This Up to four I/O pin power supplies are provided depending on the register form is efficient for quickly reconfiguring multiple port device and package. Each I/O supply must be less than or equal pins at the same time. to the voltage on the chip’s analog (V ) pin. This feature allows DDA I/O registers are also available in pin form, which combines the users to provide different I/O voltage levels for different pins on eight most commonly used port register bits into a single register the device. Refer to the specific device package pinout to for each pin. This enables very fast configuration changes to determine V capability for a given port and pin. DDIO individual pins with a single register write. The SIO port pins support an additional regulated high output capability, as described in Adjustable Output Level. Document Number: 001-56955 Rev. *K Page 38 of 120

® PSoC 3: CY8C32 Family Data Sheet 6.4.8 Analog Connections Figure 6-12. SIO Reference for Input and Output These connections apply only to GPIO pins. All GPIO pins may Input Path be used as analog inputs or outputs. The analog voltage present on the pin must not exceed the V supply voltage to which DDIO the GPIO belongs. Each GPIO may connect to one of the analog Digital global busses or to one of the analog mux buses to connect any Input pin to any internal analog resource such as ADC or comparators. Vinref In addition, one select pin provides direct connection to the high current DAC. 6.4.9 CapSense This section applies only to GPIO pins. All GPIO pins may be SIO_Ref Reference used to create CapSense buttons and sliders. See the Generator PIN “CapSense” section on page57 for more information. 6.4.10 LCD Segment Drive Voutref Output Path This section applies only to GPIO pins. All GPIO pins may be Driver used to generate Segment and Common drive signals for direct Vhigh glass drive of LCD glass. See the “LCD Direct Drive” section on page57 for details. 6.4.11 Adjustable Output Level This section applies only to SIO pins. SIO port pins support the Digital Drive ability to provide a regulated high output level for interface to Output Logic external signals that are lower in voltage than the SIO’s respective V . SIO pins are individually configurable to output DDIO either the standard V level or the regulated output, which is DDIO based on an internally generated reference. Typically the voltage DAC (VDAC) is used to generate the reference (see Figure 6-12). The “DAC” section on page58 has more details on VDAC use and reference routing to the SIO pins. Resistive pull-up and 6.4.13 SIO as Comparator pull-down drive modes are not available with SIO in regulated output mode. This section applies only to SIO pins. The adjustable input level feature of the SIOs as explained in the Adjustable Input Level 6.4.12 Adjustable Input Level section can be used to construct a comparator. The threshold for the comparator is provided by the SIO's reference generator. The This section applies only to SIO pins. SIO pins by default support reference generator has the option to set the analog signal the standard CMOS and LVTTL input levels but also support a routed through the analog global line as threshold for the differential mode with programmable levels. SIO pins are comparator. Note that a pair of SIO pins share the same grouped into pairs. Each pair shares a reference generator block threshold. which, is used to set the digital input buffer reference level for interface to external signals that differ in voltage from V . The The digital input path in Figure 6-9 on page 36 illustrates this DDIO reference sets the pins voltage threshold for a high logic level functionality. In the figure, ‘Reference level’ is the analog signal (see Figure 6-12). Available input thresholds are: routed through the analog global. The hysteresis feature can also be enabled for the input buffer of the SIO, which increases (cid:132)0.5 × Vddio noise immunity for the comparator. (cid:132)0.4 × Vddio 6.4.14 Hot Swap (cid:132)0.5 × VREF This section applies only to SIO pins. SIO pins support ‘hot swap’ (cid:132)VREF capability to plug into an application without loading the signals Typically the voltage DAC (VDAC) generates the V that are connected to the SIO pins even when no power is REF reference. The “DAC” section on page58 has more details on applied to the PSoC device. This allows the unpowered PSoC to VDAC use and reference routing to the SIO pins. maintain a high impedance load to the external device while also preventing the PSoC from being powered through a GPIO pin’s protection diode. Document Number: 001-56955 Rev. *K Page 39 of 120

® PSoC 3: CY8C32 Family Data Sheet 6.4.15 Over Voltage Tolerance (cid:132)Analog All I/O pins provide an over voltage tolerance feature at any (cid:135)High current IDAC output operating VDD. (cid:135)External reference inputs (cid:132)There are no current limitations for the SIO pins as they present a 6.4.19 JTAG Boundary Scan high impedance load to the external circuit where V < V < DDIO IN The device supports standard JTAG boundary scan chains on all 5.5V. I/O pins for board level test. (cid:132)The GPIO pins must be limited to 100 µA using a current limiting resistor. GPIO pins clamp the pin voltage to approximately one 7. Digital Subsystem diode above the V supply where V < V < V . DDIO DDIO IN DDA The digital programmable system creates application specific (cid:132)In case of a GPIO pin configured for analog input/output, the combinations of both standard and advanced digital peripherals analog voltage on the pin must not exceed the VDDIO supply and custom logic functions. These peripherals and logic are then voltage to which the GPIO belongs. interconnected to each other and to any pin on the device, A common application for this feature is connection to a bus such providing a high level of design flexibility and IP security. as I2C where different devices are running from different supply The features of the digital programmable system are outlined voltages. In the I2C case, the PSoC chip is configured into the here to provide an overview of capabilities and architecture. You Open Drain, Drives Low mode for the SIO pin. This allows an do not need to interact directly with the programmable digital external pull-up to pull the I2C bus voltage above the PSoC pin system at the hardware and register level. PSoC Creator supply. For example, the PSoC chip could operate at 1.8V, and provides a high level schematic capture graphical interface to an external device could run from 5V. Note that the SIO pin’s VIH automatically place and route resources similar to PLDs. and V levels are determined by the associated V supply IL DDIO The main components of the digital programmable system are: pin. The I/O pin must be configured into a high impedance drive (cid:132)Universal Digital Blocks (UDB) – These form the core mode, open drain low drive mode, or pull-down drive mode, for functionality of the digital programmable system. UDBs are a over voltage tolerance to work properly. Absolute maximum collection of uncommitted logic (PLD) and structural logic ratings for the device must be observed for all I/O pins. (Datapath) optimized to create all common embedded peripherals and customized functionality that are application or 6.4.16 Reset Configuration design specific. While reset is active all I/Os are reset to and held in the High (cid:132)Universal Digital Block Array – UDB blocks are arrayed within Impedance Analog state. After reset is released, the state can be a matrix of programmable interconnect. The UDB array reprogrammed on a port-by-port basis to pull-down or pull-up. To structure is homogeneous and allows for flexible mapping of ensure correct reset operation, the port reset configuration data digital functions onto the array. The array supports extensive is stored in special nonvolatile registers. The stored reset data is and flexible routing interconnects between UDBs and the automatically transferred to the port reset configuration registers Digital System Interconnect. at reset release. (cid:132)Digital System Interconnect (DSI) – Digital signals from 6.4.17 Low-Power Functionality Universal Digital Blocks (UDBs), fixed function peripherals, I/O In all low-power modes the I/O pins retain their state until the part pins, interrupts, DMA, and other system core signals are is awakened and changed or reset. To awaken the part, use a attached to the Digital System Interconnect to implement full pin interrupt, because the port interrupt logic continues to featured device connectivity. The DSI allows any digital function function in all low-power modes. to any pin or other feature routability when used with the Universal Digital Block Array. 6.4.18 Special Pin Functionality Some pins on the device include additional special functionality in addition to their GPIO or SIO functionality. The specific special function pins are listed in Pinouts on page 5. The special features are: (cid:132)Digital (cid:135)4- to 25- MHz crystal oscillator (cid:135)32.768-kHz crystal oscillator (cid:135)Wake from sleep on I2C address match. Any pin can be used for I2C if wake from sleep is not required. (cid:135)JTAG interface pins (cid:135)SWD interface pins (cid:135)SWV interface pins (cid:135)External reset Document Number: 001-56955 Rev. *K Page 40 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 7-1. CY8C32 Digital Programmable Architecture 7.1.2 Example Analog Components The following is a sample of the analog components available in PSoC Creator for the CY8C32 family. The exact amount of Digital Core System and Fixed Function Peripherals hardware resources (routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the Port Port component. O O I DSI Routing Interface I (cid:132)ADC UDB UDB UDB UDB (cid:135)Delta-sigma (cid:132)DACs UDB UDB UDB UDB UDB Array UUUDDDBBB UUUDDDBBB UUUDDDBBB UUUDDDBBB UDB Array (cid:132)(cid:135)(cid:135)(cid:135)CoCVPmoWulprtMraaegrnaettors UDB UDB UDB UDB 7.1.3 Example System Function Components DSI Routing Interface The following is a sample of the system function components O Port O Port aavmaoiluanbtl eo fi nh aPrSdwoCar eC rreesaotourr cfoers t (hUeD CBYs8, Cro3u2ti nfagm, RilyA. MT,h fela esxha) cuts ed I Digital Core System I by a component varies with the features selected in PSoC and Fixed Function Peripherals Creator for the component. (cid:132)CapSense 7.1 Example Peripherals (cid:132)LCD Drive The flexibility of the CY8C32 family’s Universal Digital Blocks (cid:132)LCD Control (UDBs) and Analog Blocks allow the user to create a wide range of components (peripherals). The most common peripherals 7.1.4 Designing with PSoC Creator were built and characterized by Cypress and are shown in the 7.1.4.1 More Than a Typical IDE PSoC Creator component catalog, however, users may also A successful design tool allows for the rapid development and create their own custom components using PSoC Creator. Using deployment of both simple and complex designs. It reduces or PSoC Creator, users may also create their own components for eliminates any learning curve. It makes the integration of a new reuse within their organization, for example sensor interfaces, design into the production stream straightforward. proprietary algorithms, and display interfaces. PSoC Creator is that design tool. The number of components available through PSoC Creator is PSoC Creator is a full featured Integrated Development too numerous to list in the datasheet, and the list is always Environment (IDE) for hardware and software design. It is growing. An example of a component available for use in optimized specifically for PSoC devices and combines a modern, CY8C32 family, but, not explicitly called out in this datasheet is powerful software development platform with a sophisticated the UART component. graphical design tool. This unique combination of tools makes 7.1.1 Example Digital Components PSoC Creator the most flexible embedded design platform available. The following is a sample of the digital components available in Graphical design entry simplifies the task of configuring a PSoC Creator for the CY8C32 family. The exact amount of particular part. You can select the required functionality from an hardware resources (UDBs, routing, RAM, flash) used by a extensive catalog of components and place it in your design. All component varies with the features selected in PSoC Creator for components are parameterized and have an editor dialog that the component. allows you to tailor functionality to your needs. (cid:132)Communications PSoC Creator automatically configures clocks and routes the I/O (cid:135)I2C to the selected pins and then generates APIs to give the (cid:135)UART application complete control over the hardware. Changing the (cid:135)SPI PSoC device configuration is as simple as adding a new component, setting its parameters, and rebuilding the project. (cid:132)Functions At any stage of development you are free to change the (cid:135)EMIF hardware configuration and even the target processor. To (cid:135)PWMs retarget your application (hardware and software) to new (cid:135)Timers devices, even from 8- to 32-bit families, just select the new (cid:135)Counters device and rebuild. (cid:132)Logic You also have the ability to change the C compiler and evaluate (cid:135)NOT an alternative. Components are designed for portability and are (cid:135)OR validated against all devices, from all families, and against all (cid:135)XOR supported tool chains. Switching compilers is as easy as editing (cid:135)AND the from the project options and rebuilding the application with no errors from the generated APIs or boot code. Document Number: 001-56955 Rev. *K Page 41 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 7-2. PSoC Creator Framework Document Number: 001-56955 Rev. *K Page 42 of 120

® PSoC 3: CY8C32 Family Data Sheet 7.1.4.2 Component Catalog 7.1.4.4 Software Development Figure 7-3. Component Catalog Figure 7-4. Code Editor Anchoring the tool is a modern, highly customizable user interface. It includes project management and integrated editors for C and assembler source code, as well the design entry tools. Project build control leverages compiler technology from top commercial vendors such as ARM® Limited, Keil™, and CodeSourcery (GNU). Free versions of Keil C51 and GNU C Compiler (GCC) for ARM, with no restrictions on code size or end product distribution, are included with the tool distribution. Upgrading to more optimizing compilers is a snap with support for the professional Keil C51 product and ARM RealView™ The component catalog is a repository of reusable design compiler. elements that select device functionality and customize your PSoC device. It is populated with an impressive selection of 7.1.4.5 Nonintrusive Debugging content; from simple primitives such as logic gates and device Figure 7-5. PSoC Creator Debugger registers, through the digital timers, counters and PWMs, plus analog components such as ADC and DAC, and communication protocols, such as I2C, and USB. See Example Peripherals on page 41 for more details about available peripherals. All content is fully characterized and carefully documented in datasheets with code examples, AC/DC specifications, and user code ready APIs. 7.1.4.3 Design Reuse The symbol editor gives you the ability to develop reusable components that can significantly reduce future design time. Just draw a symbol and associate that symbol with your proven design. PSoC Creator allows for the placement of the new symbol anywhere in the component catalog along with the content provided by Cypress. You can then reuse your content as many times as you want, and in any number of projects, without ever having to revisit the details of the implementation. With JTAG (4-wire) and SWD (2-wire) debug connectivity available on all devices, the PSoC Creator debugger offers full control over the target device with minimum intrusion. Breakpoints and code execution commands are all readily available from toolbar buttons and an impressive lineup of windows—register, locals, watch, call stack, memory and peripherals—make for an unparalleled level of visibility into the system. Document Number: 001-56955 Rev. *K Page 43 of 120

® PSoC 3: CY8C32 Family Data Sheet PSoC Creator contains all the tools necessary to complete a also contains input/output FIFOs, which are the primary parallel design, and then to maintain and extend that design for years to data interface between the CPU/DMA system and the UDB. come. All steps of the design flow are carefully integrated and (cid:132)Status and Control Module – The primary role of this block is optimized for ease-of-use and to maximize productivity. to provide a way for CPU firmware to interact and synchronize 7.2 Universal Digital Block with UDB operation. The Universal Digital Block (UDB) represents an evolutionary (cid:132)Clock and Reset Module – This block provides the UDB clocks step to the next generation of PSoC embedded digital peripheral and reset selection and control. functionality. The architecture in first generation PSoC digital blocks provides coarse programmability in which a few fixed 7.2.1 PLD Module functions with a small number of options are available. The new The primary purpose of the PLD blocks is to implement logic UDB architecture is the optimal balance between configuration expressions, state machines, sequencers, lookup tables, and granularity and efficient implementation. A cornerstone of this decoders. In the simplest use model, consider the PLD blocks as approach is to provide the ability to customize the devices digital a standalone resource onto which general purpose RTL is operation to match application requirements. synthesized and mapped. The more common and efficient use model is to create digital functions from a combination of PLD To achieve this, UDBs consist of a combination of uncommitted and datapath blocks, where the PLD implements only the logic (PLD), structured logic (Datapath), and a flexible routing random logic and state portion of the function while the datapath scheme to provide interconnect between these elements, I/O (ALU) implements the more structured elements. connections, and other peripherals. UDB functionality ranges from simple self contained functions that are implemented in one Figure 7-7. PLD 12C4 Structure UDB, or even a portion of a UDB (unused resources are available for other functions), to more complex functions that T0 T1 T2 T3 T4 T5 T6 T7 P P P P P P P P require multiple UDBs. Examples of basic functions are timers, IN0 TC TC TC TC TC TC TC TC counters, CRC generators, PWMs, dead band generators, and communications functions, such as UARTs, SPI, and I2C. Also, IN1 TC TC TC TC TC TC TC TC IN2 TC TC TC TC TC TC TC TC the PLD blocks and connectivity provide full featured general IN3 TC TC TC TC TC TC TC TC purpose programmable logic within the limits of the available IN4 TC TC TC TC TC TC TC TC resources. IN5 TC TC TC TC TC TC TC TC AND Figure 7-6. UDB Block Diagram IN6 TC TC TC TC TC TC TC TC Array IN7 TC TC TC TC TC TC TC TC PLD IN8 TC TC TC TC TC TC TC TC Chaining IN9 TC TC TC TC TC TC TC TC PLD PLD IN10 TC TC TC TC TC TC TC TC Clock 12C4 12C4 IN11 TC TC TC TC TC TC TC TC and Reset (8 PTs) (8 PTs) SELIN Control (carry in) OUT0 MC0 T T T T T T T T Status and OUT1 MC1 T T T T T T T T Control Datapath OUT2 MC2 T T T T T T T T Datapath OUT3 MC3 T T T T T T T T Chaining SELOUT (carry out) OR Array One 12C4 PLD block is shown in Figure7-7. This PLD has 12 Routing Channel inputs, which feed across eight product terms. Each product term (AND function) can be from 1 to 12 inputs wide, and in a given The main component blocks of the UDB are: product term, the true (T) or complement (C) of each input can (cid:132)PLD blocks – There are two small PLDs per UDB. These blocks be selected. The product terms are summed (OR function) to take inputs from the routing array and form registered or create the PLD outputs. A sum can be from 1 to 8 product terms combinational sum-of-products logic. PLDs are used to wide. The 'C' in 12C4 indicates that the width of the OR gate (in implement state machines, state bits, and combinational logic this case 8) is constant across all outputs (rather than variable equations. PLD configuration is automatically generated from as in a 22V10 device). This PLA like structure gives maximum graphical primitives. flexibility and insures that all inputs and outputs are permutable for ease of allocation by the software tools. There are two 12C4 (cid:132)Datapath Module – This 8-bit wide datapath contains structured PLDs in each UDB. logic to implement a dynamically configurable ALU, a variety of compare configurations and condition generation. This block Document Number: 001-56955 Rev. *K Page 44 of 120

® PSoC 3: CY8C32 Family Data Sheet 7.2.2 Datapath Module The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band generators and many others. Figure 7-8. Datapath Top Level PHUB System Bus R/W Access to All Registers F1 FIFOs ProgIrnapmRumot ufartobinmleg 6MInupxuets Control Store RAM8 Word X 16 Bit Datapath Control Data RDDFe001gisters To/FroDDAAm0101 Conditions: 2 Compares, 2 Zero Detect, 2 Ones Detect Overflow Detect OMuutxTpeous/t6F romOPRrououtgptirunatgm tom able Previous Chaining Next Datapath Datapath A1 Accumulators A0 PI Parallel Input/Output (To/From Programmable Routing) PO ALU Shift Mask 7.2.2.1 Working Registers 7.2.2.2 Dynamic Datapath Configuration RAM Dynamic configuration is the ability to change the datapath The datapath contains six primary working registers, which are function and internal configuration on a cycle-by-cycle basis, accessed by CPU firmware or DMA during normal operation. under sequencer control. This is implemented using the Table 7-1. Working Datapath Registers 8-word×16-bit configuration RAM, which stores eight unique 16-bit wide configurations. The address input to this RAM Name Function Description controls the sequence, and can be routed from any block A0 and A1 Accumulators These are sources and sinks for connected to the UDB routing matrix, most typically PLD logic, the ALU and also sources for the I/O pins, or from the outputs of this or other datapath blocks. compares. ALU D0 and D1 Data Registers These are sources for the ALU The ALU performs eight general purpose functions. They are: and sources for the compares. (cid:132)Increment F0 and F1 FIFOs These are the primary interface (cid:132)Decrement to the system bus. They can be a (cid:132)Add data source for the data registers (cid:132)Subtract and accumulators or they can (cid:132)Logical AND capture data from the accumu- (cid:132)Logical OR lators or ALU. Each FIFO is four (cid:132)Logical XOR bytes deep. (cid:132)Pass, used to pass a value through the ALU to the shift register, mask, or another UDB register Document Number: 001-56955 Rev. *K Page 45 of 120

® PSoC 3: CY8C32 Family Data Sheet Independent of the ALU operation, these functions are available: 7.2.2.7 Chaining (cid:132)Shift left The datapath can be configured to chain conditions and signals such as carries and shift data with neighboring datapaths to (cid:132)Shift right create higher precision arithmetic, shift, CRC/PRS functions. (cid:132)Nibble swap 7.2.2.8 Time Multiplexing (cid:132)Bitwise OR mask In applications that are over sampled, or do not need high clock rates, the single ALU block in the datapath can be efficiently 7.2.2.3 Conditionals shared with two sets of registers and condition generators. Carry and shift out data from the ALU are registered and can be Each datapath has two compares, with bit masking options. selected as inputs in subsequent cycles. This provides support Compare operands include the two accumulators and the two for 16-bit functions in one (8-bit) datapath. data registers in a variety of configurations. Other conditions include zero detect, all ones detect, and overflow. These 7.2.2.9 Datapath I/O conditions are the primary datapath outputs, a selection of which There are six inputs and six outputs that connect the datapath to can be driven out to the UDB routing matrix. Conditional the routing matrix. Inputs from the routing provide the computation can use the built in chaining to neighboring UDBs configuration for the datapath operation to perform in each cycle, to operate on wider data widths without the need to use routing and the serial data inputs. Inputs can be routed from other UDB resources. blocks, other device peripherals, device I/O pins, and so on. The 7.2.2.4 Variable MSB outputs to the routing can be selected from the generated conditions, and the serial data outputs. Outputs can be routed to The most significant bit of an arithmetic and shift function can be other UDB blocks, device peripherals, interrupt and DMA programmatically specified. This supports variable width CRC controller, I/O pins, and so on. and PRS functions, and in conjunction with ALU output masking, can implement arbitrary width timers, counters and shift blocks. 7.2.3 Status and Control Module 7.2.2.5 Built in CRC/PRS The primary purpose of this circuitry is to coordinate CPU The datapath has built in support for single cycle Cyclic firmware interaction with internal UDB operation. Redundancy Check (CRC) computation and Pseudo Random Figure 7-10. Status and Control Registers Sequence (PRS) generation of arbitrary width and arbitrary System Bus polynomial. CRC/PRS functions longer than 8 bits may be implemented in conjunction with PLD logic, or built in chaining may be use to extend the function into neighboring UDBs. 7.2.2.6 Input/Output FIFOs 8-bit Status Register 8-bit Control Register (Read Only) (Write/Read) Each datapath contains two four-byte deep FIFOs, which can be independently configured as an input buffer (system bus writes to the FIFO, datapath internal reads the FIFO), or an output buffer (datapath internal writes to the FIFO, the system bus reads Routing Channel from the FIFO). The FIFOs generate status that are selectable as datapath outputs and can therefore be driven to the routing, to interact with sequencers, interrupts, or DMA. The bits of the control register, which may be written to by the system bus, are used to drive into the routing matrix, and thus Figure 7-9. Example FIFO Configurations provide firmware with the opportunity to control the state of UDB System Bus System Bus processing. The status register is read-only and it allows internal UDB state to be read out onto the system bus directly from internal routing. This allows firmware to monitor the state of UDB F0 F0 F1 processing. Each bit of these registers has programmable connections to the routing matrix and routing connections are made depending on the requirements of the application. D0/D1 D0 D1 7.2.3.1 Usage Examples A0/A1/ALU A0/A1/ALU A0/A1/ALU A0 A1 As an example of control input, a bit in the control register can be allocated as a function enable bit. There are multiple ways to F1 F0 F1 enable a function. In one method the control bit output would be routed to the clock control block in one or more UDBs and serve as a clock enable for the selected UDB blocks. A status example System Bus System Bus is a case where a PLD or datapath block generated a condition, TX/RX Dual Capture Dual Buffer such as a “compare true” condition that is captured and latched by the status register and then read (and cleared) by CPU firmware. Document Number: 001-56955 Rev. *K Page 46 of 120

® PSoC 3: CY8C32 Family Data Sheet 7.2.3.2 Clock Generation An example of this is the 8-bit Timer in the upper left corner of the array. This function only requires one datapath in the UDB, Each subcomponent block of a UDB including the two PLDs, the and therefore the PLD resources may be allocated to another datapath, and Status and Control, has a clock selection and function. A function such as a Quadrature Decoder may require control block. This promotes a fine granularity with respect to more PLD logic than one UDB can supply and in this case can allocating clocking resources to UDB component blocks and utilize the unused PLD blocks in the 8-bit Timer UDB. allows unused UDB resources to be used by other functions for Programmable resources in the UDB array are generally maximum system efficiency. homogeneous so functions can be mapped to arbitrary 7.3 UDB Array Description boundaries in the array. Figure7-11 shows an example of a 16 UDB array. In addition to Figure 7-12. Function Mapping Example in a Bank of UDBs the array core, there are a DSI routing interfaces at the top and bottom of the array. Other interfaces that are not explicitly shown include the system interfaces for bus and clock distribution. The 8T-imBiet r Quadrature Decoder cer 1P6W-BMit 16-Bit PYRS n e UDB array includes multiple horizontal and vertical routing UDB UDB equ UDB UDB channels each comprised of 96 wires. The wire connections to S UDBs, at horizontal/vertical intersection and at the DSI interface HV HV HV HV are highly permutable providing efficient automatic routing in A B A B PSoC Creator. Additionally the routing allows wire by wire segmentation along the vertical and horizontal routing to further increase routing flexibility and capability. UDB UDB UDB 8-BitU DB Timer Logic Figure 7-11. Digital System Interface Structure 8-Bit SPI I2C Slave 12-Bit SPI System Connections UDB UDB UDB UDB HV HV HV HV HV HV HV HV B A B A B A B A Logic UDB UDB UDB UDB UDB UDB UDB UDB HV HV HV HV A B A B UART 12-Bit PWM UDB UDB UDB UDB 7.4 DSI Routing Interface Description The DSI routing interface is a continuation of the horizontal and UDB UDB UDB UDB vertical routing channels at the top and bottom of the UDB array core. It provides general purpose programmable routing HV HV HV HV between device peripherals, including UDBs, I/Os, analog B A B A peripherals, interrupts, DMA and fixed function peripherals. Figure7-13 illustrates the concept of the digital system UDB UDB UDB UDB interconnect, which connects the UDB array routing matrix with other device peripherals. Any digital core or fixed function HV HV HV HV peripheral that needs programmable routing is connected to this A B A B interface. Signals in this category include: System Connections (cid:132)Interrupt requests from all digital peripherals in the system. 7.3.1 UDB Array Programmable Resources (cid:132)DMA requests from all digital peripherals in the system. Figure7-12 shows an example of how functions are mapped into (cid:132)Digital peripheral data signals that need flexible routing to I/Os. a bank of 16 UDBs. The primary programmable resources of the (cid:132)Digital peripheral data signals that need connections to UDBs. UDB are two PLDs, one datapath and one status/control register. These resources are allocated independently, because they (cid:132)Connections to the interrupt and DMA controllers. have independently selectable clocks, and therefore unused blocks are allocated to other unrelated functions. (cid:132)Connection to I/O pins. (cid:132)Connection to analog system digital signals. Document Number: 001-56955 Rev. *K Page 47 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 7-13. Digital System Interconnect conjunction with drive strength control, this can implement a bidirectional I/O pin. A data output signal has the option to be single synchronized (pipelined) and a data input signal has the Timers Interrupt DMA IO Port Global Counters I2C Controller Controller Pins Clocks option to be double synchronized. The synchronization clock is the system clock (see Figure6-1). Normally all inputs from pins are synchronized as this is required if the CPU interacts with the signal or any signal derived from it. Asynchronous inputs have rare uses. An example of this is a feed through of combinational PLD logic from input pins to output pins. Digital System Routing I/F Figure 7-15. I/O Pin Synchronization Routing DO UDB ARRAY DI Digital System Routing I/F Figure 7-16. I/O Pin Output Connectivity 8 IO Data Output Connections from the UDB Array Digital System Interface Global I/O Port EMIF Del-Sig DAC Comparators Clocks Pins Interrupt and DMA routing is very flexible in the CY8C32 programmable architecture. In addition to the numerous fixed function peripherals that can generate interrupt requests, any data signal in the UDB array routing can also be used to generate a request. A single peripheral may generate multiple DO DO DO DO DO DO DO DO independent interrupt requests simplifying system and firmware PIN 0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 design. Figure7-14 shows the structure of the IDMUX (Interrupt/DMA Multiplexer). Port i Figure 7-14. Interrupt and DMA Processing in the IDMUX Interrupt and DMA Processing in IDMUX There are four more DSI connections to a given I/O port to implement dynamic output enable control of pins. This Fixed Function IRQs connectivity gives a range of options, from fully ganged 8-bits 0 controlled by one signal, to up to four individually controlled pins. 1 The output enable signal is useful for creating tri-state Interrupt bidirectional pins and buses. IRQs Controller 2 Figure 7-17. I/O Pin Output Enable Connectivity UDB Array Edge 3 Detect 4 IO Control Signal Connections from DRQs UDB Array Digital System Interface DMA termout (IRQs) 0 Fixed Function DRQs DMA 1 Controller Edge 2 Detect 7.4.1 I/O Port Routing There are a total of 20 DSI routes to a typical 8-bit I/O port, 16 OE OE OE OE OE OE OE OE PIN 0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 for data and four for drive strength control. When an I/O pin is connected to the routing, there are two primary connections available, an input and an output. In Port i Document Number: 001-56955 Rev. *K Page 48 of 120

® PSoC 3: CY8C32 Family Data Sheet 7.5 USB to any device pin and any internal digital signal accessible through the DSI. Each of the four instances has a compare PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0 output, terminal count output (optional complementary compare transceiver supporting all four USB transfer types: control, output), and programmable interrupt request line. The interrupt, bulk, and isochronous. PSoC Creator provides full Timer/Counter/PWMs are configurable as free running, one shot, configuration support. USB interfaces to hosts through two or Enable input controlled. The peripheral has timer reset and dedicated USBIO pins, which are detailed in the “I/O System and capture inputs, and a kill input for control of the comparator Routing” section on page34. outputs. The peripheral supports full 16-bit capture. USB includes the following features: Timer/Counter/PWM features include: (cid:132)Eight unidirectional data endpoints (cid:132)16-bit Timer/Counter/PWM (down count only) (cid:132)One bidirectional control endpoint 0 (EP0) (cid:132)Selectable clock source (cid:132)Shared 512-byte buffer for the eight data endpoints (cid:132)PWM comparator (configurable for LT, LTE, EQ, GTE, GT) (cid:132)Dedicated 8-byte buffer for EP0 (cid:132)Period reload on start, reset, and terminal count (cid:132)Three memory modes (cid:135)Manual Memory Management with No DMA Access (cid:132)Interrupt on terminal count, compare true, or capture (cid:135)Manual Memory Management with Manual DMA Access (cid:132)Dynamic counter reads (cid:135)Automatic Memory Management with Automatic DMA Access (cid:132)Timer capture mode (cid:132)Internal 3.3V regulator for transceiver (cid:132)Count while enable signal is asserted mode (cid:132)Internal 48 MHz main oscillator mode that auto locks to USB (cid:132)Free run mode bus clock, requiring no external crystal for USB (USB equipped (cid:132)One Shot mode (stop at end of period) parts only) (cid:132)Complementary PWM outputs with deadband (cid:132)Interrupts on bus and each endpoint event, with device wakeup (cid:132)PWM output kill (cid:132)USB Reset, Suspend, and Resume operations Figure 7-19. Timer/Counter/PWM (cid:132)Bus powered and self powered modes Figure 7-18. USB Clock IRQ Reset Timer / Counter / Enable TC / Compare! 512 X 8 PWM 16-bit Arbiter SRAM Capture Compare Kill External 22 Ω us D+ Resistors B S I E stem (SerEianl gIninteer)face UI/SOB 7.7 I2C y S Interrupts D– The I2C peripheral provides a synchronous two wire interface designed to interface the PSoC device with a two wire I2C serial 48IM MOHz communication bus. The bus is compliant with Philips ‘The I2C Specification’ version 2.1. Additional I2C interfaces can be instantiated using Universal Digital Blocks (UDBs) in PSoC Creator, as required. 7.6 Timers, Counters, and PWMs To eliminate the need for excessive CPU intervention and The Timer/Counter/PWM peripheral is a 16-bit dedicated overhead, I2C specific support is provided for status detection peripheral providing three of the most common embedded and generation of framing bits. I2C operates as a slave, a master, peripheral features. As almost all embedded systems use some or multimaster (Slave and Master). In slave mode, the unit combination of timers, counters, and PWMs. Four of them have always listens for a start condition to begin sending or receiving been included on this PSoC device family. Additional and more data. Master mode supplies the ability to generate the Start and advanced functionality timers, counters, and PWMs can also be Stop conditions and initiate transactions. Multimaster mode instantiated in Universal Digital Blocks (UDBs) as required. provides clock synchronization and arbitration to allow multiple PSoC Creator allows you to choose the timer, counter, and PWM masters on the same bus. If Master mode is enabled and Slave features that they require. The tool set utilizes the most optimal mode is not enabled, the block does not generate interrupts on resources available. externally generated Start conditions. I2C interfaces through the The Timer/Counter/PWM peripheral can select from multiple DSI routing and allows direct connections to any GPIO or SIO clock sources, with input and output signals connected through pins. the DSI routing. DSI routing allows input and output connections Document Number: 001-56955 Rev. *K Page 49 of 120

® PSoC 3: CY8C32 Family Data Sheet I2C provides hardware address detect of a 7-bit address without (cid:132)SMBus operation (through firmware support – SMBus CPU intervention. Additionally the device can wake from supported in hardware in UDBs) low-power modes on a 7-bit hardware address match. If wakeup functionality is required, I2C pin connections are limited to the (cid:132)7-bit hardware address compare two special sets of SIO pins. (cid:132)Wake from low-power modes on address match I2C features include: Data transfers follow the format shown in Figure7-20. After the START condition (S), a slave address is sent. This address is 7 (cid:132)Slave and Master, Transmitter, and Receiver operation bits long followed by an eighth bit which is a data direction bit (R/W) - a 'zero' indicates a transmission (WRITE), a 'one' (cid:132)Byte processing for low CPU overhead indicates a request for data (READ). A data transfer is always (cid:132)Interrupt or polling CPU interface terminated by a STOP condition (P) generated by the master. However, if a master still wishes to communicate on the bus, it (cid:132)Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs) can generate a repeated START condition (Sr) and address (cid:132)7 or 10-bit addressing (10-bit addressing requires firmware another slave without first generating a STOP condition. Various combinations of read/write formats are then possible within such support) a transfer. Figure 7-20. I2C Complete Transfer Timing SDA SCL 1 - 7 8 9 1 - 7 8 9 1 - 7 8 9 START STOP ADDRESS R/W ACK DATA ACK DATA ACK Condition Condition Document Number: 001-56955 Rev. *K Page 50 of 120

® PSoC 3: CY8C32 Family Data Sheet 8. Analog Subsystem (cid:132)High resolution delta-sigma ADC. (cid:132)One 8-bit DAC that provides either voltage or current output. The analog programmable system creates application specific combinations of both standard and advanced analog signal (cid:132)Two comparators with optional connection to configurable LUT processing blocks. These blocks are then interconnected to outputs. each other and also to any pin on the device, providing a high level of design flexibility and IP security. The features of the (cid:132)CapSense subsystem to enable capacitive touch sensing. analog subsystem are outlined here to provide an overview of (cid:132)Precision reference for generating an accurate analog voltage capabilities and architecture. for internal analog blocks. (cid:132)Flexible, configurable analog routing architecture provided by analog globals, analog mux bus, and analog local buses. Figure 8-1. Analog Subsystem Block Diagram A A N N AL DAC DelSig ADC RPerefecriseinocne AL O O G G Comparators R R GPIO O CMP CMP O GPIO Port U U Port T T I I N N G CapSense Subsystem G Analog Config & Status PHUB CPU Interface Registers DSI Clock Decimator Array Distribution The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and various analog resources and connections from one analog resource to another. PSoC Creator also provides component libraries that allow you to configure the various analog blocks to perform application specific functions. The tool also generates API interface libraries that allow you to write firmware that allows the communication between the analog peripheral and CPU/Memory. Document Number: 001-56955 Rev. *K Page 51 of 120

® PSoC 3: CY8C32 Family Data Sheet 8.1 Analog Routing (cid:132)Eight analog local buses (abus) to route signals between the different analog blocks The CY8C32 family of devices has a flexible analog routing architecture that provides the capability to connect GPIOs and (cid:132)Multiplexers and switches for input and output selection of the different analog blocks, and also route signals between different analog blocks analog blocks. One of the strong points of this flexible routing architecture is that it allows dynamic routing of input and output 8.1.2 Functional Description connections to the different analog blocks. Analog globals (AGs) and analog mux buses (AMUXBUS) For information on how to make pin selections for optimal analog provide analog connectivity between GPIOs and the various routing, refer to the application note, AN58304 - PSoC® 3 and analog blocks. There are 16 AGs in the CY8C32 family. The PSoC® 5 - Pin Selection for Analog Designs. analog routing architecture is divided into four quadrants as shown in Figure8-2. Each quadrant has four analog globals 8.1.1 Features (AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is connected to the corresponding AG through an analog switch. (cid:132)Flexible, configurable analog routing architecture The analog mux bus is a shared routing resource that connects (cid:132)16 analog globals (AG) and two analog mux buses to every GPIO through an analog switch. There are two (AMUXBUS) to connect GPIOs and the analog blocks AMUXBUS routes in CY8C32, one in the left half (AMUXBUSL) and one in the right half (AMUXBUSR), as shown in Figure8-2. (cid:132)Each GPIO is connected to one analog global and one analog mux bus Document Number: 001-56955 Rev. *K Page 52 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 8-2. CY8C32 Analog Interconnect V V V V d s c s d s c s a* a* a* d* Vddio0*swP0[3]inn*GPIOswP0[2]inp*GPIOP0[1]*GPIOP0[0]*GPIOP4[1]GPIOP4[0]GPIOP12[3]SIOP12[2]SIO AMUXBUSL AMUXBUSRP15[3]*GPIOP15[2]*GPIOP12[1]*SIOP12[0]*SIOP3[7]GPIOP3[6]GPIO Vddio3* AGL[4] AGR[4] AGL[5] AGR[5] AGL[6] AGR[6] USL AGL[7] AGR[7] MUXBGL[4]GL[5]GL[6]GL[7] EExxVVrreeffLL1 ExVrefL2 44 GPIO GPIO AAAAA 012345670123 3210 76543210 P3[5] P0[4*] GPIO GPIO P3[4] P0[5*] GPIO GPIO LPF P3[3] GP0P[I6O] * i0 swout swin ionu0t0 5 oiunt11 swin swout ExVrefR GP3P[I2O] P0[7]* + comp0 comp1 + GPIO - - P3[1] GGGPP44PPP[[III32OOO]] VrdeVcfbrdb(demcg1aufmd_bfv./p_vuap02(rdv0f_0e_2rame_v._f42fr_vur1eVe5x rcf(s2ve)61m_n .f(eV0[1 1pn2.):2140VV] )) cmprefbufl_1_cmpvrefcmp1_vref bg_vda_swabusl0 orCeuftOCMAPPAS9RE0NATSOERoreuft cmp1_vref refbufr_cmp rreecffbb(mu1uff_.p_0vv0r2re_e4ff2v1V r ((1e)1..f20 V2)4V) **PPGGGP11PP3P55[XXI[[0O01TT]]] in refbufl refbufr in GPP44P[[I45O]] refsel[1:0] vssa Vssa refsel[1:0] AGR[7]AGR[6]AGR[5]AGR[4]XBUSR GPIO MU P4[6] A *Vccd GPIO P4[7] *Vssd * Vccd *Vddd * Vssd ABUSL0 ABUSR0 ABUSL1 ABUSR1 ABUSL2 ABUSR2 ABUSL3 ABUSR3 * Vddd GPIO vi00DAC0VIDAC *UPS1B5[ 7IO] P6[0] USB IO GPIO 36 *P15[6] P6[1] GPIO GPIO P5[7] GGPP66PP[[II32OO]] ddssmvmp0vew0_npr_(v_wa0rcve/.rmcs28avmVp_w_)vvrrcvaemrefs2ef1 l[(10:0.7]V)vssa +v-cDqmtSzM_r0ef reDfsS2 8M GGPP55PP[[II65OO]] P15[4] dsdmsm0_0q_tzq_tzv_rverf1e f(21 (.10.224VV)) vref_vss_ext GPIO PG1P5I[O5] VdVddaed/n4a_resvda refmux[2:0] ExVrefL ExVrefR PS5I[O4] GPIO P12[7] P2[0] SIO GPIO P12[6] P2[1] GPIO GPIO *P1[7] P2[2] GPIO GPIO AMUXBUSL01234567 0123 3210 76543210 AMUXBUSR *P1[6] P2[3]* ANALOG ANALOG ANALOG ANALOG GPIO GLOBALS BUS BUS GLOBALS VPd2d[i4o]2** MUXBUSLAGL[0] AGL[1]AGL[2]AGL[3] : ATDSC VVssB Eref LPF AGL[3] AGR[3] AGR[3]AGR[2]AGR[1] AGR[0]AMUXBUSR A AGL[2] AGR[2] AGL[1] AGR[1] AGL[0] AGR[0] AMUXBUSL AMUXBUSR 13 * * * * * SCwMoinutcnxh eG cGrtioroounupp GPIO*P2[5]GPIO*P2[6]GPIO*P2[7]SIOP12[4]SIOP12[5]GPIOP6[4]GPIOP6[5]GPIOP6[6]GPIOP6[7] GPIOP5[0]GPIOP5[1]GPIOP5[2]GPIOP5[3]GPIOP1[0]GPIOP1[1]GPIOP1[2]GPIOP1[3]GPIO*P1[4]GPIO*P1[5] Vddio1 Switch Resistance * * * * * Notes: SLmaraglel (( ~~827000 OOhhmmss )) Ind Vssb Vbat Vboost Vssd XRES * DLCenDo steigsn pailnss a oren naoll tp sahcokwagne.s Rev #51 2-April-2010 Document Number: 001-56955 Rev. *K Page 53 of 120

® PSoC 3: CY8C32 Family Data Sheet Analog local buses (abus) are routing resources located within muxes is delivered to the delta-sigma modulator either directly or the analog subsystem and are used to route signals between through the input buffer. The delta-sigma modulator performs the different analog blocks. There are eight abus routes in CY8C32, actual analog to digital conversion. The modulator over-samples four in the left half (abusl [0:3]) and four in the right half (abusr the input and generates a serial data stream output. This high [0:3]) as shown in Figure8-2. Using the abus saves the analog speed data stream is not useful for most applications without globals and analog mux buses from being used for some type of post processing, and so is passed to the decimator interconnecting the analog blocks. through the Analog Interface block. The decimator converts the high speed serial data stream into parallel ADC results. The Multiplexers and switches exist on the various buses to direct modulator/decimator frequency response is [(sin x)/x]4; a typical signals into and out of the analog blocks. A multiplexer can have frequency response is shown in Figure8-5. only one connection on at a time, whereas a switch can have multiple connections on simultaneously. In Figure8-2, Figure 8-4. Delta-sigma ADC Block Diagram multiplexers are indicated by grayed ovals and switches are indicated by transparent ovals. Positive 8.2 Delta-sigma ADC Input Mux Delta Input 12 to 20 Bit The CY8C32 device contains one delta-sigma ADC. This ADC (Analog Routing) Buffer Sigma Decimator Result Modulator offers differential input, high resolution and excellent linearity, Negative EOC making it a good ADC choice for measurement applications. The Input Mux converter can be configured to output 12-bit resolution at data rates of up to 192 ksps. At a fixed clock rate, resolution can be SOC traded for faster data rates as shown in Table8-1 and Figure8-3. Figure 8-5. Delta-sigma ADC Frequency Response, Table 8-1. Delta-sigma ADC Performance Normalized to Output, Sample Rate = 48 kHz Maximum Sample Rate Bits (sps) SINAD (dB) 0 12 192 k 66 -10 8 384 k 43 -20 -30 Figure 8-3. Delta-sigma ADC Sample Rates, Range = ±1.024V e. dB -40 ns -50 o p 1,000,000 s -60 e R cy -70 n e u -80 q e 100,000 fr -90 -100 100 1,000 10,000 100,000 1,000,000 Input Frequency, Hz Input frequency, Hz s 10,000 p s s, ate Resolution and sample rate are controlled by the Decimator. e r Data is pipelined in the decimator; the output is a function of the mpl 1,000 last four samples. When the input multiplexer is switched, the Sa output data is not valid until after the fourth sample after the Continuous Resolution, bits switch. Multi-Sample 8.2.2 Operational Modes 100 The ADC can be configured by the user to operate in one of four 7 8 9 10 11 12 13 modes: Single Sample, Multi Sample, Continous, or Multi Sample (Turbo). All four modes are started by either a write to the start bit in a control register or an assertion of the Start of 8.2.1 Functional Description Conversion (SoC) signal. When the conversion is complete, a status bit is set and the output signal End of Conversion (EoC) The ADC connects and configures three basic components, asserts high and remains high until the value is read by either the input buffer, delta-sigma modulator, and decimator. The basic DMA controller or the CPU. block diagram is shown in Figure8-4. The signal from the input Document Number: 001-56955 Rev. *K Page 54 of 120

® PSoC 3: CY8C32 Family Data Sheet 8.2.2.1 Single Sample 8.2.3 Start of Conversion Input In Single Sample mode, the ADC performs one sample The SoC signal is used to start an ADC conversion. A digital conversion on a trigger. In this mode, the ADC stays in standby clock or UDB output can be used to drive this input. It can be state waiting for the SoC signal to be asserted. When SoC is used when the sampling period must be longer than the ADC signaled the ADC performs four successive conversions. The conversion time or when the ADC must be synchronized to other first three conversions prime the decimator. The ADC result is hardware. This signal is optional and does not need to be valid and available after the fourth conversion, at which time the connected if ADC is running in a continuous mode. EoC signal is generated. To detect the end of conversion, the system may poll a control register for status or configure the 8.2.4 End of Conversion Output external EoC signal to generate an interrupt or invoke a DMA The EoC signal goes high at the end of each ADC conversion. request. When the transfer is done the ADC reenters the standby This signal may be used to trigger either an interrupt or DMA state where it stays until another SoC event. request. 8.2.2.2 Continuous 8.3 Comparators Continuous sample mode is used to take multiple successive The CY8C32 family of devices contains two comparators in a samples of a single input signal. Multiplexing multiple inputs device. Comparators have these features: should not be done with this mode. There is a latency of three (cid:132)Input offset factory trimmed to less than 5 mV conversion times before the first conversion result is available. This is the time required to prime the decimator. After the first (cid:132)Rail-to-rail common mode input range (VSSA to VDDA) (cid:132)Speed and power can be traded off by using one of three result, successive conversions are available at the selected modes: fast, slow, or ultra low-power sample rate. (cid:132)Comparator outputs can be routed to lookup tables to perform 8.2.2.3 Multi Sample simple logic functions and then can also be routed to digital blocks Multi sample mode is similar to continuous mode except that the (cid:132)The positive input of the comparators may be optionally passed ADC is reset between samples. This mode is useful when the through a low pass filter. Two filters are provided input is switched between multiple signals. The decimator is (cid:132)Comparator inputs can be connections to GPIO or DAC output re-primed between each sample so that previous samples do not affect the current conversion. Upon completion of a sample, the 8.3.1 Input and Output Interface next sample is automatically initiated. The results can be transferred using either firmware polling, interrupt, or DMA. The positive and negative inputs to the comparators come from the analog global buses, the analog mux line, the analog local More information on output formats is provided in the Technical bus and precision reference through multiplexers. The output Reference Manual. from each comparator could be routed to any of the two input LUTs. The output of that LUT is routed to the UDB Digital System Interface. Document Number: 001-56955 Rev. *K Page 55 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 8-6. Analog Comparator ANAIF From + Analog comp0 + From _ Routing comp1 Analog _ Routing 4 4 4 4 4 4 4 4 LUT0 LUT1 LUT2 LUT3 UDBs 8.3.2 LUT Table 8-2. LUT Function vs. Program Word and Inputs The CY8C32 family of devices contains four LUTs. The LUT is a two input, one output lookup table that is driven by any one or Control Word Output (A and B are LUT inputs) two of the comparators in the chip. The output of any LUT is 0000b FALSE (‘0’) routed to the digital system interface of the UDB array. From the 0001b A AND B digital system interface of the UDB array, these signals can be connected to UDBs, DMA controller, I/O, or the interrupt 0010b A AND (NOT B) controller. 0011b A The LUT control word written to a register sets the logic function 0100b (NOT A) AND B on the output. The available LUT functions and the associated control word is shown in Table8-2. 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b NOT B 1011b A OR (NOT B) 1100b NOT A 1101b (NOT A) OR B 1110b A NAND B 1111b TRUE (‘1’) Document Number: 001-56955 Rev. *K Page 56 of 120

® PSoC 3: CY8C32 Family Data Sheet 8.4 LCD Direct Drive 8.4.1 LCD Segment Pin Driver The PSoC Liquid Crystal Display (LCD) driver system is a highly Each GPIO pin contains an LCD driver circuit. The LCD driver configurable peripheral designed to allow PSoC to directly drive buffers the appropriate output of the LCD DAC to directly drive a broad range of LCD glass. All voltages are generated on chip, the glass of the LCD. A register setting determines whether the eliminating the need for external components. With a high pin is a common or segment. The pin’s LCD driver then selects multiplex ratio of up to 1/16, the CY8C32 family LCD driver one of the six bias voltages to drive the I/O pin, as appropriate system can drive a maximum of 736 segments. The PSoC LCD for the display data. driver module was also designed with the conservative power 8.4.2 Display Data Flow budget of portable devices in mind, enabling different LCD drive modes and power down modes to conserve power. The LCD segment driver system reads display data and generates the proper output voltages to the LCD glass to PSoC Creator provides an LCD segment drive component. The produce the desired image. Display data resides in a memory component wizard provides easy and flexible configuration of buffer in the system SRAM. Each time you need to change the LCD resources. You can specify pins for segments and common and segment driver voltages, the next set of pixel data commons along with other options. The software configures the moves from the memory buffer into the Port Data Registers via device to meet the required specifications. This is possible DMA. because of the programmability inherent to PSoC devices. Key features of the PSoC LCD segment system are: 8.4.3 UDB and LCD Segment Control (cid:132)LCD panel direct driving A UDB is configured to generate the global LCD control signals and clocking. This set of signals is routed to each LCD pin driver (cid:132)Type A (standard) and Type B (low-power) waveform support through a set of dedicated LCD global routing channels. In addition to generating the global LCD control signals, the UDB (cid:132)Wide operating voltage range support (2V to 5V) for LCD also produces a DMA request to initiate the transfer of the next panels frame of LCD data. (cid:132)Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels 8.4.4 LCD DAC (cid:132)Internal bias voltage generation through internal resistor ladder The LCD DAC generates the contrast control and bias voltage (cid:132)Up to 62 total common and segment outputs for the LCD system. The LCD DAC produces up to five LCD drive voltages plus ground, based on the selected bias ratio. The bias (cid:132)Up to 1/16 multiplex for a maximum of 16 backplane/common voltages are driven out to GPIO pins on a dedicated LCD bias outputs bus, as required. (cid:132)Up to 62 front plane/segment outputs for direct drive 8.5 CapSense (cid:132)Drives up to 736 total segments (16 backplane × 46 front plane) The CapSense system provides a versatile and efficient means (cid:132)Up to 64 levels of software controlled contrast for measuring capacitance in applications such as touch sense buttons, sliders, proximity detection, etc. The CapSense system (cid:132)Ability to move display data from memory buffer to LCD driver uses a configuration of system resources, including a few through DMA (without CPU intervention) hardware functions primarily targeted for CapSense. Specific (cid:132)Adjustable LCD refresh rate from 10 Hz to 150 Hz resource usage is detailed in each CapSense component in PSoC Creator. (cid:132)Ability to invert LCD display for negative image A capacitive sensing method using a delta-sigma modulator (cid:132)Three LCD driver drive modes, allowing power optimization (CSD) is used. It provides capacitance sensing using a switched capacitor technique with a delta-sigma modulator to convert the Figure 8-7. LCD System sensing current to a digital code. LCD Global DAC 8.6 Temp Sensor Clock Die temperature is used to establish programming parameters for writing flash. Die temperature is measured using a dedicated sensor based on a forward biased transistor. The temperature UDB PIN sensor has its own auxiliary ADC. LCD Driver Block Display DMA RAM PHUB Document Number: 001-56955 Rev. *K Page 57 of 120

® PSoC 3: CY8C32 Family Data Sheet 8.7 DAC (cid:132)Source and sink option for current output The CY8C32 parts contain a Digital to Analog Converter (DAC). (cid:132)8 Msps conversion rate for current output The DAC is 8-bit and can be configured for either voltage or current output. The DAC supports CapSense, power supply (cid:132)1 Msps conversion rate for voltage output regulation, and waveform generation. The DAC has the following (cid:132)Monotonic in nature features: (cid:132)Data and strobe inputs can be provided by the CPU or DMA, (cid:132)Adjustable voltage or current output in 255 steps or routed directly from the DSI (cid:132)Programmable step size (range selection) (cid:132)Dedicated low-resistance output pin for high-current mode (cid:132)Eight bits of calibration to correct ± 25 percent of gain error Figure 8-8. DAC Block Diagram I Range  source  1x, 8x, 64x Vout  Reference  Scaler   Iout  R  Source        3R    I Range     sink  1x, 8x, 64x  8.7.1 Current DAC 8.7.2 Voltage DAC The current DAC (IDAC) can be configured for the ranges 0 to For the voltage DAC (VDAC), the current DAC output is routed 32 µA, 0 to 256 µA, and 0 to 2.048 mA. The IDAC can be through resistors. The two ranges available for the VDAC are 0 configured to source or sink current. to 1.024V and 0 to 4.096V. In voltage mode any load connected to the output of a DAC should be purely capacitive (the output of the VDAC is not buffered). Document Number: 001-56955 Rev. *K Page 58 of 120

® PSoC 3: CY8C32 Family Data Sheet 9. Programming, Debug Interfaces, security not possible with multichip application solutions. Resources Additionally, all device interfaces can be permanently disabled (Device Security) for applications concerned about phishing attacks due to a maliciously reprogrammed device. Permanently PSoC devices include extensive support for programming, disabling interfaces is not recommended in most applications testing, debugging, and tracing both hardware and firmware. because you cannot access the device later. Because all Three interfaces are available: JTAG, SWD, and SWV. JTAG and programming, debug, and test interfaces are disabled when SWD support all programming and debug features of the device. Device Security is enabled, PSoCs with Device Security enabled JTAG also supports standard JTAG scan chains for board level may not be returned for failure analysis. test and chaining multiple JTAG devices to a single JTAG connection. Table 9-1. Debug Configurations For more information on PSoC 3 Programming, refer to the Debug and Trace Configuration GPIO Pins Used application note AN62391 - In-System Programming for PSoC®3. All debug and trace disabled 0 Complete Debug on Chip (DoC) functionality enables full device JTAG 4 or 5 debugging in the final system using the standard production SWD 2 device. It does not require special interfaces, debugging pods, SWV 1 simulators, or emulators. Only the standard programming connections are required to fully support debug. SWD + SWV 3 The PSoC Creator IDE software provides fully integrated programming and debug support for PSoC devices. The low cost 9.1 JTAG Interface MiniProg3 programmer and debugger is designed to provide full The IEEE 1149.1 compliant JTAG interface exists on four or five programming and debug support of PSoC devices in conjunction pins (the nTRST pin is optional). The JTAG clock frequency can with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV be up to 8 MHz, or 1/3 of the CPU clock frequency for 8 and 16-bit interfaces are fully compatible with industry standard third party transfers, or 1/5 of the CPU clock frequency for 32-bit transfers, tools. whichever is least. By default, the JTAG pins are enabled on new All DOC circuits are disabled by default and can only be enabled devices but the JTAG interface can be disabled, allowing these in firmware. If not enabled, the only way to reenable them is to pins to be used as General Purpose I/O (GPIO) instead. The erase the entire device, clear flash protection, and reprogram the JTAG interface is used for programming the flash memory, device with new firmware that enables DOC. Disabling DOC debugging, I/O scan chains, and JTAG device chaining. features, robust flash protection, and hiding custom analog and digital functionality inside the PSoC device provide a level of Document Number: 001-56955 Rev. *K Page 59 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 9-1. JTAG Interface Connections between PSoC 3 and Programmer V DD Host Programmer PSoC 3 VDD V , V , V , V , V , V 1, 2, 3, 4 DDD DDA DDIO0 DDIO1 DDIO2 DDIO3 TCK TCK (P1[1] TMS  5 TMS (P1[0])  5 TDO TDI (P1[4]) TDI TDO (P1[3]) nTRST 6 nTRST (P1[5]) 6 XRES XRES or P1[2] 4, 7 GND V , V SSD SSA GND 1 The voltage levels of Host Programmer and the PSoC 3 voltage domains involved in Programming should be same. The Port 1 JTAG pins, XRES pin (XRES_N or P1[2]) are powered by V . So, V of PSoC 3 should be at same voltage DDIO1 DDIO1 level as host V . Rest of PSoC 3 voltage domains ( V , V , V , V , V ) need not be at the same voltage level as DD DDD DDA DDIO0 DDIO2 DDIO3 host Programmer. 2 Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3. 3 For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external interface circuitry to toggle power which will depend on the programming setup. The power supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other supplies. 4 For JTAG Programming, Device reset can also be done without connecting to the XRES pin or Power cycle mode by using the TMS,TCK,TDI, TDO pins of PSoC 3, and writing to a specific register. But this requires that the DPS setting in NVL is not equal to “Debug Ports Disabled”. 5 By default, PSoC 3 is configured for 4-wire JTAG mode unless user changes the DPS setting. So the TMS pin is unidirectional. But if the DPS setting is changed to non-JTAG mode, the TMS pin in JTAG is bi-directional as the SWD Protocol has to be used for acquiring the PSoC 3 device initially. After switching from SWD to JTAG mode, the TMS pin will be uni-directional. In such a case, unidirectional buffer should not be used on TMS line. 6 nTRST JTAG pin (P1[5]) cannot be used to reset the JTAG TAP controlller during first time programming of PSoC 3 as the default setting is 4-wire JTAG (nTRST disabled). Use the TMS, TCK pins to do a reset of JTAG TAP controller. 7 If XRES pin is used by host, P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES pin). For devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48-pin devices, but use dedicated XRES pin for rest of devices. Document Number: 001-56955 Rev. *K Page 60 of 120

® PSoC 3: CY8C32 Family Data Sheet 9.2 Serial Wire Debug Interface SWD can be enabled on only one of the pin pairs at a time. This only happens if, within 8 µs (key window) after reset, that pin pair The SWD interface is the preferred alternative to the JTAG (JTAG or USB) receives a predetermined sequence of 1s and 0s. interface. It requires only two pins instead of the four or five SWD is used for debugging or programming the flash memory. needed by JTAG. SWD provides all of the programming and debugging features of JTAG at the same speed. SWD does not The SWD interface can be enabled from the JTAG interface or provide access to scan chains or device chaining. The SWD disabled, allowing its pins to be used as GPIO. Unlike JTAG, the clock frequency can be up to 1/3 of the CPU clock frequency. SWD interface can always be reacquired on any device during the key window. It can then be used to reenable the JTAG SWD uses two pins, either two of the JTAG pins (TMS and TCK) interface, if desired. When using SWD or JTAG pins as standard or the USBIO D+ and D– pins. The USBIO pins are useful for in GPIO, make sure that the GPIO functionality and PCB circuits do system programming of USB solutions that would otherwise not interfere with SWD or JTAG use. require a separate programming connector. One pin is used for the data clock and the other is used for data input and output. Figure 9-2. SWD Interface Connections between PSoC 3 and Programmer V DD Host Programmer PSoC 3 VDD VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3 1, 2, 3 SWDCK SWDCK (P1[1] or P15[7]) SWDIO SWDIO (P1[0] or P15[6]) XRES XRES or P1[2]  3, 4 GND V , V SSD SSA GND 1 The voltage levels of the Host Programmer and the PSoC 3 voltage domains involved in Programming should be the same. XRES pin (XRES_N or P1[2]) is powered by V . The USB SWD pins are DDIO1 powered by V . So for Programming using the USB SWD pins with XRES pin, the V , V of DDD DDD DDIO1  PSoC 3 should be at the same voltage level as Host V . Rest of PSoC 3 voltage domains ( V , V ,   DD DDA DDIO0     V , V ) need not be at the same voltage level as host Programmer. The Port 1 SWD pins are DDIO2 DDIO3 powered by V . So V of PSoC 3 should be at same voltage level as host V for Port 1 SWD DDIO1 DDIO1 DD programming. Rest of PSoC 3 voltage domains ( V ,  V , V , V , V ) need not be at the same DDD DDA DDIO0 DDIO2 DDIO3 voltage level as host Programmer. 2 Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3. 3 For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external interface circuitry to toggle power which will depend on the programming setup. The power supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other supplies. 4 P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES pin). For devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48- pin devices, but use dedicated XRES pin for rest of devices. Document Number: 001-56955 Rev. *K Page 61 of 120

® PSoC 3: CY8C32 Family Data Sheet 9.3 Debug Features verified. You can increase flash protection levels to protect firmware IP. Flash protection can only be reset after a full device Using the JTAG or SWD interface, the CY8C32 supports the erase. Individual flash blocks can be erased, programmed, and following debug features: verified, if block security settings permit. (cid:132)Halt and single-step the CPU 9.7 Device Security (cid:132)View and change CPU and peripheral registers, and RAM addresses PSoC 3 offers an advanced security feature called device security, which permanently disables all test, programming, and (cid:132)Eight program address breakpoints debug ports, protecting your application from external access. (cid:132)One memory access breakpoint—break on reading or writing The device security is activated by programming a 32-bit key any memory address and data value (0×50536F43) to a Write Once Latch (WOL). (cid:132)Break on a sequence of breakpoints (non recursive) The Write Once Latch is a type of nonvolatile latch (NVL). The (cid:132)Debugging at the full speed of the CPU cell itself is an NVL with additional logic wrapped around it. Each WOL device contains four bytes (32 bits) of data. The wrapper (cid:132)Debug operations are possible while the device is reset, or in outputs a ‘1’ if a super-majority (28 of 32) of its bits match a low-power modes pre-determined pattern (0×50536F43); it outputs a ‘0’ if this (cid:132)Compatible with PSoC Creator and MiniProg3 programmer and majority is not reached. When the output is 1, the Write Once NV debugger latch locks the part out of Debug and Test modes; it also permanently gates off the ability to erase or alter the contents of (cid:132)Standard JTAG programming and debugging interfaces make the latch. Matching all bits is intentionally not required, so that CY8C32 compatible with other popular third-party tools (for single (or few) bit failures do not deassert the WOL output. The example, ARM / Keil) state of the NVL bits after wafer processing is truly random with 9.4 Trace Features no tendency toward 1 or 0. The WOL only locks the part after the correct 32-bit key The CY8C32 supports the following trace features when using (0×50536F43) is loaded into the NVL's volatile memory, JTAG or SWD: programmed into the NVL's nonvolatile cells, and the part is (cid:132)Trace the 8051 program counter (PC), accumulator register reset. The output of the WOL is only sampled on reset and used (ACC), and one SFR / 8051 core RAM register to disable the access. This precaution prevents anyone from (cid:132)Trace depth up to 1000 instructions if all registers are traced, reading, erasing, or altering the contents of the internal memory. or 2000 instructions if only the PC is traced (on devices that The user can write the key into the WOL to lock out external include trace memory) access only if no flash protection is set (see “Flash Security” on (cid:132)Program address trigger to start tracing page22). However, after setting the values in the WOL, a user (cid:132)Trace windowing, that is, only trace when the PC is within a still has access to the part until it is reset. Therefore, a user can given range write the key into the WOL, program the flash protection data, and then reset the part to lock it. (cid:132)Two modes for handling trace buffer full: continuous (overwriting the oldest trace data) or break when trace buffer is full If the device is protected with a WOL setting, Cypress cannot perform failure analysis and, therefore, cannot accept RMAs 9.5 Single Wire Viewer Interface from customers. The WOL can be read out via SWD port to electrically identify protected parts. The user can write the key in The SWV interface is closely associated with SWD but can also WOL to lock out external access only if no flash protection is set. be used independently. SWV data is output on the JTAG For more information on how to take full advantage of the interface’s TDO pin. If using SWV, you must configure the device security features in PSoC see the PSoC 3 TRM. for SWD, not JTAG. SWV is not supported with the JTAG interface. Disclaimer SWV is ideal for application debug where it is helpful for the Note the following details of the flash code protection features on firmware to output data similar to 'printf' debugging on PCs. The Cypress devices. SWV is ideal for data monitoring, because it requires only a Cypress products meet the specifications contained in their single pin and can output data in standard UART format or particular Cypress datasheets. Cypress believes that its family of Manchester encoded format. For example, it can be used to tune products is one of the most secure families of its kind on the a PID control loop in which the output and graphing of the three market today, regardless of how they are used. There may be error terms greatly simplifies coefficient tuning. methods, unknown to Cypress, that can breach the code The following features are supported in SWV: protection features. Any of these methods, to our knowledge, (cid:132)32 virtual channels, each 32 bits long would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of (cid:132)Simple, efficient packing and serializing protocol their code. Code protection does not mean that we are (cid:132)Supports standard UART format (N81) guaranteeing the product as “unbreakable.” 9.6 Programming Features Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly The JTAG and SWD interfaces provide full programming evolving. We at Cypress are committed to continuously support. The entire device can be erased, programmed, and improving the code protection features of our products. Document Number: 001-56955 Rev. *K Page 62 of 120

® PSoC 3: CY8C32 Family Data Sheet 10. Development Support Application Notes: PSoC application notes discuss a particular application of PSoC in depth; examples include brushless DC The CY8C32 family has a rich set of documentation, motor control and on-chip filtering. Application notes often development tools, and online resources to assist you during include example projects in addition to the application note your development process. Visit document. psoc.cypress.com/getting-started to find out more. Technical Reference Manual: The Technical Reference Manual (TRM) contains all the technical detail you need to use a PSoC 10.1 Documentation device, including a complete description of all PSoC registers. A suite of documentation, supports the CY8C32 family to ensure that you can find answers to your questions quickly. This section 10.2 Online contains a list of some of the key documents. In addition to print documentation, the Cypress PSoC forums Software User Guide: A step-by-step guide for using PSoC connect you with fellow PSoC users and experts in PSoC from Creator. The software user guide shows you how the PSoC around the world, 24 hours a day, 7 days a week. Creator build process works in detail, how to use source control 10.3 Tools with PSoC Creator, and much more. Component Datasheets: The flexibility of PSoC allows the With industry standard cores, programming, and debugging creation of new peripherals (components) long after the device interfaces, the CY8C32 family is part of a development tool has gone into production. Component datasheets provide all of ecosystem. Visit us at www.cypress.com/go/psoccreator for the the information needed to select and use a particular component, latest information on the revolutionary, easy to use PSoC Creator including a functional description, API documentation, example IDE, supported third party compilers, programmers, debuggers, code, and AC/DC specifications. and development kits. Document Number: 001-56955 Rev. *K Page 63 of 120

® PSoC 3: CY8C32 Family Data Sheet 11. Electrical Specifications Specifications are valid for –40°C ≤ T ≤ 85°C and T ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, see the component datasheets for full AC/DC specifications of individual functions. See the “Example Peripherals” section on page41 for further explanation of PSoC Creator components. 11.1 Absolute Maximum Ratings Table 11-1. Absolute Maximum Ratings DC Specifications Parameter Description Conditions Min Typ Max Units T Storage temperature Higher storage temperatures –55 25 100 °C STG reduce NVL data retention time. Recommended storage temper- ature is +25 °C ±25 °C. Extended duration storage temperatures above 85 °C degrade reliability. V Analog supply voltage relative to –0.5 – 6 V DDA V SSA V Digital supply voltage relative to –0.5 – 6 V DDD V SSD V I/O supply voltage relative to V –0.5 – 6 V DDIO SSD V Direct analog core voltage input –0.5 – 1.95 V CCA V Direct digital core voltage input –0.5 – 1.95 V CCD V Analog ground voltage V –0.5 – V + V SSA SSD SSD 0.5 V [14] DC input voltage on GPIO Includes signals sourced by V V –0.5 – V + V GPIO DDA SSD DDIO and routed internal to the pin 0.5 V DC input voltage on SIO Output disabled V –0.5 – 7 V SIO SSD Output enabled V –0.5 – 6 V SSD V Voltage at boost converter input 0.5 – 5.5 V IND V Boost converter supply V –0.5 – 5.5 V BAT SSD Ivddio Current per V supply pin – – 100 mA DDIO Vextref ADC external reference inputs Pins P0[3], P3[2] – – 2 V LU Latch up current[15] –140 – 140 mA ESD Electrostatic discharge voltage Human body model 750 – – V HBM ESD Electrostatic discharge voltage Charge device model 500 – – V CDM Note Usage above the absolute maximum conditions listed in Table11-1 may cause permanent damage to the device. Exposure to maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above normal operating conditions the device may not operate to specification. Notes 14.The VDDIO supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ VDDIO ≤ VDDA. 15.Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test. Document Number: 001-56955 Rev. *K Page 64 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.2 Device Level Specifications Specifications are valid for –40°C ≤ T ≤ 85°C and T ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter Description Conditions Min Typ Max Units V Analog supply voltage and input to Analog core regulator enabled 1.8 – 5.5 V DDA analog core regulator V Analog supply voltage, analog Analog core regulator disabled 1.71 1.8 1.89 V DDA regulator bypassed V Digital supply voltage relative to Digital core regulator enabled 1.8 – V [16] V DDD DDA V SSD V Digital supply voltage, digital Digital core regulator disabled 1.71 1.8 1.89 V DDD regulator bypassed V [17] I/IO supply voltage relative to V 1.71 – V [16] V DDIO SSIO DDA V Direct analog core voltage input Analog core regulator disabled 1.71 1.8 1.89 V CCA (Analog regulator bypass) V Direct digital core voltage input Digital core regulator disabled 1.71 1.8 1.89 V CCD (Digital regulator bypass) I [18] Active Mode, V = 1.71V–5.5V DD DD Bus clock off. Execute from CPU CPU at 3 MHz T = –40°C – – – mA instruction buffer. See “Flash T = 25°C – 0.8 – mA Program Memory” on page22. T = 85°C – – – mA CPU at 6 MHz T = –40°C – – – mA T = 25°C – 1.2 – mA T = 85°C – – – mA CPU at 12 MHz T = –40°C – – – mA T = 25°C – 2.0 – mA T = 85°C – – – mA CPU at 24 MHz T = –40°C – – – mA T = 25°C – 3.5 – mA T = 85°C – – – mA CPU at 48 MHz T = –40°C – – – mA T = 25°C – 6.6 – mA T = 85°C – – – mA V = 3.3 V, T = 25 °C, IMO and bus CPU at 3 MHz – 1.4 – mA DD clock enabled, ILO = 1 kHz, CPU CPU at 6 MHz – 2.2 – mA executing from flash and accessing SRAM, all other blocks off, all I/Os CPU at 12 MHz – 3.6 – mA tied low. CPU at 24 MHz – 6.4 – mA CPU at 48 MHz – 11.8 – mA Notes 16.The power supplies can be brought up in any sequence however once stable VDDA must be greater than or equal to all other supplies. 17.The VDDIO supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ VDDIO ≤ VDDA. 18.The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular system from the device datasheet and component datasheets. Document Number: 001-56955 Rev. *K Page 65 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 11-2. DC Specifications (continued) Parameter Description Conditions Min Typ Max Units Sleep Mode[20] CPU = OFF VDD = VDDIO = 4.5–5.5V T = –40°C – – – µA RTC = ON (= ECO32K ON, in T = 25°C – – – µA low-power mode) Sleep timer = ON (= ILO ON at T = 85°C – – – µA 1kHz)[21] V = V = 2.7–3.6V T = –40°C – – – µA DD DDIO WDT = OFF I2C Wake = OFF T = 25°C – 1 – µA Comparator = OFF T = 85°C – – – µA POR = ON V = V = 1.71–1.95V T = –40°C – – – µA DD DDIO Boost = OFF SIO pins in single ended input, T = 25°C – – – µA unregulated output mode T = 85°C – – – µA Comparator = ON V = V = 2.7–3.6V T = 25°C – – – µA DD DDIO CPU = OFF RTC = OFF Sleep timer = OFF WDT = OFF I2C Wake = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode I2C Wake = ON V = V = 2.7–3.6V T= 25°C – – – µA DD DDIO CPU = OFF RTC = OFF Sleep timer = OFF WDT = OFF Comparator = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode Hibernate Mode[20] V = V = 4.5–5.5V T = –40°C – – – nA DD DDIO T = 25°C – – – nA Hibernate mode current T = 85°C – – – nA All regulators and oscillators off. V = V = 2.7–3.6V T = –40°C – – – nA SRAM retention DD DDIO GPIO interrupts are active T = 25°C – 200 – nA Boost = OFF T = 85°C – – – nA SIO pins in single ended input, unregulated output mode VDD = VDDIO = 1.71–1.95V T = –40°C – – – nA T = 25°C – – – nA T = 85°C – – – nA Notes 19.The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in PSoC Creator, the integrated design environment. To compute total current, find CPU current at frequency of interest and add peripheral currents for your particular system from the device datasheet and component datasheets. 20.If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV. 21.Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off. Document Number: 001-56955 Rev. *K Page 66 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 11-1. Active Mode Current vs F , V = 3.3 V, Figure 11-2. Active Mode Current vs Temperature and F , CPU DD CPU Temperature = 25 °C V = 3.3 V DD Figure 11-3. Active Mode Current vs V and Temperature, DD F = 24 MHz CPU Document Number: 001-56955 Rev. *K Page 67 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 11-3. AC Specifications[22] Parameter Description Conditions Min Typ Max Units F CPU frequency 1.71V ≤ V ≤ 5.5V DC – 50.01 MHz CPU DDD F Bus frequency 1.71V ≤ V ≤ 5.5V DC – 50.01 MHz BUSCLK DDD Svdd V ramp rate – – 1 V/ns DD T Time from V /V /V /V – – 10 µs IO_INIT DDD DDA CCD CCA ≥ IPOR to I/O ports set to their reset states T Time from V /V /V /V V /V = regulated from – – 66 µs STARTUP DDD DDA CCD CCA CCA CCD ≥ PRES to CPU executing code at V /V , no PLL used, IMO DDA DDD reset vector boot mode (12 MHz typ.) T Wakeup from sleep mode – – – 15 µs SLEEP Application of non-LVD interrupt to beginning of execution of next CPU instruction T Wakeup from hibernate mode – – – 100 µs HIBERNATE Application of external interrupt to beginning of execution of next CPU instruction Figure 11-4. F vs. V CPU DD 5.5 V Valid Operating Region ge3.3 V a olt V d d V 1.71 V Valid Operating Region with SMP 0.5 V 0 V DC 1 MHz 10 MHz 50 MHz CPU Frequency Note 22.Based on device characterization (Not production tested). Document Number: 001-56955 Rev. *K Page 68 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.3 Power Regulators Specifications are valid for –40°C ≤ T ≤ 85°C and T ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description Conditions Min Typ Max Units V Input voltage 1.8 – 5.5 V DDD V Output voltage – 1.80 – V CCD Regulator output capacitor ±10%, X5R ceramic or better. The two – 1 – µF V pins must be shorted together, with CCD as short a trace as possible, see Power System on page 29 Figure 11-5. Regulators V vs V Figure 11-6. Digital Regulator PSRR vs Frequency and V CC DD DD 11.3.2 Analog Core Regulator Table 11-5. Analog Core Regulator DC Specifications Parameter Description Conditions Min Typ Max Units V Input voltage 1.8 – 5.5 V DDA V Output voltage – 1.80 – V CCA Regulator output capacitor ±10%, X5R ceramic or better – 1 – µF Figure 11-7. Analog Regulator PSRR vs Frequency and V DD Document Number: 001-56955 Rev. *K Page 69 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.3.3 Inductive Boost Regulator. Table 11-6. Inductive Boost Regulator DC Specifications Unless otherwise specified, operating conditions are: V = 2.4 V, V = 2.7 V, I = 40 mA, F = 400 kHz, L = 10µH, BAT OUT OUT SW BOOST C = 22µF || 0.1µF BOOST Parameter Description Conditions Min Typ Max Units V Input voltage T=-35°C to +65°C 0.5 – 3.6 V BAT Includes startup Over entire temperature range 0.68 – 3.6 V I Load current[23, 24] V = 1.6 – 3.6 V, V = 3.6 – 5.0 V, – – 50 mA OUT BAT OUT external diode V = 1.6 – 3.6 V, V = 1.6 – 3.6 V, – – 75 mA BAT OUT internal diode V = 0.8 – 1.6 V, V = 1.6 – 3.6 V, – – 30 mA BAT OUT internal diode V = 0.8 – 1.6 V, V = 3.6 – 5.0 V, – – 20 mA BAT OUT external diode V = 0.5 – 0.8 V, V = 1.6 – 3.6 V, – – 15 mA BAT OUT internal diode I Inductor peak current – – 700 mA LPK I Quiescent current Boost active mode – 200 – µA Q Boost standby mode, 32 khz external crystal – 12 – µA oscillator, I < 1 ìA OUT VOUT Boost voltage range[25, 26] 1.8 V 1.71 1.80 1.89 V 1.9 V 1.81 1.90 2.00 V 2.0 V 1.90 2.00 2.10 V 2.4 V 2.28 2.40 2.52 V 2.7 V 2.57 2.70 2.84 V 3.0 V 2.85 3.00 3.15 V 3.3 V 3.14 3.30 3.47 V 3.6 V 3.42 3.60 3.78 V 5.0 V External diode required 4.75 5.00 5.25 V Reg Load regulation – – 3.8 % LOAD Reg Line regulation – – 4.1 % LINE η Efficiency L = 10 µH 70 85 – % BOOST L = 22 µH 82 90 – % BOOST Notes 23.For output voltages above 3.6 V, an external diode is required. 24.Maximum output current applies for output voltages ≤ 4x input voltage. 25.Based on device characterization (Not production tested). 26.At boost frequency of 2 MHz, VOUT is limited to 2 x VBAT. At 400 kHz, VOUT is limited to 4 x VBAT. Document Number: 001-56955 Rev. *K Page 70 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 11-7. Inductive Boost Regulator AC Specifications Unless otherwise specified, operating conditions are: V = 2.4 V, V = 2.7 V, I = 40 mA, F = 400 kHz, L = 10µH, BAT OUT OUT SW BOOST C = 22µF || 0.1µF. BOOST Parameter Description Conditions Min Typ Max Units V Ripple voltage (peak-to-peak) V = 1.8V, F = 400 kHz, I = 10 mA – – 100 mV RIPPLE OUT SW OUT F Switching frequency – 0.1, 0.4, – MHz SW or 2 Table 11-8. Recommended External Components for Boost Circuit Parameter Description Conditions Min Typ Max Units L Boost inductor 4.7 10 47 µH BOOST C Filter capacitor[27] 10 22 47 µF BOOST I External Schottky diode External Schottky diode is required for 1 – – A F average forward current V > 3.6 V OUT V 20 – – V R Note 27.Based on device characterization (Not production tested). Document Number: 001-56955 Rev. *K Page 71 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 11-8. Efficiency vs V Figure 11-9. Efficiency vs V OUT BAT I = 30 mA, V ranges from 0.7 V to V , L = 22 µH I = 30 mA, V = 3.3 V, L = 22 µH OUT BAT OUT BOOST OUT OUT BOOST Figure 11-10. Efficiency vs I Figure 11-11. Efficiency vs I OUT OUT V = 2.4 V, V = 3.3 V V ranges from 0.7 V to 3.3 V, L = 22 µH BAT OUT BAT BOOST Figure 11-12. Efficiency vs Switching Frequency V = 3.3 V, V = 2.4 V, I = 40 mA OUT BAT OUT Document Number: 001-56955 Rev. *K Page 72 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.1 Inputs and Outputs Specifications are valid for –40°C ≤ T ≤ 85°C and T ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. Unless otherwise specified, all charts and graphs show typical values. 11.1.1 GPIO Table 11-9. GPIO DC Specifications Parameter Description Conditions Min Typ Max Units V Input voltage high threshold CMOS Input, PRT[×]CTL = 0 0.7 × V – – V IH DDIO V Input voltage low threshold CMOS Input, PRT[×]CTL = 0 – – 0.3 × V V IL DDIO V Input voltage high threshold LVTTL Input, PRT[×]CTL = 0.7 × V – – V IH DDIO 1, V < 2.7V DDIO V Input voltage high threshold LVTTL Input, PRT[×]CTL = 2.0 – – V IH 1, V ≥ 2.7V DDIO V Input voltage low threshold LVTTL Input, PRT[×]CTL = – – 0.3 × V V IL DDIO 1, V < 2.7V DDIO V Input voltage low threshold LVTTL Input, PRT[×]CTL = – – 0.8 V IL 1, V ≥ 2.7V DDIO V Output voltage high I = 4 mA at 3.3 V V – 0.6 – – V OH OH DDIO DDIO I = 1 mA at 1.8 V V – 0.5 – – V OH DDIO DDIO V Output voltage low I = 8 mA at 3.3 V – – 0.6 V OL OL DDIO I = 4 mA at 1.8 V – – 0.6 V OL DDIO Rpullup Pull-up resistor 3.5 5.6 8.5 kΩ Rpulldown Pull-down resistor 3.5 5.6 8.5 kΩ I Input leakage current (absolute value)[29] 25°C, V = 3.0 V – – 2 nA IL DDIO C Input capacitance[29] – – 7 pF IN V Input voltage hysteresis (Schmitt-Trigger)[29] – 40 – mV H Idiode Current through protection diode to V and – – 100 µA DDIO V SSIO Rglobal Resistance pin to analog global bus 25°C, V = 3.0 V – 320 – Ω DDIO Rmux Resistance pin to analog mux bus 25°C, V = 3.0 V – 220 – Ω DDIO Figure 11-13. GPIO Output High Voltage and Current Figure 11-14. GPIO Output Low Voltage and Current Note 28.Based on device characterization (Not production tested). Document Number: 001-56955 Rev. *K Page 73 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 11-10. GPIO AC Specifications Parameter Description Conditions Min Typ Max Units TriseF Rise time in Fast Strong Mode[29] 3.3V V Cload = 25 pF – – 12 ns DDIO TfallF Fall time in Fast Strong Mode[29] 3.3V V Cload = 25 pF – – 12 ns DDIO TriseS Rise time in Slow Strong Mode[29] 3.3V V Cload = 25 pF – – 60 ns DDIO TfallS Fall time in Slow Strong Mode[29] 3.3V V Cload = 25 pF – – 60 ns DDIO GPIO output operating frequency 2.7V < V < 5.5V, fast strong drive mode 90/10% V into 25 pF – – 33 MHz DDIO DDIO Fgpioout 1.71V < V < 2.7V, fast strong drive mode 90/10% V into 25 pF – – 20 MHz DDIO DDIO 3.3V < V < 5.5V, slow strong drive mode 90/10% V into 25 pF – – 7 MHz DDIO DDIO 1.71V < V < 3.3V, slow strong drive mode 90/10% V into 25 pF – – 3.5 MHz DDIO DDIO GPIO input operating frequency Fgpioin 1.71V < V < 5.5V 90/10% V – – 50 MHz DDIO DDIO Figure 11-15. GPIO Output Rise and Fall Times, Fast Strong Figure 11-16. GPIO Output Rise and Fall Times, Slow Strong Mode, V = 3.3 V, 25 pF Load Mode, V = 3.3 V, 25 pF Load DDIO DDIO Note 29.Based on device characterization (Not production tested). Document Number: 001-56955 Rev. *K Page 74 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.1.2 SIO Table 11-11. SIO DC Specifications Parameter Description Conditions Min Typ Max Units Vinmax Maximum input voltage All allowed values of Vddio and – – 5.5 V Vddd, see Section11.2.1 Vinref Input voltage reference (Differ- 0.5 – 0.52 × V V DDIO ential input mode) Output voltage reference (Regulated output mode) Voutref V > 3.7 1 – V – 1 V DDIO DDIO V < 3.7 1 – V – 0.5 V DDIO DDIO Input voltage high threshold V GPIO mode CMOS input 0.7 × V – – V IH DDIO Differential input mode[30] Hysteresis disabled SIO_ref + 0.2 – – V Input voltage low threshold V GPIO mode CMOS input – – 0.3 × V V IL DDIO Differential input mode[30] Hysteresis disabled – – SIO_ref – 0.2 V Output voltage high Unregulated mode I = 4 mA, V = 3.3V V – 0.4 – – V OH DDIO DDIO V OH Regulated mode[30] I = 1 mA SIO_ref – 0.65 – SIO_ref + 0.2 V OH Regulated mode[30] I = 0.1 mA SIO_ref – 0.3 – SIO_ref + 0.2 V OH Output voltage low V V = 3.30 V, I = 25 mA – – 0.8 V OL DDIO OL V = 1.80 V, I = 4 mA – – 0.4 V DDIO OL Rpullup Pull-up resistor 3.5 5.6 8.5 kΩ Rpulldown Pull-down resistor 3.5 5.6 8.5 kΩ I Input leakage current (absolute IL value)[31] V < Vddsio 25°C, Vddsio = 3.0 V, V = 3.0 V – – 14 nA IH IH V > Vddsio 25°C, Vddsio = 0 V, V = 3.0 V – – 10 µA IH IH C Input Capacitance[31] – – 7 pF IN Input voltage hysteresis Single ended mode (GPIO mode) – 40 – mV VH (Schmitt-Trigger)[31] Differential mode – 35 – mV Current through protection diode – – 100 µA Idiode to V SSIO Notes 30.See Figure 6-9 on page 36 and Figure 6-12 on page 39 for more information on SIO reference 31.Based on device characterization (Not production tested). Document Number: 001-56955 Rev. *K Page 75 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 11-17. SIO Output HighVoltage and Current, Figure 11-18. SIO Output Low Voltage and Current, Unregulated Mode Unregulated Mode Figure 11-19. SIO Output High Voltage and Current, Regulated Mode Table 11-12. SIO AC Specifications Parameter Description Conditions Min Typ Max Units TriseF Rise time in Fast Strong Mode Cload = 25 pF, V = 3.3V – – 12 ns DDIO (90/10%)[32] TfallF Fall time in Fast Strong Mode Cload = 25 pF, V = 3.3V – – 12 ns DDIO (90/10%)[32] TriseS Rise time in Slow Strong Mode Cload = 25 pF, V = 3.0 V – – 75 ns DDIO (90/10%)[32] TfallS Fall time in Slow Strong Mode Cload = 25 pF, V = 3.0 V – – 60 ns DDIO (90/10%)[32] Note 32.Based on device characterization (Not production tested). Document Number: 001-56955 Rev. *K Page 76 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 11-12. SIO AC Specifications (continued) Parameter Description Conditions Min Typ Max Units SIO output operating frequency 2.7V < V < 5.5V, Unregu- 90/10% V into 25 pF – – 33 MHz DDIO DDIO lated output (GPIO) mode, fast strong drive mode 1.71V < V < 2.7V, Unregu- 90/10% V into 25 pF – – 16 MHz DDIO DDIO lated output (GPIO) mode, fast strong drive mode 3.3V < V < 5.5V, Unregu- 90/10% V into 25 pF – – 5 MHz DDIO DDIO lated output (GPIO) mode, slow strong drive mode 1.71V < V < 3.3V, Unregu- 90/10% V into 25 pF – – 4 MHz Fsioout DDIO DDIO lated output (GPIO) mode, slow strong drive mode 2.7V < V < 5.5V, Regulated Output continuously switching – – 20 MHz DDIO output mode, fast strong drive into 25 pF mode 1.71V < V < 2.7V, Regulated Output continuously switching – – 10 MHz DDIO output mode, fast strong drive into 25 pF mode 1.71V < V < 5.5V, Regulated Output continuously switching – – 2.5 MHz DDIO output mode, slow strong drive into 25 pF mode SIO input operating frequency Fsioin 1.71V < V < 5.5V 90/10% V – – 50 MHz DDIO DDIO Figure 11-20. SIO Output Rise and Fall Times, Fast Strong Figure 11-21. SIO Output Rise and Fall Times, Slow Strong Mode, V = 3.3 V, 25 pF Load Mode, V = 3.3 V, 25 pF Load DDIO DDIO Document Number: 001-56955 Rev. *K Page 77 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.1.3 USBIO For operation in GPIO mode, the standard range for V applies, see Device Level Specifications on page 65. DDD Table 11-13. USBIO DC Specifications Parameter Description Conditions Min Typ Max Units Rusbi USB D+ pull-up resistance With idle bus 0.900 – 1.575 kΩ Rusba USB D+ pull-up resistance While receiving traffic 1.425 – 3.090 kΩ Vohusb Static output high 15 kΩ ±5% to Vss, internal pull-up 2.8 – 3.6 V enabled Volusb Static output low 15 kΩ ±5% to Vss, internal pull-up – – 0.3 V enabled Vohgpio Output voltage high, GPIO mode I = 4 mA, V ≥ 3V 2.4 – – V OH DDD Volgpio Output voltage low, GPIO mode I = 4 mA, V ≥ 3V – – 0.3 V OL DDD Vdi Differential input sensitivity |(D+)–(D–)| – – 0.2 V Vcm Differential input common mode – 0.8 – 2.5 V range Vse Single ended receiver threshold – 0.8 – 2 V Rps2 PS/2 pull-up resistance In PS/2 mode, with PS/2 pull-up 3 – 7 kΩ enabled External USB series resistor In series with each USB pin 21.78 22 22.22 Ω Rext (–1%) (+1%) Zo USB driver output impedance Including Rext 28 – 44 Ω C USB transceiver input capacitance – – – 20 pF IN Input leakage current (absolute 25°C, V = 3.0 V – – 2 nA I DDD IL value) Figure 11-22. USBIO Output High Voltage and Current, GPIO Figure 11-23. USBIO Output Low Voltage and Current, GPIO Mode Mode Document Number: 001-56955 Rev. *K Page 78 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 11-14. USBIO AC Specifications Parameter Description Conditions Min Typ Max Units Tdrate Full-speed data rate average bit rate 12 – 0.25% 12 12 + MHz 0.25% Tjr1 Receiver data jitter tolerance to next –8 – 8 ns transition Tjr2 Receiver data jitter tolerance to pair –5 – 5 ns transition Tdj1 Driver differential jitter to next –3.5 – 3.5 ns transition Tdj2 Driver differential jitter to pair transition –4 – 4 ns Tfdeop Source jitter for differential transition to –2 – 5 ns SE0 transition Tfeopt Source SE0 interval of EOP 160 – 175 ns Tfeopr Receiver SE0 interval of EOP 82 – – ns Tfst Width of SE0 interval during differ- – – 14 ns ential transition Fgpio_out GPIO mode output operating 3V ≤ V ≤ 5.5V – – 20 MHz DDD frequency V = 1.71V – – 6 MHz DDD Tr_gpio Rise time, GPIO mode, 10%/90% V > 3V, 25 pF load – – 12 ns DDD VDDD VDDD = 1.71V, 25 pF load – – 40 ns Tf_gpio Fall time, GPIO mode, 90%/10% V V > 3V, 25 pF load – – 12 ns DDD DDD V = 1.71V, 25 pF load – – 40 ns DDD Figure 11-24. USBIO Output Rise and Fall Times, GPIO Mode, V = 3.3 V, 25 pF Load DDD Table 11-15. USB Driver AC Specifications Parameter Description Conditions Min Typ Max Units Tr Transition rise time – – 20 ns Tf Transition fall time – – 20 ns TR Rise/fall time matching V , V , see USB DC 90% – 111% USB_5 USB_3.3 Specifications on page 95 Vcrs Output signal crossover voltage 1.3 – 2 V Document Number: 001-56955 Rev. *K Page 79 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.1.4 XRES Table 11-16. XRES DC Specifications Parameter Description Conditions Min Typ Max Units V Input voltage high threshold 0.7 × V – – V IH DDIO V Input voltage low threshold – – 0.3 × V IL V DDIO Rpullup Pull-up resistor 3.5 5.6 8.5 kΩ C Input capacitance[33] – 3 – pF IN V Input voltage hysteresis – 100 – mV H (Schmitt-Trigger)[33] Idiode Current through protection diode to – – 100 µA V and V DDIO SSIO Table 11-17. XRES AC Specifications Parameter Description Conditions Min Typ Max Units T Reset pulse width 1 – – µs RESET Document Number: 001-56955 Rev. *K Page 80 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.2 Analog Peripherals Specifications are valid for –40°C ≤ T ≤ 85°C and T ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.2.1 Delta-sigma ADC Unless otherwise specified, operating conditions are: (cid:132)Operation in continuous sample mode (cid:132)fclk = 6.144 MHz (cid:132)Reference = 1.024 V internal reference bypassed on P3.2 or P0.3 (cid:132)Unless otherwise specified, all charts and graphs show typical values Table 11-18. 12-bit Delta-sigma ADC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution 8 – 12 bits No. of Number of channels, single ended – – – GPIO Differential pair is formed using a No. of Number of channels, differential – – – pair of GPIOs. GPIO/2 Monotonic Yes – – – – Buffered, buffer gain = 1, Range = Ge Gain error – – ±0.2 % ±1.024V, 25 °C Buffered, buffer gain = 1, Range = Gd Gain drift – – 50 ppm/°C ±1.024V Buffered, 16-bit mode, V = 2.7V, Vos Input offset voltage DDA – – ±0.1 mV 25 °C Temperature coefficient, input offset Buffer gain = 1, 16-bit, TCVos – – 55 µV/°C voltage Range = ±1.024 V Input voltage range, single ended[34] V – V V SSA DDA Input voltage range, differential unbuf- fered[34] VSSA – VDDA V Input voltage range, differential, buffered[34] VSSA – VDDA – 1 V INL12 Integral non linearity[34] Range = ±1.024V, unbuffered – – ±1 LSB DNL12 Differential non linearity[34] Range = ±1.024V, unbuffered – – ±1 LSB INL8 Integral non linearity[34] Range = ±1.024V, unbuffered – – ±1 LSB DNL8 Differential non linearity[34] Range = ±1.024V, unbuffered – – ±1 LSB Rin_Buff ADC input resistance Input buffer used 10 – – MΩ Rin_ADC12 ADC input resistance Input buffer bypassed, 12 bit, – 148[35] – kΩ Range = ±1.024V ADC external reference input voltage, see Vextref also internal reference in Voltage Pins P0[3], P3[2] 0.9 – 1.3 V Reference on page 83 Current Consumption I Current consumption, 12 bit[34] 192 ksps, unbuffered – – 1.4 mA DD_12 I Buffer current consumption[34] – – 2.5 mA BUFF Notes 34.Based on device characterization (Not production tested). 35.By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual. Document Number: 001-56955 Rev. *K Page 81 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 11-19. Delta-sigma ADC AC Specifications Parameter Description Conditions Min Typ Max Units Startup time – – 4 Samples THD Total harmonic distortion[36] Buffer gain = 1, 16 bit, – – 0.0032 % Range = ±1.024V 12-Bit Resolution Mode SR12 Sample rate, continuous, high power[36] Range = ±1.024V, unbuffered 4 – 192 ksps BW12 Input bandwidth at max sample rate[36] Range = ±1.024V, unbuffered – 44 – kHz SINAD12int Signal to noise ratio, 12-bit, internal Range = ±1.024V, unbuffered 66 – – dB reference[36] 8-Bit Resolution Mode SR8 Sample rate, continuous, high power[36] Range = ±1.024V, unbuffered 8 – 384 ksps BW8 Input bandwidth at max sample rate[36] Range = ±1.024V, unbuffered – 88 – kHz SINAD8int Signal to noise ratio, 8-bit, internal Range = ±1.024V, unbuffered 43 – – dB reference[36] Table 11-20. Delta-sigma ADC Sample Rates, Range = ±1.024V Resolution, Continuous Multi-Sample Bits Min Max Min Max 8 8000 384000 1911 91701 9 6400 307200 1543 74024 10 5566 267130 1348 64673 11 4741 227555 1154 55351 12 4000 192000 978 46900 Figure 11-25. Delta-sigma ADC IDD vs sps, Range = ±1.024 V, Continuous Sample Mode, Input Buffer Bypassed Note 36.Based on device characterization (Not production tested). Document Number: 001-56955 Rev. *K Page 82 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.2.2 Voltage Reference Table 11-21. Voltage Reference Specifications See also ADC external reference specifications in Section11.2.1. Parameter Description Conditions Min Typ Max Units V Precision reference voltage Initial trim 1.014 (–1%) 1.024 1.034 (+1%) V REF 11.2.3 Analog Globals Table 11-22. Analog Globals Specifications Parameter Description Conditions Min Typ Max Units Rppag Resistance pin-to-pin through analog global[37] V = 3.0 V – 939 1461 Ω DDA Rppmuxbus Resistance pin-to-pin through analog mux bus[37] V = 3.0 V – 721 1135 Ω DDA 11.2.4 Comparator Table 11-23. Comparator DC Specifications Parameter Description Conditions Min Typ Max Units Input offset voltage in fast mode Factory trim, Vdda > 2.7 V, – 10 mV V Vin ≥ 0.5 V OS Input offset voltage in slow mode Factory trim, Vin ≥ 0.5 V – 9 mV Input offset voltage in fast mode[38] Custom trim – – 4 mV V OS Input offset voltage in slow mode[38] Custom trim – – 4 mV V Input offset voltage in ultra low-power – ±12 – mV OS mode V Hysteresis Hysteresis enable mode – 10 32 mV HYST V Input common mode voltage High current / fast mode V – V – 0.1 V ICM SSA DDA Low current / slow mode V – V V SSA DDA Ultra low power mode V – V – 0.9 SSA DDA CMRR Common mode rejection ratio – 50 – dB I High current mode/fast mode[39] – – 400 µA CMP Low current mode/slow mode[39] – – 100 µA Ultra low-power mode[39] – 6 – µA Table 11-24. Comparator AC Specifications Parameter Description Conditions Min Typ Max Units Response time, high current mode[39] 50 mV overdrive, measured pin-to-pin – 75 110 ns Tresp Response time, low current mode[39] 50 mV overdrive, measured pin-to-pin – 155 200 ns Response time, ultra low-power mode[39] 50 mV overdrive, measured pin-to-pin – 55 – µs Notes 37.The resistance of the analog global and analog mux bus is high if VDDA ≤ 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog mux bus under these conditions is not recommended 38.The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM. 39.Based on device characterization (Not production tested). Document Number: 001-56955 Rev. *K Page 83 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.2.5 Current Digital-to-analog Converter (IDAC) See the IDAC component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-25. IDAC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution – – 8 bits I Output current at code = 255 Range = 2.048 mA, code = 255, – 2.048 – mA OUT VDDA ≥ 2.7 V, Rload = 600 Ω Range = 2.048 mA, High mode, – 2.048 – mA code = 255, V ≤ 2.7 V, Rload = DDA 300 Ω Range = 255 µA, code = 255, Rload – 255 – µA = 600 Ω Range = 31.875 µA, code = 255, – 31.875 – µA Rload = 600 Ω Monotonicity – – Yes Ezs Zero scale error – 0 ±1 LSB Eg Gain error Range = 2.048 mA, 25 °C – – ±2.5 % Range = 255 µA, 25 ° C – – ±2.5 % Range = 31.875 µA, 25 ° C – – ±3.5 % TC_Eg Temperature coefficient of gain Range = 2.048 mA – – 0.04 % / °C error Range = 255 µA – – 0.04 % / °C Range = 31.875 µA – – 0.05 % / °C INL Integral nonlinearity Sink mode, range = 255 µA, Codes – ±0.9 ±1 LSB 8 – 255, Rload = 2.4 kΩ, Cload = 15pF Source mode, range = 255 µA, – ±1.2 ±1.5 LSB Codes 8 – 255, Rload = 2.4 kΩ, Cload = 15 pF DNL Differential nonlinearity Sink mode, range = 255 µA, Rload – ±0.3 ±1 LSB = 2.4 kΩ, Cload = 15 pF Source mode, range = 255 µA, – ±0.3 ±1 LSB Rload = 2.4 kΩ, Cload = 15 pF Vcompliance Dropout voltage, source or sink Voltage headroom at max current, 1 – – V mode Rload to Vdda or Rload to Vssa, Vdiff from Vdda Document Number: 001-56955 Rev. *K Page 84 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 11-25. IDAC DC Specifications (continued) Parameter Description Conditions Min Typ Max Units I Operating current, code = 0 Slow mode, source mode, range = – 44 100 µA DD 31.875 µA Slow mode, source mode, range = – 33 100 µA 255 µA, Slow mode, source mode, range = – 33 100 µA 2.04 mA Slow mode, sink mode, range = – 36 100 µA 31.875 µA Slow mode, sink mode, range = – 33 100 µA 255 µA Slow mode, sink mode, range = – 33 100 µA 2.04 mA Fast mode, source mode, range = – 310 500 µA 31.875 µA Fast mode, source mode, range = – 305 500 µA 255 µA Fast mode, source mode, range = – 305 500 µA 2.04 mA Fast mode, sink mode, range = – 310 500 µA 31.875 µA Fast mode, sink mode, range = – 300 500 µA 255µA Fast mode, sink mode, range = – 300 500 µA 2.04 mA Figure 11-26. IDAC INL vs Input Code, Range = 255 µA, Figure 11-27. IDAC INL vs Input Code, Range = 255 µA, Sink Source Mode Mode Document Number: 001-56955 Rev. *K Page 85 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 11-28. IDAC DNL vs Input Code, Range = 255 µA, Figure 11-29. IDAC DNL vs Input Code, Range = 255 µA, Sink Source Mode Mode Figure 11-30. IDAC INL vs Temperature, Range = 255 µA, Fast Figure 11-31. IDAC DNL vs Temperature, Range = 255 µA, Mode Fast Mode Document Number: 001-56955 Rev. *K Page 86 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 11-32. IDAC Full Scale Error vs Temperature, Range Figure 11-33. IDAC Full Scale Error vs Temperature, Range = 255 µA, Source Mode = 255 µA, Sink Mode Figure 11-34. IDAC Operating Current vs Temperature, Figure 11-35. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Source Mode Range = 255 µA, Code = 0, Sink Mode Document Number: 001-56955 Rev. *K Page 87 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 11-26. IDAC AC Specifications Parameter Description Conditions Min Typ Max Units F Update rate – – 8 Msps DAC T Settling time to 0.5 LSB Range = 31.875 µA or 255 µA, full – – 125 ns SETTLE scale transition, fast mode, 600Ω 15-pF load Figure 11-36. IDAC Step Response, Codes 0x40 - 0xC0, Figure 11-37. IDAC Glitch Response, Codes 0x7F - 0x80, 255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V 255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V Figure 11-38. IDAC PSRR vs Frequency Document Number: 001-56955 Rev. *K Page 88 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.2.6 Voltage Digital to Analog Converter (VDAC) See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-27. VDAC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution – 8 – bits INL1 Integral nonlinearity 1 V scale – ±2.1 ±2.5 LSB DNL1 Differential nonlinearity 1 V scale – ±0.3 ±1 LSB Rout Output resistance 1 V scale – 4 – kΩ 4 V scale – 16 – kΩ V Output voltage range, code = 255 1 V scale – 1 – V OUT 4 V scale, Vdda = 5 V – 4 – V Monotonicity – – Yes – V Zero scale error – 0 ±0.9 LSB OS Eg Gain error 1 V scale – – ±2.5 % 4 V scale – – ±2.5 % TC_Eg Temperature coefficient, gain error 1 V scale – – 0.03 %FSR / °C 4 V scale – – 0.03 %FSR / °C I Operating current Slow mode – – 100 µA DD Fast mode – – 500 µA Figure 11-39. VDAC INL vs Input Code, 1 V Mode Figure 11-40. VDAC DNL vs Input Code, 1 V Mode Document Number: 001-56955 Rev. *K Page 89 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 11-41. VDAC INL vs Temperature, 1 V Mode Figure 11-42. VDAC DNL vs Temperature, 1 V Mode Figure 11-43. VDAC Full Scale Error vs Temperature, 1 V Figure 11-44. VDAC Full Scale Error vs Temperature, 4 V Mode Mode Figure 11-45. VDAC Operating Current vs Temperature, 1V Figure 11-46. VDAC Operating Current vs Temperature, 1 V Mode, Slow Mode Mode, Fast Mode Document Number: 001-56955 Rev. *K Page 90 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 11-28. VDAC AC Specificationst Parameter Description Conditions Min Typ Max Units F Update rate 1 V scale – – 1000 ksps DAC 4 V scale – – 250 ksps TsettleP Settling time to 0.1%, step 25% to 1 V scale, Cload = 15 pF – 0.45 1 µs 75% 4 V scale, Cload = 15 pF – 0.8 3.2 µs TsettleN Settling time to 0.1%, step 75% to 1 V scale, Cload = 15 pF – 0.45 1 µs 25% 4 V scale, Cload = 15 pF – 0.7 3 µs Figure 11-47. VDAC Step Response, Codes 0x40 - 0xC0, 1V Figure 11-48. VDAC Glitch Response, Codes 0x7F - 0x80, 1V Mode, Fast Mode, Vdda = 5 V Mode, Fast Mode, Vdda = 5 V Figure 11-49. VDAC PSRR vs Frequency Document Number: 001-56955 Rev. *K Page 91 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.2.7 Temperature Sensor Table 11-29. Temperature Sensor Specifications Parameter Description Conditions Min Typ Max Units Temp sensor accuracy Range: –40°C to +85°C – ±5 – °C 11.2.8 LCD Direct Drive Table 11-30. LCD Direct Drive DC Specifications Parameter Description Conditions Min Typ Max Units I LCD system operating current Device sleep mode with wakeup at – 38 – μA CC 400-Hz rate to refresh LCDs, bus clock = 3 Mhz, Vddio = Vdda = 3V, 4 commons, 16 segments, 1/4 duty cycle, 50Hz frame rate, no glass connected I Current per segment driver Strong drive mode – 260 – µA CC_SEG V LCD bias range (V refers to the V ≥ 3V and V ≥ V 2 – 5 V BIAS BIAS DDA DDA BIAS main output voltage(V0) of LCD DAC) LCD bias step size V ≥ 3V and V ≥ V – 9.1 × V – mV DDA DDA BIAS DDA LCD capacitance per Drivers may be combined – 500 5000 pF segment/common driver Long term segment offset – – 20 mV I Output drive current per segment Vddio = 5.5V, strong drive mode 355 – 710 µA OUT driver) Table 11-31. LCD Direct Drive AC Specifications Parameter Description Conditions Min Typ Max Units f LCD frame rate 10 50 150 Hz LCD Document Number: 001-56955 Rev. *K Page 92 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.3 Digital Peripherals Specifications are valid for –40°C ≤ T ≤ 85 °C and T ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.3.1 Timer The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for more information, see the Timer component datasheet in PSoC Creator. Table 11-32. Timer DC Specifications Parameter Description Conditions Min Typ Max Units Block current consumption 16-bit timer, at listed input clock – – – µA frequency 3 MHz – 15 – µA 12 MHz – 60 – µA 50 MHz – 260 – µA Table 11-33. Timer AC Specifications Parameter Description Conditions Min Typ Max Units Operating frequency DC – 50.01 MHz Capture pulse width (Internal) 21 – – ns Capture pulse width (external) 42 – – ns Timer resolution 21 – – ns Enable pulse width 21 – – ns Enable pulse width (external) 42 – – ns Reset pulse width 21 – – ns Reset pulse width (external) 42 – – ns 11.3.2 Counter The following specifications apply to the Timer/Counter/PWM peripheral, in counter mode. Counters can also be implemented in UDBs; for more information, see the Counter component datasheet in PSoC Creator. Table 11-34. Counter DC Specifications Parameter Description Conditions Min Typ Max Units Block current consumption 16-bit counter, at listed input clock – – – µA frequency 3 MHz – 15 – µA 12 MHz – 60 – µA 50 MHz – 260 – µA Table 11-35. Counter AC Specifications Parameter Description Conditions Min Typ Max Units Operating frequency DC – 50.01 MHz Capture pulse 21 – – ns Resolution 21 – – ns Pulse width 21 – – ns Pulse width (external) 42 – – ns Enable pulse width 21 – – ns Enable pulse width (external) 42 – – ns Reset pulse width 21 – – ns Reset pulse width (external) 42 – – ns Document Number: 001-56955 Rev. *K Page 93 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.3.3 Pulse Width Modulation The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented in UDBs; for more information, see the PWM component datasheet in PSoC Creator.. Table 11-36. PWM DC Specifications Parameter Description Conditions Min Typ Max Units Block current consumption 16-bit PWM, at listed input clock – – – µA frequency 3 MHz – 15 – µA 12 MHz – 60 – µA 50 MHz – 260 – µA Table 11-37. Pulse Width Modulation (PWM) AC Specifications Parameter Description Conditions Min Typ Max Units Operating frequency DC – 50.01 MHz Pulse width 21 – – ns Pulse width (external) 42 – – ns Kill pulse width 21 – – ns Kill pulse width (external) 42 – – ns Enable pulse width 21 – – ns Enable pulse width (external) 42 – – ns Reset pulse width 21 – – ns Reset pulse width (external) 42 – – ns 11.3.4 I2C Table 11-38. Fixed I2C DC Specifications Parameter Description Conditions Min Typ Max Units Block current consumption Enabled, configured for 100 kbps – – 250 µA Enabled, configured for 400 kbps – – 260 µA Wake from sleep mode – – 30 µA Table 11-39. Fixed I2C AC Specifications Parameter Description Conditions Min Typ Max Units Bit rate – – 1 Mbps Controller Area Network[40] Table 11-40. CAN DC Specifications Parameter Description Conditions Min Typ Max Units I Block current consumption – – 200 µA DD Table 11-41. CAN AC Specifications Parameter Description Conditions Min Typ Max Units Bit rate Minimum 8 MHz clock – – 1 Mbit Note 40.Refer to ISO 11898 specification for details. Document Number: 001-56955 Rev. *K Page 94 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.3.5 USB Table 11-42. USB DC Specifications Parameter Description Conditions Min Typ Max Units V Device supply for USB operation USB configured, USB regulator 4.35 – 5.25 V USB_5 enabled V USB configured, USB regulator 3.15 – 3.6 V USB_3.3 bypassed V USB configured, USB regulator 2.85 – 3.6 V USB_3 bypassed[41] I Device supply current in device active V = 5 V, F = 1.5 MHz – 10 – mA USB_Configured DDD CPU mode, bus clock and IMO = 24 MHz V = 3.3 V, F = 1.5 MHz – 8 – mA DDD CPU I Device supply current in device sleep V = 5 V, connected to USB – 0.5 – mA USB_Suspended DDD mode host, PICU configured to wake on USB resume signal V = 5 V, disconnected from – 0.3 – mA DDD USB host V = 3.3 V, connected to USB – 0.5 – mA DDD host, PICU configured to wake on USB resume signal V = 3.3 V, disconnected from – 0.3 – mA DDD USB host 11.3.6 Universal Digital Blocks (UDBs) PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications, APIs, and example code. Table 11-43. UDB AC Specifications Parameter Description Conditions Min Typ Max Units Datapath Performance F Maximum frequency of 16-bit timer in – – 50.01 MHz MAX_TIMER a UDB pair F Maximum frequency of 16-bit adder in – – 50.01 MHz MAX_ADDER a UDB pair F Maximum frequency of 16-bit – – 50.01 MHz MAX_CRC CRC/PRS in a UDB pair PLD Performance F Maximum frequency of a two-pass – – 50.01 MHz MAX_PLD PLD function in a UDB pair Clock to Output Performance t Propagation delay for clock in to data 25 °C, Vddd ≥ 2.7 V – 20 25 ns CLK_OUT out, see Figure11-50. t Propagation delay for clock in to data Worst-case placement, routing, – – 55 ns CLK_OUT out, see Figure11-50. and pin selection Note 41.Rise/fall time matching (TR) not guaranteed, see USB Driver AC Specifications on page 79. Document Number: 001-56955 Rev. *K Page 95 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 11-50. Clock to Output Performance 11.4 Memory Specifications are valid for –40 °C ≤ T ≤ 85 °C and T ≤ 100 °C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.4.1 Flash Table 11-44. Flash DC Specifications Parameter Description Conditions Min Typ Max Units Erase and program voltage V pin 1.71 – 5.5 V DDD Table 11-45. Flash AC Specifications Parameter Description Conditions Min Typ Max Units T Row write time (erase + program) – 15 20 ms WRITE T Row erase time – 10 13 ms ERASE Row program time – 5 7 ms T Bulk erase time (16 KB to 64 KB) – – 35 ms BULK Sector erase time (8 KB to 16 KB) – – 15 ms Total device program time, including – – 5 seconds JTAG or SWD, and other overhead Flash data retention time, retention Average ambient temp. 20 – – years period measured from last erase cycle T ≤ 55°C, 100 K erase/program A cycles Average ambient temp. 10 – – T ≤ 85 °C, 10K erase/program A cycles 11.4.2 EEPROM Table 11-46. EEPROM DC Specifications Parameter Description Conditions Min Typ Max Units Erase and program voltage 1.71 – 5.5 V Document Number: 001-56955 Rev. *K Page 96 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 11-47. EEPROM AC Specifications Parameter Description Conditions Min Typ Max Units T Single row erase/write cycle time – 2 20 ms WRITE EEPROM data retention time, retention Average ambient temp, T ≤ 25 °C, 20 – – years A period measured from last erase cycle 1M erase/program cycles Average ambient temp, T ≤ 55 °C, 20 – – A 100K erase/program cycles Average ambient temp. 10 – – T ≤ 85 °C, 10K erase/program A cycles 11.4.3 Nonvolatile Latches (NVL)) Table 11-48. NVL DC Specifications Parameter Description Conditions Min Typ Max Units Erase and program voltage V pin 1.71 – 5.5 V DDD Table 11-49. NVL AC Specifications Parameter Description Conditions Min Typ Max Units NVL endurance Programmed at 25 °C 1K – – program/ erase cycles Programmed at 0 °C to 70 °C 100 – – program/ erase cycles NVL data retention time Programmed at 25 °C 20 – – years Programmed at 0 °C to 70 °C 20 – – years 11.4.4 SRAM Table 11-50. SRAM DC Specifications Parameter Description Conditions Min Typ Max Units V SRAM retention voltage 1.2 – – V SRAM Table 11-51. SRAM AC Specifications Parameter Description Conditions Min Typ Max Units F SRAM operating frequency DC – 50.01 MHz SRAM Document Number: 001-56955 Rev. *K Page 97 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.4.5 External Memory Interface Figure 11-51. Asynchronous Read Cycle Timing Tcel EM_CEn Taddrv Taddrh EM_Addr Address Toel EM_OEn EM_WEn Tdoesu Tdoeh EM_Data Data Table 11-52. Asynchronous Read Cycle Specifications Parameter Description Conditions Min Typ Max Units T EMIF clock period[42] Vdda ≥ 3.3 V 30.3 – – nS Tcel EM_CEn low time 2T – 5 – 2T+ 5 nS Taddrv EM_CEn low to EM_Addr valid – – 5 nS Taddrh Address hold time after EM_Wen high T – – nS Toel EM_OEn low time 2T – 5 – 2T + 5 nS Tdoesu Data to EM_OEn high setup time T + 15 – – nS Tdoeh Data hold time after EM_OEn high 3 – – nS Note 42.Limited by GPIO output frequency, see Table 11-10 on page 74. Document Number: 001-56955 Rev. *K Page 98 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 11-52. Asynchronous Write Cycle Timing Taddrv Taddrh EM_Addr Address Tcel EM_CEn Twel EM_WEn EM_OEn Tdweh Tdcev EM_Data Data Table 11-53. Asynchronous Write Cycle Specifications Parameter Description Conditions Min Typ Max Units T EMIF clock period[43] Vdda ≥ 3.3 V 30.3 – – nS Tcel EM_CEn low time T – 5 – T + 5 nS Taddrv EM_CEn low to EM_Addr valid – – 5 nS Taddrh Address hold time after EM_WEn high T – – nS Twel EM_WEn low time T – 5 – T + 5 nS Tdcev EM_CEn low to data valid – – 7 nS Tdweh Data hold time after EM_WEn high T – – nS Note 43.Limited by GPIO output frequency, see Table 11-10 on page 74. Document Number: 001-56955 Rev. *K Page 99 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 11-53. Synchronous Read Cycle Timing Tcp/2 EM_Clock Tceld Tcehd EM_CEn Taddriv Taddrv EM_Addr Address Toeld Toehd EM_OEn Tds EM_Data Data Tadscld Tadschd EM_ADSCn Table 11-54. Synchronous Read Cycle Specifications Parameter Description Conditions Min Typ Max Units T EMIF clock period[44] Vdda ≥ 3.3 V 30.3 – – nS Tcp/2 EM_Clock pulse high T/2 – – nS Tceld EM_CEn low to EM_Clock high 5 – – nS Tcehd EM_Clock high to EM_CEn high T/2 – 5 – – nS Taddrv EM_Addr valid to EM_Clock high 5 – – nS Taddriv EM_Clock high to EM_Addr invalid T/2 – 5 – – nS Toeld EM_OEn low to EM_Clock high 5 – – nS Toehd EM_Clock high to EM_OEn high T – – nS Tds Data valid before EM_OEn high T + 15 – – nS Tadscld EM_ADSCn low to EM_Clock high 5 – – nS Tadschd EM_Clock high to EM_ADSCn high T/2 – 5 – – nS Note 44.Limited by GPIO output frequency, see Table 11-10 on page 74. Document Number: 001-56955 Rev. *K Page 100 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 11-54. Synchronous Write Cycle Timing Tcp/2 EM_Clock Tceld Tcehd EM_CEn Taddriv Taddrv EM_Addr Address Tweld Twehd EM_WEn Tdh Tds EM_Data Data Tadschd Tadscld EM_ADSCn Table 11-55. Synchronous Write Cycle Specifications Parameter Description Conditions Min Typ Max Units T EMIF clock Period[45] Vdda ≥ 3.3 V 30.3 – – nS Tcp/2 EM_Clock pulse high T/2 – – nS Tceld EM_CEn low to EM_Clock high 5 – – nS Tcehd EM_Clock high to EM_CEn high T/2 – 5 – – nS Taddrv EM_Addr valid to EM_Clock high 5 – – nS Taddriv EM_Clock high to EM_Addr invalid T/2 – 5 – – nS Tweld EM_WEn low to EM_Clock high 5 – – nS Twehd EM_Clock high to EM_WEn high T/2 – 5 – – nS Tds Data valid before EM_Clock high 5 – – nS Tdh Data invalid after EM_Clock high T – – nS Tadscld EM_ADSCn low to EM_Clock high 5 – – nS Tadschd EM_Clock high to EM_ADSCn high T/2 – 5 – – nS Note 45.Limited by GPIO output frequency, see Table 11-10 on page 74. Document Number: 001-56955 Rev. *K Page 101 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.5 PSoC System Resources Specifications are valid for –40 °C ≤ T ≤ 85 °C and T ≤ 100 °C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.5.1 POR with Brown Out For brown out detect in regulated mode, V and V must be ≥ 2.0 V. Brown out detect is not available in externally regulated DDD DDA mode. Table 11-56. Precise Power-on Reset (PRES) with Brown Out DC Specifications Parameter Description Conditions Min Typ Max Units Precise POR (PPOR) PRESR Rising trip voltage Factory trim 1.64 – 1.68 V PRESF Falling trip voltage 1.62 – 1.66 V Table 11-57. Power-on Reset (POR) with Brown Out AC Specifications Parameter Description Conditions Min Typ Max Units PRES_TR Response time – – 0.5 µs V /V droop rate Sleep mode – 5 – V/sec DDD DDA 11.5.2 Voltage Monitors Table 11-58. Voltage Monitors DC Specifications Parameter Description Conditions Min Typ Max Units LVI Trip voltage LVI_A/D_SEL[3:0] = 0000b 1.68 1.73 1.77 V LVI_A/D_SEL[3:0] = 0001b 1.89 1.95 2.01 V LVI_A/D_SEL[3:0] = 0010b 2.14 2.20 2.27 V LVI_A/D_SEL[3:0] = 0011b 2.38 2.45 2.53 V LVI_A/D_SEL[3:0] = 0100b 2.62 2.71 2.79 V LVI_A/D_SEL[3:0] = 0101b 2.87 2.95 3.04 V LVI_A/D_SEL[3:0] = 0110b 3.11 3.21 3.31 V LVI_A/D_SEL[3:0] = 0111b 3.35 3.46 3.56 V LVI_A/D_SEL[3:0] = 1000b 3.59 3.70 3.81 V LVI_A/D_SEL[3:0] = 1001b 3.84 3.95 4.07 V LVI_A/D_SEL[3:0] = 1010b 4.08 4.20 4.33 V LVI_A/D_SEL[3:0] = 1011b 4.32 4.45 4.59 V LVI_A/D_SEL[3:0] = 1100b 4.56 4.70 4.84 V LVI_A/D_SEL[3:0] = 1101b 4.83 4.98 5.13 V LVI_A/D_SEL[3:0] = 1110b 5.05 5.21 5.37 V LVI_A/D_SEL[3:0] = 1111b 5.30 5.47 5.63 V HVI Trip voltage 5.57 5.75 5.92 V Table 11-59. Voltage Monitors AC Specifications Parameter Description Conditions Min Typ Max Units Response time – – 1 µs Document Number: 001-56955 Rev. *K Page 102 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.5.3 Interrupt Controller Table 11-60. Interrupt Controller AC Specifications Parameter Description Conditions Min Typ Max Units Delay from interrupt signal input to ISR Includes worse case completion of – – 25 Tcy CPU code execution from ISR code longest instruction DIV with 6 cycles 11.5.4 JTAG Interface Figure 11-55. JTAG Interface Timing (1/f_TCK) TCK T_TDI_setup T_TDI_hold TDI T_TDO_valid T_TDO_hold TDO T_TMS_setup T_TMS_hold TMS Table 11-61. JTAG Interface AC Specifications[46] Parameter Description Conditions Min Typ Max Units f_TCK TCK frequency 3.3V ≤ V ≤ 5V – – 14[47] MHz DDD 1.71V ≤ V < 3.3V – – 7[47] MHz DDD T_TDI_setup TDI setup before TCK high (T/10) – 5 – – ns T_TMS_setup TMS setup before TCK high T/4 – – T_TDI_hold TDI, TMS hold after TCK high T = 1/f_TCK max T/4 – – T_TDO_valid TCK low to TDO valid T = 1/f_TCK max – – 2T/5 T_TDO_hold TDO hold after TCK high T = 1/f_TCK max T/4 – – Notes 46.Based on device characterization (Not production tested). 47.f_TCK must also be no more than 1/3 CPU clock frequency. Document Number: 001-56955 Rev. *K Page 103 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.5.5 SWD Interface Figure 11-56. SWD Interface Timing (1/f_SWDCK) SWDCK T_SWDI_setup T_SWDI_hold SWDIO (PSoC 3 reading on SWDIO) T_SWDO_valid T_SWDO_hold SWDIO (PSoC 3 writing to SWDIO) Table 11-62. SWD Interface AC Specifications[48] Parameter Description Conditions Min Typ Max Units f_SWDCK SWDCLK frequency 3.3V ≤ V ≤ 5V – – 14[49] MHz DDD 1.71V ≤ V < 3.3V – – 7[49] MHz DDD 1.71V ≤ V < 3.3V, – – 5.5[49] MHz DDD SWD over USBIO pins T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max T/4 – – T_SWDI_hold SWDIO input hold after SWDCK high T = 1/f_SWDCK max T/4 – – T_SWDO_valid SWDCK high to SWDIO output T = 1/f_SWDCK max – – 2T/5 T_SWDO_hold SWDIO output hold after SWDCK low T = 1/f_SWDCK max T/4 – – 11.5.6 SWV Interface Table 11-63. SWV Interface AC Specifications[22] Parameter Description Conditions Min Typ Max Units SWV mode SWV bit rate – – 33 Mbit 11.6 Clocking Specifications are valid for –40°C ≤ T ≤ 85°C and T ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, A J except where noted. 11.6.1 32 kHz External Crystal Table 11-64. 32 kHz External Crystal DC Specifications[22] Parameter Description Conditions Min Typ Max Units I Operating current Low-power mode – 0.25 1.0 µA CC CL External crystal capacitance – 6 – pF DL Drive level – – 1 µW Table 11-65. 32 kHz External Crystal AC Specifications Parameter Description Conditions Min Typ Max Units F Frequency – 32.768 – kHz T Startup time High power mode – 1 – s ON Notes 48.Based on device characterization (Not production tested). 49.f_SWDCK must also be no more than 1/3 CPU clock frequency. Document Number: 001-56955 Rev. *K Page 104 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.6.2 Internal Main Oscillator Table 11-66. IMO DC Specifications Parameter Description Conditions Min Typ Max Units Supply current 24 MHz – USB mode With oscillator locking to USB bus – – 500 µA 24 MHz – non USB mode – – 300 µA 12 MHz – – 200 µA 6 MHz – – 180 µA 3 MHz – – 150 µA Figure 11-57. IMO Current vs. Frequency Table 11-67. IMO AC Specifications Parameter Description Conditions Min Typ Max Units IMO frequency stability (with factory trim) 24 MHz – Non USB mode –4 – 4 % 24 MHz – USB mode With oscillator locking to USB bus –0.25 – 0.25 % F IMO 12 MHz –3 – 3 % 6 MHz –2 – 2 % 3 MHz –1 – 1 % Startup time[50] From enable (during normal system – – 12 µs operation) or wakeup from low-power state Jitter (peak to peak)[50] Jp-p F = 24 MHz – 0.9 – ns F = 3 MHz – 1.6 – ns Jitter (long term)[50] Jperiod F = 24 MHz – 0.9 – ns F = 3 MHz – 12 – ns Note 50.Based on device characterization (Not production tested). Document Number: 001-56955 Rev. *K Page 105 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 11-58. IMO Frequency Variation vs. Temperature Figure 11-59. IMO Frequency Variation vs. V CC 11.6.3 Internal Low-Speed Oscillator Table 11-68. ILO DC Specifications Parameter Description Conditions Min Typ Max Units Operating current F = 1 kHz – 0.3 1.7 µA OUT I F = 33 kHz – 1.0 2.6 µA CC OUT F = 100 kHz – 1.0 2.6 µA OUT Leakage current Power down mode – 2.0 15 nA Table 11-69. ILO AC Specifications Parameter Description Conditions Min Typ Max Units Startup time, all frequencies Turbo mode – – 2 ms ILO frequencies (trimmed) 100 kHz 45 100 200 kHz 1 kHz 0.5 1 2 kHz F ILO ILO frequencies (untrimmed) 100 kHz 30 100 300 kHz 1 kHz 0.3 1 3.5 kHz Figure 11-60. ILO Frequency Variation vs. Temperature Figure 11-61. ILO Frequency Variation vs. V DD Document Number: 001-56955 Rev. *K Page 106 of 120

® PSoC 3: CY8C32 Family Data Sheet 11.6.4 External Crystal Oscillator Table 11-70. ECO AC Specifications Parameter Description Conditions Min Typ Max Units F Crystal frequency range 4 – 25 MHz 11.6.5 External Clock Reference Table 11-71. External Clock Reference AC Specifications[51] Parameter Description Conditions Min Typ Max Units External frequency range 0 – 33 MHz Input duty cycle range Measured at V /2 30 50 70 % DDIO Input edge rate V to V 0.1 – – V/ns IL IH 11.6.6 Phase–Locked Loop Table 11-72. PLL DC Specifications Parameter Description Conditions Min Typ Max Units I PLL operating current In = 3 MHz, Out = 24 MHz – 200 – µA DD Table 11-73. PLL AC Specifications Parameter Description Conditions Min Typ Max Units Fpllin PLL input frequency[52] 1 – 48 MHz PLL intermediate frequency[53] Output of prescaler 1 – 3 MHz Fpllout PLL output frequency[52] 24 – 50 MHz Lock time at startup – – 250 µs Jperiod-rms Jitter (rms)[51] – – 250 ps Notes 51.Based on device characterization (Not production tested). 52.This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL. 53.PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16. Document Number: 001-56955 Rev. *K Page 107 of 120

® PSoC 3: CY8C32 Family Data Sheet 12. Ordering Information In addition to the features listed in Table12-1, every CY8C32 device includes: a precision on-chip voltage reference, precision oscillators, flash, ECC, DMA, a fixed function I2C, 4 KB trace RAM, JTAG/SWD programming and debug, external memory interface, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C32 derivatives incorporate device and flash security in user-selectable security levels; see the TRM for details. Table 12-1. CY8C32 Family with Single Cycle 8051 MCU Core Analog Digital I/O[55] s Hz) Drive Block WM Part Number CPU Speed (M Flash (KB) SRAM (KB) EEPROM (KB) LCD Segment ADC DAC Comparator SC/CT Analog Opamps DFB CapSense [54]UDBs 16-bit Timer/P FS USB CAN 2.0b Total I/O GPIO SIO USBIO Package JTAG ID[56] 16 KB Flash CY8C3244AXI-153 50 16 2 0.5 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 16 4 – – 70 62 8 0 100-pin TQFP 0×1E099069 CY8C3244LTI-130 50 16 2 0.5 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 16 4 – – 46 38 8 0 68-pin QFN 0×1E082069 CY8C3244LTI-123 50 16 2 0.5 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 16 4 – – 29 25 4 0 48-pin QFN 0×1E07B069 CY8C3244PVI-133 50 16 2 0.5 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 16 4 – – 29 25 4 0 48-pin SSOP 0×1E085069 32 KB Flash CY8C3245AXI-158 50 32 4 1 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 20 4 – – 70 62 8 0 100-pin TQFP 0×1E09E069 CY8C3245LTI-163 50 32 4 1 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 20 4 – – 46 38 8 0 68-pin QFN 0×1E0A3069 CY8C3245LTI-139 50 32 4 1 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 20 4 – – 29 25 4 0 48-pin QFN 0×1E08B069 CY8C3245PVI-134 50 32 4 1 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 20 4 – – 29 25 4 0 48-pin SSOP 0×1E086069 CY8C3245AXI-166 50 32 4 1 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 20 4 ✔ – 72 62 8 2 100-pin TQFP 0×1E0A6069 CY8C3245LTI-144 50 32 4 1 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 20 4 ✔ – 31 25 4 2 48-pin QFN 0×1E090069 CY8C3245LTI-129 50 32 4 1 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 20 4 ✔ – 48 38 8 2 68-pin QFN 0×1E081069 CY8C3245PVI-150 50 32 4 1 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 20 4 ✔ – 31 25 4 2 48-pin SSOP 0×1E096069 64 KB Flash CY8C3246LTI-149 50 64 8 2 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 24 4 – – 46 38 8 0 68-pin QFN 0×1E095069 CY8C3246PVI-147 50 64 8 2 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 24 4 ✔ – 31 25 4 2 48-pin SSOP 0×1E093069 CY8C3246AXI-131 50 64 8 2 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 24 4 – – 70 62 8 0 100-pin TQFP 0×1E083069 CY8C3246LTI-162 50 64 8 2 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 24 4 – – 29 25 4 0 48-pin QFN 0×1E0A2069 CY8C3246PVI-122 50 64 8 2 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 24 4 – – 29 25 4 0 48-pin SSOP 0×1E07A069 CY8C3246AXI-138 50 64 8 2 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 24 4 ✔ – 72 62 8 2 100-pin TQFP 0×1E08A069 CY8C3246LTI-128 50 64 8 2 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 24 4 ✔ – 48 38 8 2 68-pin QFN 0×1E080069 CY8C3246LTI-125 50 64 8 2 ✔ 12-bit Del-Sig 1 2 0 0 – ✔ 24 4 ✔ – 31 25 4 2 48-pin QFN 0×1E07D069 Notes 54.UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See the Example Peripherals on page 41 for more information on how UDBs can be used. 55.The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See the I/O System and Routing on page 34 for details on the functionality of each of these types of I/O. 56.The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID. Document Number: 001-56955 Rev. *K Page 108 of 120

® PSoC 3: CY8C32 Family Data Sheet 12.1 Part Numbering Conventions PSoC 3 devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9, A, B, …, Z) unless stated otherwise. CY8Cabcdefg-xxx (cid:132)a: Architecture (cid:132)ef: Package code (cid:135)3: PSoC 3 (cid:135)Two character alphanumeric (cid:135)5: PSoC 5 (cid:135)AX: TQFP (cid:132)b: Family group within architecture (cid:135)LT: QFN (cid:135)2: CY8C32 family (cid:135)PV: SSOP (cid:135)4: CY8C34 family (cid:132)g: Temperature range (cid:135)6: CY8C36 family (cid:135)C: commercial (cid:135)8: CY8C38 family (cid:135)I: industrial (cid:132)c: Speed grade (cid:135)A: automotive (cid:135)4: 50 MHz (cid:132)xxx: Peripheral set (cid:135)6: 67 MHz (cid:135)Three character numeric (cid:132)d: Flash capacity (cid:135)No meaning is associated with these three characters. (cid:135)4: 16 KB (cid:135)5: 32 KB (cid:135)6: 64 KB Example CY8C 3 2 4 6 P V I - x x x Cypress Prefix 3: PSoC 3 Architecture 2: CY8C32 Family Family Group within Architecture 4: 50 MHz Speed Grade 6: 64 KB Flash Capacity PV: SSOP Package Code I: Industrial Temperature Range Peripheral Set All devices in the PSoC 3 CY8C32 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages. A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of life” requirements. Document Number: 001-56955 Rev. *K Page 109 of 120

® PSoC 3: CY8C32 Family Data Sheet 13. Packaging Table 13-1. Package Characteristics Parameter Description Conditions Min Typ Max Units T Operating ambient temperature –40 25.00 85 °C A T Operating junction temperature –40 – 100 °C J T Package θ (48-pin SSOP) – 49 – °C/Watt JA JA T Package θ (48-pin QFN) – 14 – °C/Watt JA JA T Package θ (68-pin QFN) – 15 – °C/Watt JA JA T Package θ (100-pin TQFP) – 34 – °C/Watt JA JA T Package θ (48-pin SSOP) – 24 – °C/Watt JC JC T Package θ (48-pin QFN) – 15 – °C/Watt JC JC T Package θ (68-pin QFN) – 13 – °C/Watt JC JC T Package θ (100-pin TQFP) – 10 – °C/Watt JC JC Table 13-2. Solder Reflow Peak Temperature Maximum Peak Maximum Time at Peak Package Temperature Temperature 48-pin SSOP 260 °C 30 seconds 48-pin QFN 260 °C 30 seconds 68-pin QFN 260 °C 30 seconds 100-pin TQFP 260 °C 30 seconds Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 48-pin SSOP MSL 3 48-pin QFN MSL 3 68-pin QFN MSL 3 100-pin TQFP MSL 3 Document Number: 001-56955 Rev. *K Page 110 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 13-1. 48-pin (300 mil) SSOP Package Outline .020 24 1 0.395 0.420 0.292 0.299 DIMENSIONS IN INCHES MIN. MAX. 25 48 0.620 0.630 0.088 0.095 SEATING PLANE .010 00..000150 0.092 0.110 GAUGE PLANE 0.004 0.024 0.025 0.040 BSC 0.008 0.008 0°-8° 0.0135 0.016 51-85061-*D Figure 13-2. 48-pin QFN Package Outline TOP VIEW SIDE VIEW BOTTOM VIEW 1.00 MAX. 7.00±0.10 0.05 MAX. 5.6±0.10 0.20 REF. 0.23±0.05 PIN 1 ID 48 37 37 48 1 36 36 1 PIN 1 DOT LASER MARK SOLDERABLE 7.00±0.10 5.6±0.10 EXPOSED 5.55 REF PAD 25 12 12 25 0.40±0.10 13 24 24 13 0.50±0.10 0.08 C NOTES: 5.55 REF 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.13g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE 001- 45616 *B PART # DESCRIPTION LT48D LEAD FREE Document Number: 001-56955 Rev. *K Page 111 of 120

® PSoC 3: CY8C32 Family Data Sheet Figure 13-3. 68-pin QFN 8×8 with 0.4 mm Pitch Package Outline (Sawn Version) TOP VIEW SIDE VIEW BOTTOM VIEW 0.900±0.100 8.000±0.100 5.7±0.10 0.200 REF 6 5 0.400 PITCH PRI N0.12 0ID 8 2 5 6 2 8 5 5 1 1 1 1 PIN 1 DOT SOLDERABLE LASER MARK 8.000±0.100 5.7±0.100.20±0.05 EX PPOASDED 6.40 REF 1 3 3 1 7 5 0.400±0.1005 7 3 1 1 3 0.05 MAX 4 8 8 4 E 6.40 REF N C PLA NOTES: 0.08 EATING S 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 001-09618 *C 2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.17g 4. ALL DIMENSIONS ARE IN MILLIMETERS Figure 13-4. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline 51-85048 *E Document Number: 001-56955 Rev. *K Page 112 of 120

® PSoC 3: CY8C32 Family Data Sheet 14. Acronyms Table 14-1. Acronyms Used in this Document (continued) Table 14-1. Acronyms Used in this Document Acronym Description FIR finite impulse response, see also IIR Acronym Description FPB flash patch and breakpoint abus analog local bus FS full-speed ADC analog-to-digital converter GPIO general-purpose input/output, applies to a PSoC AG analog global pin AHB AMBA (advanced microcontroller bus archi- HVI high-voltage interrupt, see also LVI, LVD tecture) high-performance bus, an ARM data transfer bus IC integrated circuit ALU arithmetic logic unit IDAC current DAC, see also DAC, VDAC AMUXBUS analog multiplexer bus IDE integrated development environment API application programming interface I2C, or IIC Inter-Integrated Circuit, a communications protocol APSR application program status register ARM® advanced RISC machine, a CPU architecture IIR infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO ATM automatic thump mode IMO internal main oscillator, see also ILO BW bandwidth INL integral nonlinearity, see also DNL CAN Controller Area Network, a communications protocol I/O input/output, see also GPIO, DIO, SIO, USBIO CMRR common-mode rejection ratio IPOR initial power-on reset CPU central processing unit IPSR interrupt program status register CRC cyclic redundancy check, an error-checking IRQ interrupt request protocol ITM instrumentation trace macrocell DAC digital-to-analog converter, see also IDAC, VDAC LCD liquid crystal display DFB digital filter block LIN Local Interconnect Network, a communications DIO digital input/output, GPIO with only digital protocol. capabilities, no analog. See GPIO. LR link register DMA direct memory access, see also TD LUT lookup table DNL differential nonlinearity, see also INL LVD low-voltage detect, see also LVI DNU do not use LVI low-voltage interrupt, see also HVI DR port write data registers LVTTL low-voltage transistor-transistor logic DSI digital system interconnect MAC multiply-accumulate DWT data watchpoint and trace MCU microcontroller unit ECC error correcting code MISO master-in slave-out ECO external crystal oscillator NC no connect EEPROM electrically erasable programmable read-only NMI nonmaskable interrupt memory NRZ non-return-to-zero EMI electromagnetic interference NVIC nested vectored interrupt controller EMIF external memory interface NVL nonvolatile latch, see also WOL EOC end of conversion opamp operational amplifier EOF end of frame PAL programmable array logic, see also PLD EPSR execution program status register PC program counter ESD electrostatic discharge PCB printed circuit board ETM embedded trace macrocell PGA programmable gain amplifier Document Number: 001-56955 Rev. *K Page 113 of 120

® PSoC 3: CY8C32 Family Data Sheet Table 14-1. Acronyms Used in this Document (continued) Table 14-1. Acronyms Used in this Document (continued) Acronym Description Acronym Description PHUB peripheral hub SOF start of frame PHY physical layer SPI Serial Peripheral Interface, a communications protocol PICU port interrupt control unit SR slew rate PLA programmable logic array SRAM static random access memory PLD programmable logic device, see also PAL SRES software reset PLL phase-locked loop SWD serial wire debug, a test protocol PMDD package material declaration datasheet SWV single-wire viewer POR power-on reset TD transaction descriptor, see also DMA PRES precise power-on reset THD total harmonic distortion PRS pseudo random sequence TIA transimpedance amplifier PS port read data register PSoC® Programmable System-on-Chip™ TRM technical reference manual TTL transistor-transistor logic PSRR power supply rejection ratio TX transmit PWM pulse-width modulator UART Universal Asynchronous Transmitter Receiver, a RAM random-access memory communications protocol RISC reduced-instruction-set computing UDB universal digital block RMS root-mean-square USB Universal Serial Bus RTC real-time clock USBIO USB input/output, PSoC pins used to connect to RTL register transfer language a USB port RTR remote transmission request VDAC voltage DAC, see also DAC, IDAC RX receive WDT watchdog timer SAR successive approximation register WOL write once latch, see also NVL SC/CT switched capacitor/continuous time WRES watchdog timer reset SCL I2C serial clock XRES external reset I/O pin SDA I2C serial data XTAL crystal S/H sample and hold 15. Reference Documents SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced PSoC® 3, PSoC® 5 Architecture TRM features. See GPIO. PSoC® 3 Registers TRM SOC start of conversion Document Number: 001-56955 Rev. *K Page 114 of 120

® PSoC 3: CY8C32 Family Data Sheet 16. Document Conventions Table 16-1. Units of Measure (continued) Symbol Unit of Measure 16.1 Units of Measure µF microfarads Table 16-1. Units of Measure µH microhenrys Symbol Unit of Measure µs microseconds °C degrees Celsius µV microvolts dB decibels µW microwatts fF femtofarads mA milliamperes Hz hertz ms milliseconds KB 1024 bytes mV millivolts kbps kilobits per second nA nanoamperes Khr kilohours ns nanoseconds kHz kilohertz nV nanovolts kΩ kilohms Ω ohms ksps kilosamples per second pF picofarads LSB least significant bit ppm parts per million Mbps megabits per second ps picoseconds MHz megahertz s seconds MΩ megaohms sps samples per second Msps megasamples per second sqrtHz square root of hertz µA microamperes V volts Document Number: 001-56955 Rev. *K Page 115 of 120

® PSoC 3: CY8C32 Family Data Sheet 17. Revision History Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®) Document Number: 001-56955 Submission Orig. of Rev. ECN No. Description of Change Date Change ** 2796903 11/04/09 MKEA New datasheet *A 2824546 12/09/09 MKEA Updated I2C section to reflect 1 Mbps. Updated Table 11-6 and 11- 7 (Boost AC and DC specs); also added Shottky Diode specs. Changed current for sleep/hibernate mode to include SIO; Added footnote to analog global specs. Updated Figures 1-1, 6-2, 7-14, and 8-1. Updated Table 6-2 and Table 6-3 (Hibernate and Sleep rows) and Power Modes section. Updated GPIO and SIO AC specifications. Updated Gain error in IDAC and VDAC specifications. Updated description of V spec in Table 11-1 and removed GPIO Clamp Current DDA parameter. Updated number of UDBs on page 1. Moved FILO from ILO DC to AC table. Added PCB Layout and PCB Schematic diagrams. Updated Fgpioout spec (Table 11-9). Added duty cycle frequency in PLL AC spec table. Added note for Sleep and Hibernate modes and Active Mode specs in Table 11-2. Linked URL in Section 10.3 to PSoC Creator site. Updated Ja and Jc values in Table 13-1. Updated Single Sample Mode and Fast FIR Mode sections. Updated Input Resistance specification in Del-Sig ADC table. Added Tio_init parameter. Updated PGA and UGB AC Specs. Removed SPC ADC. Updated Boost Converter section. Added section 'SIO as Comparator'; updated Hysteresis spec (differential mode) in Table 11-10. Updated V condition and deleted Vstart parameter in Table 11-6. BAT Added 'Bytes' column for Tables 4-1 to 4-5. *B 2873322 02/04/10 MKEA Changed maximum value of PPOR_TR to '1'. Updated V specification. BIAS Updated PCB Schematic. Updated Figure 8-1 and Figure 6-3. Updated Interrupt Vector table, Updated Sales links. Updated JTAG and SWD specifications. Removed Jp-p and Jperiod from ECO AC Spec table. Added note on sleep timer in Table 11-2. Updated ILO AC and DC specifications. Added Resolution parameter in VDAC and IDAC tables. Updated I typical and maximum values. OUT Changed Temperature Sensor range to –40 °C to +85 °C. Removed Latchup specification from Table 11-1. Updated DAC details Document Number: 001-56955 Rev. *K Page 116 of 120

® PSoC 3: CY8C32 Family Data Sheet Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®) Document Number: 001-56955 *C 2903576 04/01/10 MKEA Updated Vb pin in PCB Schematic. Updated Tstartup parameter in AC Specifications table. Added Load regulation and Line regulation parameters to Inductive Boost Regulator DC Specifications table. Updated I parameter in LCD Direct Drive DC Specs table. CC In page 1, updated internal oscillator range under Prescision programmable clocking to start from 3 MHz. Updated I parameter in LCD Direct Drive DC Specs table. OUT Updated Table 6-2 and Table 6-3. Added bullets on CapSense in page 1; added CapSense column in Section 12 Rem oved some references to footnote [1]. Changed INC_Rn cycles from 3 to 2 (Table 4-1). Added footnote in PLL AC Specification table. Added PLL intermediate frequency row with footnote in PLL AC Specs table. Added UDBs subsection under 11.6 Digital Peripherals. Updated Figure 2-6 (PCB Layout). Updated Pin Descriptions section and modified Figures 6-6, 6-8, 6-9. Updated LVD in Tables 6-2 and 6-3; modified Low-power modes bullet in page 1. Added note to Figures 2-5 and 6-2; Updated Figure 6-2 to add capacitors for V DDA and V pins. DDD Updated boost converter section (6.2.2). Updated Tstartup values in Table 11-3. Removed IPOR rows from Table 11-53. Updated 6.3.1.1, Power Voltage Level Monitors. Updated section 5.2 and Table 11-2 to correct suggestion of execution from flash. Updated IMO max frequency in Figure 6-1, Table 11-63, and Table 11-64. Updated V specs in Table 11-19. REF Updated IDAC uncompensated gain error in Table 11-23. Updated Delay from Interrupt signal input to ISR code execution from ISR code in Table-71. Removed other line in table. Added sentence to last paragraph of section 6.1.1.3. Updated Tresp, high and low-power modes, in Table 11-22. Updated f_TCK values in Table 11-58 and f_SWDCK values in Table 11-59. Updated SNR condition in Table 11-18. Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3. Added 1.71V <= V < 3.3V, SWD over USBIO pins value to Table 11-59. DDD Removed mention of hibernate reset (HRES) from page 1 features, Table 6-3, Section 6.2.1.4, Section 6.3, and Section 6.3.1.1. Change PPOR/PRES to TBDs in Section 6.3.1.1, Section 6.4.1.6 (changed PPOR to reset), Table 11-3 (changed PPOR to PRES), Table 11-53 (changed title, values TBD), and Table 11-54 (changed PPOR_TR to PRES_TR). Added sentence saying that LVD circuits can generate a reset to Section 6.3.1.1. Changed I values on page 1, page 5, and Table 11-2. DD Changed resume time value in Section 6.2.1.3. Changed ESD HBM value in Table 11-1. Changed sample rate row in Table 11-18. Removed V = 1.65V rows and changed BWag value in Table 11-20. DDA Changed Vioff values and changed CMRR value in Table 11-21. Changed INL max value in Table 11-25. Changed occurrences of “Block” to “Row” and deleted the “ECC not included” footnote in Table 11-41. Changed max response time value in Tables 11-54 and 11-56. Change the Startup time in Table 11-64. Added condition to intermediate frequency row in Table 11-70. Added row to Table 11-54. Added brown out note to Section 11.8.1. Document Number: 001-56955 Rev. *K Page 117 of 120

® PSoC 3: CY8C32 Family Data Sheet Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®) Document Number: 001-56955 *D 2938381 05/27/10 MKEA Replaced V with V in USBIO diagram and specification tables, added text DDIO DDD in USBIO section of Electrical Specifications. Added Table 13-2 (Package MSL) Modified Tstorag condition and changed max spec to 100 Added bullet (Pass) under ALU (section 7.2.2.2) Added figures for kHzECO and MHzECO in the External Oscillator section Updated Figure 6-1(Clocking Subsystem diagram) Removed CPUCLK_DIV in table 5-2, Deleted Clock Divider SFR subsection Updated PSoC Creator Framework image Updated SIO DC Specifications (V and V parameters) IH IL Updated bullets in Clocking System and Clocking Distribution sections Updated Figure 8-2 Updated Table 11-10 Updated PCB Layout and Schematic, updated as per MTRB review comments Updated Table 6-3 (power changed to current) In 32kHZ EC DC Specifications table, changed I Max to 0.25 CC In IMO DC Specifications table, updated Supply Current values Updated GPIO DC Specs table Modified to support a maximum 50MHz CPU speed *E 2958674 06/22/10 SHEA Minor ECN to post datasheet to external website *F 2989685 08/04/10 MKEA Added USBIO 22 ohm DP and DM resistors to Simplified Block Diagram Added to Table 6-6 a footnote and references to same. Added sentences to the resistive pull-up and pull-down description bullets. Added sentence to Section 6.4.11, Adjustable Output Level. Updated section 5.5 External Memory Interface Updated Table 11-73 JTAG Interface AC Specifications Updated Table 11-74 SWD Interface AC Specifications *G 3078568 11/04/10 MKEA Updated “Current Digital-to-analog Converter (IDAC)” on page84 Updated “Voltage Digital to Analog Converter (VDAC)” on page89 Updated Table11-2, “DC Specifications,” on page65 *H 3107314 12/10/2010 MKEA Updated delta-sigma tables and graphs. Updated Flash AC specs Formatted table 11.2. Updated interrupt controller table Updated transimpedance amplifier section Updated SIO DC specs table Updated Voltage Monitors DC Specifications table Updated LCD Direct Drive DC specs table Updated ESD value. HBM Updated IDAC and VDAC sections Removed ESO parts from ordering information Changed USBIO pins from NC to DNU and removed redundant USBIO pin description notes Updated POR with brown out DC and AC specs Updated 32 kHz External Crystal DC Specifications Updated XRES IO specs Updated Inductive boost regulator section Delta sigma ADC spec updates Updated comparator section Removed buzz mode from Power Mode Transition diagram *I 3179219 02/22/2011 MKEA Updated conditions for flash data retention time. Updated 100-pin TQFP package spec. Updated EEPROM AC specifications. Document Number: 001-56955 Rev. *K Page 118 of 120

® PSoC 3: CY8C32 Family Data Sheet Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®) Document Number: 001-56955 *J 3200146 03/28/2011 MKEA Removed Preliminary status from the data sheet. Updated JTAG ID Deleted Cin_G1, ADC input capacitance from Delta-Sigma ADC DC spec table Updated JTAG Interface AC Specifications and SWD Interface Specifications tables Updated USBIO DC specs Added 0.01 to max speed Updated Features on page 1 Added Section 5.5, Nonvolatile Latches Updated Flash AC specs Updated delta-sigma graphs, noise histogram figures and RMS Noise spec tables Add reference to application note AN58304 in section 8.1 Updated 100-pin TQFP package spec Added oscillator, I/O, VDAC, regulator graphs Updated JTAG/SWD timing diagrams Updated GPIO and SIO AC specs Updated POR with Brown Out AC spec table UpdatedIDAC graphs Added DMA timing diagram, interrupt timing and interrupt vector, I2C timing diagrams Added full chip performance graphs Changed MHzECO range. Added “Solder Reflow Peak Temperature” table. *K 3259185 05/17/2011 MKEA Added JTAG and SWD interface connection diagrams Updated T and T values in Table 13-1 JA JC Changed typ and max values for the TCVos parameter in Opamp DC specifications table. Updated Clocking subsystem diagram. Changed Vssd to Vssb in the PSoC Power System diagram Updated Ordering information. Document Number: 001-56955 Rev. *K Page 119 of 120

® PSoC 3: CY8C32 Family Data Sheet 18. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC Solutions Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 Interface cypress.com/go/interface Lighting & Power Control cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-56955 Rev. *K Revised May 20, 2011 Page 120 of 120 CapSense®, PSoC® 3, PSoC® 5, and PSoC® Creator™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All products and company names mentioned in this document may be the trademarks of their respective holders.

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