CY8C24223A, CY8C24423A ® Automotive PSoC Programmable System-on-Chip Features ■Additional system resources ❐Inter-Integrated Circuit (I2C™) slave, master, or multimaster ■Automotive Electronics Council (AEC) Q100 qualified operation up to 400 kHz ❐Watchdog and sleep timers ■Powerful Harvard-architecture processor ❐User-configurable low-voltage detection (LVD) ❐M8C processor speeds up to 24 MHz ❐Integrated supervisory circuit ❐8 × 8 multiply, 32-bit accumulate ❐On-chip precision voltage reference ❐Low power at high speed ❐Operating voltage: 3.0 V to 5.25 V ■Complete development tools ❐Automotive temperature range: –40°C to +85°C ❐Free development software (PSoC Designer™) ■Advanced peripherals (PSoC® blocks) ❐Full featured, in-circuit emulator (ICE) and programmer ❐Full-speed emulation ❐Six rail-to-rail analog PSoC blocks provide: ❐Complex breakpoint structure • Up to 14-bit analog-to-digital converters (ADCs) ❐128 KB trace memory • Up to 9-bit digital-to-analog converters (DACs) • Programmable gain amplifiers (PGAs) Logic Block Diagram • Programmable filters and comparators Analog ❐Four digital PSoC blocks provide: Port 2 Port 1 Port 0Drivers • 8- to 32-bit timers, counters, and pulse width modulators PSoC CORE (PWMs) • Cyclical redundancy check (CRC) and pseudo-random se- quence (PRS) modules System Bus • Full- or half-duplex UART Global Digital Interconnect • SPI master or slave Global Analog Interconnect • Connectable to all general purpose I/O (GPIO) pins SRAM SROM Flash 4 KB ❐Complex peripherals by combining blocks 256 Bytes CPU Core (M8C) Sleep and ■Precision, programmable clocking Interrupt Watchdog Controller ❐Internal ±5% 24- and 48-MHz oscillator ❐High accuracy 24 MHz with optional 32-kHz crystal and Multiple Clock Sources phase-locked loop (PLL) (Includes IMO, ILO, PLL, and ECO) ❐Optional external oscillator, up to 24 MHz ❐Internal low-speed, low-power oscillator for watchdog and DIGITAL SYSTEM ANALOG SYSTEM sleep functionality Analog Digital Analog ■Flexible on-chip memory Ref Block Block ❐4 KB flash program storage, 1000 erase/write cycles Array Array ❐256 bytes SRAM data storage Analog ❐In-system serial programming (ISSP) (1 Row, (2 Columns, Input ❐Partial flash updates 4 Blocks) 6 Blocks) Muxing ❐Flexible protection modes ❐EEPROM emulation in flash ■Programmable pin configurations POR and LVD Internal ❐25 mA sink, 10 mA source on all GPIOs Digital Multiply Decimator I2C Voltage Clocks Accum. ❐Pull-up, pull-down, high Z, strong, or open drain drive modes System Resets Ref. on all GPIOs SYSTEM RESOURCES ❐Up to 12 analog inputs on GPIOs[1] ❐Two 30 mA analog outputs on GPIOs ❐Configurable interrupt on all GPIOs Note 1. There are eight standard analog inputs on the GPIO. The other four analog inputs connect from the GPIO directly to specific switched-capacitor block inputs. See the PSoC Technical Reference Manual for more details. CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-52469 Rev. *J Revised December 8, 2017

CY8C24223A, CY8C24423A Contents PSoC Functional Overview ..............................................3 DC Electrical Characteristics .....................................15 PSoC Core ..................................................................3 AC Electrical Characteristics .....................................27 Digital System .............................................................3 Packaging Information ...................................................36 Analog System ............................................................4 Packaging Dimensions ..............................................36 Additional System Resources .....................................5 Thermal Impedances ................................................37 PSoC Device Characteristics ......................................5 Capacitance on Crystal Pins ....................................37 Getting Started ..................................................................6 Solder Reflow Specifications .....................................37 Application Notes ........................................................6 Tape and Reel Information ........................................38 Development Kits ........................................................6 Development Tool Selection .........................................40 Training .......................................................................6 Software ....................................................................40 CYPros Consultants ....................................................6 Development Kits ......................................................40 Solutions Library ..........................................................6 Evaluation Tools ........................................................40 Technical Support .......................................................6 Device Programmers .................................................40 Development Tools ..........................................................6 Accessories (Emulation and Programming) ..............41 PSoC Designer Software Subsystems ........................6 Ordering Information ......................................................42 Designing with PSoC Designer .......................................7 Ordering Code Definitions .........................................42 Select Components .....................................................7 Reference Information ...................................................43 Configure Components ...............................................7 Acronyms ..................................................................43 Organize and Connect ................................................7 Reference Documents ...............................................43 Generate, Verify, and Debug .......................................7 Document Conventions .............................................44 Pinouts ..............................................................................8 Glossary ....................................................................44 20-Pin Part Pinout ......................................................8 Document History Page .................................................49 28-Pin Part Pinout ......................................................9 Sales, Solutions, and Legal Information ......................51 Registers .........................................................................10 Worldwide Sales and Design Support .......................51 Register Conventions ................................................10 Products ....................................................................51 Register Mapping Tables ..........................................10 PSoC® Solutions ......................................................51 Electrical Specifications ................................................13 Cypress Developer Community .................................51 Absolute Maximum Ratings .......................................14 Technical Support .....................................................51 Operating Temperature ............................................14 Document Number: 001-52469 Rev. *J Page 2 of 51

CY8C24223A, CY8C24423A PSoC Functional Overview Digital System The digital system is composed of four digital PSoC blocks. Each The PSoC family consists of many programmable block is an 8-bit resource that can be used alone or combined system-on-chips with on-chip Controller devices. These devices with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, are designed to replace multiple traditional microcontroller unit which are called user modules. (MCU)-based system components with one, low cost single-chip programmable device. PSoC devices include configurable Figure 1. Digital System Block Diagram blocks of analog and digital logic, and programmable interconnects. This architecture makes it possible for the user to Port 1 create customized peripheral configurations that match the Port 2 Port 0 requirements of each individual application. Additionally, a fast central processing unit (CPU), flash program memory, SRAM Digital Clocks To System Bus To Analog data memory, and configurable I/O are included in a range of From Core System convenient pinouts and packages. The PSoC architecture, as shown in the Logic Block Diagram on DIGITAL SYSTEM page 1, is comprised of four main areas: PSoC core, digital system, analog system, and system resources. Configurable Digital PSoC Block Array global buses allow all the device resources to be combined into aitGnh Pccelo IuPOmdSsep ospleC rftoo epvu acird cudeksi gataoigctmaecl,e sbusylpsos cttteokosm t2 ha.4 enE Gdga PlcsohiIbxO aCasln Y daa8irglCeoi tg2aa 4blls xaloo2n c3idnkA sca .lPnu DadSeleoopdCge. nTddehiveni gc eo n 8 8 Row Input Configuration DBB00 DBB0R1owD 0CB02 DCB0344 ConfigurationRow Output 8 8 interconnects. PSoC Core GIE[7:0] Global Digital GOE[7:0] GIO[7:0] Interconnect GOO[7:0] The PSoC core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO. The M8C CPU core is a powerful processor with speeds up to 24MHz, providing a four-million instructions per second (MIPS) Digital peripheral configurations include: 8-bit Harvard-architecture microprocessor. The CPU uses an ■PWMs (8- to 32-bit) interrupt controller with multiple vectors, to simplify programming of real time embedded events. Program execution is timed and ■PWMs with dead band (8- to 24-bit) protected using the included sleep timer and watchdog timer (WDT). ■Counters (8- to 32-bit) Memory includes 4 KB of flash for program storage and 256 ■Timers (8- to 32-bit) bytes of SRAM for data storage. Program flash uses four ■Full- or half-duplex 8-bit UART with selectable parity protection levels on blocks of 64 bytes, allowing customized software IP protection. ■SPI master and slave The PSoC device incorporates flexible internal clock generators, ■I2C master, slave, or multimaster (implemented in a dedicated including a 24-MHz internal main oscillator (IMO) accurate to I2C block) ±5% over temperature and voltage. A low-power 32-kHz internal low-speed oscillator (ILO) is provided for the sleep timer and ■Cyclical redundancy checker/generator (16-bit) WDT. If crystal accuracy is desired, the 32.768-kHz external ■Infrared Data Association (IrDA) crystal oscillator (ECO) is available for use as a real time clock (RTC) and can optionally generate a crystal-accurate 24-MHz ■PRS generators (8- to 32-bit) system clock using a PLL. The clocks, together with The digital blocks can be connected to any GPIO through a programmable clock dividers (as a system resource), provide the series of global buses that can route any signal to any pin. The flexibility to integrate almost any timing requirement into the buses also allow for signal multiplexing and for performing logic PSoC device. operations. This configurability frees your designs from the PSoC GPIOs provide connection to the CPU, digital, and analog constraints of a fixed peripheral controller. resources of the device. Each pin’s drive mode may be selected Digital blocks are provided in rows of four, where the number of from eight options, allowing great flexibility in external inter- blocks varies by PSoC device family. This allows the optimum facing. Every pin also has the capability to generate a system choice of system resources for your application. Family interrupt. resources are shown in Table 1 on page 5. Document Number: 001-52469 Rev. *J Page 3 of 51

CY8C24223A, CY8C24423A Analog System Figure 2. Analog System Block Diagram The analog system is composed of six configurable blocks, each comprised of an opamp circuit allowing the creation of complex P0[7] P0[6] analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. P0[5] P0[4] Some of the common PSoC analog functions for this device (most available as user modules) are: P0[3] P0[2] ■ADCs (up to two, with 6- to 14-bit resolution, selectable as P0[1] P0[0] incremental, delta-sigma, or successive approximation register n (SAR)) efI P2[6] R ■Filters (two- and four-pole band pass, low pass, and notch) DIn N P2[4] G ■Amplifiers (up to two, with selectable gain up to 48x) A P2[3] P2[2] ■Instrumentation amplifiers (one with selectable gain up to 93x) P2[1] P2[0] ■Comparators (up to two, with 16 selectable thresholds) ■DACs (up to two, with 6- to 9-bit resolution) ■Multiplying DACs (up to two, with 6- to 9-bit resolution) ■High current output drivers (two with 30-mA drive) Array Input Configuration ■1.3V reference (as a system resource) ■DTMF dialer ACI0[1:0] ACI1[1:0] ■Modulators ■Correlators Block Array ■Peak detectors ■Many other topologies possible ACB00 ACB01 Analog blocks are arranged in a column of three, which includes ASC10 AASSDD1111 one continuous time (CT) and two switched capacitor (SC) blocks, as shown in Figure2. ASD20 ASC22 Analog Reference Interface to RefHi Reference AGNDIn Digital System RefLo Generators RefIn AGND BandGap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-52469 Rev. *J Page 4 of 51

CY8C24223A, CY8C24423A Additional System Resources System resources, some of which have been previously listed, ■The decimator provides a custom hardware filter for digital provide additional capability useful for complete systems. signal processing applications including the creation of Additional resources include a multiplier, decimator, low voltage delta-sigma ADCs. detection, and power-on reset (POR). Brief statements ■The I2C module provides 0 to 400 kHz communication over two describing the merits of each system resource follow: wires. Slave, master, and multimaster modes are all supported. ■Digital clock dividers provide three customizable clock ■LVD interrupts can signal the application of falling voltage frequencies for use in applications. The clocks can be routed levels, while the advanced POR circuit eliminates the need for to both the digital and analog systems. Additional clocks can a system supervisor. be generated using digital PSoC blocks as clock dividers. ■An internal 1.3-V voltage reference provides an absolute ■A multiply accumulate (MAC) provides a fast 8-bit multiplier reference for the analog system, including ADCs and DACs. with 32-bit accumulate, to assist in both general math as well as digital filters. PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have varying numbers of digital and analog blocks. The following table lists the resources available for specific PSoC device groups. The device covered by this data sheet is shown in the highlighted row of the table. Table 1. PSoC Device Characteristics PSoC Part Digital Digital Digital Analog Analog Analog Analog SRAM Flash Number I/O Rows Blocks Inputs Outputs Columns Blocks Size Size CY8C29x66[2] up to 64 4 16 up to 12 4 4 12 2 K 32 K CY8C28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 1 K 16 K 12 + 4[3] CY8C27x43 up to 44 2 8 up to 12 4 4 12 256 16 K CY8C24x94[2] up to 56 1 4 up to 48 2 2 6 1 K 16 K CY8C24x23A[2] up to 24 1 4 up to 12 2 2 6 256 4 K CY8C23x33 up to 26 1 4 up to 12 2 2 4 256 8 K CY8C22x45[2] up to 38 2 8 up to 38 0 4 6[3] 1 K 16 K CY8C21x45[2] up to 24 1 4 up to 24 0 4 6[3] 512 8 K CY8C21x34[2] up to 28 1 4 up to 28 0 2 4[3] 512 8 K CY8C21x23 up to 16 1 4 up to 8 0 2 4[3] 256 4 K CY8C20x34[2] up to 28 0 0 up to 28 0 0 3[3,4] 512 8 K CY8C20xx6 up to 36 0 0 up to 36 0 0 3[3,4] up to 2 K up to 32 K Notes 2. Automotive qualified devices available in this group. 3. Limited analog functionality. 4. Two analog blocks and one CapSense® block. Document Number: 001-52469 Rev. *J Page 5 of 51

CY8C24223A, CY8C24423A Getting Started ■Built-in debugger For in-depth information, along with detailed programming ■In-circuit emulation details, see the PSoC® Technical Reference Manual. ■Built-in support for communication interfaces: For up-to-date ordering, packaging, and electrical specification ❐Hardware and software I2C slaves and masters information, see the latest PSoC device datasheets on the web. ❐Full-speed USB 2.0 ❐Up to four full-duplex universal asynchronous Application Notes receiver/transmitters (UARTs), SPI master and slave, and Cypress application notes are an excellent introduction to the wireless wide variety of possible PSoC designs. PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. Development Kits PSoC Designer Software Subsystems PSoC Development Kits are available online from and through a growing number of regional and global distributors, which Design Entry include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use Training the PSoC blocks, which are called user modules. Examples of user modules are ADCs, DACs, amplifiers, and filters. Configure Free PSoC technical training (on demand, webinars, and the user modules for your chosen application and connect them workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you your designs. can use to program your application. CYPros Consultants The tool also supports easy development of multiple Certified PSoC consultants offer everything from technical configurations and dynamic reconfiguration. Dynamic assistance to completed PSoC designs. To contact or become a reconfiguration makes it possible to change configurations at run PSoC consultant go to the CYPros Consultants web site. time. In essence, this allows you to use more than 100 percent of PSoC's resources for an application. Solutions Library Code Generation Tools Visit our growing library of solution focused designs. Here you The code generation tools work seamlessly within the can find various application designs that include firmware and PSoCDesigner interface and have been tested with a full range hardware design files that enable you to complete your designs of debugging tools. You can develop your design in C, assembly, quickly. or a combination of the two. Technical Support Assemblers. The assemblers allow you to merge assembly Technical support – including a searchable Knowledge Base code seamlessly with C code. Link libraries automatically use articles and technical forums – is also available online. If you absolute addressing or are compiled in relative mode, and are cannot find an answer to your question, call our Technical linked with other software modules to get absolute addressing. Support hotline at 1-800-541-4736. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you Development Tools to create complete C programs for the PSoC family devices. The PSoC Designer™ is the revolutionary integrated design optimizing C compilers provide all of the features of C, tailored environment (IDE) that you can use to customize PSoC to meet to the PSoC architecture. They come complete with embedded your specific application requirements. PSoC Designer software libraries providing port and bus operations, standard keypad and accelerates system design and time to market. Develop your display support, and extended math functionality. applications using a library of precharacterized analog and digital Debugger peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the PSoC Designer has a debug environment that provides dynamically generated application programming interface (API) hardware in-circuit emulation, allowing you to test the program in libraries of code. Finally, debug and test your designs with the a physical system while providing an internal view of the PSoC integrated debug environment, including in-circuit emulation and device. Debugger commands allow you to read and program and standard software debug features. PSoC Designer includes: read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, ■Application editor graphical user interface (GUI) for device and and provide program run, halt, and step control. The debugger user module configuration and dynamic reconfiguration also allows you to create a trace buffer of registers and memory ■Extensive user module catalog locations of interest. ■Integrated source-code editor (C and assembly) Online Help System ■Free C compiler with no size restrictions or time limits The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional Document Number: 001-52469 Rev. *J Page 6 of 51

CY8C24223A, CY8C24423A subsystem has its own context-sensitive help. This system also precise configuration to your particular application. For example, provides tutorials and links to FAQs and an online support Forum a PWM User Module configures one or more to aid the designer. digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and In-Circuit Emulator duty cycle. Configure the parameters and properties to corre- A low-cost, high-functionality in-circuit emulator (ICE) is spond to your chosen application. Enter values directly or by available for development support. This hardware can program selecting values from drop-down menus. All the user modules single devices. are documented in datasheets that may be viewed directly in The emulator consists of a base unit that connects to the PC PSoC Designer or on the Cypress website. These user module using a USB port. The base unit is universal and operates with datasheets explain the internal operation of the User Module and all PSoC devices. Emulation pods for each device family are provide performance specifications. Each datasheet describes available separately. The emulation pod takes the place of the the use of each user module parameter, and other information PSoC device in the target board and performs full-speed you may need to successfully implement your design. (24 MHz) operation. Organize and Connect You build signal chains at the chip level by interconnecting user Designing with PSoC Designer modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete The development process for the PSoC device differs from that control over all on-chip resources. of a traditional fixed function microprocessor. The configurable Generate, Verify, and Debug analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification When you are ready to test the hardware configuration or move change during development and by lowering inventory costs. on to developing code for the project, you perform the "Generate These configurable resources, called PSoC Blocks, have the Configuration Files" step. This causes PSoC Designer to ability to implement a wide variety of user-selectable functions. generate source code that automatically configures the device to The PSoC development process can be summarized in the your specification and provides the software for the system. The following four steps: generated code provides application programming interfaces (APIs) with high-level functions to control and respond to 1.Select User Modules hardware events at run time and interrupt service routines that 2.Configure User Modules you can adapt as needed. 3.Organize and Connect A complete code development environment allows you to 4.Generate, Verify, and Debug develop and customize your applications in C, assembly language, or both. Select Components The last step in the development process takes place inside PSoC Designer provides a library of pre-built, pre-tested PSoC Designer's Debugger (access by clicking the Connect hardware peripheral components called "user modules." User icon). PSoC Designer downloads the HEX image to the ICE modules make selecting and implementing peripheral devices, where it runs at full speed. PSoC Designer debugging capabil- both analog and digital, simple. ities rival those of systems costing many times more. In addition Configure Components to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and Each of the User Modules you select establishes the basic allows you to define complex breakpoint events that include register settings that implement the selected function. They also monitoring address and data bus values, memory locations and provide parameters and properties that allow you to tailor their external signals. Document Number: 001-52469 Rev. *J Page 7 of 51

CY8C24223A, CY8C24423A Pinouts The automotive CY8C24x23A PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of digital I/O. However, V , V , and XRES are not capable of digital I/O. SS DD 20-Pin Part Pinout Table 2. 20-Pin Part Pinout (Shrink Small-Outline Package (SSOP)) Pin Type Pin Figure 3. CY8C24223A 20-Pin PSoC Device Description No. Digital Analog Name 1 I/O I P0[7] Analog column mux input AI, P0[7] 1 20 VDD AIO, P0[5] 2 19 P0[6], AI 2 I/O I/O P0[5] Analog column mux input and column AIO, P0[3] 3 18 P0[4], AI output AI, P0[1] 4 17 P0[2], AI 3 I/O I/O P0[3] Analog column mux input and column output VSS 5 SSOP 16 P0[0], AI I2C SCL, P1[7] 6 15 XRES 4 I/O I P0[1] Analog column mux input I2C SDA, P1[5] 7 14 P1[6] 5 Power V Ground connection P1[3] 8 13 P1[4], EXTCLK SS 6 I/O P1[7] I2C serial clock (SCL) I2C SCL, XTALin, P1[1] 9 12 P1[2] VSS 10 11 P1[0], XTALout, I2C SDA 7 I/O P1[5] I2C serial data (SDA) 8 I/O P1[3] 9 I/O P1[1] Crystal input (XTALin), I2C serial clock (SCL), ISSP-SCLK[5] 10 Power V Ground connection SS 11 I/O P1[0] Crystal output (XTALout), I2C serial data (SDA), ISSP-SDATA[5] 12 I/O P1[2] 13 I/O P1[4] Optional external clock input (EXTCLK) 14 I/O P1[6] 15 Input XRES Active high external reset with internal pull down 16 I/O I P0[0] Analog column mux input 17 I/O I P0[2] Analog column mux input 18 I/O I P0[4] Analog column mux input 19 I/O I P0[6] Analog column mux input 20 Power V Supply voltage DD LEGEND: A = Analog, I = Input, and O = Output. Note 5. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details. Document Number: 001-52469 Rev. *J Page 8 of 51

CY8C24223A, CY8C24423A 28-Pin Part Pinout Table 3. 28-Pin Part Pinout (SSOP) Pin Type Pin Figure 4. CY8C24423A 28-Pin PSoC Device Description No. Digital Analog Name 1 I/O I P0[7] Analog column mux input AI, P0[7] 1 28 VDD 2 I/O I/O P0[5] Analog column mux input and column AIO, P0[5] 2 27 P0[6], AI output AIO, P0[3] 3 26 P0[4], AI AI, P0[1] 4 25 P0[2], AI 3 I/O I/O P0[3] Analog column mux input and column P2[7] 5 24 P0[0], AI output P2[5] 6 23 P2[6], External VRef 4 I/O I P0[1] Analog column mux input AI, P2[3] 7 22 P2[4], External AGND SSOP 5 I/O P2[7] AI, P2[1] 8 21 P2[2], AI 6 I/O P2[5] VSS 9 20 P2[0], AI 7 I/O I P2[3] Direct switched capacitor block input I2C SCL, P1[7] 10 19 XRES I2C SDA, P1[5] 11 18 P1[6] 8 I/O I P2[1] Direct switched capacitor block input P1[3] 12 17 P1[4], EXTCLK 9 Power V Ground connection SS I2C SCL, XTALin, P1[1] 13 16 P1[2] 10 I/O P1[7] I2C serial clock (SCL) VSS 14 15 P1[0], XTALout, I2C SDA 11 I/O P1[5] I2C serial data (SDA) 12 I/O P1[3] 13 I/O P1[1] Crystal input (XTALin), I2C serial clock (SCL), ISSP-SCLK[6] 14 Power V Ground connection SS 15 I/O P1[0] Crystal output (XTALout), I2C serial data (SDA), ISSP-SDATA[6] 16 I/O P1[2] 17 I/O P1[4] Optional external clock input (EXTCLK) 18 I/O P1[6] 19 Input XRES Active high external reset with internal pull down 20 I/O I P2[0] Direct switched capacitor block input 21 I/O I P2[2] Direct switched capacitor block input 22 I/O P2[4] External analog ground (AGND) 23 I/O P2[6] External voltage reference (VRef) 24 I/O I P0[0] Analog column mux input 25 I/O I P0[2] Analog column mux input 26 I/O I P0[4] Analog column mux input 27 I/O I P0[6] Analog column mux input 28 Power V Supply voltage DD LEGEND: A = Analog, I = Input, and O = Output. Note 6. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details. Document Number: 001-52469 Rev. *J Page 9 of 51

CY8C24223A, CY8C24423A Registers Register Conventions Register Mapping Tables This section lists the registers of the automotive CY8C24x23A The PSoC device has a total register address space of 512 PSoC device. For detailed register information, refer to the PSoC bytes. The register space is referred to as I/O space and is Technical Reference Manual. divided into two banks, bank 0 and bank 1. The XIO bit in the Flag register (CPU_F) determines which bank the user is The register conventions specific to this section are listed in the currently in. When the XIO bit is set to ‘1’, the user is in bank 1. following table. Note In the following register mapping tables, blank fields are Table 4. Abbreviations Reserved and must not be accessed. Convention Description R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific Document Number: 001-52469 Rev. *J Page 10 of 51

CY8C24223A, CY8C24423A Table 5. Register Map Bank 0 Table: User Space Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access PRT0DR 00 RW 40 ASC10CR0 80 RW C0 PRT0IE 01 RW 41 ASC10CR1 81 RW C1 PRT0GS 02 RW 42 ASC10CR2 82 RW C2 PRT0DM2 03 RW 43 ASC10CR3 83 RW C3 PRT1DR 04 RW 44 ASD11CR0 84 RW C4 PRT1IE 05 RW 45 ASD11CR1 85 RW C5 PRT1GS 06 RW 46 ASD11CR2 86 RW C6 PRT1DM2 07 RW 47 ASD11CR3 87 RW C7 PRT2DR 08 RW 48 88 C8 PRT2IE 09 RW 49 89 C9 PRT2GS 0A RW 4A 8A CA PRT2DM2 0B RW 4B 8B CB 0C 4C 8C CC 0D 4D 8D CD 0E 4E 8E CE 0F 4F 8F CF 10 50 ASD20CR0 90 RW D0 11 51 ASD20CR1 91 RW D1 12 52 ASD20CR2 92 RW D2 13 53 ASD20CR3 93 RW D3 14 54 ASC21CR0 94 RW D4 15 55 ASC21CR1 95 RW D5 16 56 ASC21CR2 96 RW I2C_CFG D6 RW 17 57 ASC21CR3 97 RW I2C_SCR D7 # 18 58 98 I2C_DR D8 RW 19 59 99 I2C_MSCR D9 # 1A 5A 9A INT_CLR0 DA RW 1B 5B 9B INT_CLR1 DB RW 1C 5C 9C DC 1D 5D 9D INT_CLR3 DD RW 1E 5E 9E INT_MSK3 DE RW 1F 5F 9F DF DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW DBB00DR2 22 RW 62 A2 INT_VC E2 RC DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW DCB02DR0 28 # 68 A8 MUL_X E8 W DCB02DR1 29 W 69 A9 MUL_Y E9 W DCB02DR2 2A RW 6A AA MUL_DH EA R DCB02CR0 2B # 6B AB MUL_DL EB R DCB03DR0 2C # 6C AC ACC_DR1 EC RW DCB03DR1 2D W 6D AD ACC_DR0 ED RW DCB03DR2 2E RW 6E AE ACC_DR3 EE RW DCB03CR0 2F # 6F AF ACC_DR2 EF RW 30 ACB00CR3 70 RW RDI0RI B0 RW F0 31 ACB00CR0 71 RW RDI0SYN B1 RW F1 32 ACB00CR1 72 RW RDI0IS B2 RW F2 33 ACB00CR2 73 RW RDI0LT0 B3 RW F3 34 ACB01CR3 74 RW RDI0LT1 B4 RW F4 35 ACB01CR0 75 RW RDI0RO0 B5 RW F5 36 ACB01CR1 76 RW RDI0RO1 B6 RW F6 37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF # Blank fields are Reserved and must not be accessed. # Access is bit specific. Document Number: 001-52469 Rev. *J Page 11 of 51

CY8C24223A, CY8C24423A Table 6. Register Map Bank 1 Table: Configuration Space Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access PRT0DM0 00 RW 40 ASC10CR0 80 RW C0 PRT0DM1 01 RW 41 ASC10CR1 81 RW C1 PRT0IC0 02 RW 42 ASC10CR2 82 RW C2 PRT0IC1 03 RW 43 ASC10CR3 83 RW C3 PRT1DM0 04 RW 44 ASD11CR0 84 RW C4 PRT1DM1 05 RW 45 ASD11CR1 85 RW C5 PRT1IC0 06 RW 46 ASD11CR2 86 RW C6 PRT1IC1 07 RW 47 ASD11CR3 87 RW C7 PRT2DM0 08 RW 48 88 C8 PRT2DM1 09 RW 49 89 C9 PRT2IC0 0A RW 4A 8A CA PRT2IC1 0B RW 4B 8B CB 0C 4C 8C CC 0D 4D 8D CD 0E 4E 8E CE 0F 4F 8F CF 10 50 ASD20CR0 90 RW GDI_O_IN D0 RW 11 51 ASD20CR1 91 RW GDI_E_IN D1 RW 12 52 ASD20CR2 92 RW GDI_O_OU D2 RW 13 53 ASD20CR3 93 RW GDI_E_OU D3 RW 14 54 ASC21CR0 94 RW D4 15 55 ASC21CR1 95 RW D5 16 56 ASC21CR2 96 RW D6 17 57 ASC21CR3 97 RW D7 18 58 98 D8 19 59 99 D9 1A 5A 9A DA 1B 5B 9B DB 1C 5C 9C DC 1D 5D 9D OSC_GO_EN DD RW 1E 5E 9E OSC_CR4 DE RW 1F 5F 9F OSC_CR3 DF RW DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW 23 AMD_CR0 63 RW A3 VLT_CR E3 RW DBB01FN 24 RW 64 A4 VLT_CMP E4 R DBB01IN 25 RW 65 A5 E5 DBB01OU 26 RW AMD_CR1 66 RW A6 E6 27 ALT_CR0 67 RW A7 E7 DCB02FN 28 RW 68 A8 IMO_TR E8 W DCB02IN 29 RW 69 A9 ILO_TR E9 W DCB02OU 2A RW 6A AA BDG_TR EA RW 2B 6B AB ECO_TR EB W DCB03FN 2C RW 6C AC EC DCB03IN 2D RW 6D AD ED DCB03OU 2E RW 6E AE EE 2F 6F AF EF 30 ACB00CR3 70 RW RDI0RI B0 RW F0 31 ACB00CR0 71 RW RDI0SYN B1 RW F1 32 ACB00CR1 72 RW RDI0IS B2 RW F2 33 ACB00CR2 73 RW RDI0LT0 B3 RW F3 34 ACB01CR3 74 RW RDI0LT1 B4 RW F4 35 ACB01CR0 75 RW RDI0RO0 B5 RW F5 36 ACB01CR1 76 RW RDI0RO1 B6 RW F6 37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF # Blank fields are Reserved and must not be accessed. # Access is bit specific. Document Number: 001-52469 Rev. *J Page 12 of 51

CY8C24223A, CY8C24423A Electrical Specifications This section presents the DC and AC electrical specifications of the automotive CY8C24x23A PSoC devices. For the latest electrical specifications, visit http://www.cypress.com. Specifications are valid for –40°C  T  85°C and T  100°C, except where noted. A J Refer to Table 21 on page 27 for the electrical specifications of the IMO using slow IMO (SLIMO) mode. Figure 5. Voltage versus CPU Frequency Figure 6. IMO Frequency Trim Options 5.25 5.25 SLIMO SLIMO 4.75 Valierdatinogn 4.75 Mode = 1 Mode = 0 O p egi V) R V) Voltage ( Voltage ( 3.6 MSoLdIeM =O 1 MSoLdIeM =O 0 V DD 3.0 V DD 3.0 0 0 93 kHz 12 MHz 24 MHz 6 MHz 12 MHz 24 MHz CPU Frequency IMO Frequency (nominal setting) Document Number: 001-52469 Rev. *J Page 13 of 51

CY8C24223A, CY8C24423A Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 7. Absolute Maximum Ratings Symbol Description Min Typ Max Units Notes T Storage temperature –55 25 +100 °C Higher storage temperatures STG reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Time spent in storage at a temperature greater than 65 °C counts toward the Flash DR electrical specification in Table 20 on page 26. T Bake temperature – 125 See C BAKETEMP package label t Bake time See – 72 Hours BAKETIME package label T Ambient temperature with power applied –40 – +85 °C A V Supply voltage on V relative to V –0.5 – +6.0 V DD DD SS V DC input voltage V – 0.5 – V + 0.5 V IO SS DD V DC voltage applied to tristate V – 0.5 – V + 0.5 V IOZ SS DD I Maximum current into any port pin –25 – +50 mA MIO ESD Electrostatic discharge voltage 2000 – – V Human body model ESD. LU Latch up current – – 200 mA Operating Temperature Table 8. Operating Temperature Symbol Description Min Typ Max Units Notes T Ambient temperature –40 – +85 °C A T Junction temperature –40 – +100 °C The temperature rise from J ambient to junction is package specific. See Table 33 on page 37. The user must limit the power consumption to comply with this requirement. Document Number: 001-52469 Rev. *J Page 14 of 51

CY8C24223A, CY8C24423A DC Electrical Characteristics DC Chip-Level Specifications Table9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and A A are for design guidance only. Table 9. DC Chip-Level Specifications Symbol Description Min Typ Max Units Notes V Supply voltage 3.0 – 5.25 V See DC POR and LVD specifications, DD Table 19 on page 25. I Supply current – 5 8 mA Conditions are V = 5.0 V, DD DD CPU = 3MHz, 48 MHz disabled, VC1 = 1.5MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. IMO = 24 MHz. I Supply current – 3.3 6.0 mA Conditions are V = 3.3 V, DD3 DD CPU = 3MHz, 48 MHz disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, Analog power = off. IMO = 24 MHz. I Sleep (mode) current with POR, LVD, sleep – 3 6.5 A V = 3.3 V, –40°C  T  55°C, SB DD A timer, and WDT.[7] Analog power = off. I Sleep (mode) current with POR, LVD, sleep – 4 25 A V = 3.3 V, 55°C < T  85°C, SBH DD A timer, and WDT at high temperature.[7] Analog power = off. I Sleep (mode) current with POR, LVD, sleep – 4 7.5 A Conditions are with properly loaded, SBXTL timer, WDT, and external crystal.[7] 1W max, 32.768 kHz crystal. V = 3.3 V, –40°C  T  55°C, DD A Analog power = off. I Sleep (mode) current with POR, LVD, sleep – 5 26 A Conditions are with properly loaded, SBXTLH timer, WDT, and external crystal at high 1W max, 32.768 kHz crystal. temperature.[7] V = 3.3 V, 55°C < T  85°C, DD A Analog power = off. V Reference voltage (bandgap) 1.28 1.30 1.32 V Trimmed for appropriate V . REF DD Note 7. Standby current includes all functions (POR, LVD, WDT, sleep timer) needed for reliable system operation. This must be compared with devices that have similar functions enabled. Document Number: 001-52469 Rev. *J Page 15 of 51

CY8C24223A, CY8C24423A DC GPIO Specifications Table10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and A A are for design guidance only. Table 10. DC GPIO Specifications Symbol Description Min Typ Max Units Notes R Pull-up resistor 4 5.6 8 k PU R Pull-down resistor 4 5.6 8 k Also applies to the internal pull-down PD resistor on the XRES pin. V High output level V – 1.0 – – V I = 10 mA, V = 4.75 to 5.25V OH DD OH DD (maximum 40 mA on even port pins (for example, P0[2], P1[4]), maximum 40 mA on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined I OH budget. V Low output level – – 0.75 V I = 25 mA, V = 4.75 to 5.25V OL OL DD (maximum 100 mA on even port pins (for example, P0[2], P1[4]), maximum 100 mA on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined I OL budget. I High-level source current 10 – – mA V  V – 1.0 V, see the limitations of OH OH DD the total current in the note for V . OH I Low-level sink current 25 – – mA V  0.75 V, see the limitations of the total OL OL current in the note for V . OL V Input low level – – 0.8 V IL V Input high level 2.1 – V IH V Input hysteresis – 60 – mV H I Input leakage (absolute value) – 1 – nA Gross tested to 1 A. IL C Capacitive load on pins as input – 3.5 10 pF Package and pin dependent. IN T = 25°C A C Capacitive load on pins as output – 3.5 10 pF Package and pin dependent. OUT T = 25°C A Document Number: 001-52469 Rev. *J Page 16 of 51

CY8C24223A, CY8C24423A DC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at A A 25°C and are for design guidance only. The operational amplifier is a component of both the analog CT PSoC blocks and the analog SC PSoC blocks. The guaranteed specifications are measured in the analog CT PSoC block. Table 11. 5-V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes V Input offset voltage (absolute value) OSOA Power = low, Opamp bias = high – 1.6 10 mV Power = medium, Opamp bias = high 1.3 8 mV – Power = high, Opamp bias = high 1.2 7.5 mV – TCV Average input offset voltage drift – 7.0 35.0 V/°C OSOA I Input leakage current (Port 0 analog pins) – 20 – pA Gross tested to 1 A. EBOA C Input capacitance (Port 0 analog pins) – 4.5 9.5 pF Package and pin dependent. INOA T = 25°C. A V Common mode voltage range 0.0 – V V The common-mode input voltage CMOA DD Common mode voltage range (high power or 0.5 – VDD – 0.5 V range is measured through an high opamp bias) analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. G Open loop gain Specification is applicable at high OLOA Power = low, Opamp bias = high 60 – – dB power. For all other bias modes Power = medium, Opamp bias = high 60 – – dB (except high power, high opamp Power = high, Opamp bias = high 80 – – dB bias), minimum is 60 dB. V High output voltage swing (internal signals) OHIGHOA Power = low, Opamp bias = high V – 0.2 – – V DD Power = medium, Opamp bias = high V – 0.2 – – V DD Power = high, Opamp bias = high V – 0.5 – – V DD V Low output voltage swing (internal signals) OLOWOA Power = low, Opamp bias = high – – 0.2 V Power = medium, Opamp bias = high – – 0.2 V Power = high, Opamp bias = high – – 0.5 V I Supply current (including associated AGND SOA buffer) Power = low, Opamp bias = high – 150 200 A Power = low, Opamp bias = high – 300 400 A Power = medium, Opamp bias = high – 600 800 A Power = medium, Opamp bias = high – 1200 1600 A Power = high, Opamp bias = high – 2400 3200 A Power = high, Opamp bias = high – 4600 6400 A PSRR Supply voltage rejection ratio 64 80 – dB V V (V – 2.25V) or OA SS IN DD (V – 1.25 V) V  V . DD IN DD Document Number: 001-52469 Rev. *J Page 17 of 51

CY8C24223A, CY8C24423A Table 12. 3.3-V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes V Input offset voltage (absolute value) Power = high, Opamp bias = high OSOA Power = low, Opamp bias = high – 1.65 10 mV is not allowed. Power = medium, Opamp bias = high – 1.32 8 mV Power = high, Opamp bias = high – – – mV TCV Average input offset voltage drift – 7.0 35.0 V/°C OSOA I Input leakage current (Port 0 analog pins) – 20 – pA Gross tested to 1 A. EBOA C Input capacitance (Port 0 analog pins) – 4.5 9.5 pF Package and pin dependent. INOA T = 25°C A V Common mode voltage range 0.2 – V – 0.2 V The common-mode input voltage CMOA DD range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. G Open loop gain Specification is applicable at high OLOA Power = low, Opamp bias = low 60 – – dB power. For all other bias modes Power = medium, Opamp bias = low 60 – – dB (except high power, high opamp Power = high, Opamp bias = low 80 – – dB bias), minimum is 60 dB. V High output voltage swing (internal signals) OHIGHOA Power = low, Opamp bias = low V – 0.2 – – V DD Power = medium, Opamp bias = low V – 0.2 – – V DD Power = high, Opamp bias = low V – 0.2 – – V DD V Low output voltage swing (internal signals) OLOWOA Power = low, Opamp bias = low – – 0.2 V Power = medium, Opamp bias = low – – 0.2 V Power = high, Opamp bias = low – – 0.2 V I Supply current (including associated AGND Power = high, Opamp bias = high SOA buffer) is not allowed. Power = low, Opamp bias = low – 150 200 A Power = low, Opamp bias = high – 300 400 A Power = medium, Opamp bias = low – 600 800 A Power = medium, Opamp bias = high – 1200 1600 A Power = high, Opamp bias = low – 2400 3200 A Power = high, Opamp bias = high – – – A PSRR Supply voltage rejection ratio 64 80 – dB V VIN (V – 2.25) or OA SS DD (V – 1.25 V) VIN  V . DD DD DC Low Power Comparator Specifications Table13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V at 25°C and are for design A A guidance only. Table 13. DC Low Power Comparator Specifications Symbol Description Min Typ Max Units Notes V Low power comparator (LPC) reference 0.2 – V – 1 V REFLPC DD voltage range I LPC supply current – 10 40 A SLPC V LPC voltage offset – 2.5 30 mV OSLPC Document Number: 001-52469 Rev. *J Page 18 of 51

CY8C24223A, CY8C24423A DC Analog Output Buffer Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at A A 25°C and are for design guidance only. Table 14. 5-V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes V Input offset voltage (absolute value) – 3 12 mV OSOB TCV Average input offset voltage drift – +6 – V/°C OSOB V Common mode input voltage range 0.5 – V – 1.0 V CMOB DD R Output resistance OUTOB Power = low – 1 –  Power = high – 1 –  V High output voltage swing (Load = 32 to V /2) OHIGHOB DD Power = low 0.5 × V + 1.1 – – V DD Power = high 0.5 × V + 1.1 – – V DD V Low output voltage swing (Load = 32 to V /2) OLOWOB DD Power = low – – 0.5 × V – 1.3 V DD Power = high – – 0.5 × V – 1.3 V DD I Supply current including bias cell (no load) SOB Power = low – 1.1 5.1 mA Power = high – 2.6 8.8 mA PSRR Supply voltage rejection ratio 52 64 – dB V > (V – 1.25). OB OUT DD C Load Capacitance – – 200 pF This specification L applies to the external circuit that is being driven by the analog output buffer. Table 15. 3.3-V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes V Input offset voltage (absolute value) – 3 12 mV OSOB TCV Average input offset voltage drift – +6 – V/°C OSOB V Common mode input voltage range 0.5 – V – 1.0 V CMOB DD R Output resistance OUTOB Power = low – 1 –  Power = high – 1 –  V High output voltage swing (Load = 1 k to V /2) OHIGHOB DD Power = low 0.5 × V + 1.0 – – V DD Power = high 0.5 × V + 1.0 – – V DD V Low output voltage swing (Load = 1 k to V /2) OLOWOB DD Power = low – – 0.5 × V – 1.0 V DD Power = high – – 0.5 × V – 1.0 V DD I Supply current including bias cell (no load) SOB Power = low – 0.8 2.0 mA Power = high – 2.0 4.3 mA PSRR Supply voltage rejection ratio 52 64 – dB V > (V – 1.25). OB OUT DD C Load Capacitance – – 200 pF This specification L applies to the external circuit that is being driven by the analog output buffer. Document Number: 001-52469 Rev. *J Page 19 of 51

CY8C24223A, CY8C24423A DC Analog Reference Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at A A 25°C and are for design guidance only. The guaranteed specifications for RefHI and RefLO are measured through the analog continuous time PSoC blocks. The power levels for RefHI and RefLO refer to the analog reference control register. AGND is measured at P2[4] in AGND bypass mode. Each analog continuous time PSoC block adds a maximum of 10 mV additional offset error to guaranteed AGND specifications from the local AGND buffer. Reference control power can be set to medium or high unless otherwise noted. Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the analog reference. Some coupling of the digital signal may appear on the AGND. Table 16. 5-V DC Analog Reference Specifications Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b000 RefPower = high V Ref High V /2 + Bandgap V /2 + 1.136 V /2 + 1.288 V /2 + 1.409 V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.138 V /2 + 0.003 V /2 + 0.132 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.417 V /2 – 1.289 V /2 – 1.154 V REFLO DD DD DD DD RefPower = high V Ref High V /2 + Bandgap V /2 + 1.202 V /2 + 1.290 V /2 + 1.358 V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.055 V /2 + 0.001 V /2 + 0.055 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.369 V /2 – 1.295 V /2 – 1.218 V REFLO DD DD DD DD RefPower = medium V Ref High V /2 + Bandgap V /2 + 1.211 V /2 + 1.292 V /2 + 1.357 V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.055 V /2 V /2 + 0.052 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.368 V /2 – 1.298 V /2 – 1.224 V REFLO DD DD DD DD RefPower = medium V Ref High V /2 + Bandgap V /2 + 1.215 V /2 + 1.292 V /2 + 1.353 V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.040 V /2 – 0.001 V /2 + 0.033 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.368 V /2 – 1.299 V /2 – 1.225 V REFLO DD DD DD DD 0b001 RefPower = high V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = high V /2, P2[6] = 1.3 V) – 0.076 0.021 0.041 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 1.3 V) – 0.025 0.011 0.085 DD RefPower = high V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = low V /2, P2[6] = 1.3 V) – 0.069 0.014 0.043 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 1.3 V) – 0.029 0.005 0.052 DD RefPower = medium V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = high V /2, P2[6] = 1.3 V) – 0.072 0.011 0.048 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 1.3 V) – 0.031 0.002 0.057 DD RefPower = medium V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = low V /2, P2[6] = 1.3 V) – 0.070 0.009 0.047 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 1.3 V) – 0.033 0.001 0.039 DD Document Number: 001-52469 Rev. *J Page 20 of 51

CY8C24223A, CY8C24423A Table 16. 5-V DC Analog Reference Specifications (continued) Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b010 RefPower = high V Ref High V V – 0.121 V – 0.003 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.040 V /2 V /2 + 0.034 V AGND DD DD DD DD V Ref Low V V V + 0.006 V + 0.019 V REFLO SS SS SS SS RefPower = high V Ref High V V – 0.083 V – 0.002 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.040 V /2 – 0.001 V /2 + 0.033 V AGND DD DD DD DD V Ref Low V V V + 0.004 V + 0.016 V REFLO SS SS SS SS RefPower = medium V Ref High V V – 0.075 V – 0.002 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.040 V /2 – 0.001 V /2 + 0.032 V AGND DD DD DD DD V Ref Low V V V + 0.003 V + 0.015 V REFLO SS SS SS SS RefPower = medium V Ref High V V – 0.074 V – 0.002 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.040 V /2 – 0.001 V /2 + 0.032 V AGND DD DD DD DD V Ref Low V V V + 0.002 V + 0.014 V REFLO SS SS SS SS 0b011 RefPower = high V Ref High 3 × Bandgap 3.753 3.874 3.979 V REFHI Opamp bias = high V AGND 2 × Bandgap 2.511 2.590 2.657 V AGND V Ref Low Bandgap 1.243 1.297 1.333 V REFLO RefPower = high V Ref High 3 × Bandgap 3.767 3.881 3.974 V REFHI Opamp bias = low V AGND 2 × Bandgap 2.518 2.592 2.652 V AGND V Ref Low Bandgap 1.241 1.295 1.330 V REFLO RefPower = medium V Ref High 3 × Bandgap 2.771 3.885 3.979 V REFHI Opamp bias = high V AGND 2 × Bandgap 2.521 2.593 2.649 V AGND V Ref Low Bandgap 1.240 1.295 1.331 V REFLO RefPower = medium V Ref High 3 × Bandgap 3.771 3.887 3.977 V REFHI Opamp bias = low V AGND 2 × Bandgap 2.522 2.594 2.648 V AGND V Ref Low Bandgap 1.239 1.295 1.332 V REFLO 0b100 RefPower = high V Ref High 2 × Bandgap + P2[6] 2.481 + P2[6] 2.569 + P2[6] 2.639 + P2[6] V REFHI Opamp bias = high (P2[6] = 1.3 V) V AGND 2 × Bandgap 2.511 2.590 2.658 V AGND V Ref Low 2 × Bandgap – P2[6] 2.515 – P2[6] 2.602 – P2[6] 2.654 – P2[6] V REFLO (P2[6] = 1.3 V) RefPower = high V Ref High 2 × Bandgap + P2[6] 2.498 + P2[6] 2.579 + P2[6] 2.642 + P2[6] V REFHI Opamp bias = low (P2[6] = 1.3 V) V AGND 2 × Bandgap 2.518 2.592 2.652 V AGND V Ref Low 2 × Bandgap – P2[6] 2.513 – P2[6] 2.598 – P2[6] 2.650 – P2[6] V REFLO (P2[6] = 1.3 V) RefPower = medium V Ref High 2 × Bandgap + P2[6] 2.504 + P2[6] 2.583 + P2[6] 2.646 + P2[6] V REFHI Opamp bias = high (P2[6] = 1.3 V) V AGND 2 × Bandgap 2.521 2.592 2.650 V AGND V Ref Low 2 × Bandgap – P2[6] 2.513 – P2[6] 2.596 – P2[6] 2.649 – P2[6] V REFLO (P2[6] = 1.3 V) RefPower = medium V Ref High 2 × Bandgap + P2[6] 2.505 + P2[6] 2.586 + P2[6] 2.648 + P2[6] V REFHI Opamp bias = low (P2[6] = 1.3 V) V AGND 2 × Bandgap 2.521 2.594 2.648 V AGND V Ref Low 2 × Bandgap – P2[6] 2.513 – P2[6] 2.595 – P2[6] 2.648 – P2[6] V REFLO (P2[6] = 1.3 V) Document Number: 001-52469 Rev. *J Page 21 of 51

CY8C24223A, CY8C24423A Table 16. 5-V DC Analog Reference Specifications (continued) Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b101 RefPower = high V Ref High P2[4] + Bandgap P2[4] + 1.228 P2[4] + 1.284 P2[4] + 1.332 V REFHI Opamp bias = high (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.358 P2[4] – 1.293 P2[4] – 1.226 V REFLO (P2[4] = V /2) DD RefPower = high V Ref High P2[4] + Bandgap P2[4] + 1.236 P2[4] + 1.289 P2[4] + 1.332 V REFHI Opamp bias = low (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.357 P2[4] – 1.297 P2[4] – 1.229 V REFLO (P2[4] = V /2) DD RefPower = medium V Ref High P2[4] + Bandgap P2[4] + 1.237 P2[4] + 1.291 P2[4] + 1.337 V REFHI Opamp bias = high (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.356 P2[4] – 1.299 P2[4] – 1.232 V REFLO (P2[4] = V /2) DD RefPower = medium V Ref High P2[4] + Bandgap P2[4] + 1.237 P2[4] + 1.292 P2[4] + 1.337 V REFHI Opamp bias = low (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.357 P2[4] – 1.300 P2[4] – 1.233 V REFLO (P2[4] = V /2) DD 0b110 RefPower = high V Ref High 2 × Bandgap 2.512 2.594 2.654 V REFHI Opamp bias = high V AGND Bandgap 1.250 1.303 1.346 V AGND V Ref Low V V V + 0.011 V + 0.027 V REFLO SS SS SS SS RefPower = high V Ref High 2 × Bandgap 2.515 2.592 2.654 V REFHI Opamp bias = low V AGND Bandgap 1.253 1.301 1.340 V AGND V Ref Low V V V + 0.006 V + 0.02 V REFLO SS SS SS SS RefPower = medium V Ref High 2 × Bandgap 2.518 2.593 2.651 V REFHI Opamp bias = high V AGND Bandgap 1.254 1.301 1.338 V AGND V Ref Low V V V + 0.004 V + 0.017 V REFLO SS SS SS SS RefPower = medium V Ref High 2 × Bandgap 2.517 2.594 2.650 V REFHI Opamp bias = low V AGND Bandgap 1.255 1.300 1.337 V AGND V Ref Low V V V + 0.003 V + 0.015 V REFLO SS SS SS SS 0b111 RefPower = high V Ref High 3.2 × Bandgap 4.011 4.143 4.203 V REFHI Opamp bias = high V AGND 1.6 × Bandgap 2.020 2.075 2.118 V AGND V Ref Low V V V + 0.011 V + 0.026 V REFLO SS SS SS SS RefPower = high V Ref High 3.2 × Bandgap 4.022 4.138 4.203 V REFHI Opamp bias = low V AGND 1.6 × Bandgap 2.023 2.075 2.114 V AGND V Ref Low V V V + 0.006 V + 0.017 V REFLO SS SS SS SS RefPower = medium V Ref High 3.2 × Bandgap 4.026 4.141 4.207 V REFHI Opamp bias = high V AGND 1.6 × Bandgap 2.024 2.075 2.114 V AGND V Ref Low V V V + 0.004 V + 0.015 V REFLO SS SS SS SS RefPower = medium V Ref High 3.2 × Bandgap 4.030 4.143 4.206 V REFHI Opamp bias = low V AGND 1.6 × Bandgap 2.024 2.076 2.112 V AGND V Ref Low V V V + 0.003 V + 0.013 V REFLO SS SS SS SS Document Number: 001-52469 Rev. *J Page 22 of 51

CY8C24223A, CY8C24423A Table 17. 3.3-V DC Analog Reference Specifications Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b000 RefPower = high V Ref High V /2 + Bandgap V /2 + 1.170 V /2 + 1.288 V /2 + 1.376 V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.098 V /2 + 0.003 V /2 + 0.097 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.386 V /2 – 1.287 V /2 – 1.169 V REFLO DD DD DD DD RefPower = high V Ref High V /2 + Bandgap V /2 + 1.210 V /2 + 1.290 V /2 + 1.355 V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.055 V /2 + 0.001 V /2 + 0.054 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.359 V /2 – 1.292 V /2 – 1.214 V REFLO DD DD DD DD RefPower = medium V Ref High V /2 + Bandgap V /2 + 1.198 V /2 + 1.292 V /2 + 1.368 V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.041 V /2 V /2 + 0.04 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.362 V /2 – 1.295 V /2 – 1.220 V REFLO DD DD DD DD RefPower = medium V Ref High V /2 + Bandgap V /2 + 1.202 V /2 + 1.292 V /2 + 1.364 V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.033 V /2 V /2 + 0.030 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.364 V /2 – 1.297 V /2 – 1.222 V REFLO DD DD DD DD 0b001 RefPower = high V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = high V /2, P2[6] = 0.5 V) – 0.072 0.017 0.041 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) – 0.029 0.010 0.048 DD RefPower = high V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = low V /2, P2[6] = 0.5 V) – 0.066 0.010 0.043 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) – 0.024 0.004 0.034 DD RefPower = medium V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = high V /2, P2[6] = 0.5 V) – 0.073 0.007 0.053 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) – 0.028 0.002 0.033 DD RefPower = medium V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = low V /2, P2[6] = 0.5 V) – 0.073 0.006 0.056 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) – 0.030 0.032 DD 0b010 RefPower = high V Ref High V V – 0.102 V – 0.003 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.040 V /2 + 0.001 V /2 + 0.039 V AGND DD DD DD DD V Ref Low V V V + 0.005 V + 0.020 V REFLO SS SS SS SS RefPower = high V Ref High V V – 0.082 V – 0.002 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.031 V /2 V /2 + 0.028 V AGND DD DD DD DD V Ref Low V V V + 0.003 V + 0.015 V REFLO SS SS SS SS RefPower = medium V Ref High V V – 0.083 V – 0.002 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.032 V /2 – 0.001 V /2 + 0.029 V AGND DD DD DD DD V Ref Low V V V + 0.002 V + 0.014 V REFLO SS SS SS SS RefPower = medium V Ref High V V – 0.081 V – 0.002 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.033 V /2 – 0.001 V /2 + 0.029 V AGND DD DD DD DD V Ref Low V V V + 0.002 V + 0.013 V REFLO SS SS SS SS 0b011 All power settings – – – – – – – Not allowed at 3.3 V Document Number: 001-52469 Rev. *J Page 23 of 51

CY8C24223A, CY8C24423A Table 17. 3.3-V DC Analog Reference Specifications (continued) Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b100 All power settings – – – – – – – Not allowed at 3.3 V 0b101 RefPower = high V Ref High P2[4] + Bandgap P2[4] + 1.211 P2[4] + 1.285 P2[4] + 1.348 V REFHI Opamp bias = high (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.354 P2[4] – 1.290 P2[4] – 1.197 V REFLO (P2[4] = V /2) DD RefPower = high V Ref High P2[4] + Bandgap P2[4] + 1.209 P2[4] + 1.289 P2[4] + 1.353 V REFHI Opamp bias = low (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.352 P2[4] – 1.294 P2[4] – 1.222 V REFLO (P2[4] = V /2) DD RefPower = medium V Ref High P2[4] + Bandgap P2[4] + 1.218 P2[4] + 1.291 P2[4] + 1.351 V REFHI Opamp bias = high (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.351 P2[4] – 1.296 P2[4] – 1.224 V REFLO (P2[4] = V /2) DD RefPower = medium V Ref High P2[4] + Bandgap P2[4] + 1.215 P2[4] + 1.292 P2[4] + 1.354 V REFHI Opamp bias = low (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.352 P2[4] – 1.297 P2[4] – 1.227 V REFLO (P2[4] = V /2) DD 0b110 RefPower = high V Ref High 2 × Bandgap 2.460 2.594 2.695 V REFHI Opamp bias = high V AGND Bandgap 1.257 1.302 1.335 V AGND V Ref Low V V V + 0.01 V + 0.029 V REFLO SS SS SS SS RefPower = high V Ref High 2 × Bandgap 2.462 2.592 2.692 V REFHI Opamp bias = low V AGND Bandgap 1.256 1.301 1.332 V AGND V Ref Low V V V + 0.005 V + 0.017 V REFLO SS SS SS SS RefPower = medium V Ref High 2 × Bandgap 2.473 2.593 2.682 V REFHI Opamp bias = high V AGND Bandgap 1.257 1.301 1.330 V AGND V Ref Low V V V + 0.003 V + 0.014 V REFLO SS SS SS SS RefPower = medium V Ref High 2 × Bandgap 2.470 2.594 2.685 V REFHI Opamp bias = low V AGND Bandgap 1.256 1.300 1.332 V AGND V Ref Low V V V + 0.002 V + 0.012 V REFLO SS SS SS SS 0b111 All power settings – – – – – – – Not allowed at 3.3 V DC Analog PSoC Block Specifications Table15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and A A are for design guidance only. Table 18. DC Analog PSoC Block Specifications Symbol Description Min Typ Max Units Notes R Resistor unit value (continuous time) – 12.2 – k CT C Capacitor unit value (switched capacitor) – 80 – fF SC Document Number: 001-52469 Rev. *J Page 24 of 51

CY8C24223A, CY8C24423A DC POR and LVD Specifications Table19 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and A A are for design guidance only. Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable System-on-Chip Technical Reference Manual for more information on the VLT_CR register. Table 19. DC POR and LVD Specifications Symbol Description Min Typ Max Units Notes V value for PPOR trip V must be greater than or DD DD V PORLEV[1:0] = 00b – 2.36 2.40 V equal to 2.5 V during startup, PPOR0 V PORLEV[1:0] = 01b – 2.82 2.95 V reset from the XRES pin, or PPOR1 V PORLEV[1:0] = 10b – 4.55 4.70 V reset from Watchdog. PPOR2 V value for LVD trip DD V VM[2:0] = 000b 2.40 2.450 2.51[8] V LVD0 V VM[2:0] = 001b 2.85 2.920 2.99[9] V LVD1 V VM[2:0] = 010b 2.95 3.02 3.09 V LVD2 V VM[2:0] = 011b 3.06 3.13 3.20 V LVD3 V VM[2:0] = 100b 4.37 4.48 4.55 V LVD4 V VM[2:0] = 101b 4.50 4.64 4.75 V LVD5 V VM[2:0] = 110b 4.62 4.73 4.83 V LVD6 V VM[2:0] = 111b 4.71 4.81 4.95 V LVD7 Notes 8. Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply. 9. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply. Document Number: 001-52469 Rev. *J Page 25 of 51

CY8C24223A, CY8C24423A DC Programming Specifications Table20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and A A are for design guidance only. Table 20. DC Programming Specifications Symbol Description Min Typ Max Units Notes V V for programming and erase 4.5 5.0 5.5 V This specification DDP DD applies to the functional requirements of external programmer tools V Low V for verify 3.0 3.1 3.2 V This specification DDLV DD applies to the functional requirements of external programmer tools V High V for verify 5.1 5.2 5.3 V This specification DDHV DD applies to the functional requirements of external programmer tools V Supply voltage for flash write operation 3.0 – 5.25 V This specification DDIWRITE applies to this device when it is executing internal flash writes I Supply current during programming or verify – 5 25 mA DDP V Input low voltage during programming or verify – – 0.8 V ILP V Input high voltage during programming or verify 2.1 – – V IHP I Input current when applying V to P1[0] or P1[1] – – 0.2 mA Driving internal pull down ILP ILP during programming or verify resistor. I Input current when applying V to P1[0] or P1[1] – – 1.5 mA Driving internal pull down IHP IHP during programming or verify resistor. V Output low voltage during programming or verify – – 0.75 V OLV V Output high voltage during programming or verify V – 1.0 – V V OHV DD DD Flash Flash endurance (per block)[10, 11] 1,000 – – – Erase/write cycles per ENPB block Flash Flash endurance (total)[11, 12] 64,000 – – – Erase/write cycles ENT Flash Flash data retention 10 – – Years DR Notes 10.The erase/write cycle limit per block (FlashENPB) is only guaranteed if the device operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25V. 11.For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information. 12.The maximum total number of allowed erase/write cycles is the minimum FlashENPB value multiplied by the number of flash blocks in the device. Document Number: 001-52469 Rev. *J Page 26 of 51

CY8C24223A, CY8C24423A AC Electrical Characteristics AC Chip-Level Specifications Table21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and A A are for design guidance only. Table 21. AC Chip-Level Specifications Symbol Description Min Typ Max Units Notes F IMO frequency for 24 MHz 22.8[13] 24 25.2[13] MHz Trimmed for 5 V or 3.3 V operation using factory IMO24 trim values. See Figure 6 on page 13. SLIMO mode = 0. F IMO frequency for 6 MHz 5.5[13] 6 6.5[13] MHz Trimmed for 5 V or 3.3 V operation using factory IMO6 trim values. See Figure 6 on page 13. SLIMO mode = 1. F CPU frequency (5 V V nominal) 0.089[13] – 25.2[13] MHz Minimum CPU frequency is 0.022 MHz when CPU1 DD SLIMO mode = 0. F CPU frequency (3.3 V V 0.089[13] – 12.6[13] MHz Minimum CPU frequency is 0.022 MHz when CPU2 DD nominal) SLIMO mode = 0. F Digital PSoC block frequency (5 V 0 – 50.4[13,14] MHz Refer to AC Digital Block Specifications on BLK5 V nominal) page 32. DD F Digital PSoC block frequency (3.3 0 – 25.2[13,14] MHz Refer to AC Digital Block Specifications on BLK33 V V nominal) page 32. DD F ILO frequency 15 32 64 kHz This specification applies when the ILO has 32K1 been trimmed. F ILO untrimmed frequency 5 – 100 kHz After a reset and before the M8C processor 32KU starts to execute, the ILO is not trimmed. F External crystal oscillator – 32.76 – kHz Accuracy is capacitor and crystal dependent. 32K2 8 50% duty cycle. F PLL frequency – 23.98 – MHz Is a multiple (x732) of crystal frequency. PLL 6 t PLL lock time 0.5 – 10 ms Refer to Figure 7 on page 28. PLLSLEW t PLL lock time for low gain setting 0.5 – 50 ms Refer to Figure 8 on page 28. PLLSLEWSLOW t External crystal oscillator startup to – 1700 2620 ms Refer to Figure 9 on page 28. OS 1% t External crystal oscillator startup to – 2800 3800 ms The crystal oscillator frequency is within 100 OSACC 100 ppm ppm of its final value by the end of the t OSACC period. Correct operation assumes a properly loaded 1µW maximum drive level 32.768 kHz crystal. 3.0V  V  5.25 V, –40C  T  85C. DD A t External reset pulse width 10 – – s XRST DC24M 24 MHz duty cycle 40 50 60 % DC ILO duty cycle 20 50 80 % ILO Step24M 24 MHz trim step size – 50 – kHz Fout48M 48 MHz output frequency 45.6[13] 48.0 50.4[13] MHz Trimmed. Using factory trim values. F Maximum frequency of signal on – – 12.6[13] MHz MAX row input or row output. SR Power supply slew rate – – 250 V/ms V slew rate during power up. POWERUP DD t Time between end of POR state – 16 100 ms Power up from 0 V. POWERUP and CPU code execution t [15] 24 MHz IMO cycle-to-cycle jitter – 200 700 ps JIT_IMO (RMS) 24 MHz IMO long term N – 300 900 ps N = 32 cycle-to-cycle jitter (RMS) 24 MHz IMO period jitter (RMS) – 100 400 ps t [15] PLL cycle-to-cycle jitter (RMS) – 200 800 ps JIT_PLL PLL long term N cycle-to-cycle – 300 1200 ps N = 32 jitter (RMS) PLL period jitter (RMS) – 100 700 ps Notes 13.Accuracy derived from IMO with appropriate trim for VDD range. 14.See the individual user module data sheets for information on maximum frequencies for user modules. 15.Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information. Document Number: 001-52469 Rev. *J Page 27 of 51

CY8C24223A, CY8C24423A Figure 7. PLL Lock Timing Diagram PLL Enable Tt 24 MHz PLLSLEW F PLL PLL 0 Gain Figure 8. PLL Lock for Low Gain Setting Timing Diagram PLL Enable Tt 24 MHz PLLSLEWLOW F PLL PLL 1 Gain Figure 9. External Crystal Oscillator Startup Timing Diagram 32K Select 32 kHz Tt OS F 32K2 Document Number: 001-52469 Rev. *J Page 28 of 51

CY8C24223A, CY8C24423A AC GPIO Specifications Table22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and A A are for design guidance only. Table 22. AC GPIO Specifications Symbol Description Min Typ Max Units Notes F GPIO operating frequency 0 – 12.6[16] MHz Normal strong mode GPIO t Rise time, normal strong mode, Cload = 50 pF 3 – 18 ns V = 4.5 to 5.25 V, 10% to 90% RISEF DD t Fall time, normal strong mode, Cload = 50 pF 2 – 18 ns V = 4.5 to 5.25 V, 10% to 90% FALLF DD t Rise time, slow strong mode, Cload = 50 pF 10 27 – ns V = 3 to 5.25 V, 10% to 90% RISES DD t Fall time, slow strong mode, Cload = 50 pF 10 22 – ns V = 3 to 5.25 V, 10% to 90% FALLS DD Figure 10. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TtRRIisSeEFF TtFFAaLllLFF TtRRIisSeESS TtFFAaLllLSS Note 16.Accuracy derived from IMO with appropriate trim for VDD range. Document Number: 001-52469 Rev. *J Page 29 of 51

CY8C24223A, CY8C24423A AC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at A A 25°C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the analog CT PSoC block. Power = high and Opamp bias = high is not allowed at 3.3 V. Table 23. 5-V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units t Rising settling time from 80% of V to 0.1% of V ROA (10 pF load, unity gain) Power = low, Opamp bias = low – – 3.9 s Power = medium, Opamp bias = high – – 0.72 s Power = high, Opamp bias = high – – 0.62 s t Falling settling time from 20% of V to 0.1% of V SOA (10 pF load, unity gain) Power = low, Opamp bias = low – – 5.9 s Power = medium, Opamp bias = high – – 0.92 s Power = high, Opamp bias = high – – 0.72 s SR Rising slew rate (20% to 80%) (10 pF load, unity gain) ROA Power = low, Opamp bias = low 0.15 – – V/s Power = medium, Opamp bias = high 1.7 – – V/s Power = high, Opamp bias = high 6.5 – – V/s SR Falling slew rate (80% to 20%) (10 pF load, unity gain) FOA Power = low, Opamp bias = low 0.01 – – V/s Power = medium, Opamp bias = high 0.5 – – V/s Power = high, Opamp bias = high 4.0 – – V/s BW Gain bandwidth product OA Power = low, Opamp bias = low 0.75 – – MHz Power = medium, Opamp bias = high 3.1 – – MHz Power = high, Opamp bias = high 5.4 – – MHz E Noise at 1 kHz (Power = medium, Opamp bias = high) – 100 – nV/rt-Hz NOA T able 24. 3.3-V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units t Rising settling time from 80% of V to 0.1% of V ROA (10 pF load, unity gain) Power = low, Opamp bias = low – – 3.92 s Power = medium, Opamp bias = high – – 0.72 s t Falling settling time from 20% of V to 0.1% of V SOA (10 pF load, unity gain) Power = low, Opamp bias = low – – 5.41 s Power = medium, Opamp bias = high – – 0.72 s SR Rising slew rate (20% to 80%) (10 pF load, unity gain) ROA Power = low, Opamp bias = low 0.31 – – V/s Power = medium, Opamp bias = high 2.7 – – V/s SR Falling slew rate (80% to 20%) (10 pF load, unity gain) FOA Power = low, Opamp bias = low 0.24 – – V/s Power = medium, Opamp bias = high 1.8 – – V/s BW Gain bandwidth product OA Power = low, Opamp bias = low 0.67 – – MHz Power = medium, Opamp bias = high 2.8 – – MHz E Noise at 1 kHz (Power = medium, Opamp bias = high) – 100 – nV/rt-Hz NOA Document Number: 001-52469 Rev. *J Page 30 of 51

CY8C24223A, CY8C24423A When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 k resistance and the external capacitor. Figure 11. Typical AGND Noise with P2[4] Bypass   nV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 12. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 0.01 0.1 1 10 100 Freq (kHz) Document Number: 001-52469 Rev. *J Page 31 of 51

CY8C24223A, CY8C24423A AC Low Power Comparator Specifications Table25 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and A A are for design guidance only. Table 25. AC Low Power Comparator Specifications Symbol Description Min Typ Max Units Notes t LPC response time – – 50 s  50 mV overdrive comparator RLPC reference set within V REFLPC AC Digital Block Specifications Table26 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and A A are for design guidance only. Table 26. AC Digital Block Specifications Function Description Min Typ Max Units Notes All functions Block input clock frequency V  4.75 V – – 50.4[18] MHz DD V < 4.75 V – – 25.2[18] MHz DD Timer Input clock frequency No capture, V  4.75 V – – 50.4[18] MHz DD No capture, V < 4.75 V – – 25.2[18] MHz DD With capture – – 25.2[18] MHz Capture pulse width 50[17] – – ns Counter Input clock frequency No enable input, V  4.75 V – – 50.4[18] MHz DD No enable input, V < 4.75 V – – 25.2[18] MHz DD With enable input – – 25.2[18] MHz Enable input pulse width 50[17] – – ns Dead Band Kill pulse width Asynchronous restart mode 20 – – ns Synchronous restart mode 50[17] – – ns Disable mode 50[17] – – ns Input clock frequency V  4.75 V – – 50.4[18] MHz DD V < 4.75 V – – 25.2[18] MHz DD CRCPRS Input clock frequency (PRS Mode) V  4.75 V – – 50.4[18] MHz DD V < 4.75 V – – 25.2[18] MHz DD CRCPRS Input clock frequency – – 25.2[18] MHz (CRC Mode) SPIM Input clock frequency – – 8.4[18] MHz The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. SPIS Input clock (SCLK) frequency – – 4.2[18] MHz The input clock is the SPI SCLK in SPIS mode. Width of SS_Negated between transmissions 50[17] – – ns Transmitter Input clock frequency The baud rate is equal to the input V  4.75 V, 2 stop bits – – 50.4[18] MHz clock frequency divided by 8. DD V  4.75 V, 1 stop bit – – 25.2[18] MHz DD V < 4.75 V – – 25.2[18] MHz DD Receiver Input clock frequency The baud rate is equal to the input V  4.75 V, 2 stop bits – – 50.4[18] MHz clock frequency divided by 8. DD V  4.75 V, 1 stop bit – – 25.2[18] MHz DD V < 4.75 V – – 25.2[18] MHz DD Notes 17.50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). 18.Accuracy derived from IMO with appropriate trim for VDD range. Document Number: 001-52469 Rev. *J Page 32 of 51

CY8C24223A, CY8C24423A AC Analog Output Buffer Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at A A 25°C and are for design guidance only. Table 27. 5-V AC Analog Output Buffer Specifications Symbol Description Min Typ Max Units t Rising settling time to 0.1%, 1 V Step, 100 pF load ROB Power = low – – 2.5 s Power = high – – 2.5 s t Falling settling time to 0.1%, 1 V Step, 100 pF load SOB Power = low – – 2.2 s Power = high – – 2.2 s SR Rising slew rate (20% to 80%), 1 V Step, 100 pF load ROB Power = low 0.65 – – V/s Power = high 0.65 – – V/s SR Falling slew rate (80% to 20%), 1 V Step, 100 pF load FOB Power = low 0.65 – – V/s Power = high 0.65 – – V/s BW Small signal bandwidth, 20 mV , 3dB BW, 100 pF load OB pp Power = low 0.8 – – MHz Power = high 0.8 – – MHz BW Large signal bandwidth, 1 V , 3dB BW, 100 pF load OB pp Power = low 300 – – kHz Power = high 300 – – kHz Table 28. 3.3-V AC Analog Output Buffer Specifications Symbol Description Min Typ Max Units t Rising settling time to 0.1%, 1 V Step, 100 pF load ROB Power = low – – 3.8 s Power = high – – 3.8 s t Falling settling time to 0.1%, 1 V Step, 100 pF load SOB Power = low – – 2.6 s Power = high – – 2.6 s SR Rising slew rate (20% to 80%), 1 V Step, 100 pF load ROB Power = low 0.5 – – V/s Power = high 0.5 – – V/s SR Falling slew rate (80% to 20%), 1 V Step, 100 pF load FOB Power = low 0.5 – – V/s Power = high 0.5 – – V/s BW Small signal bandwidth, 20 mV , 3dB BW, 100 pF load OB pp Power = low 0.7 – – MHz Power = high 0.7 – – MHz BW Large signal bandwidth, 1 V , 3dB BW, 100 pF load OB pp Power = low 200 – – kHz Power = high 200 – – kHz Document Number: 001-52469 Rev. *J Page 33 of 51

CY8C24223A, CY8C24423A AC External Clock Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at A A 25°C and are for design guidance only. Table 29. 5 V AC External Clock Specifications Symbol Description Min Typ Max Units F Frequency 0.093 – 24.6 MHz OSCEXT – High period 20.6 – 5300 ns – Low period 20.6 – – ns – Power-up IMO to switch 150 – – s Table 30. 3.3 V AC External Clock Specifications Symbol Description Min Typ Max Units F Frequency with CPU clock divide by 1[19] 0.093 – 12.3 MHz OSCEXT F Frequency with CPU clock divide by 2 or greater[20] 0.186 – 24.6 MHz OSCEXT – High period with CPU clock divide by 1 41.7 – 5300 ns – Low period with CPU clock divide by 1 41.7 – – ns – Power-up IMO to switch 150 – – s AC Programming Specifications Table31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and A A are for design guidance only. Table 31. AC Programming Specifications Symbol Description Min Typ Max Units Notes t Rise time of SCLK 1 – 20 ns RSCLK t Fall time of SCLK 1 – 20 ns FSCLK t Data setup time to falling edge of SCLK 40 – – ns SSCLK t Data hold time from falling edge of SCLK 40 – – ns HSCLK F Frequency of SCLK 0 – 8 MHz SCLK t Flash erase time per block – 20 80[21] ms ERASEB t Flash block write time – 80 320[21] ms WRITE t Data out delay from falling edge of SCLK – – 45 ns V  3.6 DSCLK DD t Data out delay from falling edge of SCLK – – 50 ns 3.0  V  3.6 DSCLK3 DD t Flash erase time (bulk) – 20 – ms Erase all blocks and ERASEALL protection fields at once t Total flash block program time – – 200[21] ms T  0°C PRGH J (t + t ), hot ERASEB WRITE t Total flash block program time – – 400[21] ms T  0°C PRGC J (t + t ), cold ERASEB WRITE Notes 19.Maximum CPU frequency is 12 MHz nominal at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 20.If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. 21.For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information. Document Number: 001-52469 Rev. *J Page 34 of 51

CY8C24223A, CY8C24423A AC I2C Specifications Table32 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and A A are for design guidance only. Table 32. AC Characteristics of the I2C SDA and SCL Pins Standard Mode Fast Mode Symbol Description Units Min Max Min Max F SCL clock frequency 0 100[22] 0 400[22] kHz SCLI2C t Hold time (repeated) START condition. After this 4.0 – 0.6 – s HDSTAI2C period, the first clock pulse is generated. t LOW period of the SCL clock 4.7 – 1.3 – s LOWI2C t HIGH period of the SCL clock 4.0 – 0.6 – s HIGHI2C t Setup time for a repeated START condition 4.7 – 0.6 – s SUSTAI2C t Data hold time 0 – 0 – s HDDATI2C t Data setup time 250 – 100[23] – ns SUDATI2C t Setup time for STOP condition 4.0 – 0.6 – s SUSTOI2C t Bus free time between a STOP and START condition 4.7 – 1.3 – s BUFI2C t Pulse width of spikes are suppressed by the input – – 0 50 ns SPI2C filter. Figure 13. Definition for Timing for Fast/Standard Mode on the I2C Bus I2C_SDA t tSUDATI2C tHDDATI2CtSUSTAI2C tSPI2C tBUFI2C HDSTAI2C I2C_SCL t t t HIGHI2C LOWI2C SUSTOI2C P S S Sr START Condition Repeated START Condition STOP Condition Notes 22.FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the FSCLI2C specification adjusts accordingly. 23.A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSUDATI2C  250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-52469 Rev. *J Page 35 of 51

CY8C24223A, CY8C24423A Packaging Information This section illustrates the packaging specifications for the automotive CY8C24x23A PSoC device, along with the thermal impedances for the package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the emulator pod drawings at http://www.cypress.com. Packaging Dimensions Figure 14. 20-Pin (210-Mil) SSOP 51-85077 *F Document Number: 001-52469 Rev. *J Page 36 of 51

CY8C24223A, CY8C24423A Figure 15. 28-Pin (210-Mil) SSOP 51-85079 *F Thermal Impedances Solder Reflow Specifications Table35 shows the solder reflow temperature limits that must Table 33. Thermal Impedances per Package not be exceeded. Package Typical JA [24] Table 35. Solder Reflow Specifications 20-pin SSOP 117°C/W Maximum Peak Maximum Time Package 28-pin SSOP 101°C/W Temperature (TC) above TC – 5 °C 20-Pin SSOP 260 C 30 seconds Capacitance on Crystal Pins 28-Pin SSOP 260 C 30 seconds Table 34. Capacitance on Crystal Pins Package Package Capacitance 20-pin SSOP 2.6 pF 28-pin SSOP 2.8 pF Note 24.TJ = TA + Power × JA Document Number: 001-52469 Rev. *J Page 37 of 51

CY8C24223A, CY8C24423A Tape and Reel Information Figure 16. 20-Pin SSOP Carrier Tape Drawing 51-51101 *C Document Number: 001-52469 Rev. *J Page 38 of 51

CY8C24223A, CY8C24423A Figure 17. 28-Pin SSOP Carrier Tape Drawing 51-51100 *D Table 36. Tape and Reel Specifications Minimum Cover Tape Hub Size Minimum Leading Standard Full Reel Package Trailing Empty Width (mm) (inches) Empty Pockets Quantity Pockets 20-Pin SSOP 13.3 4 42 25 2000 28-Pin SSOP 13.3 7 42 25 1000 Document Number: 001-52469 Rev. *J Page 39 of 51

CY8C24223A, CY8C24423A Development Tool Selection Evaluation Tools All evaluation tools can be purchased from the Cypress Online This section presents the development tools available for the Store. CY8C24x23A family. CY3210-PSoCEval1 Software The CY3210-PSoCEval1 kit features an evaluation board and PSoC Designer the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, an RS-232 port, and At the core of the PSoC development software suite is PSoC plenty of breadboarding space to meet all of your evaluation Designer, used to generate PSoC firmware applications. PSoC needs. The kit includes: Designer is available free of charge at http://www.cypress.com and includes a free C compiler. ■Evaluation board with LCD module PSoC Programmer ■MiniProg programming unit Flexible enough to be used on the bench in development, yet ■28-Pin CY8C29466-24PXI PDIP PSoC device sample (2) suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate ■PSoC Designer software CD directly from PSoC Designer or PSoC Express. PSoC ■Getting Started guide Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is ■USB 2.0 cable available free of charge at http://www.cypress.com. CY3210-24X23 Evaluation Pod (EvalPod) Development Kits PSoC EvalPods are pods that connect to the ICE (CY3215-DK All development kits can be purchased from the Cypress Online kit) to allow debugging capability. They can also function as a Store. The online store also has the most up to date information standalone device without debugging capability. The EvalPod on kit contents, descriptions, and availability. has a 28-pin DIP footprint on the bottom for easy connection to development kits or other hardware. The top of the EvalPod has CY3215-DK Basic Development Kit prototyping headers for easy connection to the device's pins. CY3210-24X23 provides evaluation of the CY8C24x23A PSoC The CY3215-DK is for prototyping and development with PSoC device family. Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor Device Programmers and view the contents of specific memory locations. Advanced emulation features are also supported through PSoC Designer. All device programmers can be purchased from the Cypress The kit includes: Online Store. ■ICE-Cube unit CY3210-MiniProg1 ■28-Pin PDIP emulation pod for CY8C29466-24PXI The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a ■28-Pin CY8C29466-24PXI PDIP PSoC device samples (two) small, compact prototyping programmer that connects to the PC ■PSoC Designer software CD via a provided USB 2.0 cable. The kit includes: ■ISSP cable ■MiniProg programming unit ■MiniEval socket programming and evaluation board ■MiniEval socket programming and evaluation board ■Backward compatibility cable (for connecting to legacy pods) ■28-pin CY8C29466-24PXI PDIP PSoC device sample ■Universal 110/220 power supply (12 V) ■PSoC Designer software CD ■European plug adapter ■Getting Started guide ■USB 2.0 cable ■USB 2.0 cable ■Getting Started guide CY3207ISSP In-System Serial Programmer (ISSP) ■Development kit registration form The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Document Number: 001-52469 Rev. *J Page 40 of 51

CY8C24223A, CY8C24423A Note CY3207ISSP needs special software and is not compatible ■110 ~ 240-V power supply, Euro-Plug adapter with PSoC Programmer. This software is free and can be ■USB 2.0 cable downloaded from http://www.cypress.com. The kit includes: ■CY3207 programmer unit ■PSoC ISSP software CD Accessories (Emulation and Programming) Table 37. Emulation and Programming Accessories Part Number Pin Package Pod Kit[25] Foot Kit[26] Adapter[27] CY8C24223A-24PVXA 20-pin SSOP CY3250-24X23A CY3250-20SSOP-FK AS-20-20-01SS-6 CY8C24423A-24PVXA 28-pin SSOP CY3250-24X23A CY3250-28SSOP-FK AS-28-28-02SS-6ENP-GANG Notes 25.Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples. 26.Foot kit includes surface mount feet that can be soldered to the target PCB. 27.Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. Document Number: 001-52469 Rev. *J Page 41 of 51

CY8C24223A, CY8C24423A Ordering Information The following table lists the automotive CY8C24x23A PSoC device group’s key package features and ordering codes. Table 38. CY8C24x23A Automotive PSoC Device Key Features and Ordering Information Package Ordering Code Flash (Bytes) SRAM (Bytes) Temperature Range Digital Blocks Analog Blocks Digital I/O Pins Analog Inputs Analog Outputs XRES Pin 20-Pin (210-Mil) SSOP CY8C24223A-24PVXA 4 K 256 –40°C to +85°C 4 6 16 8 2 Yes 20-Pin (210-Mil) SSOP CY8C24223A-24PVXAT 4 K 256 –40°C to +85°C 4 6 16 8 2 Yes (Tape and Reel) 28-Pin (210-Mil) SSOP CY8C24423A-24PVXA 4 K 256 –40°C to +85°C 4 6 24 12[1] 2 Yes 28-Pin (210-Mil) SSOP CY8C24423A-24PVXAT 4 K 256 –40°C to +85°C 4 6 24 12[1] 2 Yes (Tape and Reel) Ordering Code Definitions CY 8 C 24 xxx-SPxx Package Type: Thermal Rating: PX = PDIP Pb-free C = Commercial SX = SOIC Pb-free I = Industrial PVX = SSOP Pb-free E = Automotive Extended –40°C to +125°C LFX/LKX = QFN Pb-free A = Automotive –40°C to +85°C AX = TQFP Pb-free CPU Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = PSoC Company ID: CY = Cypress Document Number: 001-52469 Rev. *J Page 42 of 51

CY8C24223A, CY8C24423A Reference Information Acronyms The following table lists the acronyms that are used in this document. Table 39. Acronyms Used in this Datasheet Acronym Description Acronym Description AC alternating current MAC multiply-accumulate ADC analog-to-digital converter MCU microcontroller unit AEC Automotive Electronics Council MIPS million instructions per second API application programming interface PCB printed circuit board CMOS complementary metal oxide semiconductor PDIP plastic dual inline package CPU central processing unit PGA programmable gain amplifier CRC cyclic redundancy check PLL phase-locked loop DAC digital-to-analog converter POR power-on reset DC direct current PPOR precision POR DTMF dual-tone multi-frequency PRS pseudo-random sequence ECO external crystal oscillator PSoC® Programmable System-on-Chip EEPROM electrically erasable programmable read-only PWM pulse-width modulator memory GPIO general-purpose I/O RMS root mean square I2C inter-integrated circuit RTC real time clock I/O input/output SAR successive approximation register ICE in-circuit emulator SC switched capacitor IDE integrated development environment SLIMO slow IMO ILO internal low speed oscillator SPI serial peripheral interface IMO internal main oscillator SRAM static random-access memory IrDA infrared data association SROM supervisory read-only memory ISSP in-system serial programming SSOP shrunk small outline package LCD liquid crystal display UART universal asynchronous receiver transmitter LED light-emitting diode USB universal serial bus LPC low power comparator WDT watchdog timer LVD low-voltage detect XRES external reset Reference Documents CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34, CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical Reference Manual (TRM) (001-14463) Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459) Understanding Data Sheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503) Document Number: 001-52469 Rev. *J Page 43 of 51

CY8C24223A, CY8C24423A Document Conventions Units of Measure The following table lists the units of measure that are used in this document. Table 40. Units of Measure Symbol Unit of Measure Symbol Unit of Measure KB 1024 bytes ms millisecond dB decibel mV millivolt C degree Celsius mVpp millivolts peak-to-peak fF femto farad nA nanoampere Hz hertz ns nanosecond kHz kilohertz nV nanovolt k kilohm  ohm MHz megahertz ppm parts per million µA microampere % percent µs microsecond pA picoampere µV microvolt pF picofarad µW microwatt ps picosecond mA milliampere V volt mm millimeter W watt Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are in decimal format. Glossary active high 1.A logic signal having its asserted state as the logic 1 state. 2.A logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. analog-to-digital A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts converter (ADC) a voltage to a digital number. The digital-to-analog converter (DAC) performs the reverse operation. Application A series of software routines that comprise an interface between a computer application and lower level services programming and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create interface (API) software applications. asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap A stable voltage reference design that matches the positive temperature coefficient of VT with the negative reference temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. bandwidth 1.The frequency range of a message or information processing system measured in hertz. 2.The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. Document Number: 001-52469 Rev. *J Page 44 of 51

CY8C24223A, CY8C24423A Glossary (continued) bias 1.A systematic deviation of a value from a reference value. 2.The amount by which the average of a set of values departs from a reference value. 3.The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1.A functional unit that performs a single function, such as an oscillator. 2.A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. buffer 1.A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which data is written. 2.A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3.An amplifier used to lower the output impedance of a system. bus 1.A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2.A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3.One or more conductors that serve as a common connection for a group of related devices. clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler A program that translates a high level language, such as C, into machine language. configuration In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to space ‘1’. crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. debugger A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition. digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. digital-to-analog A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital converter (DAC) converter (ADC) performs the reverse operation. Document Number: 001-52469 Rev. *J Page 45 of 51

CY8C24223A, CY8C24423A Glossary (continued) duty cycle The relationship of a clock period high time to its low time, expressed as a percent. emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop (XRES) and return to a pre-defined state. flash An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is off. flash block The smallest amount of flash ROM space that may be programmed at one time and the smallest amount of flash space that may be protected. frequency The number of cycles or events per unit of time, for a periodic function. gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at the V supply voltage and pulled high with resistors. DD The bus operates up to100 kbits/second in standard mode and 400 kbits/second in fast mode. ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service A block of code that normal code execution is diverted to when the CPU receives a hardware interrupt. Many routine (ISR) interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. jitter 1.A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2.The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. low voltage detect A circuit that senses V and provides an interrupt to the system when V falls below a selected threshold. DD DD (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the flash, SRAM, and register space. master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. Document Number: 001-52469 Rev. *J Page 46 of 51

CY8C24223A, CY8C24423A Glossary (continued) microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal The reference to a circuit containing both analog and digital techniques and components. modulator A device that imposes a signal on a carrier. noise 1.A disturbance that affects a signal and that may distort the information carried by the signal. 2.The random variations of one or more characteristics of any entity such as voltage, current, or data. oscillator A circuit that may be crystal controlled and is used to generate a clock frequency. parity A technique for testing transmitted data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference loop (PLL) signal. pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. port A group of pins, usually eight. power-on reset A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware (POR) reset. PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark of Cypress. PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied value. modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. register A storage device with a specific capacity, such as a bit or byte. reset A means of bringing a system back to a known state. See hardware reset and software reset. ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. serial 1.Pertaining to a process in which all events occur one after the other. 2.Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. Document Number: 001-52469 Rev. *J Page 47 of 51

CY8C24223A, CY8C24423A Glossary (continued) shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. SRAM An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform flash operations. The functions of the SROM may be accessed in normal user code, operating from flash. stop bit A signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1.A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2.A system whose operation is synchronized by a clock signal. tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules Pre-built, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level analog and digital PSoC blocks. User modules also provide high level API (Application Programming Interface) for the peripheral function. user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. V A name for a power net meaning "voltage drain". The most positive power supply signal. Usually 5 V or 3.3 V. DD V A name for a power net meaning "voltage source." The most negative power supply signal. SS watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. Document Number: 001-52469 Rev. *J Page 48 of 51

CY8C24223A, CY8C24423A Document History Page Document Title: CY8C24223A, CY8C24423A Automotive PSoC® Programmable System-on-Chip Document Number: 001-52469 Orig. of Submission Revision ECN Description of Change Change Date ** 2678061 VIVG / PYRS 03/24/09 New data sheet for Automotive A-Grade *A 2685606 SHEA 04/08/09 Minor ECN to correct the spec number in Document History. *B 2702925 BTK 05/06/2009 Post to external web *C 2742354 BTK / PYRS 07/22/09 Changed title. Updated Features section. Updated text of PSoC Functional Overview section. Updated Getting Started section. Made corrections and minor text edits to Pinouts section. Changed the name of the Register Reference section to "Registers". Added clarifying comments to some electrical specifica- tions. Updated some figures. Changed T specification per MASJ input. RAMP Fixed all AC specifications to conform to a ±5% IMO accuracy. Made other miscellaneous minor text edits. Deleted some non-applicable or redundant infor- mation. Added a footnote to clarify that 8 of the 12 analog inputs are regular and the other 4 are direct SC block connections. Updated Development Tool Selection section. *D 2822792 BTK / AESA 12/07/2009 Added T T I , I , F , DC , and T electrical specifi- PRGH, PRGC, OL OH 32KU ILO POWERUP cations. Corrected the Flash electrical specification. Updated all footnotes ENT for Table20, “DC Programming Specifications,” on page26. Added maximum values and updated typical values for T and T electrical specifica- ERASEB WRITE tions. Replaced T electrical specification with SR electrical speci- RAMP POWERUP fication. Added “Contents” on page2. *E 2888007 NJF 03/30/2010 Updated Cypress website links. Removed reference to PSoC Designer 4.4. Added T andT parameters in Absolute Maximum Ratings on BAKETEMP BAKETIME page 14. Updated 3.3 V DC Analog Reference Specifications on page 21. Removed Third Party Tools and Build a PSoC Emulator into Your Board. Updated links in Sales, Solutions, and Legal Information. *F 3070556 BTK 10/25/2010 Added CY8C24223A-24PVXA(T) devices to datasheet. Updated the following sections: Getting Started, Development Tools, and Designing with PSoC Designer Moved Acronyms and Document Conventions to the end of document. Added Reference Information and Glossary sections. Updated datasheet as per Cypress style guide and new datasheet template. *G 3110316 BTK / NJF 05/12/11 Updated I2C timing diagram to improve clarity. Updated wording, formatting, and notes of the AC Digital Block Specifications table to improve clarity. Added V , V , and V electrical specifications to give more information DDP DDLV DDHV for programming the device. Updated solder reflow temperature specifications to give more clarity. Updated the jitter specifications. Updated PSoC Device Characteristics table. Updated the F electrical specification. 32KU Updated note for R electrical specification. PD Updated note for the T electrical specification to add more clarity. STG Added Tape and Reel Information section. Added C electrical specification. L Updated Analog Reference specifications. *H 3980449 AESA 04/24/13 Updated Figure 16 and Figure 17. Document Number: 001-52469 Rev. *J Page 49 of 51

CY8C24223A, CY8C24423A Document Title: CY8C24223A, CY8C24423A Automotive PSoC® Programmable System-on-Chip Document Number: 001-52469 Orig. of Submission Revision ECN Description of Change Change Date *I 4691432 KUK 03/18/2015 Updated Electrical Specifications: Updated DC Electrical Characteristics: Updated DC Analog Reference Specifications: Updated description. Updated Packaging Information: Updated Packaging Dimensions: spec 51-85077 – Changed revision from *E to *F. spec 51-85079 – Changed revision from *E to *F. Updated Tape and Reel Information: spec 51-51100 – Changed revision from *C to *D. Updated to new template. Completing Sunset Review. *J 5987976 AESATMP8 12/08/2017 Updated logo and Copyright. Document Number: 001-52469 Rev. *J Page 50 of 51

CY8C24223A, CY8C24423A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions ARM® Cortex® Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Forums | WICED IOT Forums | Projects | Video | Blogs | Interface cypress.com/interface Training | Components Internet of Things cypress.com/iot Technical Support Memory cypress.com/memory cypress.com/support Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless © Cypress Semiconductor Corporation, 2009-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-52469 Rev. *J Revised December 8, 2017 Page 51 of 51

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