CY8C24123A CY8C24223A CY8C24423A ® PSoC Programmable System-on-Chip PSoC® Programmable System-on-Chip Features ■New CY8C24x23A PSoC device ❐Derived from the CY8C24x23 device ■Powerful Harvard-architecture processor ❐Low power and low voltage (2.4 V) ❐M8C processor speeds up to 24 MHz ■Additional system resources ❐8 × 8 multiply, 32-bit accumulate ❐I2C slave, master, and multi-master to 400 kHz ❐Low power at high speed ❐Watchdog and sleep timers ❐Operating voltage: 2.4 V to 5.25 V ❐User-configurable low-voltage detection (LVD) ❐Operating voltages down to 1.0 V using on-chip switch mode pump (SMP) ❐Integrated supervisory circuit ❐Industrial temperature range: –40 °C to +85 °C ❐On-chip precision voltage reference ■Advanced peripherals (PSoC® blocks) ■Complete development tools ❐Six rail-to-rail analog PSoC blocks provide: ❐Free development software (PSoC Designer™) • Up to 14-bit analog-to-digital converters (ADCs) ❐Full-featured, in-circuit emulator (ICE), and programmer ❐Full-speed emulation • Up to 9-bit digital-to-analog converters (DACs) ❐Complex breakpoint structure • Programmable gain amplifiers (PGAs) ❐128 KB trace memory • Programmable filters and comparators ❐Four digital PSoC blocks provide: • 8- to 32-bit timers and counters, 8- and 16-bit pulse-width Logic Block Diagram modulators (PWMs) Analog • Cyclical redundancy check (CRC) and pseudo random Port 2 Port 1 Port 0Drivers sequence (PRS) modules PSoC CORE • Full-duplex universal asynchronous receiver transmitter (UART) System Bus • Multiple serial peripheral interface (SPI) masters or slaves • Can connect to all general-purpose I/O (GPIO) pins Global Digital Interconnect Global Analog Interconnect ❐Complex peripherals by combining blocks SRAM SROM Flash 4KB ■Precision, programmable clocking 256 Bytes CPU Core (M8C) Sleep and ❐Internal ±5% 24- / 48-MHz main oscillator Interrupt Watchdog Controller ❐High accuracy 24 MHz with optional 32 kHz crystal and phase-locked loop (PLL) Multiple Clock Sources ❐Optional external oscillator up to 24 MHz (Includes IMO, ILO, PLL, and ECO) ❐Internal oscillator for watchdog and sleep DIGITAL SYSTEM ANALOG SYSTEM ■Flexible on-chip memory Analog ❐4 KB flash program storage 50,000 erase/write cycles Ref ❐256-bytes SRAM data storage Digital Analog Block Block ❐In-system serial programming (ISSP) Array Array Analog ❐Partial flash updates Input ❐Flexible protection modes Muxing ❐Electronically erasable programmable read only memory (EEPROM) emulation in flash ■Programmable pin configurations Internal Switch ❐25-mA sink, 10-mA source on all GPIOs CDliogcitkasl MAcucltuipmly. Decimator I2C SPyOsRte man Rd eLsVeDts Voltage Mode Ref. Pump ❐Pull-up, pull-down, high Z, strong, or open-drain drive modes SYSTEM RESOURCES on all GPIOs ❐Eight standard analog inputs on all GPIOs, and four additional analog inputs with restricted routing ❐Two 30 mA analog outputs on all GPIOs ❐Configurable interrupt on all GPIOs Errata: For information on silicon errata, see “Errata” on page67. Details include trigger conditions, devices affected, and proposed workaround. CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 38-12028 Rev. *W Revised May 3, 2017

CY8C24123A CY8C24223A CY8C24423A More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you to quickly and effectively integrate the device into your design. Following is an abbreviated list for PSoC 1: ■Overview: PSoC Portfolio, PSoC Roadmap ❐Visit the PSoC 1 TRM page for the complete list of TRMs. Following documents provide detailed descriptions of the Ar- ■Product Selectors: PSoC 1, PSoC 3, PSoC 4, or PSoC5LP chitecture, Programming specification and Register map de- In addition, PSoC Designer offers a device selection tool within tails of CY8C2XXXX PSoC 1 device family. PSoC1, at the time of creating a new project. • PSoC1 CY8C2XXXX TRM ■Datasheets: Describe and provide electrical specifications for • PSoC1 ISSP Programming Specifications all the PSoC 1 family of devices. Visit the PSoC 1 datasheets web page for a complete list ■Development Kits: ■Application notes and code examples: ❐CY3210 - CY8C24x23 PSoC(R) Evaluation Pods (EvalPod) are 28-pin PDIP adapters that seamlessly connect any PSoC ❐Visit the PSoC 1 Code Examples web page for a comprehen- device to the 28-pin PDIP connector on any Cypress PSoC sive list of code examples development kit. CY3210-24x23 provides evaluation of the ❐Cypress offers a large number of PSoC application notes CY8C24x23A PSoC device family on any PSoC developer covering a broad range of topics, from basic to advanced kit. PSoC developer kits are sold separately. level. Recommended application notes for getting started ❐Visit the PSoC® 1 Kits page and refer the Kit Selector Guide with PSoC1 are: document to find out the suitable development kits and • AN75320: Getting Started with PSoC® 1 debuggers for all PSoC 1 families. • AN2094: PSoC®1 - Getting Started with GPIO ■The CY3217-MiniProg1 and CY8CKIT-002 PSoC® MiniProg3 • AN2015: PSoC® 1 - Getting Started with Flash & E2PROM device provide an interface for flash programming. • AN2014: Basics of PSoC® 1 Programming • AN32200: PSoC® 1 - Clocks and Global Resources ■Knowledge Base Articles (KBA): Provide design and appli- cation tips from experts on the devices/kits. For example, Flash • AN2010: PSoC®1 Best Practices and Recommendations read/write access from firmware, explains how we can read ■Technical Reference Manual (TRM): and write to flash in PSoC 1 devices PSoC Designer PSoC Designer is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design of systems based on CapSense (see Figure1). With PSoC Designer, you can: 1.Drag and drop user modules to build your hardware system 3.Configure user module design in the main design workspace 4.Explore the library of user modules 2.Codesign your application firmware with the PSoC hardware, 5.Review user module datasheets using the PSoC Designer IDE C compiler Figure 1. PSoC Designer Features 1 2 3 5 4 Document Number: 38-12028 Rev. *W Page 2 of 71

CY8C24123A CY8C24223A CY8C24423A Contents PSoC Functional Overview ..............................................4 AC Electrical Characteristics .....................................37 PSoC Core ..................................................................4 Packaging Information ...................................................51 Digital System .............................................................4 Packaging Dimensions ..............................................51 Analog System ............................................................5 Thermal Impedances .................................................57 Additional System Resources .....................................6 Capacitance on Crystal Pins .....................................57 PSoC Device Characteristics ......................................6 Solder Reflow Specifications .....................................57 Getting Started ..................................................................7 Development Tool Selection .........................................58 Application Notes ........................................................7 Software ....................................................................58 Development Kits ........................................................7 Development Kits ......................................................58 Training .......................................................................7 Evaluation Tools ........................................................58 CYPros Consultants ....................................................7 Device Programmers .................................................59 Solutions Library ..........................................................7 Accessories (Emulation and Programming) ..............59 Technical Support .......................................................7 Ordering Information ......................................................60 Development Tools ..........................................................8 Ordering Code Definitions .........................................60 PSoC Designer Software Subsystems ........................8 Acronyms ........................................................................61 Designing with PSoC Designer .......................................9 Acronyms Used .........................................................61 Select User Modules ...................................................9 Reference Documents ....................................................61 Configure User Modules ..............................................9 Document Conventions .................................................62 Organize and Connect ................................................9 Units of Measure .......................................................62 Generate, Verify, and Debug .......................................9 Numeric Conventions ................................................62 Pinouts ............................................................................10 Glossary ..........................................................................62 8-Pin Part Pinout .......................................................10 Errata ...............................................................................67 20-Pin Part Pinout .....................................................11 Part Numbers Affected ..............................................67 28-Pin Part Pinout .....................................................12 CY8C24123A Qualification Status ............................67 32-Pin Part Pinout .....................................................13 CY8C24123A Errata Summary .................................67 56-Pin Part Pinout .....................................................14 Document History Page .................................................68 Register Reference .........................................................15 Sales, Solutions, and Legal Information ......................71 Register Conventions ................................................15 Worldwide Sales and Design Support .......................71 Register Mapping Tables ..........................................15 Products ....................................................................71 Electrical Specifications ................................................18 PSoC® Solutions ......................................................71 Absolute Maximum Ratings .......................................18 Cypress Developer Community .................................71 Operating Temperature .............................................19 Technical Support .....................................................71 DC Electrical Characteristics .....................................19 Document Number: 38-12028 Rev. *W Page 3 of 71

CY8C24123A CY8C24223A CY8C24423A PSoC Functional Overview Digital System The digital system consists of four digital PSoC blocks. Each The PSoC family consists of many programmable block is an 8-bit resource that may be used alone or combined system-on-chips with on-chip controller devices. These devices with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, are designed to replace multiple traditional MCU-based system which are called user module references. components with a low-cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital Figure 2. Digital System Block Diagram logic, and programmable interconnects. This architecture makes it possible for you to create customized peripheral configurations Port 1 that match the requirements of each individual application. Port 2 Port 0 Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. Digital Clocks To System Bus To Analog From Core System The PSoC architecture, shown in Figure2, consists of four main areas: PSoC core, digital system, analog system, and system resources. Configurable global busing allows combining all the DIGITAL SYSTEM device resources into a complete custom system. The PSoC Digital PSoC Block Array CY8C24x23A family can have up to three I/O ports that connect ttPooS ftohoueCr g dCloigobitaraell dbilgoictakls a anndd a snixa laonga ilnotge rbclooncnkes.cts, providing access 8 8 Row Input Configuration DBB00 DBB0R1owD 0CB02 DCB0344 ConfigurationRow Output 8 8 The PSoC core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIOs. GIE[7:0] Global Digital GOE[7:0] The M8C CPU core is a powerful processor with speeds up to GIO[7:0] Interconnect GOO[7:0] 24Hz, providing a four-MIPS 8-bit Harvard-architecture microprocessor. The CPU uses an interrupt controller with Digital peripheral configurations are: 11vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the ■PWMs (8- and 16-bit) included sleep and watchdog timers (WDT). ■PWMs with dead band (8- and 16-bit) Memory encompasses 4 KB of flash for program storage, 256bytes of SRAM for data storage, and up to 2 KB of EEPROM ■Counters (8- to 32-bit) emulated using the flash. Program flash uses four protection ■Timers (8- to 32-bit) levels on blocks of 64 bytes, allowing customized software IP protection. ■UART 8-bit with selectable parity The PSoC device incorporates flexible internal clock generators, ■SPI master and slave including a 24 MHz internal main oscillator (IMO) accurate to ±2.5% to ±5% over temperature and voltage[1]. The 24 MHz IMO ■I2C slave and multi-master (one is available as a system can also be doubled to 48 MHz for use by the digital system. A resource) low power 32 kHz internal low speed oscillator (ILO) is provided ■CRC generator (8- to 32-bit) for the sleep timer and WDT. If crystal accuracy is required, the ECO (32.768 kHz external crystal oscillator) is available for use ■IrDA as a real time clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, ■PRS generators (8- to 32-bit) together with programmable clock dividers (as a System The digital blocks may be connected to any GPIO through a Resource), provide the flexibility to integrate almost any timing series of global buses that can route any signal to any pin. The requirement into the PSoC device. buses also allow for signal multiplexing and performing logic PSoC GPIOs provide connection to the CPU, digital, and analog operations. This configurability frees your designs from the resources of the device. Each pin’s drive mode may be selected constraints of a fixed peripheral controller. from eight options, allowing great flexibility in external Digital blocks are provided in rows of four, where the number of interfacing. Every pin can generate a system interrupt on high blocks varies by PSoC device family. This gives a choice of level, low level, and change from last read. system resources for your application. Family resources are shown in Table 1 on page 6. Note 1. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0°C or above 70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see “Errata” on page67. Document Number: 38-12028 Rev. *W Page 4 of 71

CY8C24123A CY8C24223A CY8C24423A Analog System Figure 3. Analog System Block Diagram The analog system consists of six configurable blocks, each P0[7] P0[6] consisting of an opamp circuit that allows the creation of complex analog signal flows. Analog peripherals are very flexible and can P0[5] P0[4] be customized to support specific application requirements. Some of the more common PSoC analog functions (most P0[3] P0[2] available as user modules) are: P0[1] P0[0] ■ADCs (up to two, with 6- to 14-bit resolution, selectable as n efI P2[6] incremental, delta sigma, and SAR) R P2[3] n DI ■Filters (two and four pole band-pass, low-pass, and notch) N P2[4] G A ■Amplifiers (up to two, with selectable gain to 48x) P2[1] P2[2] P2[0] ■Instrumentation amplifiers (one with selectable gain to 93x) ■Comparators (up to two, with 16 selectable thresholds) ■DACs (up to two, with 6 to 9-bit resolution) Array Input Configuration ■Multiplying DACs (up to two, with 6 to 9-bit resolution) ■High current output drivers (two with 30 mA drive as a PSoC Core resource) ACI0[1:0] ACI1[1:0] ■1.3 V reference (as a system resource) ■DTMF dialer Block Array ■Modulators ACB00 ACB01 ■Correlators ASC10 ASD11 ■Peak detectors ASD20 ASC21 ■Many other topologies possible Analog blocks are arranged in a column of three, which includes Analog Reference one continuous time (CT) and two switched capacitor (SC) blocks, as shown in Figure3 Interface to RefHi Reference AGNDIn Digital System RefLo Generators RefIn AGND Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 38-12028 Rev. *W Page 5 of 71

CY8C24123A CY8C24223A CY8C24423A Additional System Resources System resources, some of which are listed in the previous ■The decimator provides a custom hardware filter for digital sections, provide additional capability useful to complete signal processing applications including the creation of Delta systems. Additional resources include a multiplier, decimator, Sigma ADCs. switch-mode pump, low-voltage detection, and power-on-reset ■The I2C module provides 100- and 400-kHz communication (POR). Statements describing the merits of each system over two wires. slave, master, and multi-master are supported. resource follow: ■Low-voltage detection (LVD) interrupts can signal the appli- ■Digital clock dividers provide three customizable clock cation of falling voltage levels, while the advanced POR circuit frequencies for use in applications. The clocks can be routed eliminates the need for a system supervisor. to both the digital and analog systems. Additional clocks may be generated using digital PSoC blocks as clock dividers. ■An internal 1.3 V reference provides an absolute reference for the analog system, including ADCs and DACs. ■A multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math and ■An integrated switch-mode pump generates normal operating digital filters. voltages from a single 1.2 V battery cell, providing a low cost boost converter. PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or 4 analog blocks. Table1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is highlighted in this table. Table 1. PSoC Device Characteristics PSoC Part Digital Digital Digital Analog Analog Analog Analog SRAM Flash Number I/O Rows Blocks Inputs Outputs Columns Blocks Size Size CY8C29x66 up to 64 4 16 up to 12 4 4 12 2 K 32 K CY8C28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 1 K 16 K 12 + 4[2] CY8C27x43 up to 44 2 8 up to 12 4 4 12 256 16 K CY8C24x94 up to 56 1 4 up to 48 2 2 6 1 K 16 K CY8C24x23A up to 24 1 4 up to 12 2 2 6 256 4 K CY8C23x33 up to 26 1 4 up to 12 2 2 4 256 8 K CY8C22x45 up to 38 2 8 up to 38 0 4 6[2] 1 K 16 K CY8C21x45 up to 24 1 4 up to 24 0 4 6[2] 512 8 K CY8C21x34 up to 28 1 4 up to 28 0 2 4[2] 512 8 K CY8C21x23 up to 16 1 4 up to 8 0 2 4[2] 256 4 K CY8C20x34 up to 28 0 0 up to 28 0 0 3[2,3] 512 8 K CY8C20xx6 up to 36 0 0 up to 36 0 0 3[2,3] up to up to 2 K 32 K Notes 2. Limited analog functionality. 3. Two analog blocks and one CapSense®. Document Number: 38-12028 Rev. *W Page 6 of 71

CY8C24123A CY8C24223A CY8C24423A Getting Started covers a wide variety of topics and skill levels to assist you in your designs. For in depth information, along with detailed programming details, see the PSoC® Technical Reference Manual. CYPros Consultants For up-to-date ordering, packaging, and electrical specification Certified PSoC Consultants offer everything from technical information, see the latest PSoC device datasheets on the web. assistance to completed PSoC designs. To contact or become a PSoC Consultant go to the CYPros Consultants web site. Application Notes Solutions Library Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and Development Kits hardware design files that enable you to complete your designs quickly. PSoC Development Kits are available online from and through a growing number of regional and global distributors, which Technical Support include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Technical support – including a searchable knowledge base articles and technical forums – is also available online. If you Training cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, Document Number: 38-12028 Rev. *W Page 7 of 71

CY8C24123A CY8C24223A CY8C24423A Development Tools Code Generation Tools The code generation tools work seamlessly within the PSoC Designer™ is the revolutionary integrated design PSoCDesigner interface and have been tested with a full range environment (IDE) that you can use to customize PSoC to meet of debugging tools. You can develop your design in C, assembly, your specific application requirements. PSoC Designer software or a combination of the two. accelerates system design and time to market. Develop your Assemblers. The assemblers allow you to merge assembly applications using a library of precharacterized analog and digital code seamlessly with C code. Link libraries automatically use peripherals (called user modules) in a drag-and-drop design absolute addressing or are compiled in relative mode, and linked environment. Then, customize your design by leveraging the with other software modules to get absolute addressing. dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the C Language Compilers. C language compilers are available integrated debug environment, including in-circuit emulation and that support the PSoC family of devices. The products allow you standard software debug features. PSoC Designer includes: to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored ■Application editor graphical user interface (GUI) for device and to the PSoC architecture. They come complete with embedded user module configuration and dynamic reconfiguration libraries providing port and bus operations, standard keypad and ■Extensive user module catalog display support, and extended math functionality. ■Integrated source-code editor (C and assembly) Debugger ■Free C compiler with no size restrictions or time limits PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in ■Built-in debugger a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and ■In-circuit emulation read and write data memory, and read and write I/O registers. ■Built-in support for communication interfaces: You can read and write CPU registers, set and clear breakpoints, ❐Hardware and software I2C slaves and masters and provide program run, halt, and step control. The debugger ❐Full-speed USB 2.0 also lets you to create a trace buffer of registers and memory locations of interest. ❐Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and Online Help System wireless PSoC Designer supports the entire library of PSoC 1 devices and The online help system displays online, context-sensitive help. runs on Windows XP, Windows Vista, and Windows 7. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also PSoC Designer Software Subsystems provides tutorials and links to FAQs and an Online Support Forum to aid the designer. Design Entry In-Circuit Emulator In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use A low-cost, high-functionality in-circuit emulator (ICE) is the PSoC blocks, which are called user modules. Examples of available for development support. This hardware can program user modules are analog-to-digital converters (ADCs), single devices. digital-to-analog converters (DACs), amplifiers, and filters. The emulator consists of a base unit that connects to the PC Configure the user modules for your chosen application and using a USB port. The base unit is universal and operates with connect them to each other and to the proper pins. Then all PSoC devices. Emulation pods for each device family are generate your project. This prepopulates your project with APIs available separately. The emulation pod takes the place of the and libraries that you can use to program your application. PSoC device in the target board and performs full-speed The tool also supports easy development of multiple (24MHz) operation. configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this lets you to use more than 100 percent of PSoC's resources for an application. Document Number: 38-12028 Rev. *W Page 8 of 71

CY8C24123A CY8C24223A CY8C24423A Designing with PSoC Designer module parameter, and other information that you may need to successfully implement your design. The development process for the PSoC device differs from that Organize and Connect of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a Build signal chains at the chip level by interconnecting user unique flexibility that pays dividends in managing specification modules to each other and the I/O pins. Perform the selection, change during development and lowering inventory costs. These configuration, and routing so that you have complete control over configurable resources, called PSoC blocks, have the ability to all on-chip resources. implement a wide variety of user-selectable functions. The PSoC development process is: Generate, Verify, and Debug 1.Select user modules. When you are ready to test the hardware configuration or move 2.Configure user modules. on to developing code for the project, perform the “Generate Configuration Files” step. This causes PSoC Designer to 3.Organize and connect. generate source code that automatically configures the device to 4.Generate, verify, and debug. your specification and provides the software for the system. The generated code provides APIs with high-level functions to control Select User Modules and respond to hardware events at run time, and interrupt PSoC Designer provides a library of prebuilt, pretested hardware service routines that you can adapt as needed. peripheral components called “user modules.” User modules A complete code development environment lets you to develop make selecting and implementing peripheral devices, both and customize your applications in C, assembly language, or analog and digital, simple. both. Configure User Modules The last step in the development process takes place inside PSoC Designer’s Debugger (accessed by clicking the Connect Each user module that you select establishes the basic register icon). PSoC Designer downloads the HEX image to the ICE settings that implement the selected function. They also provide where it runs at full-speed. PSoC Designer debugging parameters and properties that allow you to tailor their precise capabilities rival those of systems costing many times more. In configuration to your particular application. For example, a PWM addition to traditional single-step, run-to-breakpoint, and User Module configures one or more digital PSoC blocks, one watch-variable features, the debug interface provides a large for each eight bits of resolution. Using these parameters, you can trace buffer. It lets you to define complex breakpoint events that establish the pulse width and duty cycle. Configure the include monitoring address and data bus values, memory parameters and properties to correspond to your chosen locations, and external signals. application. Enter values directly or by selecting values from drop-down menus. All of the user modules are documented in datasheets that may be viewed directly in PSoCDesigner or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user Document Number: 38-12028 Rev. *W Page 9 of 71

CY8C24123A CY8C24223A CY8C24423A Pinouts This section describes, lists, and illustrates the CY8C24x23A PSoC device pins and pinout configurations. Every port pin (labeled with a “P”) is capable of digital I/O. However, V , V , SMP, and XRES are not capable of digital I/O. SS DD 8-Pin Part Pinout Table 2. 8-Pin PDIP and SOIC Pin Type Pin Description No. Digital Analog Name 1 I/O I/O P0[5] Analog column mux input and column Figure 4. CY8C24123A 8-Pin PSoC Device output 2 I/O I/O P0[3] Analog column mux input and column A, IO, P0[5] 1 8 VDD output A, IO, P0[3] 2 PDIP7 P0[4], A, I 3 I/O P1[1] Crystal input (XTALin), I2C serial clock I2C SCL, XTALin, P1[1] 3SOIC6 P0[2], A, I (SCL), ISSP-SCLK[4] VSS 4 5 P1[0], XTALout, I2C SDA 4 Power V Ground connection SS 5 I/O P1[0] Crystal output (XTALout), I2C serial data (SDA), ISSP-SDATA[4] 6 I/O I P0[2] Analog column mux input 7 I/O I P0[4] Analog column mux input 8 Power V Supply voltage DD LEGEND: A = Analog, I = Input, and O = Output. Note 4. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 38-12028 Rev. *W Page 10 of 71

CY8C24123A CY8C24223A CY8C24423A 20-Pin Part Pinout Table 3. 20-Pin PDIP, SSOP, and SOIC Pin Type Pin Description No. Digital Analog Name 1 I/O I P0[7] Analog column mux input Figure 5. CY8C24223A 20-Pin PSoC Device 2 I/O I/O P0[5] Analog column mux input and column output 3 I/O I/O P0[3] Analog column mux input and column output A, I, P0[7] 1 20 VDD A, IO, P0[5] 2 19 P0[6], A, I 4 I/O I P0[1] Analog column mux input A, IO, P0[3] 3 18 P0[4], A, I 5 Power SMP SMP connection to external components A, I, P0[1] 4 PDIP 17 P0[2], A, I required SMP 5 SSOP 16 P0[0], A, I I2C SCL, P1[7] 6 15 XRES 6 I/O P1[7] I2C SCL I2C SDA, P1[5] 7 SOIC 14 P1[6] 7 I/O P1[5] I2C SDA P1[3] 8 13 P1[4], EXTCLK I2C SCL, XTALin, P1[1] 9 12 P1[2] 8 I/O P1[3] VSS 10 11 PI21C[0 S],D XATALout, 9 I/O P1[1] XTALin, I2C SCL, ISSP-SCLK[5] 10 Power V Ground connection. SS 11 I/O P1[0] XTALout, I2C SDA, ISSP-SDATA[5] 12 I/O P1[2] 13 I/O P1[4] Optional external clock input (EXTCLK) 14 I/O P1[6] 15 Input XRES Active high external reset with internal pull-down 16 I/O I P0[0] Analog column mux input 17 I/O I P0[2] Analog column mux input 18 I/O I P0[4] Analog column mux input 19 I/O I P0[6] Analog column mux input 20 Power V Supply voltage DD LEGEND: A = Analog, I = Input, and O = Output. Note 5. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 38-12028 Rev. *W Page 11 of 71

CY8C24123A CY8C24223A CY8C24423A 28-Pin Part Pinout Table 4. 28-Pin PDIP, SSOP, and SOIC Pin Type Pin Description No. Digital Analog Name 1 I/O I P0[7] Analog column mux input Figure 6. CY8C24423A 28-Pin PSoC Device 2 I/O I/O P0[5] Analog column mux input and column output 3 I/O I/O P0[3] Analog column mux input and column output A, I, P0[7] 1 28 VDD A, IO, P0[5] 2 27 P0[6], A, I 4 I/O I P0[1] Analog column mux input A, IO, P0[3] 3 26 P0[4], A, I 5 I/O P2[7] A, I, P0[1] 4 25 P0[2], A, I P2[7] 5 24 P0[0], A, I 6 I/O P2[5] P2[5] 6 PDIP 23 P2[6], External VRef 7 I/O I P2[3] Direct switched capacitor block input A, I, P2[3] 7 SSOP 22 P2[4], External AGND A, I, P2[1] 8 21 P2[2], A, I 8 I/O I P2[1] Direct switched capacitor block input SOIC SMP 9 20 P2[0], A, I 9 Power SMP SMP connection to external components I2CSCL, P1[7] 10 19 XRES required I2C SDA, P1[5] 11 18 P1[6] 10 I/O P1[7] I2C SCL P1[3] 12 17 P1[4], EXTCLK I2C SCL, XTALin, P1[1] 13 16 P1[2] 11 I/O P1[5] I2C SDA VSS 14 15 P1[0], XTALout, I2 CSDA 12 I/O P1[3] 13 I/O P1[1] XTALin, I2C SCL, ISSP-SCLK[6] 14 Power V Ground connection. SS 15 I/O P1[0] XTALout, I2C SDA, ISSP-SDATA[6] 16 I/O P1[2] 17 I/O P1[4] Optional EXTCLK Not for Production 18 I/O P1[6] 19 Input XRES Active high external reset with internal pull-down 20 I/O I P2[0] Direct switched capacitor block input 21 I/O I P2[2] Direct switched capacitor block input 22 I/O P2[4] External analog ground (AGND) 23 I/O P2[6] External voltage reference (V ) REF 24 I/O I P0[0] Analog column mux input 25 I/O I P0[2] Analog column mux input 26 I/O I P0[4] Analog column mux input 27 I/O I P0[6] Analog column mux input 28 Power V Supply voltage DD LEGEND: A = Analog, I = Input, and O = Output. Note 6. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 38-12028 Rev. *W Page 12 of 71

CY8C24123A CY8C24223A CY8C24423A 32-Pin Part Pinout Table 5. 32-Pin QFN[7] Type Pin Pin No. Description Digital Analog Name 1 I/O P2[7] Figure 7. CY8C24423A 32-Pin PSoC Device 2 I/O P2[5] O O 3 I/O I P2[3] Direct switched capacitor block input A, I A, I A, I A, I A, I A, I 4 I/O I P2[1] Direct switched capacitor block input P0[1], P0[3], P0[5], P0[7], VDDP0[6], P0[4], NC 5 Power V Ground connection SS 2 1 0 9 8 7 6 5 3 3 3 2 2 2 2 2 6 Power SMP SMP connection to external components P2[7] 1 24 P0[2], A, I required P2[5] 2 23 P0[0], A, I 7 I/O P1[7] I2C SCL A, I, P2[3] 3 22 P2[6], External VRef A, I, P2[1] 4 QFN 21 P2[4], External AGND 8 I/O P1[5] I2C SDA VSS 5 (Top View) 20 P2[2], A, I 9 NC No connection. Pin must be left floating SMP 6 19 P2[0], A, I I2C SCL, P1[7] 7 18 XRES 10 I/O P1[3] I2C SDA, P1[5] 8 17 P1[6] 11 I/O P1[1] XTALin, I2C SCL, ISSP-SCLK[8] 9 10 11 12 13 14 15 16 12 Power VSS Ground Connection NC 1[3] 1[1]VSS 1[0] 1[2] 1[4] NC 1143 II//OO PP11[[20]] XTALout, I2C SDA, ISSP-SDATA[8] P TALin, P ALout, P P TCLK, P X T X 15 I/O P1[4] Optional EXTCLK CL, A, X E S D 16 NC No connection. Pin must be left floating 2C C S I 2 17 I/O P1[6] I 18 Input XRES Active high external reset with internal pull-down 19 I/O I P2[0] Direct switched capacitor block input 20 I/O I P2[2] Direct switched capacitor block input 21 I/O P2[4] External AGND 22 I/O P2[6] External V REF 23 I/O I P0[0] Analog column mux input 24 I/O I P0[2] Analog column mux input 25 NC No connection. Pin must be left floating 26 I/O I P0[4] Analog column mux input 27 I/O I P0[6] Analog column mux input 28 Power V Supply voltage DD 29 I/O I P0[7] Analog column mux input 30 I/O I/O P0[5] Analog column mux input and column output 31 I/O I/O P0[3] Analog column mux input and column output 32 I/O I P0[1] Analog column mux input LEGEND: A = Analog, I = Input, and O = Output. Notes 7. The center pad on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 8. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 38-12028 Rev. *W Page 13 of 71

CY8C24123A CY8C24223A CY8C24423A 56-Pin Part Pinout The 56-pin SSOP part is for the CY8C24000A On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 6. 56-Pin SSOP OCD Type Pin Pin No. Description Digital Analog Name 1 NC No connection. Pin must be left floating Figure 8. CY8C24000A 56-Pin PSoC Device 2 I/O I P0[7] Analog column mux input 3 I/O I P0[5] Analog column mux input and column output NC 1 56 VDD 4 I/O I P0[3] Analog column mux input and column output AI, P0[7] 2 55 P0[6], AI 5 I/O I P0[1] Analog column mux input AIO, P0[5] 3 54 P0[4], AIO 6 I/O P2[7] AIO, P0[3] 4 53 P0[2], AIO 7 I/O P2[5] AI, PP20[[71]] 56 5521 PP02[[06]],, AEIxternal VRef 8 I/O I P2[3] Direct switched capacitor block input P2[5] 7 50 P2[4], External AGND 9 I/O I P2[1] Direct switched capacitor block input AI, P2[3] 8 49 P2[2], AI 10 NC No connection. Pin must be left floating AI, P2[1] 9 48 P2[0], AI 11 NC No connection. Pin must be left floating NC 10 47 NC NC 11 46 NC 12 NC No connection. Pin must be left floating NC 12 45 NC 13 NC No connection. Pin must be left floating NC 13 44 NC 14 OCD OCDE OCD even data I/O OCDE 14 SSOP 43 CCLK 15 OCD OCDO OCD odd data output OCDO 15 42 HCLK SMP 16 41 XRES 16 Power SMP SneMnPts connection to required external compo- NC 17 40 NC NC 18 39 NC 17 NC No connection. Pin must be left floating NC 19 38 NC 18 NC No connection. Pin must be left floating NC 20 37 NC 19 NC No connection. Pin must be left floating NC 21 36 NC 20 NC No connection. Pin must be left floating NC 22 35 NC I2C SCL, P1[7] 23 34 P1[6] 21 NC No connection. Pin must be left floating I2C SDA, P1[5] 24 33 P1[4], EXTCLK 22 NC No connection. Pin must be left floating NC 25 32 P1[2] 23 I/O P1[7] I2C SCL P1[3] 26 31 P1[0], XTALOut, I2C SDA, SDATA 24 I/O P1[5] I2C SDA SCLK, I2C SCL, XTALIn, P1[1] 27 30 NC 25 NC No connection. Pin must be left floating VSS 28 29 NC 26 I/O P1[3] 27 I/O P1[1] XTALin, I2C SCL, ISSP-SCLK[9] 28 Power VDD Supply voltage 29 NC No connection. Pin must be left floating 30 NC No connection. Pin must be left floating 31 I/O P1[0] XTALout, I2C SDA, ISSP-SDATA[9] 32 I/O P1[2] 33 I/O P1[4] Optional EXTCLK 34 I/O P1[6] 35 NC No connection. Pin must be left floating 36 NC No connection. Pin must be left floating 37 NC No connection. Pin must be left floating 38 NC No connection. Pin must be left floating 39 NC No connection. Pin must be left floating 40 NC No connection. Pin must be left floating 41 Input XRES Active high external reset with internal pull-down. 42 OCD HCLK OCD high speed clock output. 43 OCD CCLK OCD CPU clock output. 44 NC No connection. Pin must be left floating 45 NC No connection. Pin must be left floating 46 NC No connection. Pin must be left floating 47 NC No connection. Pin must be left floating 48 I/O I P2[0] Direct switched capacitor block input. 49 I/O I P2[2] Direct switched capacitor block input. 50 I/O P2[4] External AGND. 51 I/O P2[6] External VREF. 52 I/O I P0[0] Analog column mux input. 53 I/O I P0[2] Analog column mux input and column output. 54 I/O I P0[4] Analog column mux input and column output. 55 I/O I P0[6] Analog column mux input. 56 Power VDD Supply voltage. LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug. Note 9. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 38-12028 Rev. *W Page 14 of 71

CY8C24123A CY8C24223A CY8C24423A Register Reference This section lists the registers of the CY8C24x23A PSoC device. For detailed register information, see the PSoC Programmable Sytem-on-Chip Reference Manual. Register Conventions Register Mapping Tables The PSoC device has a total register address space of Abbreviations Used 512bytes. The register space is referred to as I/O space and is The register conventions specific to this section are listed in the divided into two banks, Bank 0 and Bank 1. The XOI bit in the following table. Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set, the user is in Bank 1. Table 7. Abbreviations Note In the following register mapping tables, blank fields are Convention Description reserved and must not be accessed. R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific Document Number: 38-12028 Rev. *W Page 15 of 71

CY8C24123A CY8C24223A CY8C24423A Table 8. Register Map Bank 0 Table: User Space Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access PRT0DR 00 RW 40 ASC10CR0 80 RW C0 PRT0IE 01 RW 41 ASC10CR1 81 RW C1 PRT0GS 02 RW 42 ASC10CR2 82 RW C2 PRT0DM2 03 RW 43 ASC10CR3 83 RW C3 PRT1DR 04 RW 44 ASD11CR0 84 RW C4 PRT1IE 05 RW 45 ASD11CR1 85 RW C5 PRT1GS 06 RW 46 ASD11CR2 86 RW C6 PRT1DM2 07 RW 47 ASD11CR3 87 RW C7 PRT2DR 08 RW 48 88 C8 PRT2IE 09 RW 49 89 C9 PRT2GS 0A RW 4A 8A CA PRT2DM2 0B RW 4B 8B CB 0C 4C 8C CC 0D 4D 8D CD 0E 4E 8E CE 0F 4F 8F CF 10 50 ASD20CR0 90 RW D0 11 51 ASD20CR1 91 RW D1 12 52 ASD20CR2 92 RW D2 13 53 ASD20CR3 93 RW D3 14 54 ASC21CR0 94 RW D4 15 55 ASC21CR1 95 RW D5 16 56 ASC21CR2 96 RW I2C_CFG D6 RW 17 57 ASC21CR3 97 RW I2C_SCR D7 # 18 58 98 I2C_DR D8 RW 19 59 99 I2C_MSCR D9 # 1A 5A 9A INT_CLR0 DA RW 1B 5B 9B INT_CLR1 DB RW 1C 5C 9C DC 1D 5D 9D INT_CLR3 DD RW 1E 5E 9E INT_MSK3 DE RW 1F 5F 9F DF DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW DBB00DR2 22 RW 62 A2 INT_VC E2 RC DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW DCB02DR0 28 # 68 A8 MUL_X E8 W DCB02DR1 29 W 69 A9 MUL_Y E9 W DCB02DR2 2A RW 6A AA MUL_DH EA R DCB02CR0 2B # 6B AB MUL_DL EB R DCB03DR0 2C # 6C AC ACC_DR1 EC RW DCB03DR1 2D W 6D AD ACC_DR0 ED RW DCB03DR2 2E RW 6E AE ACC_DR3 EE RW DCB03CR0 2F # 6F AF ACC_DR2 EF RW 30 ACB00CR3 70 RW RDI0RI B0 RW F0 31 ACB00CR0 71 RW RDI0SYN B1 RW F1 32 ACB00CR1 72 RW RDI0IS B2 RW F2 33 ACB00CR2 73 RW RDI0LT0 B3 RW F3 34 ACB01CR3 74 RW RDI0LT1 B4 RW F4 35 ACB01CR0 75 RW RDI0RO0 B5 RW F5 36 ACB01CR1 76 RW RDI0RO1 B6 RW F6 37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF # Blank fields are Reserved and must not be accessed. # Access is bit specific. Document Number: 38-12028 Rev. *W Page 16 of 71

CY8C24123A CY8C24223A CY8C24423A Table 9. Register Map Bank 1 Table: Configuration Space Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access PRT0DM0 00 RW 40 ASC10CR0 80 RW C0 PRT0DM1 01 RW 41 ASC10CR1 81 RW C1 PRT0IC0 02 RW 42 ASC10CR2 82 RW C2 PRT0IC1 03 RW 43 ASC10CR3 83 RW C3 PRT1DM0 04 RW 44 ASD11CR0 84 RW C4 PRT1DM1 05 RW 45 ASD11CR1 85 RW C5 PRT1IC0 06 RW 46 ASD11CR2 86 RW C6 PRT1IC1 07 RW 47 ASD11CR3 87 RW C7 PRT2DM0 08 RW 48 88 C8 PRT2DM1 09 RW 49 89 C9 PRT2IC0 0A RW 4A 8A CA PRT2IC1 0B RW 4B 8B CB 0C 4C 8C CC 0D 4D 8D CD 0E 4E 8E CE 0F 4F 8F CF 10 50 ASD20CR0 90 RW GDI_O_IN D0 RW 11 51 ASD20CR1 91 RW GDI_E_IN D1 RW 12 52 ASD20CR2 92 RW GDI_O_OU D2 RW 13 53 ASD20CR3 93 RW GDI_E_OU D3 RW 14 54 ASC21CR0 94 RW D4 15 55 ASC21CR1 95 RW D5 16 56 ASC21CR2 96 RW D6 17 57 ASC21CR3 97 RW D7 18 58 98 D8 19 59 99 D9 1A 5A 9A DA 1B 5B 9B DB 1C 5C 9C DC 1D 5D 9D OSC_GO_EN DD RW 1E 5E 9E OSC_CR4 DE RW 1F 5F 9F OSC_CR3 DF RW DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW 23 AMD_CR0 63 RW A3 VLT_CR E3 RW DBB01FN 24 RW 64 A4 VLT_CMP E4 R DBB01IN 25 RW 65 A5 E5 DBB01OU 26 RW AMD_CR1 66 RW A6 E6 27 ALT_CR0 67 RW A7 E7 DCB02FN 28 RW 68 A8 IMO_TR E8 W DCB02IN 29 RW 69 A9 ILO_TR E9 W DCB02OU 2A RW 6A AA BDG_TR EA RW 2B 6B AB ECO_TR EB W DCB03FN 2C RW 6C AC EC DCB03IN 2D RW 6D AD ED DCB03OU 2E RW 6E AE EE 2F 6F AF EF 30 ACB00CR3 70 RW RDI0RI B0 RW F0 31 ACB00CR0 71 RW RDI0SYN B1 RW F1 32 ACB00CR1 72 RW RDI0IS B2 RW F2 33 ACB00CR2 73 RW RDI0LT0 B3 RW F3 34 ACB01CR3 74 RW RDI0LT1 B4 RW F4 35 ACB01CR0 75 RW RDI0RO0 B5 RW F5 36 ACB01CR1 76 RW RDI0RO1 B6 RW F6 37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF # Blank fields are Reserved and must not be accessed. # Access is bit specific. Document Number: 38-12028 Rev. *W Page 17 of 71

CY8C24123A CY8C24223A CY8C24423A Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C24x23A PSoC device. For the latest electrical specifications, check if you have the most recent datasheet by visiting the website at http://www.cypress.com. Specifications are valid for –40 °C  T  85 °C and T  100 °C, except where noted. A J Refer to Table 30 on page 37 for the electrical specifications for the IMO using SLIMO mode. Figure 9. Voltage versus CPU Frequency Figure 10. IMO Frequency Trim Options 5.25 5.25 0 S= LIMO SLIMO e Mdode=1 Mode=0 o 4.75 O V 4.75 M Vdd Volta Regpieornatianlgid Vdd Voltage 3.60 SLIMO g SLIMO SLIMO e Mode=1 Mode=0 3.00 3.00 SLIMO SLIMO Mode=1Mode=1 2.40 2.40 93 kHz 3 MHz 12 MHz 24 MHz 93 kHz 6 MHz 12 MHz 24 MHz CPU Frequency IMOF requency Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 10. Absolute Maximum Ratings Symbol Description Min Typ Max Units Notes T Storage temperature –55 25 +100 °C Higher storage temperatures STG reduce data retention time. Recommended storage temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 65 °C degrades reliability. T Bake temperature – 125 See °C BAKETEMP package label t Bake time See – 72 Hours BAKETIME package label T Ambient temperature with power applied –40 – +85 °C A V Supply voltage on V relative to V –0.5 – +6.0 V DD DD SS V DC input voltage V – 0.5 – V + 0.5 V IO SS DD V DC voltage applied to tri-state V – 0.5 – V + 0.5 V IOZ SS DD I Maximum current into any port pin –25 – +50 mA MIO ESD Electrostatic discharge voltage 2000 – – V Human body model ESD. LU Latch up current – – 200 mA Document Number: 38-12028 Rev. *W Page 18 of 71

CY8C24123A CY8C24223A CY8C24423A Operating Temperature Table 11. Operating Temperature Symbol Description Min Typ Max Units Notes T Ambient temperature –40 – +85 °C A T Junction temperature –40 – +100 °C The temperature rise from ambient J to junction is package specific. See Table 49 on page 57. You must limit the power consumption to comply with this requirement DC Electrical Characteristics DC Chip-Level Specifications Table12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters A A A are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 12. DC Chip-Level Specifications Symbol Description Min Typ Max Units Notes V Supply voltage 2.4 – 5.25 V See DC POR and LVD specifications, DD Table 27 on page 35 I Supply current – 5 8 mA Conditions are V = 5.0 V, T = 25 °C, DD DD A CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off SLIMO mode = 0. IMO = 24 MHz I Supply current – 3.3 6.0 mA Conditions are V = 3.3 V, T = 25 °C, DD3 DD A CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. SLIMO mode = 0. IMO = 24 MHz I Supply current – 2 4 mA Conditions are V = 2.7 V, T = 25 °C, DD27 DD A CPU = 0.75 MHz, SYSCLK doubler disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz, analog power = off. SLIMO mode = 1. IMO = 6 MHz I Sleep (mode) current with POR, LVD, sleep timer, – 3 6.5 µA Conditions are with internal slow speed SB and WDT.[10] oscillator, V = 3.3 V, –40 °C  T  DD A 55 °C, analog power = off I Sleep (mode) current with POR, LVD, sleep timer, – 4 25 µA Conditions are with internal slow speed SBH and WDT at high temperature.[10] oscillator, V = 3.3 V, 55 °C < T  DD A 85 °C, analog power = off I Sleep (mode) current with POR, LVD, sleep timer, – 4 7.5 µA Conditions are with properly loaded, SBXTL WDT, and external crystal.[10] 1 µW max, 32.768 kHz crystal. V = 3.3 V, –40 °C  T  55 °C, analog DD A power = off I Sleep (Mode) current with POR, LVD, sleep timer, – 5 26 µA Conditions are with properly loaded, 1µW SBXTLH WDT, and external crystal at high temperature.[10] max, 32.768 kHz crystal. V = 3.3 V, 55 °C < T  85 °C, analog DD A power = off V Reference voltage (Bandgap) 1.28 1.30 1.32 V Trimmed for appropriate V . REF DD V > 3.0 V DD V Reference voltage (Bandgap) 1.16 1.30 1.32 V Trimmed for appropriate V . REF27 DD V = 2.4 V to 3.0 V DD Note 10.Standby current includes all functions (POR, LVD, WDT, sleep time) needed for reliable system operation. This must be compared with devices that have similar functions enabled. Document Number: 38-12028 Rev. *W Page 19 of 71

CY8C24123A CY8C24223A CY8C24423A DC GPIO Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. A A A Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 13. 5 V and 3.3 V DC GPIO Specifications Symbol Description Min Typ Max Units Notes R Pull-up resistor 4 5.6 8 k PU R Pull-down resistor 4 5.6 8 k PD V High output level V – 1.0 – – V I = 10 mA, V = 4.75 to 5.25 V OH DD OH DD (maximum 40 mA on even port pins (for example, P0[2], P1[4]), maximum 40 mA on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined I budget. OH V Low output level – – 0.75 V I = 25 mA, V = 4.75 to 5.25 V OL OL DD (maximum 100 mA on even port pins (for example, P0[2], P1[4]), maximum 100 mA on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined I budget. OL I High level source current 10 – – mA V = V – 1.0 V, see the limitations OH OH DD of the total current in the note for V OH I Low level sink current 25 – – mA V = 0.75 V, see the limitations of the OL OL total current in the note for V OL V Input low level – – 0.8 V V = 3.0 to 5.25 IL DD V Input high level 2.1 – V V = 3.0 to 5.25 IH DD V Input hysterisis – 60 – mV H I Input leakage (absolute value) – 1 – nA Gross tested to 1 µA IL C Capacitive load on pins as input – 3.5 10 pF Package and pin dependent. IN Temp = 25 °C C Capacitive load on pins as output – 3.5 10 pF Package and pin dependent. OUT Temp = 25 °C Table 14. 2.7 V DC GPIO Specifications Symbol Description Min Typ Max Units Notes R Pull-up resistor 4 5.6 8 k PU R Pull-down resistor 4 5.6 8 k PD V High output level V – 0.4 – – V I = 2 mA (6.25 Typ), V = 2.4 to OH DD OH DD 3.0 V (16 mA maximum, 50 mA Typ combined I budget). OH V Low output level – – 0.75 V I = 11.25 mA, V = 2.4 to 3.0 V (90 OL OL DD mA maximum combined I budget). OL I High level source current 2 – – mA V = V – 0.4, see the limitations of OH OH DD total current in note for V . OH V Input low level – – 0.75 V V = 2.4 to 3.0 IL DD V Input high level 2.0 – – V V = 2.4 to 3.0 IH DD V Input hysteresis – 90 – mV H I Low level sink current 11.25 – – mA V = .75, see the limitations of total OL OL current in note for V . OL I Input leakage (absolute value) – 1 – nA Gross tested to 1 µA IL C Capacitive load on pins as input – 3.5 10 pF Package and pin dependent. IN Temp = 25 °C C Capacitive load on pins as output – 3.5 10 pF Package and pin dependent. OUT Temp = 25 °C Document Number: 38-12028 Rev. *W Page 20 of 71

CY8C24123A CY8C24223A CY8C24423A DC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. A A A Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. The operational amplifier is a component of both the analog continuous time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the analog continuous time PSoC block. Typical parameters are measured at 5 V at 25°C and are for design guidance only. Table 15. 5 V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes V Input offset voltage (absolute value) OSOA Power = low, Opamp bias = high – 1.6 10 mV Power = medium, Opamp bias = high 1.3 8 mV – Power = high, Opamp bias = high 1.2 7.5 mV – TCV Average input offset voltage drift – 7.0 35.0 µV/°C OSOA I Input leakage current (port 0 analog pins) – 20 – pA Gross tested to 1 µA EBOA C Input capacitance (port 0 analog pins) – 4.5 9.5 pF Package and pin dependent. INOA Temp = 25 °C V Common mode voltage range 0.0 – V V The common mode input voltage CMOA DD Common mode voltage range (high power or high V – 0.5 range is measured through an 0.5 – DD Opamp bias) analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. G Open loop gain Specification is applicable at high OLOA Power = low, Opamp bias = high 60 – – dB Opamp bias. For low Opamp bias Power = medium, Opamp bias = high 60 – – dB mode, minimum is 60 dB. Power = high, Opamp bias = high 80 – – dB V High output voltage swing (internal signals) OHIGHOA Power = low, Opamp bias = high V – 0.2 – – V DD Power = medium, Opamp bias = high V – 0.2 – – V DD Power = high, Opamp bias = high V – 0.5 – – V DD V Low output voltage swing (internal signals) OLOWOA Power = low, Opamp bias = high – – 0.2 V Power = medium, Opamp bias = high – – 0.2 V Power = high, Opamp bias = high – – 0.5 V I Supply current (including associated AGND buffer) SOA Power = low, Opamp bias = low – 150 200 µA Power = low, Opamp bias = high – 300 400 µA Power = medium, Opamp bias = low – 600 800 µA Power = medium, Opamp bias = high – 1200 1600 µA Power = high, Opamp bias = low – 2400 3200 µA Power = high, Opamp bias = high – 4600 6400 µA PSRR Supply voltage rejection ratio 64 80 – dB V V (V – 2.25) or OA SS IN DD (V – 1.25 V) V  V DD IN DD Document Number: 38-12028 Rev. *W Page 21 of 71

CY8C24123A CY8C24223A CY8C24423A Table 16. 3.3 V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes V Input offset voltage (absolute value) Power = high, Opamp bias = high OSOA Power = low, Opamp bias = high – 1.65 10 mV setting is not allowed for 3.3 V V DD Power = medium, Opamp bias = high – 1.32 8 mV operation. Power = high, Opamp bias = high – – – mV TCV Average input offset voltage drift – 7.0 35.0 µV/°C OSOA I Input leakage current (port 0 analog pins) – 20 – pA Gross tested to 1 A EBOA C Input capacitance (port 0 analog pins) – 4.5 9.5 pF Package and pin dependent. INOA Temp = 25 °C V Common mode voltage range 0.2 – V – 0.2 V The common-mode input voltage CMOA DD range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. G Open loop gain Specification is applicable at low OLOA Power = low, ppamp Opamp bias = low 60 – – dB Opamp bias. For high Opamp bias Power = medium, Opamp bias = low 60 – – dB mode (except high power, high Power = high, Opamp bias = low 80 – – dB Opamp bias), minimum is 60 dB. V High output voltage swing (internal signals) Power = high, Opamp bias = high OHIGHOA Power = low, Opamp bias = low V – 0.2 – – V setting is not allowed for 3.3 V V DD DD Power = medium, Opamp bias = low V – 0.2 – – V operation. DD Power = high, Opamp bias = low V – 0.2 – – V DD V Low output voltage swing (internal signals) Power = high, Opamp bias = high OLOWOA Power = low, ppamp Opamp bias = low – – 0.2 V setting is not allowed for 3.3 V V DD Power = medium, Opamp bias = low – – 0.2 V operation. Power = high, Opamp bias = low – – 0.2 V I Supply current (including associated AGND Power = high, Opamp bias = high SOA buffer) setting is not allowed for 3.3 V V DD Power = low, Opamp bias = low – 150 200 A operation. Power = low, Opamp bias = high – 300 400 A Power = medium, Opamp bias = low – 600 800 A Power = medium, Opamp bias = high – 1200 1600 A Power = high, Opamp bias = low – 2400 3200 A Power = high, Opamp bias = high – – – A PSRR Supply voltage rejection ratio 64 80 – dB V V (V – 2.25) or OA SS IN DD (V – 1.25 V) V  V DD IN DD Document Number: 38-12028 Rev. *W Page 22 of 71

CY8C24123A CY8C24223A CY8C24423A Table 17. 2.7 V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes V Input offset voltage (absolute value) Power = high, Opamp bias = high OSOA Power = low, Opamp bias = high – 1.65 10 mV setting is not allowed for 2.7 V V DD Power = medium, Opamp bias = high – 1.32 8 mV operation. Power = high, Opamp bias = high – – – mV TCV Average input offset voltage drift – 7.0 35.0 V/°C OSOA I Input leakage current (port 0 analog pins) – 20 – pA Gross tested to 1 A EBOA C Input capacitance (port 0 analog pins) – 4.5 9.5 pF Package and pin dependent. INOA Temp = 25°C V Common mode voltage range 0.2 – V – 0.2 V The common-mode input voltage CMOA DD range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. G Open loop gain Specification is applicable at low OLOA Power = low, Opamp bias = low 60 – – dB Opamp bias. For high Opamp bias Power = medium, Opamp bias = low 60 – – dB mode, (except high power, high Power = high, Opamp bias = low 80 – – dB Opamp bias), minimum is 60 dB. V High output voltage swing (internal signals) Power = high, Opamp bias = high OHIGHOA Power = low, Opamp bias = low V – 0.2 – – V setting is not allowed for 2.7 V V DD DD Power = medium, Opamp bias = low V – 0.2 – – V operation. DD Power = high, Opamp bias = low V – 0.2 – – V DD V Low output voltage swing (internal signals) Power = high, Opamp bias = high OLOWOA Power = low, Opamp bias = low – – 0.2 V setting is not allowed for 2.7 V V DD Power = medium, Opamp bias = low – – 0.2 V operation. Power = high, Opamp bias = low – – 0.2 V I Supply current (including associated AGND Power = high, Opamp bias = high SOA buffer) setting is not allowed for 2.7 V V DD Power = low, Opamp bias = low – 150 200 A operation. Power = low, Opamp bias = high – 300 400 A Power = medium, Opamp bias = low – 600 800 A Power = medium, Opamp bias = high – 1200 1600 A Power = high, Opamp bias = low – 2400 3200 A Power = high, Opamp bias = high – – – A PSRR Supply voltage rejection ratio 64 80 – dB V V (V – 2.25) or OA SS IN DD (V – 1.25 V) V  V DD IN DD DC Low Power Comparator Specifications Table18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters A A A are measured at 5 V at 25 °C and are for design guidance only. Table 18. DC Low Power Comparator Specifications Symbol Description Min Typ Max Units Notes V Low power comparator (LPC) reference voltage 0.2 – V – 1 V REFLPC DD range I LPC supply current – 10 40 µA SLPC V LPC voltage offset – 2.5 30 mV OSLPC Document Number: 38-12028 Rev. *W Page 23 of 71

CY8C24123A CY8C24223A CY8C24423A DC Analog Output Buffer Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. A A A Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 19. 5 V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes C Load Capacitance – – 200 pF This specification applies to the L external circuit that is being driven by the analog output buffer. V Input offset voltage (absolute value) – 3 12 mV OSOB TCV Average input offset voltage drift – +6 – V/°C OSOB V Common mode input voltage range 0.5 – V – 1.0 V CMOB DD R Output resistance OUTOB Power = low – 1 – W Power = high – 1 – W V High output voltage swing OHIGHOB (Load = 32 ohms to V ) DD/2 Power = low 0.5 × V + 1.1 – – V DD Power = high 0.5 × V + 1.1 – – V DD V Low output voltage swing OLOWOB (Load = 32 ohms to V ) DD/2 Power = low – – .5 × V – 1.3 V DD Power = high – – 0.5 × V – 1.3 V DD I Supply current including Opamp bias SOB cell (No Load) – 1.1 5.1 mA Power = low – 2.6 8.8 mA Power = high PSRR Supply voltage rejection ratio 52 64 – dB V > (V – 1.25) OB OUT DD Table 20. 3.3 V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes C Load Capacitance – – 200 pF This specification applies to the L external circuit that is being driven by the analog output buffer. V Input offset voltage (absolute value) – 3 12 mV OSOB TCV Average input offset voltage drift – +6 – V/°C OSOB V Common mode input voltage range 0.5 – V – 1.0 V CMOB DD R Output resistance OUTOB Power = low – 1 –  Power = high – 1 –  V High output voltage swing (Load = 1 K OHIGHOB ohms to V ) DD/2 Power = low 0.5 × V + 1.0 – – V DD Power = high 0.5 × V + 1.0 – – V DD V Low output voltage swing (Load = 1 K OLOWOB ohms to V ) DD/2 Power = low – – 0.5 × V – 1.0 V DD Power = high – – 0.5 × V – 1.0 V DD I Supply current including Opamp bias SOB cell (no load) – 0.8 2.0 mA Power = low – 2.0 4.3 mA Power = high PSRR Supply voltage rejection ratio 52 64 – dB V > (V – 1.25) OB OUT DD Document Number: 38-12028 Rev. *W Page 24 of 71

CY8C24123A CY8C24223A CY8C24423A Table 21. 2.7 V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes C Load Capacitance – – 200 pF This specification applies to the L external circuit that is being driven by the analog output buffer. V Input offset voltage (absolute value) – 3 12 mV OSOB TCV Average input offset voltage drift – +6 – V/°C OSOB V Common mode input voltage range 0.5 – V – 1.0 V CMOB DD R Output resistance OUTOB Power = low – 1 –  Power = high – 1 –  V High output voltage swing (Load = 1 OHIGHOB K ohms to V ) DD/2 Power = low 0.5 × V + 0.2 – – V DD Power = high 0.5 × V + 0.2 – – V DD V Low output voltage swing (Load = 1 OLOWOB K ohms to V ) DD/2 Power = low – – 0.5 × V – 0.7 V DD Power = high – – 0.5 × V – 0.7 V DD I Supply current including Opamp SOB bias cell (No Load) 0.8 2.0 mA Power = low – 2.0 4.3 mA Power = high PSRR Supply voltage rejection ratio 52 64 – dB V > (V – 1.25). OB OUT DD Document Number: 38-12028 Rev. *W Page 25 of 71

CY8C24123A CY8C24223A CY8C24423A DC Switch Mode Pump Specifications Table22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters A A A are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 22. DC Switch Mode Pump (SMP) Specifications Symbol Description Min Typ Max Units Notes V 5 V 5 V output voltage from pump 4.75 5.0 5.25 V Configuration listed in footnote.[11] PUMP Average, neglecting ripple. SMP trip voltage is set to 5.0V. V 3 V 3.3 V output voltage from pump 3.00 3.25 3.60 V Configuration listed in footnote.[11] PUMP Average, neglecting ripple. SMP trip voltage is set to 3.25 V. V 2 V 2.6 V output voltage from pump 2.45 2.55 2.80 V Configuration listed in footnote.[11] PUMP Average, neglecting ripple. SMP trip voltage is set to 2.55 V. I Available output current Configuration listed in footnote.[11] PUMP V = 1.8 V, V = 5.0 V 5 – – mA SMP trip voltage is set to 5.0 V. BAT PUMP V = 1.5 V, V = 3.25 V 8 – – mA SMP trip voltage is set to 3.25 V. BAT PUMP V = 1.3 V, V = 2.55 V 8 – – mA SMP trip voltage is set to 2.55 V. BAT PUMP V 5 V Input voltage range from battery 1.8 – 5.0 V Configuration listed in footnote.[11] BAT SMP trip voltage is set to 5.0 V. V 3 V Input voltage range from battery 1.0 – 3.3 V Configuration listed in footnote.[11] BAT SMP trip voltage is set to 3.25 V. V 2 V Input voltage range from battery 1.0 – 3.0 V Configuration listed in footnote.[11] BAT SMP trip voltage is set to 2.55 V. V Minimum input voltage from 1.2 – – V Configuration listed in footnote.[11] BATSTART battery to start pump 0 °C  T  100. 1.25 V at T = –40 °C A A V Line regulation (over V – 5 – %V Configuration listed in footnote.[11] V PUMP_Line BAT O O range) is the V Value for PUMP Trip” DD specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 27 on page 35. V Load regulation – 5 – %V Configuration listed in footnote.[11] V PUMP_Load O O is the “V value for PUMP Trip” DD specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 27 on page 35. V Output voltage ripple (depends – 100 – mVpp Configuration listed in footnote.[11] PUMP_Ripple on capacitor/load) Load is 5 mA. E Efficiency 35 50 – % Configuration listed in footnote.[11] 3 Load is 5 mA. SMP trip voltage is set to 3.25 V. E Efficiency – – – 2 F Switching frequency – 1.3 – MHz PUMP DC Switching duty cycle – 50 – % PUMP Note 11.L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure11 Document Number: 38-12028 Rev. *W Page 26 of 71

CY8C24123A CY8C24223A CY8C24423A Figure 11. Basic Switch Mode Pump Circuit D1 Vdd V PUMP L 1 SMP + VBAT Battery PSoC C1 Vss Document Number: 38-12028 Rev. *W Page 27 of 71

CY8C24123A CY8C24223A CY8C24423A DC Analog Reference Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. A A A Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. The guaranteed specifications for RefHI and RefLo are measured through the Analog Continuous Time PSoC blocks. The power levels for RefHi and RefLo refer to the Analog Reference Control register. AGND is measured at P2[4] in AGND bypass mode. Each Analog Continuous Time PSoC block adds a maximum of 10 mV additional offset error to guaranteed AGND specifications from the local AGND buffer. Reference control power can be set to medium or high unless otherwise noted. Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the analog reference. Some coupling of the digital signal may appear on the AGND. Table 23. 5 V DC Analog Reference Specifications Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b000 RefPower = high V Ref High V /2 + Bandgap V /2 + 1.136 V /2 + 1.288 V /2 + 1.409 V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.138 V /2 + 0.003 V /2 + 0.132 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.417 V /2 – 1.289 V /2 – 1.154 V REFLO DD DD DD DD RefPower = high V Ref High V /2 + Bandgap V /2 + 1.202 V /2 + 1.290 V /2 + 1.358 V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.055 V /2 + 0.001 V /2 + 0.055 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.369 V /2 – 1.295 V /2 – 1.218 V REFLO DD DD DD DD RefPower = medium V Ref High V /2 + Bandgap V /2 + 1.211 V /2 + 1.292 V /2 + 1.357 V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.055 V /2 V /2 + 0.052 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.368 V /2 – 1.298 V /2 – 1.224 V REFLO DD DD DD DD RefPower = medium V Ref High V /2 + Bandgap V /2 + 1.215 V /2 + 1.292 V /2 + 1.353 V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.040 V /2 – 0.001 V /2 + 0.033 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.368 V /2 – 1.299 V /2 – 1.225 V REFLO DD DD DD DD 0b001 RefPower = high V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = high V /2, P2[6] = 1.3 V) 0.076 0.021 0.041 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 1.3 V) 0.025 0.011 0.085 DD RefPower = high V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = low V /2, P2[6] = 1.3 V) 0.069 0.014 0.043 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 1.3 V) 0.029 0.005 0.052 DD RefPower = medium V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = high V /2, P2[6] = 1.3 V) 0.072 0.011 0.048 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 1.3 V) 0.031 0.002 0.057 DD RefPower = medium V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = low V /2, P2[6] = 1.3 V) 0.070 0.009 0.047 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 1.3 V) 0.033 0.001 0.039 DD Document Number: 38-12028 Rev. *W Page 28 of 71

CY8C24123A CY8C24223A CY8C24423A Table 23. 5 V DC Analog Reference Specifications (continued) Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b010 RefPower = high V Ref High V V – 0.121 V – 0.003 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.040 V /2 V /2 + 0.034 V AGND DD DD DD DD V Ref Low V V V + 0.006 V + 0.019 V REFLO SS SS SS SS RefPower = high V Ref High V V – 0.083 V – 0.002 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.040 V /2 – 0.001 V /2 + 0.033 V AGND DD DD DD DD V Ref Low V V V + 0.004 V + 0.016 V REFLO SS SS SS SS RefPower = medium V Ref High V V – 0.075 V – 0.002 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.040 V /2 – 0.001 V /2 + 0.032 V AGND DD DD DD DD V Ref Low V V V + 0.003 V + 0.015 V REFLO SS SS SS SS RefPower = medium V Ref High V V – 0.074 V – 0.002 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.040 V /2 – 0.001 V /2 + 0.032 V AGND DD DD DD DD V Ref Low V V V + 0.002 V + 0.014 V REFLO SS SS SS SS 0b011 RefPower = high V Ref High 3 × Bandgap 3.753 3.874 3.979 V REFHI Opamp bias = high V AGND 2 × Bandgap 2.511 2.590 2.657 V AGND V Ref Low Bandgap 1.243 1.297 1.333 V REFLO RefPower = high V Ref High 3 × Bandgap 3.767 3.881 3.974 V REFHI Opamp bias = low V AGND 2 × Bandgap 2.518 2.592 2.652 V AGND V Ref Low Bandgap 1.241 1.295 1.330 V REFLO RefPower = medium V Ref High 3 × Bandgap 2.771 3.885 3.979 V REFHI Opamp bias = high V AGND 2 × Bandgap 2.521 2.593 2.649 V AGND V Ref Low Bandgap 1.240 1.295 1.331 V REFLO RefPower = medium V Ref High 3 × Bandgap 3.771 3.887 3.977 V REFHI Opamp bias = low V AGND 2 × Bandgap 2.522 2.594 2.648 V AGND V Ref Low Bandgap 1.239 1.295 1.332 V REFLO 0b100 RefPower = high V Ref High 2 × Bandgap + P2[6] 2.481 + P2[6] 2.569 + P2[6] 2.639 + P2[6] V REFHI Opamp bias = high (P2[6] = 1.3 V) V AGND 2 × Bandgap 2.511 2.590 2.658 V AGND V Ref Low 2 × Bandgap – P2[6] 2.515 – P2[6] 2.602 – P2[6] 2.654 – P2[6] V REFLO (P2[6] = 1.3 V) RefPower = high V Ref High 2 × Bandgap + P2[6] 2.498 + P2[6] 2.579 + P2[6] 2.642 + P2[6] V REFHI Opamp bias = low (P2[6] = 1.3 V) V AGND 2 × Bandgap 2.518 2.592 2.652 V AGND V Ref Low 2 × Bandgap – P2[6] 2.513 – P2[6] 2.598 – P2[6] 2.650 – P2[6] V REFLO (P2[6] = 1.3 V) RefPower = medium V Ref High 2 × Bandgap + P2[6] 2.504 + P2[6] 2.583 + P2[6] 2.646 + P2[6] V REFHI Opamp bias = high (P2[6] = 1.3 V) V AGND 2 × Bandgap 2.521 2.592 2.650 V AGND V Ref Low 2 × Bandgap – P2[6] 2.513 – P2[6] 2.596 – P2[6] 2.649 – P2[6] V REFLO (P2[6] = 1.3 V) RefPower = medium V Ref High 2 × Bandgap + P2[6] 2.505 + P2[6] 2.586 + P2[6] 2.648 + P2[6] V REFHI Opamp bias = low (P2[6] = 1.3 V) V AGND 2 × Bandgap 2.521 2.594 2.648 V AGND V Ref Low 2 × Bandgap – P2[6] 2.513 – P2[6] 2.595 – P2[6] 2.648 – P2[6] V REFLO (P2[6] = 1.3 V) Document Number: 38-12028 Rev. *W Page 29 of 71

CY8C24123A CY8C24223A CY8C24423A Table 23. 5 V DC Analog Reference Specifications (continued) Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b101 RefPower = high V Ref High P2[4] + Bandgap (P2[4] P2[4] + 1.228 P2[4] + 1.284 P2[4] + 1.332 V REFHI Opamp bias = high = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap (P2[4] P2[4] – 1.358 P2[4] – 1.293 P2[4] – 1.226 V REFLO = V /2) DD RefPower = high V Ref High P2[4] + Bandgap (P2[4] P2[4] + 1.236 P2[4] + 1.289 P2[4] + 1.332 V REFHI Opamp bias = low = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap (P2[4] P2[4] – 1.357 P2[4] – 1.297 P2[4] – 1.229 V REFLO = V /2) DD RefPower = medium V Ref High P2[4] + Bandgap (P2[4] P2[4] + 1.237 P2[4] + 1.291 P2[4] + 1.337 V REFHI Opamp bias = high = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap (P2[4] P2[4] – 1.356 P2[4] – 1.299 P2[4] – 1.232 V REFLO = V /2) DD RefPower = medium V Ref High P2[4] + Bandgap (P2[4] P2[4] + 1.237 P2[4] + 1.292 P2[4] + 1.337 V REFHI Opamp bias = low = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap (P2[4] P2[4] – 1.357 P2[4] – 1.300 P2[4] – 1.233 V REFLO = V /2) DD 0b110 RefPower = high V Ref High 2 × Bandgap 2.512 2.594 2.654 V REFHI Opamp bias = high V AGND Bandgap 1.250 1.303 1.346 V AGND V Ref Low V V V + 0.011 V + 0.027 V REFLO SS SS SS SS RefPower = high V Ref High 2 × Bandgap 2.515 2.592 2.654 V REFHI Opamp bias = low V AGND Bandgap 1.253 1.301 1.340 V AGND V Ref Low V V V + 0.006 V + 0.02 V REFLO SS SS SS SS RefPower = medium V Ref High 2 × Bandgap 2.518 2.593 2.651 V REFHI Opamp bias = high V AGND Bandgap 1.254 1.301 1.338 V AGND V Ref Low V V V + 0.004 V + 0.017 V REFLO SS SS SS SS RefPower = medium V Ref High 2 × Bandgap 2.517 2.594 2.650 V REFHI Opamp bias = low V AGND Bandgap 1.255 1.300 1.337 V AGND V Ref Low V V V + 0.003 V + 0.015 V REFLO SS SS SS SS 0b111 RefPower = high V Ref High 3.2 × Bandgap 4.011 4.143 4.203 V REFHI Opamp bias = high V AGND 1.6 × Bandgap 2.020 2.075 2.118 V AGND V Ref Low V V V + 0.011 V + 0.026 V REFLO SS SS SS SS RefPower = high V Ref High 3.2 × Bandgap 4.022 4.138 4.203 V REFHI Opamp bias = low V AGND 1.6 × Bandgap 2.023 2.075 2.114 V AGND V Ref Low V V V + 0.006 V + 0.017 V REFLO SS SS SS SS RefPower = medium V Ref High 3.2 × Bandgap 4.026 4.141 4.207 V REFHI Opamp bias = high V AGND 1.6 × Bandgap 2.024 2.075 2.114 V AGND V Ref Low V V V + 0.004 V + 0.015 V REFLO SS SS SS SS RefPower = medium V Ref High 3.2 × Bandgap 4.030 4.143 4.206 V REFHI Opamp bias = low V AGND 1.6 × Bandgap 2.024 2.076 2.112 V AGND V Ref Low V V V + 0.003 V + 0.013 V REFLO SS SS SS SS Document Number: 38-12028 Rev. *W Page 30 of 71

CY8C24123A CY8C24223A CY8C24423A Table 24. 3.3 V DC Analog Reference Specifications Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b000 RefPower = high V Ref High V /2 + Bandgap V /2 + 1.170 V /2 + 1.288 V /2 + 1.376 V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.098 V /2 + 0.003 V /2 + 0.097 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.386 V /2 – 1.287 V /2 – 1.169 V REFLO DD DD DD DD RefPower = high V Ref High V /2 + Bandgap V /2 + 1.210 V /2 + 1.290 V /2 + 1.355 V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.055 V /2 + 0.001 V /2 + 0.054 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.359 V /2 – 1.292 V /2 – 1.214 V REFLO DD DD DD DD RefPower = medium V Ref High V /2 + Bandgap V /2 + 1.198 V /2 + 1.292 V /2 + 1.368 V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.041 V /2 V /2 + 0.04 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.362 V /2 – 1.295 V /2 – 1.220 V REFLO DD DD DD DD RefPower = medium V Ref High V /2 + Bandgap V /2 + 1.202 V /2 + 1.292 V /2 + 1.364 V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.033 V /2 V /2 + 0.030 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.364 V /2 – 1.297 V /2 – 1.222 V REFLO DD DD DD DD 0b001 RefPower = high V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = high V /2, P2[6] = 0.5 V) 0.072 0.017 0.041 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) 0.029 0.010 0.048 DD RefPower = high V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = low V /2, P2[6] = 0.5 V) 0.066 0.010 0.043 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) 0.024 0.004 0.034 DD RefPower = medium V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = high V /2, P2[6] = 0.5 V) 0.073 0.007 0.053 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) 0.028 0.002 0.033 DD RefPower = medium V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = low V /2, P2[6] = 0.5 V) 0.073 0.006 0.056 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) 0.030 0.032 DD 0b010 RefPower = high V Ref High V V – 0.102 V – 0.003 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.040 V /2 + 0.001 V /2 + 0.039 V AGND DD DD DD DD V Ref Low V V V + 0.005 V + 0.020 V REFLO SS SS SS SS RefPower = high V Ref High V V – 0.082 V – 0.002 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.031 V /2 V /2 + 0.028 V AGND DD DD DD DD V Ref Low V V V + 0.003 V + 0.015 V REFLO SS SS SS SS RefPower = medium V Ref High V V – 0.083 V – 0.002 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.032 V /2 – 0.001 V /2 + 0.029 V AGND DD DD DD DD V Ref Low V V V + 0.002 V + 0.014 V REFLO SS SS SS SS RefPower = medium V Ref High V V – 0.081 V – 0.002 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.033 V /2 – 0.001 V /2 + 0.029 V AGND DD DD DD DD V Ref Low V V V + 0.002 V + 0.013 V REFLO SS SS SS SS 0b011 All power settings – – – – – – – Not allowed at 3.3 V Document Number: 38-12028 Rev. *W Page 31 of 71

CY8C24123A CY8C24223A CY8C24423A Table 24. 3.3 V DC Analog Reference Specifications (continued) Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b100 All power settings – – – – – – – Not allowed at 3.3 V 0b101 RefPower = high V Ref High P2[4] + Bandgap (P2[4] P2[4] + 1.211 P2[4] + 1.285 P2[4] + 1.348 V REFHI Opamp bias = high = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap (P2[4] P2[4] – 1.354 P2[4] – 1.290 P2[4] – 1.197 V REFLO = V /2) DD RefPower = high V Ref High P2[4] + Bandgap (P2[4] P2[4] + 1.209 P2[4] + 1.289 P2[4] + 1.353 V REFHI Opamp bias = low = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap (P2[4] P2[4] – 1.352 P2[4] – 1.294 P2[4] – 1.222 V REFLO = V /2) DD RefPower = medium V Ref High P2[4] + Bandgap (P2[4] P2[4] + 1.218 P2[4] + 1.291 P2[4] + 1.351 V REFHI Opamp bias = high = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap (P2[4] P2[4] – 1.351 P2[4] – 1.296 P2[4] – 1.224 V REFLO = V /2) DD RefPower = medium V Ref High P2[4] + Bandgap (P2[4] P2[4] + 1.215 P2[4] + 1.292 P2[4] + 1.354 V REFHI Opamp bias = low = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap (P2[4] P2[4] – 1.352 P2[4] – 1.297 P2[4] – 1.227 V REFLO = V /2) DD 0b110 RefPower = high V Ref High 2 × Bandgap 2.460 2.594 2.695 V REFHI Opamp bias = high V AGND Bandgap 1.257 1.302 1.335 V AGND V Ref Low V V V + 0.01 V + 0.029 V REFLO SS SS SS SS RefPower = high V Ref High 2 × Bandgap 2.462 2.592 2.692 V REFHI Opamp bias = low V AGND Bandgap 1.256 1.301 1.332 V AGND V Ref Low V V V + 0.005 V + 0.017 V REFLO SS SS SS SS RefPower = medium V Ref High 2 × Bandgap 2.473 2.593 2.682 V REFHI Opamp bias = high V AGND Bandgap 1.257 1.301 1.330 V AGND V Ref Low V V V + 0.003 V + 0.014 V REFLO SS SS SS SS RefPower = medium V Ref High 2 × Bandgap 2.470 2.594 2.685 V REFHI Opamp bias = low V AGND Bandgap 1.256 1.300 1.332 V AGND V Ref Low V V V + 0.002 V + 0.012 V REFLO SS SS SS SS 0b111 All power settings – – – – – – – Not allowed at 3.3 V Document Number: 38-12028 Rev. *W Page 32 of 71

CY8C24123A CY8C24223A CY8C24423A Table 25. 2.7 V DC Analog Reference Specifications Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b000 All power settings – – – – – – – Not allowed at 2.7 V 0b001 RefPower = medium V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = high V /2, P2[6] = 0.5 V) 0.739 0.016 0.759 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) 1.675 0.013 1.825 DD RefPower = medium V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = low V /2, P2[6] = 0.5 V) 0.098 0.011 0.067 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) 0.308 0.004 0.362 DD RefPower = low V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = high V /2, P2[6] = 0.5 V) 0.042 0.005 0.035 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) 0.030 0.030 DD RefPower = low V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = low V /2, P2[6] = 0.5 V) 0.367 0.005 0.308 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) 0.345 0.301 DD 0b010 RefPower = high V Ref High V V – 0.100 V – 0.003 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.038 V /2 V /2 + 0.036 V AGND DD DD DD DD V Ref Low V V V + 0.005 V + 0.016 V REFLO SS SS SS SS RefPower = high V Ref High V V – 0.065 V – 0.002 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.025 V /2 V /2 + 0.023 V AGND DD DD DD DD V Ref Low V V V + 0.003 V + 0.012 V REFLO SS SS SS SS RefPower = medium V Ref High V V – 0.054 V – 0.002 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.024 V /2 – 0.001 V /2 + 0.020 V AGND DD DD DD DD V Ref Low V V V + 0.002 V + 0.012 V REFLO SS SS SS SS RefPower = medium V Ref High V V – 0.042 V – 0.002 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.027 V /2 – 0.001 V /2 + 0.022 V AGND DD DD DD DD V Ref Low V V V + 0.001 V + 0.010 V REFLO SS SS SS SS RefPower = low V Ref High V V – 0.042 V – 0.002 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.028 V /2 – 0.001 V /2 + 0.023 V AGND DD DD DD DD V Ref Low V V V + 0.001 V + 0.010 V REFLO SS SS SS SS RefPower = low V Ref High V V – 0.036 V – 0.002 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.184 V /2 – 0.001 V /2 + 0.159 V AGND DD DD DD DD V Ref Low V V V + 0.001 V + 0.009 V REFLO SS SS SS SS Document Number: 38-12028 Rev. *W Page 33 of 71

CY8C24123A CY8C24223A CY8C24423A Table 25. 2.7 V DC Analog Reference Specifications (continued) Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b011 All power settings – – – – – – – Not allowed at 2.7 V 0b100 All power settings – – – – – – – Not allowed at 2.7 V 0b101 All power settings – – – – – – – Not allowed at 2.7 V 0b110 RefPower = high V Ref High 2 × Bandgap Not allowed Not allowed Not allowed V REFHI Opamp bias = high V AGND Bandgap 1.160 1.302 1.340 V AGND V Ref Low V V V + 0.007 V + 0.025 V REFLO SS SS SS SS RefPower = high V Ref High 2 × Bandgap Not allowed Not allowed Not allowed V REFHI Opamp bias = low V AGND Bandgap 1.160 1.301 1.338 V AGND V Ref Low V V V + 0.004 V + 0.017 V REFLO SS SS SS SS RefPower = medium V Ref High 2 × Bandgap Not allowed Not allowed Not allowed V REFHI Opamp bias = high V AGND Bandgap 1.160 1.301 1.338 V AGND V Ref Low V V V + 0.003 V + 0.013 V REFLO SS SS SS SS RefPower = medium V Ref High 2 × Bandgap Not allowed Not allowed Not allowed V REFHI Opamp bias = low V AGND Bandgap 1.160 1.300 1.337 V AGND V Ref Low V V V + 0.002 V + 0.011 V REFLO SS SS SS SS RefPower = low V Ref High 2 × Bandgap Not allowed Not allowed Not allowed V REFHI Opamp bias = high V AGND Bandgap 1.252 1.300 1.339 V AGND V Ref Low V V V + 0.002 V + 0.011 V REFLO SS SS SS SS RefPower = low V Ref High 2 × Bandgap Not allowed Not allowed Not allowed V REFHI Opamp bias = low V AGND Bandgap 1.252 1.300 1.339 V AGND V Ref Low V V V + 0.001 V + 0.01 V REFLO SS SS SS SS 0b111 All power settings – – – – – – – Not allowed at 2.7 V DC Analog PSoC Block Specifications Table25 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C  T  85°C, 3.0 V to 3.6 V and –40°C  T  85°C, or 2.4 V to 3.0 V and –40°C  T  85°C, respectively. Typical parameters A A A are measured at 5 V, 3.3 V, and 2.7 V at 25°C and are for design guidance only. Table 26. DC Analog PSoC Block Specifications Symbol Description Min Typ Max Units Notes R Resistor unit value (continuous time) – 12.2 – k CT C Capacitor unit value (switched capacitor) – 80 – fF SC Document Number: 38-12028 Rev. *W Page 34 of 71

CY8C24123A CY8C24223A CY8C24423A DC POR, SMP, and LVD Specifications Table26 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters A A A are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for more information on the VLT_CR register. Table 27. DC POR and LVD Specifications Symbol Description Min Typ Max Units Notes V value for PPOR trip V must be greater than or DD DD V PORLEV[1:0] = 00b 2.36 2.40 V equal to 2.5 V during startup, PPOR0 V PORLEV[1:0] = 01b – 2.82 2.95 V reset from the XRES pin, or PPOR1 V PORLEV[1:0] = 10b 4.55 4.70 V reset from watchdog. PPOR2 V value for LVD trip V VDMD[2:0] = 000b 2.40 2.450 2.51[12] V0 VLVD0 VM[2:0] = 001b 2.85 2.920 2.99[13] V0 VLVD1 VM[2:0] = 010b 2.95 3.02 3.09 V0 VLVD2 VM[2:0] = 011b 3.06 3.13 3.20 V0 VLVD3 VM[2:0] = 100b 4.37 4.48 4.55 V0 LVD4 V VM[2:0] = 101b 4.50 4.64 4.75 V LVD5 V VM[2:0] = 110b 4.62 4.73 4.83 V LVD6 V VM[2:0] = 111b 4.71 4.81 4.95 V LVD7 V value for SMP trip V VDMD[2:0] = 000b 2.500 2.550 2.62[14] V VPUMP0 VM[2:0] = 001b 2.96 3.02 3.09 V0 VPUMP1 VM[2:0] = 010b 3.03 3.10 3.16 V0 VPUMP2 VM[2:0] = 011b 3.18 3.250 3.32[15] V0 VPUMP3 VM[2:0] = 100b 4.54 4.64 4.74 V0 PUMP4 V VM[2:0] = 101b 4.62 4.73 4.83 V PUMP5 V VM[2:0] = 110b 4.71 4.82 4.92 V PUMP6 V VM[2:0] = 111b 4.89 5.00 5.12 V PUMP7 Notes 12.Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply. 13.Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply. 14.Always greater than 50 mV above VLVD0. 15.Always greater than 50 mV above VLVD3. Document Number: 38-12028 Rev. *W Page 35 of 71

CY8C24123A CY8C24223A CY8C24423A DC Programming Specifications Table28 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters A A A are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 28. DC Programming Specifications Symbol Description Min Typ Max Units Notes V V for programming and erase 4.5 5 5.5 V This specification applies DDP DD to the functional require- ments of external programmer tools V Low V for verify 2.4 2.5 2.6 V This specification applies DDLV DD to the functional require- ments of external programmer tools V High V for verify 5.1 5.2 5.3 V This specification applies DDHV DD to the functional require- ments of external programmer tools V Supply voltage for flash write operation 2.7 5.25 V This specification applies DDIWRITE to this device when it is executing internal flash writes I Supply current during programming or verify – 5 25 mA DDP V Input low voltage during programming or verify – – 0.8 V ILP V Input high voltage during programming or verify 2.1 – – V IHP I Input current when applying V to P1[0] or P1[1] – – 0.2 mA Driving internal pull-down ILP ILP during programming or verify resistor I Input current when applying V to P1[0] or P1[1] – – 1.5 mA Driving internal pull-down IHP IHP during programming or verify resistor V Output low voltage during programming or verify – – V + 0.75 V OLV SS V Output high voltage during programming or verify V – 1.0 – V V OHV DD DD Flash Flash endurance (per block) 50,000[16] – – – Erase/write cycles per ENPB block Flash Flash endurance (total)[17] 1,800,000 – – – Erase/write cycles ENT Flash Flash data retention 10 – – Years DR DC I2C Specifications Table29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters A A A are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 29. DC I2C Specifications[18] Symbol Description Min Typ Max Units Notes V Input low level – – 0.3 × V V 2.4 V V 3.6 V ILI2C DD DD – – 0.25 × V V 4.75 V V 5.25 V DD DD V Input high level 0.7 × V – – V 2.4 V V 5.25 V IHI2C DD DD Notes 16.The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to 3.6 V, and 4.75 V to 5.25 V. 17.A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36 × 2 blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs application note Design Aids – Reading and Writing PSoC® Flash – AN2015 for more information. 18.All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs. Document Number: 38-12028 Rev. *W Page 36 of 71

CY8C24123A CY8C24223A CY8C24423A AC Electrical Characteristics AC Chip-Level Specifications These tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters A A A are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 30. 5 V and 3.3 V AC Chip-Level Specifications Symbol Description Min Typ Max Units Notes F [19] Internal main oscillator (IMO) frequency for 22.8 24 25.2[20,21] MHz Trimmed for 5 V or 3.3 V operation IMO24 24 MHz using factory trim values. See Figure 10 on page 18. SLIMO mode = 0. F IMO frequency for 6 MHz 5.5 6 6.5[20,21] MHz Trimmed for 5 V or 3.3 V operation IMO6 using factory trim values. See Figure 10 on page 18. SLIMO mode = 1. F CPU frequency (5 V nominal) 0.937 24 24.6[20] MHz SLIMO mode = 0. CPU1 F CPU frequency (3.3 V nominal) 0.937 12 12.3[21] MHz SLIMO mode = 0. CPU2 F Digital PSoC block frequency 0 48 49.2[20,22] MHz Refer to the AC Digital Block 48M Specifications. F Digital PSoC block frequency 0 24 24.6[22] MHz 24M F ILO frequency 15 32 64 kHz 32K1 F External crystal oscillator – 32.768 – kHz Accuracy is capacitor and crystal 32K2 dependent. 50% duty cycle. F ILO untrimmed frequency 5 – 100 kHz After a reset and before the M8C 32K_U starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on timing this F PLL frequency – 23.986 – MHz Is a multiple (x732) of crystal PLL frequency. T PLL lock time 0.5 – 10 ms PLLSLEW T PLL lock time for low gain setting 0.5 – 50 ms PLLSLEWSLOW T External crystal oscillator startup to 1% – 1700 2620 ms OS T External crystal oscillator startup to – 2800 3800 ms The crystal oscillator frequency is OSACC 100ppm within 100 ppm of its final value by the end of the T period. Correct osacc operation assumes a properly loaded 1 µW maximum drive level 32.768 kHz crystal. 3.0 V  V  5.5 V, DD –40 °C  T  85°C. A t External reset pulse width 10 – – s XRST Notes 19.Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0°C or above 70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see “Errata” on page67. 20.4.75 V < VDD < 5.25 V. 21.3.0 V < VDD < 3.6 V. See application note Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 for information on trimming for operation at 3.3 V. 22.See the individual user module datasheets for information on maximum frequencies for user modules. 23.Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information. Document Number: 38-12028 Rev. *W Page 37 of 71

CY8C24123A CY8C24223A CY8C24423A Table 30. 5 V and 3.3 V AC Chip-Level Specifications (continued) Symbol Description Min Typ Max Units Notes DC24M 24 MHz duty cycle 40 50 60 % DC ILO duty cycle 20 50 80 % ILO Step24M 24 MHz trim step size – 50 – kHz Fout48M 48 MHz output frequency 46.8 48.0 49.2[24, 25] MHz Trimmed. Using factory trim values. F Maximum frequency of signal on row input – – 12.3 MHz MAX or row output. SR Power supply slew rate – – 250 V/ms V slew rate during power-up. POWER_UP DD t Time from end of POR to CPU executing – 16 100 ms Power-up from 0 V. See the System POWERUP code Resets section of the PSoC Technical Reference Manual. t [26] 24 MHz IMO cycle-to-cycle jitter (RMS) – 200 700 ps N = 32 jit_IMO 24 MHz IMO long term N cycle-to-cycle – 300 900 ps jitter (RMS) 24 MHz IMO period jitter (RMS) – 100 400 ps t [26] 24 MHz IMO cycle-to-cycle jitter (RMS) – 200 800 ps N = 32 jit_PLL 24 MHz IMO long term N cycle-to-cycle – 300 1200 jitter (RMS) 24 MHz IMO period jitter (RMS) – 100 700 Notes 24.4.75 V < VDD < 5.25 V. 25.3.0 V < VDD < 3.6 V. See application note Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 for information on trimming for operation at 3.3 V. 26.Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information. Document Number: 38-12028 Rev. *W Page 38 of 71

CY8C24123A CY8C24223A CY8C24423A Table 31. 2.7 V AC Chip-Level Specifications Symbol Description Min Typ Max Units Notes F IMO frequency for 12 MHz 11.5 12 12.7[27, 28] MHz Trimmed for 2.7 V operation using IMO12 factory trim values. See Figure 10 on page 18. SLIMO mode = 1. F IMO frequency for 6 MHz 5.5 6 6.5[27, 28] MHz Trimmed for 2.7 V operation using IMO6 factory trim values. See Figure 10 on page 18. SLIMO mode = 1. F CPU frequency (2.7 V nominal)0 0.9370 30 3.15[27] MHz0 SLIMO mode = 0. CPU1 F Digital PSoC block frequency 0 12 12.7[27, 28] MHz0 Refer to the AC Digital Block BLK27 (2.7 V nominal) Specifications. F ILO frequency 8 32 96 kHz 32K1 F ILO untrimmed frequency 5 – 100 kHz After a reset and before the M8C 32K_U starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on timing this t External reset pulse width 10 – – µs XRST DC12M 12 MHz duty cycle 40 50 60 % DC ILO duty cycle 20 50 80 % ILO F Maximum frequency of signal on row input – – 12.7 MHz MAX or row output. SR Power supply slew rate – – 250 V/ms V slew rate during power-up. POWER_UP DD t Time from end of POR to CPU executing – 16 100 ms Power-up from 0 V. See the System POWERUP code Resets section of the PSoC Technical Reference Manual. t [29] 12 MHz IMO cycle-to-cycle jitter (RMS) – 400 1000 ps N = 32 jit_IMO 12 MHz IMO long term N cycle-to-cycle – 600 1300 ps jitter (RMS) 12 MHz IMO period jitter (RMS) – 100 500 ps t [29] 12 MHz IMO cycle-to-cycle jitter (RMS) – 400 1000 ps N = 32 jit_PLL 12 MHz IMO long term N cycle-to-cycle – 700 1300 jitter (RMS) 12 MHz IMO period jitter (RMS) – 300 500 Notes 27.2.4 V < VDD < 3.0 V. 28.Refer to application note Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 for information on trimming for operation at 3.3 V. 29.Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information. Document Number: 38-12028 Rev. *W Page 39 of 71

CY8C24123A CY8C24223A CY8C24423A Figure 12. PLL Lock Timing Diagram PLL Enable T 24 MHz PLLSLEW F PLL PLL 0 Gain Figure 13. PLL Lock for Low Gain Setting Timing Diagram PLL Enable T 24 MHz PLLSLEWLOW F PLL PLL 1 Gain Figure 14. External Crystal Oscillator Startup Timing Diagram 32K Select 32 kHz T OS F 32K2 Document Number: 38-12028 Rev. *W Page 40 of 71

CY8C24123A CY8C24223A CY8C24423A AC GPIO Specifications These tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters A A A are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 32. 5 V and 3.3 V AC GPIO Specifications Symbol Description Min Typ Max Units Notes F GPIO operating frequency 0 – 12 MHz Normal Strong Mode GPIO tRiseF Rise time, normal strong mode, Cload = 50 pF 3 – 18 ns V = 4.5 to 5.25 V, 10% to 90% DD tFallF Fall time, normal strong mode, Cload = 50 pF 2 – 18 ns V = 4.5 to 5.25 V, 10% to 90% DD tRiseS Rise time, slow strong mode, Cload = 50 pF 10 27 – ns V = 3 to 5.25 V, 10% to 90% DD tFallS Fall time, slow strong mode, Cload = 50 pF 10 22 – ns V = 3 to 5.25 V, 10% to 90% DD Table 33. 2.7 V AC GPIO Specifications Symbol Description Min Typ Max Units Notes F GPIO operating frequency 0 – 3 MHz Normal strong mode GPIO tRiseF Rise time, normal strong mode, Cload = 50 pF 6 – 50 ns V = 2.4 to 3.0 V, 10% to 90% DD tFallF Fall time, normal strong mode, Cload = 50 pF 6 – 50 ns V = 2.4 to 3.0 V, 10% to 90% DD tRiseS Rise time, slow strong mode, Cload = 50 pF 18 40 120 ns V = 2.4 to 3.0 V, 10% to 90% DD tFallS Fall time, slow strong mode, Cload = 50 pF 18 40 120 ns V = 2.4 to 3.0 V, 10% to 90% DD Figure 15. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TFallF TRiseS TFallS Document Number: 38-12028 Rev. *W Page 41 of 71

CY8C24123A CY8C24223A CY8C24423A AC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. A A A Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the analog continuous time PSoC block. Power = high and Opamp bias = high is not supported at 3.3 V and 2.7 V. Table 34. 5 V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units t Rising settling time from 80% of V to 0.1% of V ROA (10 pF load, unity gain) Power = low, Opamp bias = low – – 3.9 µs Power = medium, Opamp bias = high – – 0.72 µs Power = high, Opamp bias = high – – 0.62 µs t Falling settling time from 20% of V to 0.1% of V SOA (10 pF load, unity gain) Power = low, Opamp bias = low – – 5.9 µs Power = medium, Opamp bias = high – – 0.92 µs Power = high, Opamp bias = high – – 0.72 µs SR Rising slew rate (20% to 80%) (10 pF load, unity gain) ROA Power = low, Opamp bias = low 0.15 – – V/µs Power = medium, Opamp bias = high 1.7 – – V/µs Power = high, Opamp bias = high 6.5 – – V/µs SR Falling slew rate (20% to 80%) (10 pF load, unity gain) FOA Power = low, Opamp bias = low 0.01 – – V/µs Power = medium, Opamp bias = high 0.5 – – V/µs Power = high, Opamp bias = high 4.0 – – V/µs BW Gain bandwidth product OA Power = low, Opamp bias = low 0.75 – – MHz Power = medium, Opamp bias = high 3.1 – – MHz Power = high, Opamp bias = high 5.4 – – MHz E Noise at 1 kHz (Power = medium, Opamp bias = high) – 100 – nV/rt-Hz NOA Table 35. 3.3 V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units t Rising settling time from 80% of V to 0.1% of V ROA (10 pF load, unity gain) Power = low, Opamp bias = low – – 3.92 µs Power = medium, Opamp bias = high – – 0.72 µs t Falling settling time from 20% of V to 0.1% of V SOA (10 pF load, unity gain) Power = low, Opamp bias = low – – 5.41 µs Power = medium, Opamp bias = high – – 0.72 µs SR Rising slew rate (20% to 80%) (10 pF load, unity gain) ROA Power = low, Opamp bias = low 0.31 – – V/µs Power = medium, Opamp bias = high 2.7 – – V/µs SR Falling slew rate (20% to 80%) (10 pF load, unity gain) FOA Power = low, Opamp bias = low 0.24 – – V/µs Power = medium, Opamp bias = high 1.8 – – V/µs BW Gain bandwidth product OA Power = low, Opamp bias = low 0.67 – – MHz Power = medium, Opamp bias = high 2.8 – – MHz E Noise at 1 kHz (Power = medium, Opamp bias = high) – 100 – nV/rt-Hz NOA Document Number: 38-12028 Rev. *W Page 42 of 71

CY8C24123A CY8C24223A CY8C24423A Table 36. 2.7 V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units t Rising settling time from 80% of V to 0.1% of V ROA (10 pF load, unity gain) Power = low, Opamp bias = low – – 3.92 µs Power = medium, Opamp bias = high – – 0.72 µs t Falling settling time from 20% of V to 0.1% of V SOA (10 pF load, unity gain) Power = low, Opamp bias = low – – 5.41 µs Power = medium, Opamp bias = high – – 0.72 µs SR Rising slew rate (20% to 80%) (10 pF load, unity gain) ROA Power = low, Opamp bias = low 0.31 – – V/µs Power = medium, Opamp bias = high 2.7 – – V/µs SR Falling slew rate (20% to 80%) (10 pF load, unity gain) FOA Power = low, Opamp bias = low 0.24 – – V/µs Power = medium, Opamp bias = high 1.8 – – V/µs BW Gain bandwidth product OA Power = low, Opamp bias = low 0.67 – – MHz Power = medium, Opamp bias = high 2.8 – – MHz E Noise at 1 kHz (Power = medium, Opamp bias = high) – 100 – nV/rt-Hz NOA When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 K resistance and the external capacitor. Figure 16. Typical AGND Noise with P2[4] Bypass   nV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Document Number: 38-12028 Rev. *W Page 43 of 71

CY8C24123A CY8C24223A CY8C24423A Figure 17. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 0.01 0.1 1 10 100 Freq (kHz) AC Low Power Comparator Specifications Table37 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters A A A are measured at 5 V at 25 °C and are for design guidance only. Table 37. AC Low Power Comparator Specifications Symbol Description Min Typ Max Units Notes t LPC response time – – 50 µs  50 mV overdrive comparator RLPC reference set within V REFLPC Document Number: 38-12028 Rev. *W Page 44 of 71

CY8C24123A CY8C24223A CY8C24423A AC Digital Block Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. A A A Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 38. 5 V and 3.3 V AC Digital Block Specifications Function Description Min Typ Max Unit Notes All functions Block input clock frequency V  4.75 V – – 50.4 MHz DD V < 4.75 V – – 25.2 MHz DD Timer Input clock frequency No capture, V 4.75 V – – 50.4 MHz DD No capture, V < 4.75 V – – 25.2 MHz DD With capture – – 25.2 MHz Capture pulse width 50[30] – – ns Counter Input clock frequency No enable input, V  4.75 V – – 50.4 MHz DD No enable input, V < 4.75 V – – 25.2 MHz DD With enable input – – 25.2 MHz Enable input pulse width 50[30] – – ns Dead Band Kill pulse width Asynchronous restart mode 20 – – ns Synchronous restart mode 50[30] – – ns Disable mode 50[30] – – ns Input clock frequency V  4.75 V – – 50.4 MHz DD V < 4.75 V – – 25.2 MHz DD CRCPRS Input clock frequency (PRS Mode) V  4.75 V – – 50.4 MHz DD V < 4.75 V – – 25.2 MHz DD CRCPRS Input clock frequency – – 25.2 MHz (CRC Mode) SPIM Input clock frequency – – 8.2 MHz The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. SPIS Input clock (SCLK) frequency – – 4.1 MHz The input clock is the SPI SCLK in SPIS mode. Width of SS_negated between 50[30] – – ns transmissions Transmitter Input clock frequency The baud rate is equal to the input clock frequency divided by 8. V  4.75 V, 2 stop bits – – 50.4 MHz DD V  4.75 V, 1 stop bit – – 25.2 MHz DD V < 4.75 V – – 25.2 MHz DD Receiver Input clock frequency The baud rate is equal to the input clock frequency divided by 8. V  4.75 V, 2 stop bits – – 50.4 MHz DD V  4.75 V, 1 stop bit – – 25.2 MHz DD V < 4.75 V – – 25.2 MHz DD Note 30.50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 38-12028 Rev. *W Page 45 of 71

CY8C24123A CY8C24223A CY8C24423A Table 39. 2.7 V AC Digital Block Specifications Function Description Min Typ Max Units Notes All Block input clock frequency – – 12.7 MHz 2.4 V < V < 3.0 V DD Functions Timer Capture pulse width 100[31] – – ns Input clock frequency, with or without capture – – 12.7 MHz Counter Enable Input Pulse Width 100[31] – – ns Input clock frequency, no enable input – – 12.7 MHz Input clock frequency, enable input – – 12.7 MHz Dead Band Kill pulse width: Asynchronous restart mode 20 – – ns Synchronous restart mode 100[31] – – ns Disable mode0 100[31] – – ns Input clock frequency – – 12.7 MHz CRCPRS Input clock frequency – – 12.7 MHz (PRS Mode) CRCPRS Input clock frequency – – 12.7 MHz (CRC Mode) SPIM Input clock frequency – – 6.35 MHz The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. SPIS Input clock frequency – – 4.23 MHz Width of SS_ Negated between transmissions 100[31] – – ns Transmitter Input clock frequency – – 12.7 MHz The baud rate is equal to the input clock frequency divided by 8. Receiver Input clock frequency – – 12.7 MHz The baud rate is equal to the input clock frequency divided by 8. Note 31.50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). Document Number: 38-12028 Rev. *W Page 46 of 71

CY8C24123A CY8C24223A CY8C24423A AC Analog Output Buffer Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. A A A Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 40. 5 V AC Analog Output Buffer Specifications Symbol Description Min Typ Max Units t Rising settling time to 0.1%, 1 V Step, 100 pF load ROB Power = low – – 2.5 µs Power = high – – 2.5 µs t Falling settling time to 0.1%, 1 V Step, 100 pF load SOB Power = low – – 2.2 µs Power = high – – 2.2 µs SR Rising slew rate (20% to 80%), 1 V Step, 100 pF load ROB Power = low 0.65 – – V/µs Power = high 0.65 – – V/µs SR Falling slew rate (80% to 20%), 1 V Step, 100 pF load FOB Power = low 0.65 – – V/µs Power = high 0.65 – – V/µs BW Small signal bandwidth, 20mV , 3dB BW, 100 pF load OB pp Power = low 0.8 – – MHz Power = high 0.8 – – MHz BW Large signal bandwidth, 1V , 3dB BW, 100 pF load OB pp Power = low 300 – – kHz Power = high 300 – – kHz Table 41. 3.3 V AC Analog Output Buffer Specifications Symbol Description Min Typ Max Units t Rising settling time to 0.1%, 1 V Step, 100 pF load ROB Power = low – – 3.8 µs Power = high – – 3.8 µs t Falling settling time to 0.1%, 1 V Step, 100 pF load SOB Power = low – – 2.6 µs Power = high – – 2.6 µs SR Rising slew rate (20% to 80%), 1 V Step, 100 pF load ROB Power = low 0.5 – – V/µs Power = high 0.5 – – V/µs SR Falling slew rate (80% to 20%), 1 V Step, 100 pF load FOB Power = low 0.5 – – V/µs Power = high 0.5 – – V/µs BW Small signal bandwidth, 20mV , 3dB BW, 100 pF load OB pp Power = low 0.7 – – MHz Power = high 0.7 – – MHz BW Large signal bandwidth, 1V , 3dB BW, 100 pF load OB pp Power = low 200 – – kHz Power = high 200 – – kHz Document Number: 38-12028 Rev. *W Page 47 of 71

CY8C24123A CY8C24223A CY8C24423A Table 42. 2.7 V AC Analog Output Buffer Specifications Symbol Description Min Typ Max Units t Rising settling time to 0.1%, 1 V Step, 100 pF load ROB Power = low – – 4 µs Power = high – – 4 µs t Falling settling time to 0.1%, 1 V Step, 100 pF load SOB Power = low – – 3 µs Power = high – – 3 µs SR Rising slew rate (20% to 80%), 1 V Step, 100 pF load ROB Power = low 0.4 – – V/µs Power = high 0.4 – – V/µs SR Falling slew rate (80% to 20%), 1 V Step, 100 pF load FOB Power = low 0.4 – – V/µs Power = high 0.4 – – V/µs BW Small signal bandwidth, 20 mV , 3dB BW, 100 pF load OB pp Power = low 0.6 – – MHz Power = high 0.6 – – MHz BW Large signal bandwidth, 1 V , 3dB BW, 100 pF load OB pp Power = low 180 – – kHz Power = high 180 – – kHz AC External Clock Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. A A A Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 43. 5 V AC External Clock Specifications Symbol Description Min Typ Max Units F Frequency 0.093 – 24.6 MHz OSCEXT – High period 20.6 – 5300 ns – Low period 20.6 – – ns – Power-up IMO to switch 150 – – s Table 44. 3.3 V AC External Clock Specifications Symbol Description Min Typ Max Units F Frequency with CPU clock divide by 1[32] 0.093 – 12.3 MHz OSCEXT F Frequency with CPU clock divide by 2 or greater[33] 0.186 – 24.6 MHz OSCEXT – High period with CPU clock divide by 1 41.7 – 5300 ns – Low period with CPU clock divide by 1 41.7 – – ns – Power-up IMO to switch 150 – – s Notes 32.Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 33.If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. Document Number: 38-12028 Rev. *W Page 48 of 71

CY8C24123A CY8C24223A CY8C24423A Table 45. 2.7 V AC External Clock Specifications Symbol Description Min Typ Max Units Notes F Frequency with CPU clock divide by 1[34] 0.093 – 12.3 MHz OSCEXT F Frequency with CPU clock divide by 2 or greater[35] 0.186 – 12.3 MHz OSCEXT – High period with CPU clock divide by 1 41.7 – 5300 ns – Low period with CPU clock divide by 1 41.7 – – ns – Power-up IMO to switch 150 – – µs AC Programming Specifications Table46 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters A A A are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 46. AC Programming Specifications Symbol Description Min Typ Max Units Notes t Rise time of SCLK 1 – 20 ns RSCLK t Fall time of SCLK 1 – 20 ns FSCLK t Data setup time to falling edge of SCLK 40 – – ns SSCLK t Data hold time from falling edge of SCLK 40 – – ns HSCLK F Frequency of SCLK 0 – 8 MHz SCLK t Flash erase time (block) – 20 – ms ERASEB t Flash block write time – 80 – ms WRITE t Data out delay from falling edge of SCLK – – 45 ns V  3.6 DSCLK DD t Data out delay from falling edge of SCLK – – 50 ns 3.0  V  3.6 DSCLK3 DD t Data out delay from falling edge of SCLK – – 70 ns 2.4  V  3.0 DSCLK2 DD t Flash erase time (Bulk) – 20 – ms Erase all blocks and ERASEALL protection fields at once t Flash block erase + flash block write time – – 200[36] ms 0 °C  Tj  100 °C PROGRAM_HOT t Flash block erase + flash block write time – – 400[36] ms –40 °C  Tj  0 °C PROGRAM_COLD Notes 34.Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 35.If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. 36.For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs application note Design Aids – Reading and Writing PSoC® Flash – AN2015 for more information. Document Number: 38-12028 Rev. *W Page 49 of 71

CY8C24123A CY8C24223A CY8C24423A AC I2C Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. A A A Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 47. AC Characteristics of the I2C SDA and SCL Pins for V > 3.0 V DD Standard-Mode Fast-Mode Symbol Description Units Min Max Min Max F SCL clock frequency 0 100 0 400 kHz SCLI2C t Hold time (repeated) start condition. After this period, the first clock 4.0 – 0.6 – µs HDSTAI2C pulse is generated t Low period of the SCL clock 4.7 – 1.3 – µs LOWI2C t High period of the SCL clock 4.0 – 0.6 – µs HIGHI2C t Setup time for a repeated start condition 4.7 – 0.6 – µs SUSTAI2C t Data hold time 0 – 0 – µs HDDATI2C t Data setup time 250 – 100[37] – ns SUDATI2C t Setup time for stop condition 4.0 – 0.6 – µs SUSTOI2C t Bus free time between a stop and start condition 4.7 – 1.3 – µs BUFI2C t Pulse width of spikes are suppressed by the input filter – – 0 50 ns SPI2C Table 48. AC Characteristics of the I2C SDA and SCL Pins for VDD 3.0 V (Fast Mode Not Supported) Standard-Mode Fast-Mode Symbol Description Units Min Max Min Max F SCL clock frequency 0 100 – – kHz SCLI2C t Hold time (repeated) start condition. After this period, the first clock 4.0 – – – µs HDSTAI2C pulse is generated t Low period of the SCL clock 4.7 – – – µs LOWI2C t High period of the SCL clock 4.0 – – – µs HIGHI2C t Setup time for a repeated start condition 4.7 – – – µs SUSTAI2C t Data hold time 0 – – – µs HDDATI2C t Data setup time 250 – – – ns SUDATI2C t Setup time for stop condition 4.0 – – – µs SUSTOI2C t Bus free time between a stop and start condition 4.7 – – – µs BUFI2C t Pulse width of spikes are suppressed by the input filter – – – – ns SPI2C Figure 18. Definition for Timing for Fast-/Standard-Mode on the I2C Bus I2C_SDA T TSUDATI2C THDDATI2CTSUSTAI2C TSPI2C TBUFI2C HDSTAI2C I2C_SCL T T T HIGHI2C LOWI2C SUSTOI2C P S S Sr START Condition Repeated START Condition STOP Condition Note 37.A fast-mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSUDAT  250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSUDAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 38-12028 Rev. *W Page 50 of 71

CY8C24123A CY8C24223A CY8C24423A Packaging Information This section illustrates the packaging specifications for the CY8C24x23A PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, see the emulator pod drawings at http://www.cypress.com/design/MR10161. Packaging Dimensions Figure 19. 8-Pin PDIP (300 Mils) 51-85075 *D Document Number: 38-12028 Rev. *W Page 51 of 71

CY8C24123A CY8C24223A CY8C24423A Figure 20. 8-Pin SOIC (150 Mils) 51-85066 *H Figure 21. 20-Pin Molded DIP (300 Mils) 51-85011 *D Document Number: 38-12028 Rev. *W Page 52 of 71

CY8C24123A CY8C24223A CY8C24423A Figure 22. 20-Pin SSOP (210 Mils) 51-85077 *F Figure 23. 20-Pin Molded SOIC (300 Mils) 51-85024 *F Document Number: 38-12028 Rev. *W Page 53 of 71

CY8C24123A CY8C24223A CY8C24423A Figure 24. 28-Pin Molded DIP (300 Mils) 51-85014 *G Figure 25. 28-Pin SSOP (210 Mils) 51-85079 *F Document Number: 38-12028 Rev. *W Page 54 of 71

CY8C24123A CY8C24223A CY8C24423A Figure 26. 28-Pin SOIC (300 Mils) 51-85026 *H Document Number: 38-12028 Rev. *W Page 55 of 71

CY8C24123A CY8C24223A CY8C24423A Figure 27. 32-Pin QFN (Sawn) Package 001-30999 *D Important Note For information on the preferred dimensions for mounting QFN packages, see the application note, Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com. Figure 28. 56-Pin SSOP (300 Mils) 51-85062 *F Document Number: 38-12028 Rev. *W Page 56 of 71

CY8C24123A CY8C24223A CY8C24423A Thermal Impedances Capacitance on Crystal Pins Table 49. Thermal Impedances per Package Table 50. Typical Package Capacitance on Crystal Pins Package Typical  [38] Package Package Capacitance JA 8-pin PDIP 123 °C/W 8-pin PDIP 2.8 pF 8-pin SOIC 185 °C/W 8-pin SOIC 2.0 pF 20-pin PDIP 109 °C/W 20-pin PDIP 3.0 pF 20-pin SSOP 117 °C/W 20-pin SSOP 2.6 pF 20-pin SOIC 81 °C/W 20-pin SOIC 2.5 pF 28-pin PDIP 69 °C/W 28-pin PDIP 3.5 pF 28-pin SSOP 101 °C/W 28-pin SSOP 2.8 pF 28-pin SOIC 74 °C/W 28-pin SOIC 2.7 pF 32-pin QFN[39] 22 °C/W 32-pin QFN 2.0 pF Solder Reflow Specifications Table51 shows the solder reflow temperature limits that must not be exceeded. Table 51. Solder Reflow Specifications Package Maximum Peak Temperature (T ) Maximum Time above T – 5 °C C C 8-pin PDIP 260 °C 30 seconds 8-pin SOIC 260 °C 30 seconds 20-pin PDIP 260 °C 30 seconds 20-pin SSOP 260 °C 30 seconds 20-pin SOIC 260 °C 30 seconds 28-pin PDIP 260 °C 30 seconds 28-pin SSOP 260 °C 30 seconds 28-pin SOIC 260 °C 30 seconds 32-pin QFN 260 °C 30 seconds Notes 38.TJ = TA + Power × JA 39.To achieve the thermal impedance specified for the QFN package, refer to Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at www.amkor.com. Document Number: 38-12028 Rev. *W Page 57 of 71

CY8C24123A CY8C24223A CY8C24423A Development Tool Selection CY3210-MiniProg1 The CY3210-MiniProg1 kit lets you to program PSoC devices This section presents the development tools available for all through the MiniProg1 programming unit. The MiniProg is a current PSoC device families including the CY8C24x23A family. small, compact prototyping programmer that connects to the PC through a provided USB 2.0 cable. The kit includes: Software ■MiniProg programming unit PSoC Designer ■MiniEval socket programming and evaluation board At the core of the PSoC development software suite is PSoCDesigner, used to generate PSoC firmware applications. ■28-pin CY8C29466-24PXI PDIP PSoC device sample PSoCDesigner is available free of charge at ■28-pin CY8C27443-24PXI PDIP PSoC device sample http://www.cypress.com and includes a free C compiler. ■PSoC Designer software CD PSoC Programmer ■Getting Started guide Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works ■USB 2.0 cable either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is CY3210-PSoCEval1 compatible with both PSoC ICE-Cube In-Circuit Emulator and The CY3210-PSoCEval1 kit features an evaluation board and PSoC MiniProg. PSoC programmer is available free ofcharge at the MiniProg1 programming unit. The evaluation board includes http://www.cypress.com. an LCD module, potentiometer, LEDs, and plenty of bread- boarding space to meet all of your evaluation needs. The kit Development Kits includes: All development kits can be purchased from the Cypress Online ■Evaluation board with LCD module Store. ■MiniProg programming unit CY3215-DK Basic Development Kit ■28-pin CY8C29466-24PXI PDIP PSoC device sample (2) The CY3215-DK is for prototyping and development with ■PSoC Designer software CD PSoCDesigner. This kit supports in-circuit emulation and the ■Getting Started guide software interface lets you to run, halt, and single step the processor and view the content of specific memory locations. ■USB 2.0 cable Advance emulation features also supported through PSoC CY3214-PSoCEvalUSB Designer. The kit includes: The CY3214-PSoCEvalUSB evaluation kit features a ■PSoC Designer software CD development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive ■ICE-Cube in-circuit emulator sensing development and debugging support. This evaluation ■ICE Flex-Pod for CY8C29x66 family board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your ■Cat-5 adapter evaluation needs. The kit includes: ■Mini-Eval programming board ■PSoCEvalUSB board ■110 ~ 240 V power supply, Euro-Plug adapter ■LCD module ■MIniProg programming unit ■iMAGEcraft C compiler (registration required) ■Mini USB cable ■ISSP cable ■PSoC Designer and Example Projects CD ■USB 2.0 cable and Blue Cat-5 cable ■Getting Started guide ■2 CY8C29466-24PXI 28-PDIP chip samples ■Wire pack Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store. Document Number: 38-12028 Rev. *W Page 58 of 71

CY8C24123A CY8C24223A CY8C24423A Device Programmers CY3207ISSP In-System Serial Programmer (ISSP) All device programmers can be purchased from the Cypress The CY3207ISSP is a production programmer. It includes Online Store. protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. CY3216 Modular Programmer Note CY3207ISSP needs special software and is not compatible The CY3216 Modular Programmer kit features a modular with PSoC Programmer. The kit includes: programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and ■CY3207 programmer unit supports multiple Cypress products. The kit includes: ■PSoC ISSP software CD ■Modular programmer base ■110 ~ 240 V power supply, Euro-Plug adapter ■Three programming module cards ■USB 2.0 cable ■MiniProg programming unit ■PSoC Designer software CD ■Getting Started guide ■USB 2.0 cable Accessories (Emulation and Programming) Table 52. Emulation and Programming Accessories Part Number Pin Package Flex-Pod Kit[40] Foot Kit[41] Adapter[42] All non-QFN All non-QFN CY3250-24X23A CY3250-8DIP-FK, Adapters can be found at CY3250-8SOIC-FK, http://www.emulation.com. CY3250-20DIP-FK, CY3250-20SOIC-FK, CY3250-20SSOP-FK, CY3250-28DIP-FK, CY3250-28SOIC-FK, CY3250-28SSOP-FK Notes 40.Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 41.Foot kit includes surface mount feet that can be soldered to the target PCB. 42.Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. Document Number: 38-12028 Rev. *W Page 59 of 71

CY8C24123A CY8C24223A CY8C24423A Ordering Information The following table lists the CY8C24x23A PSoC device’s key package features and ordering codes. Table 53. CY8C24x23A PSoC Device Key Features and Ordering Information Package Ordering Code Flash (Bytes) SRAM (Bytes) Switch Mode Pump Temperature Range Digital Blocks Analog Blocks Digital I/O Pins Analog Inputs Analog Outputs XRES Pin 8-pin (300-mil) DIP CY8C24123A-24PXI 4K 256 No –40 °C to +85 °C 4 6 6 4 2 No 8-pin (150-mil) SOIC CY8C24123A-24SXI 4K 256 No –40 °C to +85 °C 4 6 6 4 2 No 8-pin (150-mil) SOIC CY8C24123A-24SXIT 4K 256 No –40 °C to +85 °C 4 6 6 4 2 No (Tape and Reel) 20-pin (300-mil) DIP CY8C24223A-24PXI 4K 256 Yes –40 °C to +85 °C 4 6 16 8 2 Yes 20-pin (210-mil) SSOP CY8C24223A-24PVXI 4K 256 Yes –40 °C to +85 °C 4 6 16 8 2 Yes 20-pin (210-mil) SSOP CY8C24223A-24PVXIT 4K 256 Yes –40 °C to +85 °C 4 6 16 8 2 Yes (Tape and Reel) 20-pin (300-mil) SOIC CY8C24223A-24SXI 4K 256 Yes –40 °C to +85 °C 4 6 16 8 2 Yes 20-pin (300-mil) SOIC CY8C24223A-24SXIT 4K 256 Yes –40 °C to +85 °C 4 6 16 8 2 Yes (Tape and Reel) 28-pin (210-mil) SSOP CY8C24423A-24PVXI 4K 256 Yes –40 °C to +85 °C 4 6 24 10 2 Yes 28-pin (210-mil) SSOP CY8C24423A-24PVXIT 4K 256 Yes –40 °C to +85 °C 4 6 24 10 2 Yes (Tape and Reel) 28-pin (300-mil) SOIC CY8C24423A-24SXI 4K 256 Yes –40 °C to +85 °C 4 6 24 10 2 Yes 28-pin (300-mil) SOIC CY8C24423A-24SXIT 4K 256 Yes –40 °C to +85 °C 4 6 24 10 2 Yes (Tape and Reel) 32-pin (5 × 5 mm 1.00 max) CY8C24423A-24LTXI 4K 256 Yes –40 °C to +85 °C 4 6 24 10 2 Yes Sawn QFN 32-pin (5 × 5 mm 1.00 max) CY8C24423A-24LTXIT 4K 256 Yes –40 °C to +85 °C 4 6 24 10 2 Yes Sawn QFN (Tape and Reel) 56-pin OCD SSOP CY8C24000A-24PVXI[43] 4K 256 Yes –40 °C to +85 °C 4 6 24 10 2 Yes Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE). Ordering Code Definitions CY 8 C 24 xxx-SPxx Package Type: Thermal Rating: PX = PDIP Pb-free C = Commercial SX = SOIC Pb-free I = Industrial PVX = SSOP Pb-free E = Extended LFX/LKX = QFN Pb-free AX = TQFP Pb-Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Note 43.This part may be used for in-circuit debugging. It is NOT available for production. Document Number: 38-12028 Rev. *W Page 60 of 71

CY8C24123A CY8C24223A CY8C24423A Acronyms Acronyms Used Table54 lists the acronyms that are used in this document. Table 54. Acronyms Used in this Datasheet Acronym Description Acronym Description AC alternating current MIPS million instructions per second ADC analog-to-digital converter OCD on-chip debug API application programming interface PCB printed circuit board CMOS complementary metal oxide semiconductor PDIP plastic dual-in-line package CPU central processing unit PGA programmable gain amplifier CRC cyclic redundancy check PLL phase-locked loop CT continuous time POR power on reset DAC digital-to-analog converter PPOR precision power on reset DC direct current PRS pseudo-random sequence DTMF dual-tone multi-frequency PSoC® Programmable System-on-Chip ECO external crystal oscillator PWM pulse width modulator EEPROM electrically erasable programmable read-only memory QFN quad flat no leads GPIO general purpose I/O RTC real time clock ICE in-circuit emulator SAR successive approximation IDE integrated development environment SC switched capacitor ILO internal low speed oscillator SLIMO slow IMO IMO internal main oscillator SMP switch mode pump I/O input/output SOIC small-outline integrated circuit IrDA infrared data association SPITM serial peripheral interface ISSP in-system serial programming SRAM static random access memory LCD liquid crystal display SROM supervisory read only memory LED light-emitting diode SSOP shrink small-outline package LPC low power comparator UART universal asynchronous receiver / transmitter LVD low voltage detect USB universal serial bus MAC multiply-accumulate WDT watchdog timer MCU microcontroller unit XRES external reset Reference Documents CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34, CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical Reference Manual (TRM) (001-14463) Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459) Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com. Document Number: 38-12028 Rev. *W Page 61 of 71

CY8C24123A CY8C24223A CY8C24423A Document Conventions Units of Measure Table55 lists the units of measures. Table 55. Units of Measure Symbol Units of Measure Symbol Units of Measure kB 1024 bytes µs microsecond dB decibels ms millisecond °C degree Celsius ns nanosecond fF femto farad ps picosecond pF picofarad µV microvolts kHz kilohertz mV millivolts MHz megahertz mVpp millivolts peak-to-peak rt-Hz root hertz nV nanovolts k kilohm V volts  ohm µW microwatts µA microampere W watt mA milliampere mm millimeter nA nanoampere ppm parts per million pA pikoampere % percent mH millihenry Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals. Glossary active high 5.A logic signal having its asserted state as the logic 1 state. 6.A logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. analog-to-digital A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts (ADC) a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. API (Application A series of software routines that comprise an interface between a computer application and lower level services Programming and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create Interface) software applications. asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. Bandgap A stable voltage reference design that matches the positive temperature coefficient of VT with the negative reference temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. bandwidth 1.The frequency range of a message or information processing system measured in hertz. 2.The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. Document Number: 38-12028 Rev. *W Page 62 of 71

CY8C24123A CY8C24223A CY8C24423A Glossary (continued) bias 1.A systematic deviation of a value from a reference value. 2.The amount by which the average of a set of values departs from a reference value. 3.The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1.A functional unit that performs a single function, such as an oscillator. 2.A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. buffer 1.A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written. 2.A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3.An amplifier used to lower the output impedance of a system. bus 1.A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2.A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3.One or more conductors that serve as a common connection for a group of related devices. clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler A program that translates a high level language, such as C, into machine language. configuration In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. space crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. debugger A hardware and software system that allows the user to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition. digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. digital-to-analog A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC) (DAC) converter performs the reverse operation. Document Number: 38-12028 Rev. *W Page 63 of 71

CY8C24123A CY8C24223A CY8C24423A Glossary (continued) duty cycle The relationship of a clock period high time to its low time, expressed as a percent. emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop (XRES) and return to a pre-defined state. flash An electrically programmable and erasable, non-volatile technology that provides users with the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is off. Flash block The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. frequency The number of cycles or events per unit of time, for a periodic function. gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ICE The in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many routine (ISR) interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. jitter 1.A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2.The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. low-voltage detect A circuit that senses V and provides an interrupt to the system when V falls lower than a selected threshold. DD DD (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. Document Number: 38-12028 Rev. *W Page 64 of 71

CY8C24123A CY8C24223A CY8C24423A Glossary (continued) microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal The reference to a circuit containing both analog and digital techniques and components. modulator A device that imposes a signal on a carrier. noise 1.A disturbance that affects a signal and that may distort the information carried by the signal. 2.The random variations of one or more characteristics of any entity such as voltage, current, or data. oscillator A circuit that may be crystal controlled and is used to generate a clock frequency. parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference loop (PLL) signal. pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. port A group of pins, usually eight. power on reset A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is one type of (POR) hardware reset. PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark of Cypress. PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurand. modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. register A storage device with a specific capacity, such as a bit or byte. reset A means of bringing a system back to a know state. See hardware reset and software reset. ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. serial 1.Pertaining to a process in which all events occur one after the other. 2.Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. Document Number: 38-12028 Rev. *W Page 65 of 71

CY8C24123A CY8C24223A CY8C24423A Glossary (continued) shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. SRAM An acronym for static random access memory. A memory device allowing users to store and retrieve data at a high rate of speed. The term static is used because, after a value has been loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. stop bit A signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1.A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2.A system whose operation is synchronized by a clock signal. tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. V A name for a power net meaning “voltage drain.” The most positive power supply signal. Usually 5 V or 3.3 V. DD V A name for a power net meaning “voltage source.” The most negative power supply signal. SS watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. Document Number: 38-12028 Rev. *W Page 66 of 71

CY8C24123A CY8C24223A CY8C24423A Errata This section describes the errata for the CY8C24xxxA device family. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number Ordering Information CY8C24123A CY8C24123A-24PXI CY8C24123A-24SXI CY8C24123A-24SXIT CY8C24223A-24PXI CY8C24223A-24PVXI CY8C24223A-24PVXIT CY8C24223A-24SXI CY8C24223A-24SXIT CY8C24423A-24PVXI CY8C24423A-24PVXIT CY8C24423A-24SXI CY8C24423A-24SXIT CY8C24423A-24LFXI CY8C24423A-24LTXI CY8C24423A-24LTXIT CY8C24000A-24PVXI CY8C24123A Qualification Status Product Status: Production CY8C24123A Errata Summary The following table defines the errata applicability to available CY8C24123A family devices. Items Part Number Silicon Revision Fix Status [1.]. Internal Main Oscillator (IMO) Tolerance Deviation at CY8C24123A *A No silicon fix planned. Temperature Extremes Workaround is required. 1.Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extremes ■ Problem Definition Asynchronous Digital Communications Interfaces may fail framing beyond 0 to 70°C. This problem does not affect end-product usage between 0 and 70°C. ■ Parameters Affected The IMO frequency tolerance. The worst case deviation when operated below 0°C and above +70°C and within the upper and lower datasheet temperature range is ±5%. ■ Trigger Condition(S) The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the data sheet limit of ±2.5% when operated beyond the temperature range of 0 to +70°C. ■ Scope of Impact This problem may affect UART, IrDA, and FSK implementations. ■ Workaround Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface. ■ Fix Status Silicon fix is not planned. The workaround mentioned above should be used. Document Number: 38-12028 Rev. *W Page 67 of 71

CY8C24123A CY8C24223A CY8C24423A Document History Page Document Title: CY8C24123A/CY8C24223A/CY8C24423A, PSoC® Programmable System-on-Chip Document Number: 38-12028 Orig. of Submission Revision ECN Description of Change Change Date ** 236409 SFV See ECN New silicon and new document – Preliminary datasheet. *A 247589 SFV See ECN Changed the title to read “Final” datasheet. Updated Electrical Specifications chapter. *B 261711 HMT See ECN Input all SFV memo changes. Updated Electrical Specifications chapter. *C 279731 HMT See ECN Update Electrical Specifications chapter, including 2.7 VIL DC GPIO spec. Add Solder Reflow Peak Temperature table. Clean up pinouts and fine tune wording and format throughout. *D 352614 HMT See ECN Add new color and CY logo. Add URL to preferred dimensions for mounting MLF packages. Update Transmitter and Receiver AC Digital Block Electrical Specifications. Re-add ISSP pinout identifier. Delete Electrical Specification sentence re: devices running at greater than 12 MHz. Update Solder Reflow Peak Temperature table. Fix CY.com URLs. Update CY copyright. *E 424036 HMT See ECN Fix SMP 8-pin SOIC error in Feature and Order table. Update 32-pin QFN E-Pad dimensions and rev. *A. Add ISSP note to pinout tables. Update typical and recommended Storage Temperature per industrial specs. Add OCD non-production pinout and package diagram. Update CY branding and QFN convention. Update package diagram revisions. *F 521439 HMT See ECN Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add new Dev. Tool section. Add CY8C20x34 to PSoC Device Characteristics table. *G 2256806 UVS / See ECN Added Sawn pin information. PYRS *H 2425586 DSO / See ECN Corrected Ordering Information to include CY8C24423A-24LTXI and AESA CY8C24423A-24LTXIT *I 2619935 OGNE / 12/11/2008 Changed title to “CY8C24123A, CY8C24223A, CY8C24423A PSoC® AESA Programmable System-on-Chip™” Updated package diagram 001-30999 to *A. Added note on digital signaling in DC Analog Reference Specifications on page 28. Added Die Sales information note to Ordering Information on page 60. *J 2692871 DPT / 04/16/2009 Updated Max package thickness for 32-pin QFN package PYRS Formatted Notes Updated “Getting Started” on page7 Updated “Development Tools” on page8 and “Designing with PSoC Designer” on page9 *K 2762168 JVY / 06/25/2009 Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as AESA follows: Modified FIMO6 and TWRITE specifications. Replaced T (time) specification with SR (slew rate) specifi- RAMP POWER_UP cation. Added note [9] to Flash Endurance specification. Added IOH, IOL, DC , F , T , T , T , and ILO 32K_U POWERUP ERASEALL PROGRAM_HOT T specifications. PROGRAM_COLD Document Number: 38-12028 Rev. *W Page 68 of 71

CY8C24123A CY8C24223A CY8C24423A Document History Page (continued) Document Title: CY8C24123A/CY8C24223A/CY8C24423A, PSoC® Programmable System-on-Chip Document Number: 38-12028 Orig. of Submission Revision ECN Description of Change Change Date *L 2897881 MAXK / 03/23/2010 Add “More Information” on page2. Update unit in Table10-28 and Table39 of NJF SPIS Maximum Input Clock Frequency from ns to MHz. Update revision of package diagrams for 8 PDIP, 8 SOIC, 20 PDIP, 20 SSOP, 20 SOIC, 28 PDIP, 28 SSOP, 28 SOIC, 32 QFN. Updated Cypress website links. Removed reference to PSoC Designer 4.4. Updated 56-Pin SSOP definitions and diagram. Added T andT parameters in Absolute Maximum BAKETEMP BAKETIME Ratings. Updated 5 V DC Analog Reference Specifications table. Updated Note in Packaging Information. Added Note 29. Updated Solder Reflow Specifications table. Removed Third Party Tools and Build a PSoC Emulator into your Board. Removed inactive parts from Ordering Information. Update trademark info. and Sales, Solutions, and Legal Information. *M 2942375 VMAD 06/02/2010 Updated content to match current style guide and datasheet template. No technical updates. *N 3032514 NJF 09/17/10 Added PSoC Device Characteristics table. Added DC I2C Specifications table. Added F max limit. 32K_U Added Tjit_IMO specification, removed existing jitter specifications. Updated Analog reference tables. Updated Units of Measure, Acronyms, Glossary, and References sections. Updated solder reflow specifications. No specific changes were made to AC Digital Block Specifications table and I2C Timing Diagram. They were updated for clearer understanding. Updated Figure 13 since the labelling for y-axis was incorrect. Template and styles update. *O 3098766 YJI 12/01/2010 No technical updates. Completing Sunset Review. *P 3351721 YJI 08/31/2011 Full annual review of document. No changes are required. *Q 3367463 BTK / GIR 09/22/2011 Updated text under DC Analog Reference Specifications on page 28. Removed package diagram spec 51-85188 as there is no active MPN using this outline drawing. The text “Pin must be left floating” is included under Description of NC pin in Table 5 on page 13 and Table 6 on page 14. Updated Table 51 on page 57 to give more clarity. Removed Footnote #35. *R 3598291 LURE / 04/24/2012 Changed the PWM description string from “8- to 32-bit” to “8- and 16-bit”. XZNG *S 3991993 PMAD 05/08/2013 Updated Packaging Information: spec 51-85066 – Changed revision from *E to *F. spec 51-85014 – Changed revision from *F to *G. spec 51-85026 – Changed revision from *F to *G. spec 001-30999 – Changed revision from *C to *D. spec 51-85062 – Changed revision from *E to *F. Updated Reference Documents (Removed 001-17397 spec, 001-14503 spec related information). Added Errata. Document Number: 38-12028 Rev. *W Page 69 of 71

CY8C24123A CY8C24223A CY8C24423A Document History Page (continued) Document Title: CY8C24123A/CY8C24223A/CY8C24423A, PSoC® Programmable System-on-Chip Document Number: 38-12028 Orig. of Submission Revision ECN Description of Change Change Date *T 4066332 PMAD 07/17/2013 Added Errata Footnotes (Note 1, 19). Updated PSoC Functional Overview: Updated PSoC Core: Added Note 1 and referred the same note in 4th paragraph in PSoC Core. Updated Electrical Specifications: Updated AC Electrical Characteristics: Updated AC Chip-Level Specifications: Added Note 19 and referred the same note in F parameter. IMO24 Updated minimum and maximum values of F parameter. IMO24 Updated AC Digital Block Specifications: Replaced all instances of maximum value “49.2” with “50.4” and “24.6” with “25.2” in Table38. Updated to new template. *U 4479672 RJVB 08/20/2014 Updated Packaging Information: Updated Packaging Dimensions: spec 51-85011 – Changed revision from *C to *D. spec 51-85024 – Changed revision from *E to *F. spec 51-85026 – Changed revision from *G to *H. Updated Errata: Updated CY8C24123A Errata Summary: Updated details in “Fix Status” column in the table. Updated details in “Fix Status” bulleted point below the table. Completing Sunset Review. *V 4622083 RKRM 01/13/2015 Added More Information. *W 5688158 XKJ 05/03/2017 Updated Packaging Information: Updated Packaging Dimensions: spec 51-85066 – Changed revision from *G to *H. Updated Ordering Information: Updated part numbers. Updated Errata: Updated Part Numbers Affected: Updated part numbers. Updated to new template. Document Number: 38-12028 Rev. *W Page 70 of 71

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