CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 ® CapSense Express™ Button Capacitive Controllers CapSense® Express™ Button Capacitive Controllers Features Overview ■10/8/6/4 capacitive button input These CapSense Express™ controllers support four to ten ❐Robust sensing algorithm capacitive sensing (CapSense) buttons. The device functionality ❐High sensitivity, low noise is configured through an I2C port and can be stored in onboard nonvolatile memory for automatic loading at power-on. The ❐Immunity to RF and AC noise CY8C20110 is optimized for dimming LEDs in 15 selectable duty ❐Low radiated EMC noise cycles for back light applications. The device can be configured ❐Supports wide range of input capacitance, sensor shapes, to have up to 10 GPIOs connected to the PWM output. The PWM and sizes duty cycle is programmable for variable LED intensities. ■Target applications The four key blocks that make up these devices are: a robust ❐Printers capacitive sensing core with high immunity against radiated and ❐Cellular handsets conductive noise, control registers with nonvolatile storage, ❐LCD monitors configurable outputs, and I2C communications. The user can ❐Portable DVD players configure registers with parameters needed to adjust the operation and sensitivity of the CapSense buttons and outputs ■Low operating current and permanently store the settings. The standard I2C serial ❐Active current: continuous sensor scan: 1.5 mA communication interface enables the host to configure the ❐Deep sleep current: 4 µA device and read sensor information in real time. The I2C address is fully configurable without any external hardware strapping. ■Industry's best configurability ❐Custom sensor tuning, one optional capacitor ❐Output supports strong drive for LED ❐Output state can be controlled through I2C or directly from CapSense® input state ❐Run time reconfigurable over I2C ■Advanced features ❐All GPIOs support LED dimming with configurable delay option in CY8C20110 ❐Interrupt outputs ❐User defined inputs ❐Wake on interrupt input ❐Sleep control pin ❐Nonvolatile storage of custom settings ❐Easy integration into existing products – configure output to match system ❐No external components required ❐World-class free configuration tool ■Wide range of operating voltages ❐2.4 V to 2.9 V ❐3.10 V to 3.6 V ❐4.75 V to 5.25 V ■I2C communication ❐Supported from 1.8 V ❐Internal pull-up resistor support option ❐Data rate up to 400 kbps ❐Configurable I2C addressing ■Industrial temperature range: –40 °C to +85 °C ■Available in 16-pin QFN, 8-pin, and 16-pin SOIC packages Errata: For information on silicon errata, see “Errata” on page40. Details include trigger conditions, devices affected, and proposed workaround. CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-54606 Rev. *N Revised May 11, 2017

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Contents Pinouts -16-Pin QFN .........................................................3 Button Layout Design ................................................18 Pin Definitions ..................................................................3 Recommended via Hole Placement ..........................18 Pinouts - 16-Pin SOIC .......................................................4 Example PCB Layout Design with Two Pin Definitions ..................................................................4 CapSense Buttons and Two LEDs ............................20 Pinouts - 8-pin SOIC .........................................................5 Operating Voltages .........................................................21 Pin Definitions ..................................................................5 CapSense Constraints ...................................................21 Typical Circuits .................................................................6 Absolute Maximum Ratings ..........................................22 I2C Interface ......................................................................8 Operating Temperature ..................................................22 I2C Device Addressing ................................................8 Electrical Specifications ................................................23 I2C Clock Stretching ....................................................8 DC Electrical Specifications ......................................23 Format for Register Write and Read ...........................9 CapSense Electrical Characteristics .........................26 Operating Modes of I2C Commands .............................10 AC Electrical Specifications .......................................26 Normal Mode .............................................................10 Appendix .........................................................................29 Setup Mode ...............................................................10 Examples of Frequently Used I2C Commands .........29 Device Operation Modes ................................................10 Ordering Information ......................................................30 Active Mode ...............................................................10 Ordering Code Definitions .........................................30 Periodic Sleep Mode .................................................10 Thermal Impedances .....................................................31 Deep Sleep Mode ......................................................10 Solder Reflow Specifications ........................................31 Sleep Control Pin ............................................................10 Package Diagrams ..........................................................32 Interrupt Pin to Master ...................................................10 Acronyms ........................................................................34 LED Dimming ..................................................................10 Reference Documents ....................................................34 LED Dimming Mode 1: Change Intensity on Document Conventions .................................................34 ON/OFF Button Status ..............................................11 Units of Measure .......................................................34 LED Dimming Mode 2: Flash Intensity on Numeric Conventions ................................................34 ON Button Status ......................................................11 Glossary ..........................................................................35 LED Dimming Mode 3: Hold Intensity After Errata ...............................................................................40 ON/OFF Button Transition .........................................12 CY8C20110 ...............................................................40 LED Dimming Mode 4: Toggle Intensity on CY8C20140/142/160/180/1A0 ..................................41 ON/OFF or OFF/ON Button Transitions ....................12 Document History Page .................................................43 Registers .........................................................................13 Sales, Solutions, and Legal Information ......................45 Register Map .............................................................13 Worldwide Sales and Design Support .......................45 Device IDs .................................................................17 Products ....................................................................45 CapSense Express Commands ................................17 PSoC® Solutions ......................................................45 Register Conventions ................................................17 Cypress Developer Community .................................45 Layout Guidelines and Best Practices .........................18 Technical Support .....................................................45 CapSense Button Shapes .........................................18 Document Number: 001-54606 Rev. *N Page 2 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Pinouts -16-Pin QFN Figure 1. 16-pin QFN (3 × 3 × 0.6 mm) (no e-pad) Pinout[1]   QFN Pin Definitions 16-pin QFN (no e-pad)[1, 2] Pin No. Pin Name Description 1 GP0[0] Configurable as CapSense or GPIO 2 GP0[1] Configurable as CapSense or GPIO 3 I2C SCL I2C clock 4 I2C SDA I2C data 5 GP1[0] Configurable as CapSense or GPIO 6 GP1[1][3] Configurable as CapSense or GPIO 7 VSS Ground connection 8 GP1[2][3] Configurable as CapSense or GPIO 9 GP1[3] Configurable as CapSense or GPIO 10 GP1[4] Configurable as CapSense or GPIO 11 XRES Active high external reset with internal pull-down 12 GP0[2] Configurable as CapSense or GPIO 13 VDD Supply voltage 14 GP0[3] Configurable as CapSense or GPIO 15 CSInt Integrating capacitor Input. The external capacitance is required only if 5:1 SNR cannot be achieved. Typical range is 1 nF to 4.7 nF 16 GP0[4] Configurable as CapSense or GPIO Notes 1. CY8C20110 (10 Buttons) / CY8C20180 (8 Buttons) / CY8C20160 (6 Buttons) / CY8C20140 (4 Buttons) 2. 8/6/4 available configurable IOs can be configured to any of the 10 IOs of the package. After any of the 8/6/4 IOs are chosen, the remaining 2/4/6 IOs of the package are not available for any functionality. 3. Avoid using GP1[1] and GP1[2] for driving LEDs. These two pins have special functions during power-up which is used at factory. LEDs connected to these two pins blink during the power-up of the device. Document Number: 001-54606 Rev. *N Page 3 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Pinouts - 16-Pin SOIC Figure 2. 16-pin SOIC (150 Mils) Pinout[4] VDD VSS Pin Definitions 16-pin SOIC[4, 5] Pin No. Name Description 1 GP0[3] Configurable as CapSense or GPIO 2 CSint Integrating capacitor input. The external capacitance is required only if 5:1 SNR cannot be achieved. Typical range is 1 nF to 4.7 nF. 3 GP0[4] Configurable as CapSense or GPIO 4 GP0[0] Configurable as CapSense or GPIO 5 GP0[1] Configurable as CapSense or GPIO 6 I2C SCL I2C clock 7 I2C SDA I2C data 8 GP1[0] Configurable as CapSense or GPIO 9 GP1[1][6] Configurable as CapSense or GPIO 10 VSS Ground connection 11 GP1[2][6] Configurable as CapSense or GPIO 12 GP1[3] Configurable as CapSense or GPIO 13 GP1[4] Configurable as CapSense or GPIO 14 XRES Active high external reset with internal pull-down 15 GP0[2] Configurable as CapSense or GPIO 16 VDD Supply voltage Notes 4. CY8C20110 (10 Buttons) / CY8C20180 (8 Buttons) / CY8C20160 (6 Buttons) / CY8C20140 (4 Buttons) 5. 8/6/4 available configurable IOs can be configured to any of the 10 IOs of the package. After any of the 8/6/4 IOs are chosen, the remaining 2/4/6 IOs of the package are not available for any functionality. 6. Avoid using GP1[1] and GP1[2] for driving LEDs. These two pins have special functions during power-up which is used at factory. LEDs connected to these two pins blink during the power-up of the device. Document Number: 001-54606 Rev. *N Page 4 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Pinouts - 8-pin SOIC Figure 3. 8-pin SOIC (150 Mils) pinout CY8C20142 (4 Button)   Pin Definitions 8-pin SOIC CY8C20142 (4 Button) Pin No. Name Description 1 VSS Ground 2 I2C SCL I2C Clock 3 I2C SDA I2C Data 4 GP1[0][7] Configurable as CapSense or GPIO 5 GP1[1][7] Configurable as CapSense or GPIO 6 GP0[0] Configurable as CapSense or GPIO 7 GP0[1] Configurable as CapSense or GPIO 8 VDD Supply voltage Important Note For information on the preferred dimensions for mounting QFN packages, see the "Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages" available at http://www.amkor.com. Note 7. Avoid using GP1[0] and GP1[1] for driving LED. These two pins have special functions during power up which is used at factory. LEDs connected to these two pins will blink during power up of the device. Document Number: 001-54606 Rev. *N Page 5 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Typical Circuits Figure 4. Circuit 1 – Five Buttons and Five LEDs with I2C Interface CapSense sensor B2 B3 VDD_CE VDD_CE R1 C1 R2 560E 1.2nF 560E C2 0.1uF VDD_CE U1 16 15 14 13 D1 LED R5 560E 1 GPO[4] CSint GP0[3] VDD 12 R6 560E B4 C aspeSnesnosre GPO[0] GPO[2] VDD_CE R3 R4 R7 560E 4.7K 4.7K D2 LED 2 11 GPO[1] XRES VDD_CE R8 330E CY8C20110 I2C COMMINTERFACE R10 330E 34 II22CC__SSCDLAGP1[0] GP1[1] VSS GP1[2] GGPP11[[34]] 910 RR911 556600EE DD34 LLEEDD 5 6 7 8 R12 R13 R14 560E 560E 560E D5 LED VDD_CE B1 B0 CapSense sensor Figure 5. Circuit 2 – Two Buttons and Two LEDs with I2C Interface CapSense CapSense Sensor Sensor Document Number: 001-54606 Rev. *N Page 6 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Typical Circuits (continued) Figure 6. Circuit 3 – Compatibility with 1.8 V I2C Signaling[8, 9] CapSense CapSense Sensor Sensor Figure 7. Circuit 4 – Powering Down CapSense Express Device for Low Power Requirements[10] Output enable Output VDD LDO I2C Pull LED UPs Master SDA Or CapSense Express I2C Host BUS SCL Notes 8. 1.8 V  VDD_I2C  VDD_CE and 2.4 V  VDD_CE  5.25 V. 9. The I2C drive mode of the CapSense device should be configured properly before using in an I2C environment with external pull-ups. Please refer to I2C_ADDR_DM register and its factory setting. 10.Fshoor uloldw b peo fwroemr r tehqeu israemmee nstosu, rifc Ve DsDu cish ttoh abte t uturnrninegd ooffff ,t hthei sV cDoDn ecnesput rceasn t hbaet unsoe sdi.g Tnhael isre aqpupirleiemde tnot tihse t hdaetv tihcee wVDhDiles oit fi sC uanppSoewnseere Edx. pTrhees sI2, CI2 Csi gpnualll-su sphso, aunldd n LoEt Dbes driven high by the master in this situation. If a port pin or group of port pins of the master can cater to the power supply requirements of the circuit, the LDO can be avoided. Document Number: 001-54606 Rev. *N Page 7 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 I2C Interface The CapSense Express devices support the industry-standard I2C protocol, which can be used for: ■Configuring the device ■Reading the status and data registers of the device ■Controlling device operation ■Executing commands The I2C address can be modified during configuration. I2C Device Addressing The device uses a seven-bit addressing protocol. The I2C data transfer is always initiated by the master sending a one-byte address: the first seven bits contain the address and the LSB indicates the data transfer direction. Zero in the LSB bit indicates the write transaction from master and one indicates the read transfer by the master. The following table shows examples for different I2C addresses. Table 1. I2C Address Examples 7-bit Slave Address D7 D6 D5 D4 D3 D2 D1 D0 8-bit Slave Address 1 0 0 0 0 0 0 1 0(W) 02 1 0 0 0 0 0 0 1 1(R) 03 75 1 0 0 1 0 1 1 0(W) 96 75 1 0 0 1 0 1 1 1(W) 97 I2C Clock Stretching bit is transmitted. The I2C master must check the SCL status (it ‘Clock stretching’ or ‘bus stalling’ in I2C communication protocol should be high) before the I2C master initiates any data transfer with CapSense Express. If the master fails to do so and is a state in which the slave holds the SCL line low to indicate continues to communicate, the communication is erroneous. that it is busy. In this condition, the master is expected to wait until the SCL is released by the slave. Also note that, while using CapSense Express Devices on an I2C Wdehveicne a, nt hI2eC CmaapsSteern csoem Emxupnreicsast esst waliltsh tthhee CI2aCp Sbeunss ea Eftxepr rethses bthues , I2I2CC bmuass tbeer fsohreo uClda npoSte gnesnee rEaxtep rae ssst adrte ovric set ogpe cnoenradtiteiosn a inn acknowledgement (ACK/NCK) for the previous transaction. An reception of each byte (that is, just before the ACK/NAK bit) until acknowledgement state produced by the CapSense Express processing of the byte is complete and critical internal functions are executed. Use a fully I2C compliant master to communicate Device for the previous data after the master generates a start condition or stop condition, may produce unexpected behavior with the CapSense Express device. from CapSense Express I2C slave interface. If the I2C master does not support clock stretching (a bit banged software I2C Master), the master must wait for a specific amount The following diagrams represent the ACK time delays shown in Format for Register Write and Read on page 9 for write and read. of time (as specified in Format for Register Write and Read on page 9) for each register write and read operation before the next Document Number: 001-54606 Rev. *N Page 8 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Figure 8. Write ACK Time Representation[11] Figure 9. Read ACK Time Representation[12] Format for Register Write and Read Register write format Start Slave Addr + W A Reg Addr A Data A Data A . . . . . Data A Stop Register read format Start Slave Addr + W A Reg Addr A Stop Start Slave Addr + R A Data A Data A . . . . . Data N Stop Legends: Master A – ACK Slave N – NAK Notes 11.Time to process the received data. 12.Time taken for the device to send next byte. Document Number: 001-54606 Rev. *N Page 9 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Operating Modes of I2C Commands The sleep interval should be 8 Hz or 1 Hz when using save to flash command. The configuration sequence should be: Normal Mode 1.Write configuration data to registers with sleep interval being In normal mode of operation, the acknowledgment time[13] is 8Hz or 1 Hz optimized. The timings remain approximately the same for 2.Save the settings to flash different configurations of the slave. To reduce the 3.Change the sleep interval as per design. acknowledgment times in normal mode, the registers 0x06– 0x09, 0x0C, 0x0D, 0x10–0x17, 0x50, 0x51, 0x57–0x60, 0x7E Deep Sleep Mode are given only read access. Write to these registers can be done Deep Sleep mode provides the lowest power consumption only in setup mode. because there is no operation running. All CapSense scanning Setup Mode is disabled during this mode. In this mode, the device wakes up only using an external GPIO interrupt. A sleep timer interrupt All registers have read and write access (except those which are cannot wake up a device from deep sleep mode. This is treated read only) in this mode. The acknowledgment times[14] are as a continuous sleep mode without periodic wakeups. Refer to longer compared to normal mode. When CapSense scanning is the application note “CapSense Express Power and Sleep disabled (command code 0x0A in command register 0xA0), the Considerations” - AN44209 for details on different sleep modes. acknowledgment times can be improved to values similar to the To get the lowest power during this mode the sleep timer normal mode of operation. frequency should be set to 1 Hz. Device Operation Modes Sleep Control Pin CapSense Express devices are configured to operate in any of The devices require a dedicated sleep control pin to enable the following three modes to meet different power consumption reliable I2C communication in case any sleep mode is enabled. requirements: This is achieved by pulling the sleep control pin low to wake up ■Active Mode the device and start I2C communication. The sleep control pin can be configured on any GPIO. ■Periodic Sleep Mode Interrupt Pin to Master ■Deep Sleep Mode To inform the master of any button press a GPIO can be Active Mode configured as interrupt output and all CapSense buttons can be In the Active mode, all the device blocks including the CapSense connected to this GPIO with an OR logic operator. This can be subsystem are powered. Typical active current consumption of configured using the software tool. the device across the operating voltage range is 1.5 mA. LED Dimming Periodic Sleep Mode Sleep mode provides an intermediate power operation mode. It To change the brightness and intensity of the LEDs, the host is enabled by configuring the corresponding device registers master (MCU, MPU, DSP, and so on) must send I2C commands (0x7E, 0x7F). The device goes into sleep after there is no event and program the PWM registers to enable output pins, set duty for stay awake counter (Reg 0x80) number of sleep intervals. cycle, and mode configuration. The single PWM source is The device wakes up on sleep interval and scans the capacitive connected to all GPIO pins and has a common user defined duty sensors before going back to sleep again. If any sensor is active, cycle. Each PWM enabled pin has two possible outputs: PWM then the device wakes up. The device can also wake up from and 0/1 (depending on the configuration). Four different modes Sleep mode with a GPIO interrupt. The sleep interval is of LED[15] dimming are possible, as shown in LED Dimming configured through registers. The following sleep intervals are Mode 1: Change Intensity on ON/OFF Button Status on page 11 supported in CapSense Express: to LED Dimming Mode 4: Toggle Intensity on ON/OFF or OFF/ON Button Transitions on page 12. The operation mode and ■1.95 ms (512 Hz) duty cycle of the PWM enabled pins is common. This means that one pin cannot behave as in Mode 1 and another pin as in Mode ■15.6 ms (64 Hz) 2. ■125 ms (8 Hz) ■1 s (1 Hz) Notes 13.Errata: The worst case Acknowledgment time for all critical registers is 140µs. For more information, see “Errata” on page40. 14.Errata: The CY8C20110 device acknowledges to host within 100 µs, but is not accessible for any other operation until configuration is successfully stored into flash memory and the device is ready to execute the next command. For more information, see “Errata” on page40. 15.Errata: Applicable only for CY8C20110 device. For more information, see “Errata” on page40. Document Number: 001-54606 Rev. *N Page 10 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 LED Dimming Mode 1: Change Intensity on ON/OFF Button Status   LED Dimming Mode 2: Flash Intensity on ON Button Status   Document Number: 001-54606 Rev. *N Page 11 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 LED Dimming Mode 3: Hold Intensity After ON/OFF Button Transition   LED Dimming Mode 4: Toggle Intensity on ON/OFF or OFF/ON Button Transitions   Note LED DIMMING is available only in CY8C20110. Document Number: 001-54606 Rev. *N Page 12 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Registers Register Map Register Factory Default I2C Max ACK I2C Max ACK Writable Only in Name A(idnd Hreesxs) Access SETUP Mode[16] Values(i no fH Reexg)isters TMimoed ein ( mNosr)[m17a]l TMimodee i n(m Sse)t[u17p] INPUT_PORT0 00 R – 00 0.1 – INPUT_PORT1 01 R – 00 0.1 – STATUS_POR0 02 R – 00 0.1 – STATUS_POR1 03 R – 00 0.1 – OUTPUT_PORT0 04 W – 00 0.1 – OUTPUT_PORT1 05 W – 00 0.1 – CS_ENABL0 06 RW YES 00 – 11 CS_ENABLE 07 RW YES 00 – 11 GPIO_ENABLE0 08 RW YES 00 – 11 GPIO_ENABLE1 09 RW YES 00 – 11 INVERSION_MASK0 0A RW – 00 0.11 – INVERSION_MASK1 0B RW – 00 0.11 – INT_MASK0 0C RW YES 00 – 11 INT_MASK1 0D RW YES 00 – 11 STATUS_HOLD_MSK0 0E RW – 03/1F [18] 0.11 – STATUS_HOLD_MSK1 0F RW – 03/1F [18] 0.11 – DM_PULL_UP0 10 RW YES 00 – 11 DM_STRONG0 11 RW YES 00 – 11 DM_HIGHZ0 12 RW YES 00 – 11 DM_OD_LOW0 13 RW YES 00 – 11 DM_PULL_UP1 14 RW YES 00 – 11 DM_STRONG1 15 RW YES 00 – 11 DM_HIGHZ1 16 RW YES 00 – 11 DM_OD_LOW1 17 RW YES 00 – 11 PWM_ENABLE0[19] 18 RW – 00 0.1 – PWM_ENABLE1[19] 19 RW – 00 0.1 – PWM_MODE_DC[19] 1A RW – 00 0.1 – PWM_DELAY[19] 1B RW – 00 0.1 – OP_SEL_00 1C RW – 00 0.12 11 OPR1_PRT0_00 1D RW – 00 0.12 11 OPR1_PRT1_00 1E RW – 00 0.12 11 OPR2_PRT0_00 1F RW – 00 0.12 11 OPR2_PRT1_00 20 RW – 00 0.12 11 OP_SEL_01 21 RW –] 00 0.12 11 OPR1_PRT0_01 22 RW – 00 0.12 11 OPR1_PRT1_01 23 RW – 00 0.12 11 OPR2_PRT0_01 24 RW – 00 0.12 11 OPR2_PRT1_01 25 RW – 00 0.12 11 OP_SEL_02 26 RW – 00 0.12 11 Notes 16.These registers are writable only after entering into setup mode. All the other registers available for read and write in Normal as well as in Setup mode. 17.The "I2C Max ACK Time" values mentioned in this table are for 3.3-V and 5-V operation; the timing values for 2.7-V operation are 4x the values provided in this table. Refer to Operating Voltages on page 21. 18.The factory defaults of Reg 0x0E and 0x0F is 0x03 for 20142 device and 0x1F for 20140/60/80/10 devices. 19.Errata: These registers are available only in CY8C20110. For more information, see “Errata” on page40. Document Number: 001-54606 Rev. *N Page 13 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Register Map (continued) Register Factory Default I2C Max ACK I2C Max ACK Writable Only in Name A(idnd Hreesxs) Access SETUP Mode[16] Values(i no fH Reexg)isters TMimoed ein ( mNosr)[m17a]l TMimodee i n(m Sse)t[u17p] OPR1_PRT0_02 27 RW – 00 0.12 11 OPR1_PRT1_02 28 RW – 00 0.12 11 OPR2_PRT0_02 29 RW – 00 0.12 11 OPR2_PRT1_02 2A RW – 00 0.12 11 OP_SEL_03 2B RW – 00 0.12 11 OPR1_PRT0_03 2C RW – 00 0.12 11 OPR1_PRT1_03 2D RW – 00 0.12 11 OPR2_PRT0_03 2E RW – 00 0.12 11 OPR2_PRT1_03 2F RW – 00 0.12 11 OP_SEL_04 30 RW – 00 0.12 11 OPR1_PRT0_04 31 RW – 00 0.12 11 OPR1_PRT1_04 32 RW – 00 0.12 11 OPR2_PRT0_04 33 RW – 00 0.12 11 OPR2_PRT1_04 34 RW – 00 0.12 11 OP_SEL_10 35 RW – 00 0.12 11 OPR1_PRT0_10 36 RW – 00 0.12 11 OPR1_PRT1_10 37 RW – 00 0.12 11 OPR2_PRT0_10 38 RW – 00 0.12 11 OPR2_PRT1_10 39 RW – 00 0.12 11 OP_SEL_11 3A RW – 00 0.12 11 OPR1_PRT0_11 3B RW – 00 0.12 11 OPR1_PRT1_11 3C RW – 00 0.12 11 OPR2_PRT0_11 3D RW – 00 0.12 11 OPR2_PRT1_11 3E RW – 00 0.12 11 OP_SEL_12 3F RW – 00 0.12 11 OPR1_PRT0_12 40 RW – 00 0.12 11 OPR1_PRT1_12 41 RW – 00 0.12 11 OPR2_PRT0_12 42 RW – 00 0.12 11 OPR2_PRT1_12 43 RW – 00 0.12 11 OP_SEL_13 44 RW – 00 0.12 11 OPR1_PRT0_13 45 RW – 00 0.12 11 OPR1_PRT1_13 46 RW – 00 0.12 11 OPR2_PRT0_13 47 RW – 00 0.12 11 OPR2_PRT1_13 48 RW – 00 0.12 11 OP_SEL_14 49 RW – 00 0.12 11 OPR1_PRT0_14 4A RW – 00 0.12 11 OPR1_PRT1_14 4B RW – 00 0.12 11 OPR2_PRT0_14 4C RW – 00 0.12 11 OPR2_PRT1_14 4D RW – 00 0.12 11 CS_NOISE_TH 4E RW – 28 0.11 11 CS_BL_UPD_TH 4F RW – 64 0.11 11 CS_SETL_TIME 50 RW YES A0 – 35 CS_OTH_SET 51 RW YES 00 – 35 CS_HYSTERISIS 52 RW – 0A 0.11 11 CS_DEBOUNCE 53 RW – 03 0.11 11 Document Number: 001-54606 Rev. *N Page 14 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Register Map (continued) Register Factory Default I2C Max ACK I2C Max ACK Writable Only in Name A(idnd Hreesxs) Access SETUP Mode[16] Values(i no fH Reexg)isters TMimoed ein ( mNosr)[m17a]l TMimodee i n(m Sse)t[u17p] CS_NEG_NOISE_TH 54 RW – 14 0.11 11 CS_LOW_BL_RST 55 RW – 14 0.11 11 CS_FILTERING[20,21] 56 RW – 20 0.11 11 CS_SCAN_POS_00 57 RW YES FF – 11 CS_SCAN_POS_01 58 RW YES FF – 11 CS_SCAN_POS_02 59 RW YES FF – 11 CS_SCAN_POS_03 5A RW YES FF – 11 CS_SCAN_POS_04 5B RW YES FF – 11 CS_SCAN_POS_10 5C RW YES FF – 11 CS_SCAN_POS_11 5D RW YES FF – 11 CS_SCAN_POS_12 5E RW YES FF – 11 CS_SCAN_POS_13 5F RW YES FF – 11 CS_SCAN_POS_14 60 RW YES FF – 11 CS_FINGER_TH_00 61 RW – 64 0.14 11 CS_FINGER_TH_01 62 RW – 64 0.14 11 CS_FINGER_TH_02 63 RW – 64 0.14 11 CS_FINGER_TH_03 64 RW – 64 0.14 11 CS_FINGER_TH_04 65 RW – 64 0.14 11 CS_FINGER_TH_10 66 RW – 64 0.14 11 CS_FINGER_TH_11 67 RW – 64 0.14 11 CS_FINGER_TH_12 68 RW – 64 0.14 11 CS_FINGER_TH_13 69 RW – 64 0.14 11 CS_FINGER_TH_14 6A RW – 64 0.14 11 CS_IDAC_00 6B RW – 0A 0.14 11 CS_IDAC_01 6C RW – 0A 0.14 11 CS_IDAC_02 6D RW – 0A 0.14 11 CS_IDAC_03 6E RW – 0A 0.14 11 CS_IDAC_04 6F RW – 0A 0.14 11 CS_IDAC_10 70 RW – 0A 0.14 11 CS_IDAC_11 71 RW – 0A 0.14 11 CS_IDAC_12 72 RW – 0A 0.14 11 CS_IDAC_13 73 RW – 0A 0.14 11 CS_IDAC_14 74 RW – 0A 0.14 11 75[22] 76[22] 77[22] 78[22] I2C_ADDR_LOCK 79 RW – 01 0.11 11 DEVICE_ID 7A R – 42/40/60/80/10[23] 0.11 11 DEVICE_STATUS 7B R – 03 0.11 11 I2C_ADDR_DM 7C RW – 00 0.11 11 Notes 20.Errata: Added two on-chip filtering algorithms for improved CapSense performance and better noise immunity. 21.Errata: If a finger is on the sensor, during power-up the sensor triggers and the baseline gets stuck. Baseline is stuck only when Averaging Filter is enabled. For more information, see “Errata” on page40. 22.The register 0x75–0x78, 0x7,D and 0x8A–0x8D are reserved. 23.The Device ID for different devices are tabulated in Device IDs on page 17. Document Number: 001-54606 Rev. *N Page 15 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Register Map (continued) Register Factory Default I2C Max ACK I2C Max ACK Writable Only in Name A(idnd Hreesxs) Access SETUP Mode[16] Values(i no fH Reexg)isters TMimoed ein ( mNosr)[m17a]l TMimodee i n(m Sse)t[u17p] 7D[25] SLEEP_PIN 7E RW YES 00 0.1 11 SLEEP_CTRL 7F RW – 00 0.1 11 SLEEP_SA_CNTR 80 RW – 00 0.1 11 CS_READ_BUTTON 81 RW – 00 0.12 11 CS_READ_BLM 82 R – 00 0.12 11 CS_READ_BLL 83 R – 00 0.12 11 CS_READ_DIFFM 84 R – 00 0.12 11 CS_READ_DIFFL 85 R – 00 0.12 11 CS_READ_RAWM 86 R – 00 0.12 11 CS_READ_RAWL 87 R – 00 0.12 11 CS_READ_STATUSM 88 R – 00 0.12 11 CS_READ_STATUSL 89 R – 00 0.12 11 8A[25] 8B[25] 8C[25] 8D[25] COMMAND_REG A0 W – 00 0.1 11 Notes 24.These registers are writable only after entering into setup mode. All the other registers available for read and write in Normal as well as in Setup mode. 25.The register 0x75–0x78, 0x7D and 0x8A–0x8D are reserved. Document Number: 001-54606 Rev. *N Page 16 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Device IDs Part Number Device ID CY8C20142 42 CY8C20140 40 CY8C20160 60 CY8C20180 80 CY8C20110 10 Note All the Ack times specified are maximum values with all buttons enabled and filer enabled, with maximum order for 5-V and 3.3-V operation. The timing values for 2.7-V operation will be 4x these values. CapSense Express Commands Duration the Device is not accessible Command[26] Description Executable Mode after ACK (in ms)[27] W 00 A0 00 Get firmware revision Setup/Normal 0 W 00 A0 01[28] Store current configuration to NVM Setup/Normal 120 W 00 A0 02 Restore factory configuration Setup/Normal 120 W 00 A0 03 Write NVM POR defaults Setup/Normal 120 W 00 A0 04 Read NVM POR defaults Setup/Normal 5 W 00 A0 05 Read current configurations (RAM) Setup/Normal 5 W 00 A0 06 Reconfigure device (POR) Setup 5 W 00 A0 07 Set normal mode of operation Setup/Normal 0 W 00 A0 08 Set setup mode of operation Setup/Normal 1.2*(loop time[29] + 1 ms) W 00 A0 09 Start scan Setup/Normal 10 W 00 A0 0A Stop scan Setup/Normal 5 W 00 A0 0B Get CapSense scan status Setup/Normal 0 Register Conventions This table lists the register conventions that are specific to this section. Convention Description RW Register has both read and write access R Register has only read access Notes 26.The ‘W’ indicates the write transfer. The next byte of data represents the 7-bit I2C address. 27.The "not accessible" timing values are the maximum values for 5-V and 3.3-V operation. The timing values for 2.7-V operation will be 4x the values provided in this table. Refer to Operating Voltages on page 21. 28.Errata: Save to flash command fails when the sleep interval is set to 512 or 64 Hz. For more information, see “Errata” on page40. 29.Loop time can be measured by probing any sensor using an oscilloscope and measuring the time between two consecutive scans. Document Number: 001-54606 Rev. *N Page 17 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Layout Guidelines and Best Practices This section provides a set of high level rules for board design. Cypress also provides an extensive set of design guidelines for CapSense board designs. Refer to the “Getting Started with CapSense Design Guide” for complete system guidelines. CapSense Button Shapes   Button Layout Design X: Button to ground clearance (Refer to Table 2 on page 18) Y: Button to button clearance (Refer to Table 2 on page 18) Recommended via Hole Placement Table 2. Recommended Layout Guidelines and Best Practices S. No. Category Min Max Recommendations/Remarks Solid round pattern, round with LED hole, rectangle with 1 Button shape – – round corners 2 Button size 5 mm 15 mm 10 mm Equal to button 3 Button-button spacing – 8 mm [X] ground clearance 4 Button ground clearance 0.5 mm 2 mm Button ground clearance = Overlay thickness [Y] 5 Ground flood-top layer – – Hatched ground 7-mil trace and 45-mil grid (15% filling) 6 Ground flood-bottom layer – – Hatched ground 7-mil trace and 70-mil grid (10% filling) Trace length from sensor to 7 – 200 mm < 100 mm PSoC-buttons 8 Trace width 0.17 mm 0.20 mm 0.17 mm (7-mil) Document Number: 001-54606 Rev. *N Page 18 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Table 2. Recommended Layout Guidelines and Best Practices (continued) S. No. Category Min Max Recommendations/Remarks Traces should be routed on the non sensor side. If any 9 Trace routing – – non CapSense trace crosses CapSense trace, ensure that intersection is orthogonal. Via should be placed near the edge of the button/slider to 10 Via position for the sensors – – reduce trace length thereby increasing sensitivity. 11 Via hole size for sensor traces – – 10-mil 12 Number of vias on sensor trace 1 2 1 Place CapSense series resistors close to PSoC for noise CapSense series resistor 13 – 10 mm suppression. CapSense resistors have highest priority placement place them first. Distance between any 14 10-mil 20-mil 20-mil CapSense trace to ground flood Mount the device on the layer opposite to sensor. The 15 Device placement – – CapSense trace length between the device and sensors should be minimum Placement of components in Top layer – sensor pads and 16 – – 2-layer PCB bottom layer – PSoC, other components, and traces. Top layer – sensor pads, second layer – CapSense traces, Placement of components in 17 – – third layer – hatched ground, 4-layer PCB bottom layer – PSoC, other components, and non CapSense traces Should to be non conductive material. Glass, ABS plastic, 18 Overlay material – – Formica Adhesive should be non conductive and dielectrically 19 Overlay adhesives – – homogenous. 467MP and 468MP adhesives made by 3M are recommended. Cut a hole in the sensor pad and use rear mountable 20 LED back lighting – – LEDs. Refer the PCB layout below. Standard board thickness for CapSense FR4 based 21 Board thickness – – designs is 1.6mm. The recommended maximum overlay thickness is 5 mm (with external CSInt)/ 2 mm (without external CSInt). For more details refer to the section “The Integrating Capacitor (Cint)” in AN53490. Note Some device packages does not have CSInt pin and external capacitor cannot be connected. Document Number: 001-54606 Rev. *N Page 19 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Example PCB Layout Design with Two CapSense Buttons and Two LEDs Figure 10. Top Layer Figure 11. Bottom Layer Document Number: 001-54606 Rev. *N Page 20 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Operating Voltages For details on I2C 1x ACK time, refer to Register Map on page 13 and CapSense Express Commands on page 17. I2C 4x ACK time is approximately four times the values mentioned in these tables. CapSense Constraints Parameter Min Typ Max Units Notes Parasitic capacitance (C ) of the CapSense sensor – – 30 pF – P Supply voltage variation (V ) – – ±5% – – DD Document Number: 001-54606 Rev. *N Page 21 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Absolute Maximum Ratings Parameter Description Min Typ Max Unit Notes Higher storage temperatures reduce data retention time. Recommended storage T Storage temperature –55 25 +100 °C temperature is +25 °C ± 25 °C STG (0 °C to 50 °C). Extended duration storage temperatures above 65 °C degrade reliability See Package T Bake temperature – 125 °C – BAKETEMP label See t Bake time package – 72 Hours – BAKETIME label Ambient temperature with power T –40 – +85 °C – A applied Supply voltage on V relative to V DD –0.5 – +6.0 V – DD V SS V DC input voltage V – 0.5 – V + 0.5 V – IO SS DD V DC voltage applied to tristate V – 0.5 – V + 0.5 V – IOZ SS DD Maximum current into any GPIO I –25 – +50 mA – MIO pin ESD Electro static discharge voltage 2000 – – V Human body model ESD LU Latch-up current – – 200 mA – Operating Temperature Parameter Description Min Typ Max Unit Notes T Ambient temperature –40 – +85 °C – A T Junction temperature –40 – +100 °C – J Document Number: 001-54606 Rev. *N Page 22 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Electrical Specifications DC Electrical Specifications DC Chip-Level Specifications Table 3. DC Chip-Level Specifications Parameter Description Min Typ Max Unit Notes V Supply voltage 2.40 – 5.25 V – DD I Supply current – 1.5 2.5 mA Conditions are V = 3.10 V, DD DD T = 25 °C A ISB Deep sleep mode current with – 2.6 4 µA V = 2.55 V, 0 °C < T < 40 °C DD A POR and LVD active ISB Deep sleep mode current with – 2.8 5 µA V = 3.3 V, –40 °C < T < 85 °C DD A POR and LVD active ISB Deep sleep mode current with – 5.2 6.4 µA V = 5.25 V, –40 °C < T < 85 °C DD A POR and LVD active DC GPIO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and – 40°C< T < 85 °C, 3.10 V to 3.6 V and –40 °C < T < 85 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design A A guidance only. Table 4. 5-V and 3.3-V DC GPIO Specifications Parameter Description Min Typ Max Unit Notes I < 10 µA, V > 3.10 V, maximum V High output voltage on Port 0 pins V – 0.2 – – V OH DD OH1 DD of 20 mA source current in all I/Os. I = 1 mA, V > 3.10 V, maximum V High output voltage on Port 0 pins V – 0.9 – – V OH DD OH2 DD of 20 mA source current in all I/Os. I < 10 µA, V > 3.10 V, maximum V High output voltage on Port 1 pins V – 0.2 – – V OH DD OH3 DD of 20 mA source current in all I/Os. I = 5 mA, V > 3.10 V, maximum V High output voltage on Port 1 pins V – 0.9 – – V OH DD OH4 DD of 20 mA source current in all I/Os. I = 20 mA/pin, V > 3.10, OL DD maximum of 40/60 mA sink current V Low output voltage – – 0.75 V OL on even port pins and of 40/60 mA sink current on odd port pins.[30] V (cid:0) 3.1 V, maximum of 20 mA I High output current on Port 0 pins 0.01 – 1 mA DD OH1 source current in all IOs V  3.1 V, maximum of 20 mA I High output current on Port 1 pins 0.01 – 5 mA DD OH2 source current in all IOs V  3.1 V, maximum of 60 mA sink DD current on pins P0_2, P1_2, P1_3, I Low output current – – 20 mA P1_4 and 60 mA sink current on OL pins P0_0, P0_1, P0_3, P0_4, P1_0, P1_1 V Input low voltage – – 0.75 V V = 3.10 V to 3.6 V. IL DD V Input high voltage 1.6 – – V V = 3.10 V to 3.6 V. IH DD V Input low voltage – – 0.8 V V = 4.75 V to 5.25 V. IL DD V Input high voltage 2.0 – – V V = 4.75 V to 5.25 V. IH DD Note 30.The maximum sink current is 40 mA for 20140 and 20142 devices and for all other devices the maximum sink current is 60 mA. Document Number: 001-54606 Rev. *N Page 23 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Table 4. 5-V and 3.3-V DC GPIO Specifications (continued) Parameter Description Min Typ Max Unit Notes V Input hysteresis voltage – 140 – mV – H I Input leakage – 1 – nA Gross tested to 1 µA. IL Package and pin dependent. C Capacitive load on pins as input 0.5 1.7 5 pF IN Temp = 25 °C. Package and pin dependent. C Capacitive load on pins as output 0.5 1.7 5 pF OUT Temp = 25 °C. This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 2.90 V and – 40°C<T < 85 °C, respectively. Typical parameters apply to 2.7 V at 25 °C and are for design guidance only. A Table 5. 2.7-V DC GPIO Specifications Parameter Description Min Typ Max Unit Notes I <10 µA, maximum of 10 mA V High output voltage on Port 0 pins V – 0.2 – – V OH OH1 DD source current in all I/Os. I = 0.2 mA, maximum of 10 mA V High output voltage on Port 0 pins V – 0.5 – – V OH OH2 DD source current in all I/Os. I <10 µA, maximum of 10 mA V High output voltage on Port 1 pins V – 0.2 – – V OH OH3 DD source current in all I/Os. I = 2 mA, maximum of 10 mA V High output voltage on Port 1 pins V – 0.5 – – V OH OH4 DD source current in all I/Os. I = 10 mA/pin, V > 3.10, OL DD maximum of 20/30 mA sink current V Low output voltage – – 0.75 V OL1 on even port pins and of 20/30 mA sink current on odd port pins. [31] V < 2.9 V, maximum of 10 mA I High output current 0.01 – 2 mA DD OH source current in all I/Os V < 2.9 V, maximum of 30 mA sink DD current on pins P0_2, P1_2, P1_3, I Low output current on Port 0 pins – – 10 mA P1_4 and 30 mA sink current on OL1 pins P0_0, P0_1, P0_3, P0_4, P1_0, P1_1 V < 2.9 V, maximum of 50 mA sink DD current on pins P0_2, P1_2, P1_3, I Low output current – – 20 mA P1_4 and 50 mA sink current on OL2 pins P0_0, P0_1, P0_3, P0_4, P1_0, P1_1 V = 2.4 to 2.90 V and 3.10 V to V Input low voltage – – 0.75 V DD IL 3.6 V. V Input high voltage 1.4 – – V V = 2.4 to 2.7 V. IH1 DD V = 2.7 to 2.90 V and 3.10 V to V Input high voltage 1.6 – – V DD IH2 3.6 V. V Input hysteresis voltage – 60 – mV H I Input leakage – 1 – nA Gross tested to 1 µA. IL Package and pin dependent. C Capacitive load on pins as input 0.5 1.7 5 pF IN Temp = 25 °C. Package and pin dependent. C Capacitive load on pins as output 0.5 1.7 5 pF OUT Temp = 25 °C Note 31.The maximum sink current per port is 20 mA for 20140 and 20142 devices and for all other devices the maximum sink current is 30 mA. Document Number: 001-54606 Rev. *N Page 24 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 DC POR and LVD Specifications Table 6. DC POR and LVD Specifications Parameter Description Min Typ Max Unit Notes V value for PPOR trip V must be greater than or equal DD DD V V = 2.7 V – 2.36 2.40 V to 2.5 V during startup or internal PPOR0 DD V V = 3.3 V, 5 V – 2.60 2.65 V reset. PPOR1 DD V value for LVD trip V DD LVD0 V = 2.7 V 2.39 2.45 2.51 V V DD – LVD2 V = 3.3 V 2.75 2.92 2.99 V V DD LVD6 V = 5 V 3.98 4.05 4.12 V DD DC Flash Write Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and – 40°C< T < 85 °C, 3.10 V to 3.6 V and –40 °C < T < 85 °C or 2.4 V to 2.90 V and –40 °C < T < 85 °C, respectively. Typical parameters A A A apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Flash Endurance and Retention specifications are valid only within the range: 25 °C ± 20 °C during the flash write operation. It is at the user’s own risk to operate out of this temperature range. If flash writing is done out of this temperature range, the endurance and data retention reduces. Table 7. DC Flash Write Specifications Symbol Description Min Typ Max Units Notes Supply voltage for flash write V 2.7 – – V – DDIWRITE operations Supply current for flash write I – 5 25 mA – DDP operations Flash Flash endurance 50,000[32] – – – Erase/write cycles ENPB Flash Flash data retention 10 – – Years – DR DC I2C Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and – 40°C< T < 85 °C, 3.10 V to 3.6 V and –40 °C < T < 85 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design A A guidance only. Table 8. DC I2C Specifications Symbol[33] Description Min Typ Max Units Notes 2.4 V V  2.9 V V Input low level – – 0.3 × V V DD ILI2C DD 3.1 V V  3.6 V DD – – 0.25 × V V 4.75 V  V  5.25 V DD DD V Input high level 0.7 × V – – V 2.4 V  V  5.25 V IHI2C DD DD V Low output voltage – – 0.4 V I = 5 mA/pin OLP OL C Capacitive load on I2C pins 0.5 1.7 5 pF Package and pin dependent. I2C Temp = 25 °C R Pull-up resistor 4 5.6 8 k – PU Notes 32.Commands involving flash writes (0x01, 0x02, 0x03) and flash read (0x04) must be executed only within the same VCC voltage range detected at POR (power on, or command 0x06) and above 2.7 V. 33.All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs. Document Number: 001-54606 Rev. *N Page 25 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 CapSense Electrical Characteristics Conditions for Max (V) Typ (V) Min (V) Result Supply Voltage The device automatically reconfigures itself to work in 2.7 V mode < 2.9 3.6 3.3 3.1 of operation. > 2.9 or < 3.10 This range is not recommended for CapSense usage. The scanning for CapSense parameters shuts down until the < 2.45 V voltage returns to over 2.45 V. 2.90 2.7 2.45 The device automatically reconfigures itself to work in 3.3 V mode > 3.10 of operation. < 2.4 V The device goes into reset. The scanning for CapSense parameters shuts down until the 5.25 5.0 4.75 < 4.73 V voltage returns to over 4.73 V. AC Electrical Specifications AC Chip-Level Specifications Table 9. 5-V and 3.3-V AC Chip-Level Specifications Parameter Description Min Typ Max Units Notes Internal low-speed oscillator Calculations during sleep operations F 15 32 64 kHz 32K1 (ILO) frequency are done based on ILO frequency. t External reset pulse width 10 – – µs – XRST Time from end of POR to CPU t – 150 – ms – POWERUP executing code SR Power supply slew rate – – 250 V/ms – POWER_UP Table 10. 2.7-V AC Chip-Level Specifications Parameter Description Min Typ Max Units Notes Calculations during sleep F ILO frequency 8 32 96 kHz operations are done based on ILO 32K1 frequency. t External reset pulse width 10 – – µs – XRST Time from end of POR to CPU t – 600 – ms – POWERUP executing code SR Power supply slew rate – – 250 V/ms – POWER_UP Document Number: 001-54606 Rev. *N Page 26 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 AC GPIO Specifications Table 11. 5-V and 3.3-V AC GPIO Specifications Parameter Description Min Max Unit Notes Rise time, strong mode, V = 3.10 V to 3.6 V and 4.75 V to 5.25 V, 10% t 15 80 ns DD Rise0 Cload = 50 pF, Port 0 to 90% Rise time, strong mode, t 15 50 ns V = 3.10 V to 3.6 V, 10% to 90% Rise1 Cload = 50 pF, Port 1 DD Fall time, strong mode, V = 3.10 V to 3.6 V and 4.75 V to 5.25 V, 10% t 10 50 ns DD Fall Cload = 50 pF, all ports to 90% Table 12. 2.7-V AC GPIO Specifications Parameter Description Min Max Unit Notes Rise time, strong mode, t 15 100 ns V = 2.4 V to 2.90 V, 10% to 90% Rise0 Cload = 50 pF, Port 0 DD Rise time, strong mode, t 15 70 ns V = 2.4 V to 2.90 V, 10% to 90% Rise1 Cload = 50 pF, Port 1 DD Fall time, strong mode, t 10 70 ns V = 2.4 V to 2.90 V, 10% to 90% Fall Cload = 50 pF DD AC I2C Specifications Table 13. AC I2C Specifications Standard Mode Fast Mode Parameter Description Units Notes Min Max Min Max Fast mode not F I2C SCL clock frequency 0 100 0 400 kbps supported for SCL V < 3.0 V. DD Hold time (repeated) START t I2C condition. After this period, the 4.0 – 0.6 – µs – HDSTA first clock pulse is generated t I2C LOW period of the SCL clock 4.7 – 1.3 – µs – LOW t I2C HIGH period of the SCL clock 4.0 – 0.6 – µs – HIGH t I2C Setup time for a repeated START 4.7 – 0.6 – µs – SUSTA condition t I2C Data hold time 0 – 0 – µs – HDDAT t I2C Data setup time 250 – 100 – ns – SUDAT t I2C Setup time for STOP condition 4.0 – 0.6 – µs – SUSTO t I2C BUS free time between a STOP 4.7 – 1.3 – µs – BUF and START condition t I2C Pulse width of spikes suppressed – – 0 50 ns – SP by the input filter Document Number: 001-54606 Rev. *N Page 27 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Figure 12. Definition of Timing for Fast/Standard Mode on the I2C Bus I2C_SDA T TSUDATI2C THDDATI2CTSUSTAI2C TSPI2C TBUFI2C HDSTAI2C I2C_SCL T T T HIGHI2C LOWI2C SUSTOI2C P S S Sr START Condition Repeated START Condition STOP Condition Document Number: 001-54606 Rev. *N Page 28 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Appendix Examples of Frequently Used I2C Commands S. No. Requirement I2C commands[34] Comment 1 Enter into setup mode W 00 A0 08 – 2 Enter into normal mode W 00 A0 07 – Load factory defaults to RAM 3 W 00 A0 02 – registers W 00 A0 08 Enter into setup mode 4 Do a software reset W 00 A0 06 Do software reset Save current configuration to 5 flash[35] W 00 A0 01 Enter into setup mode W 00 A0 08 Load factory defaults to RAM Load factory defaults to SRAM W 00 A0 02 6 registers and save as user Save the configuration to flash. Wait for time specified in W 00 A0 01 configuration CapSense Express Commands on page 17. W 00 A0 06 Do software reset Enter into setup mode W 00 A0 08 Configuring CapSense buttons Enable GP00 as CapSense W 00 06 01 7 Save the configuration to flash. Wait for time specified in button W 00 A0 01 CapSense Express Commands on page 17. W 00 A0 06 Do software reset Select CapSense button for reading scan result W 00 81 01 Read CapSense button(GP00) Set the read point to 82h 8 W 00 82 scan results Consecutive 6 reads get baseline, difference count and raw R 00 RD. RD. RD. count (all two byte each) Read CapSense button status W 00 88 Set the read pointer to 88 9 register R 00 RD Reading a byte gets status CapSense inputs Notes 34.The ‘W’ indicates the write transfer and the next byte of data represents the 7-bit I2C address. The I2C address is assumed to be ‘0’ in the above examples. Similarly ‘R’ indicates the read transfer followed by 7-bit address and data byte read operations. 35.Errata: Save to flash command fails when the sleep interval is set to 512 or 64 Hz. For more information, see “Errata” on page40. Document Number: 001-54606 Rev. *N Page 29 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Ordering Information Table 14. Key Features and Ordering Information Package Operating CapSense Ordering Code Package Type GPIOs XRES Pin Diagram Temperature Block CY8C20110-LDX2I 001-09116 16-pin QFN[36] Industrial Yes 10 Yes CY8C20110-SX2I 51-85068 16-pin SOIC Industrial Yes 10 Yes CY8C20180-LDX2I 001-09116 16-pin QFN[36] Industrial Yes 08 Yes CY8C20180-SX2I 51-85068 16-pin SOIC Industrial Yes 08 Yes CY8C20160-LDX2I 001-09116 16-pin QFN[36] Industrial Yes 06 Yes CY8C20160-SX2I 51-85068 16-pin SOIC Industrial Yes 06 Yes CY8C20140-LDX2I 001-09116 16-pin QFN[36] Industrial Yes 04 Yes CY8C20140-SX2I 51-85068 16-pin SOIC Industrial Yes 04 Yes CY8C20142-SX1I 51-85066 8-pin SOIC Industrial Yes 04 No Note For die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE). Ordering Code Definitions CY 8 C 201 XX - XX X X I Temperature Range: I = Industrial X = 2 or 1 2 = 16-pin device; 1 = 8-pin device Pb-free Package Type: XX = LD or S LD = 16-pin QFN; S = 16-pin SOIC Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Controllers Company ID: CY = Cypress Note 36.Earlier termed as COL. Document Number: 001-54606 Rev. *N Page 30 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Thermal Impedances Table 15. Thermal Impedances by Package Package Typical  [37] JA 16-pin QFN[1] 46 °C/W 16-pin SOIC 79.96 °C/W 8-pin SOIC 127.22 °C/W Solder Reflow Specifications Table 16. Solder Reflow Specifications Package Maximum Peak Temperature (T ) Maximum Time above T – 5 °C C C 16-pin QFN[1] 260 C 30 seconds 16-pin SOIC 260 C 30 seconds 8-pin SOIC 260 C 30 seconds Note 37.TJ = TA + Power × JA. Document Number: 001-54606 Rev. *N Page 31 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Package Diagrams Figure 13. 16-pin Chip On Lead (3 × 3 × 0.6 mm) LG16A/LD16A (Sawn) Package Outline, 001-09116 001-09116 *J Figure 14. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068 51-85068 *E Document Number: 001-54606 Rev. *N Page 32 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Package Diagrams (continued) Figure 15. 8-pin SOIC (150 Mils) S08.15/SZ08.15 Package Outline, 51-85066 51-85066 *H Document Number: 001-54606 Rev. *N Page 33 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Acronyms Table17 lists the acronyms that are used in this document. Table 17. Acronyms Used in this Datasheet Acronym Description Acronym Description AC alternating current LVD low voltage detect CMOS complementary metal oxide semiconductor MCU microcontroller unit DC direct current PCB printed circuit board EEPROM electrically erasable programmable read-only POR power on reset memory EMC electromagnetic compatibility PPOR precision power on reset GPIO general-purpose I/O PSoC® Programmable System-on-Chip I/O input/output PWM pulse width modulator IDAC current DAC QFN quad flat no leads ILO internal low speed oscillator RF radio frequency LCD liquid crystal display SOIC small-outline integrated circuit LDO low dropout regulator SRAM static random access memory LED light-emitting diode XRES external reset LSB least-significant bit Reference Documents Capsense® Express™ Power And Sleep Considerations - AN44209 (001-44209) Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com. Document Conventions Units of Measure Table18 lists the units of measures. Table 18. Units of Measure Symbol Unit of Measure Symbol Unit of Measure C degree Celsius mm millimeter Hz hertz ms millisecond kbps kilo bits per second mV millivolt kHz kilohertz nA nanoampere k kilohm ns nanosecond LSB least significant bit % percent µA microampere pF picofarad µF microfarad V volt µs microsecond W watt mA milliampere Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals. Document Number: 001-54606 Rev. *N Page 34 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Glossary active high 1.A logic signal having its asserted state as the logic 1 state. 2.A logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. analog-to-digital A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts (ADC) a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. Application A series of software routines that comprise an interface between a computer application and lower level services programming and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that interface (API) create software applications. asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. Bandgap A stable voltage reference design that matches the positive temperature coefficient of VT with the negative reference temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. bandwidth 1.The frequency range of a message or information processing system measured in hertz. 2.The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. bias 1.A systematic deviation of a value from a reference value. 2.The amount by which the average of a set of values departs from a reference value. 3.The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1.A functional unit that performs a single function, such as an oscillator. 2.A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. buffer 1.A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which data is written. 2.A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3.An amplifier used to lower the output impedance of a system. bus 1.A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2.A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3.One or more conductors that serve as a common connection for a group of related devices. clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler A program that translates a high level language, such as C, into machine language. Document Number: 001-54606 Rev. *N Page 35 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Glossary (continued) configuration In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. space crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. debugger A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition. digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. digital-to-analog A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC) (DAC) converter performs the reverse operation. duty cycle The relationship of a clock period high time to its low time, expressed as a percent. emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. External Reset An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop (XRES) and return to a pre-defined state. Flash An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is OFF. Flash block The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. frequency The number of cycles or events per unit of time, for a periodic function. gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). input/output (I/O) A device that introduces data into or extracts data from a system. Document Number: 001-54606 Rev. *N Page 36 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Glossary (continued) interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many routine (ISR) interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. jitter 1.A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2.The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. low-voltage A circuit that senses V and provides an interrupt to the system when V falls lower than a selected threshold. DD DD detect (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal The reference to a circuit containing both analog and digital techniques and components. modulator A device that imposes a signal on a carrier. noise 1.A disturbance that affects a signal and that may distort the information carried by the signal. 2.The random variations of one or more characteristics of any entity such as voltage, current, or data. oscillator A circuit that may be crystal controlled and is used to generate a clock frequency. parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). Phase-locked An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference loop (PLL) signal. pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. port A group of pins, usually eight. Power on reset A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of (POR) hardware reset. PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark of Cypress. Document Number: 001-54606 Rev. *N Page 37 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Glossary (continued) PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. register A storage device with a specific capacity, such as a bit or byte. reset A means of bringing a system back to a know state. See hardware reset and software reset. ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. serial 1.Pertaining to a process in which all events occur one after the other. 2.Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. SRAM An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. stop bit A signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1.A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2.A system whose operation is synchronized by a clock signal. tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. Document Number: 001-54606 Rev. *N Page 38 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Glossary (continued) V A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V. DD V A name for a power net meaning "voltage source." The most negative power supply signal. SS watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. Document Number: 001-54606 Rev. *N Page 39 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Errata CY8C20110 This section discusses the changes between the firmware revisions ×15 and ×1B in CY8C20110 devices. All shipments of samples and production parts with firmware version ×1B will encounter the following changes from the previous (×15) version of the firmware. Cypress inventory has been rotated to the ×1B firmware by WW35, and all distributor inventory will be rotated by WW42 of 2008. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number Package Type Operating Range CY8C20110 All packages Commercial / Industrial Product Status The CY8C20110 CapSense Express device has been qualified and is available in production quantities. From now on, customers are requested to use production release of CY8C20110 with x1B firmware version. CapSense Express CY8C20110 Errata Summary Table19 defines the errata applicable to CY8C20110 device. Table 19. CapSense Express CY8C20110 Errata Summary Item Issues/Changes Description Fix Status Worst case Ack timing of 140 µs for all critical registers (Input, Output, CapSense Global Reduction of I2C ACK timing response by the Parameters, CapSense Buttons/Slider 1 I2C ACK CapSense Express slave. Read-back Values). For more information on Time in Normal Operating Mode. critical registers I2C timings, refer to application note AN44208 “CapSense Express - I2C Communication Timing Analysis”. The CY8C20110 device ACK to host within 100 µs, but is not accessible for any other Reduction of I2C ACK timing response by the operation until configuration is successfully stored CapSense Express slave. into flash memory and the device is ready to 2 I2C ACK Time when executing commands to store execute the next command. For more information configuration in Flash. on I2C timings, refer to application note AN44208 “CapSense Express - I2C Communication Timing Analysis”. Averaging Filter This smoothens the raw count data, and results in better noise immunity and performance. The filter can average 2, 4, 8, or 16 samples. Addition of two on-chip filtering algorithms for im- Drop the Sample Filter 3 Data Filtering proved CapSense performance and better noise This discards any acquired CapSense sample if immunity. an I2C communication occurs after the scan process has already started. For more information on filtering, refer to application note AN48430 “CapSense Express -Noise Filtering Methods”. Four configuration registers (18h, 19h, 1Ah, 1Bh) are added to set PWM duty cycles and modes. This set of registers provides options that support 15 duty cycles on PWM output and 4 modes of The PWM output functionality has been added on PWM operations, which are defined as Normal, 4 PWM Control GPIOs to support LED brightness control. Single Pulse, Delayed Transition, and Toggle Flip-Flop. For more information on duty cycles and PWM mode settings, refer to application note AN47716 “Configuring PWM for LED Intensity Control”. Document Number: 001-54606 Rev. *N Page 40 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Table 19. CapSense Express CY8C20110 Errata Summary (continued) Item Issues/Changes Description Fix Status No fix will be provided. When using save to flash follow these steps: Save to flash command fails when the sleep 1. Write configuration data to registers with sleep 5 Save to Flash interval is set to 512 or 64 Hz. interval set to 8 or 1 Hz 2. Save the settings to flash 3. Change the sleep interval settings per design If a finger is on the sensor during power-up the No fix will be provided. Disable the Averaging False Triggering During sensor triggers and the baseline gets stuck. This 6 Filter if your design requires a finger on the sensor Power-Up only happens when the Averaging Filter is during power-up. enabled. During boot-up, CapSense Express device misinterprets an incoming byte as its own Erroneous I2C address, leading to confusion in the I2C state No fix will be provided. Do not initiate I2C 7 START condition machine. It controls the SCL and SDA line transactions on bus before the device boots up. detection in-between the I2C transfer, leading to bus communication failure. CY8C20140/142/160/180/1A0 This section describes the changes between the firmware revisions ×15 and ×1B in CapSense Express devices (CY8C20140/142/160/180/1A0). All shipments of samples and production parts with firmware version ×1B will encounter the following changes from the previous (×15) version of the firmware. Cypress inventory has been rotated to the ×1B firmware by WW35, and all distributor inventory will be rotated by WW42 of 2008. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number Package Type Operating Range CY8C20140 All packages Commercial/Industrial CY8C20142 All packages Commercial/Industrial CY8C20160 All packages Commercial/Industrial CY8C20180 All packages Commercial/Industrial CY8C201A0 All packages Commercial/Industrial Product Status The CY8C20140/142/160/180/1A0 CapSense Express devices have been qualified and are available in production quantities. From now on, customers are requested to use the production release of CapSense Express device with x1B firmware version. Document Number: 001-54606 Rev. *N Page 41 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 CapSense Express CY8C20140/142/160/180/1A0 Errata Summary Table20 defines the errata applicable to Cypress CapSense Express devices. Table 20. CapSense Express CY8C20140/142/160/180/1A0 Errata Summary Item Issues Description Fix Status Worst case Ack timing of 140 µs for all critical registers (Input, Output, CapSense Global Reduction of I2C ACK timing response by the Parameters, and CapSense Buttons and 1 I2C ACK CapSense Express slave. Slider Read-back Values). For more information on critical register I2C timings, (Time in Normal Operating Mode) refer to application note AN44208 “CapSense Express - I2C Communication Timing Analysis”. The CapSense Express device ACK to host within 100 µs but is not accessible for any other operation until the configuration is Reduction of I2C ACK timing response by the successfully stored into flash memory, and CapSense Express slave. the CapSense Express device is ready to 2 I2C ACK (Time when executing commands to store configuration execute the next command. For more in Flash) information on I2C timings to store configuration in Flash, refer to application note AN44208 “CapSense Express - I2C Communication Timing Analysis”. Averaging Filter This smoothens the raw count data, and results in better noise immunity and performance. The filter can average 2, 4, 8, or 16 samples. Addition of two on-chip filtering algorithms for improved Drop the Sample Filter 3 Data Filtering CapSense performance and better noise immunity. This discards any acquired CapSense sample if an I2C communication occurs after the scan process has already started. For more information on filtering, refer to application note AN48430 “CapSense Express-Noise Filtering Methods”. No fix will be provided. When using save to flash follow these steps: 1. Write configuration data to registers with 4 Save to Flash Save to flash command fails when the sleep interval is sleep interval set to 8 or 1 Hz set to 512 or 64 Hz. 2. Save the settings to flash 3. Change the sleep interval settings per design If a finger is on the sensor during power-up the sensor No fix will be provided. Disable the Averaging False Triggering 5 triggers and the baseline gets stuck. This only happens Filter if your design requires a finger on the During Power-Up when the Averaging Filter is enabled. sensor during power-up. During boot-up, CapSense Express device Erroneous I2C misinterprets an incoming byte as its own address, No fix will be provided. Do not initiate I2C 6 START condition leading to confusion in the I2C state machine. It controls transactions on bus before the device boots detection the SCL and SDA line in-between the I2C transfer, up. leading to bus communication failure. Document Number: 001-54606 Rev. *N Page 42 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Document History Page Document Title: CY8C20110/CY8C20180/CY8C20160/CY8C20140/CY8C20142, CapSense® Express™ Button Capacitive Controllers Document Number: 001-54606 Orig. of Submission Rev. ECN Description of Change Change Date ** 2741726 SLAN / FSU 07/21/2009 New data sheet. Added Contents. Updated Absolute Maximum Ratings (Added F32k u, t parameters POWERUP *A 2821828 SSHH / FSU 12/4/2009 and their details). Updated Electrical Specifications (Updated DC Electrical Specifications (Updated DC Flash Write Specifications (Updated Note 32))). Updated Pin Definitions (Added a Note “For information on the preferred dimensions for mounting QFN packages, see the "Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages" available at http://www.amkor.com.” below the column). *B 2892629 NJF 03/15/2010 Updated Absolute Maximum Ratings (Added T andT BAKETEMP BAKETIME parameters and their details). Updated Package Diagrams (Updated Figure1 (Changed 16-pin COL to 16-pin QFN). Updated Features (Changed the part number from CY8C21110 to CY8C20110). *C 3002214 SLAN 07/29/2010 Added Acronyms and Units of Measure. Minor edits across the document. Updated Pin Definitions (Added Note 3 and referred the same Note in all GP1[1] and GP1[2] pins). Updated Pin Definitions (Added Note 6 and referred the same Note in all GP1[1] and GP1[2] pins). Updated Pin Definitions (Added Note 7 and referred the same Note in all GP1[1] and GP1[2] pins). *D 3042142 ARVM 09/30/2010 Updated Absolute Maximum Ratings (Removed F32k u, t param- POWERUP eters and their details). Updated Electrical Specifications (Updated AC Electrical Specifications (Added AC Chip-Level Specifications section)). Updated Typical Circuits (Updated Figure4 (Replaced with updated one)). Updated in new template. Updated Electrical Specifications (Updated DC Electrical Specifications (Updated DC GPIO Specifications (Removed sub-section “2.7-V DC Spec for I2C Line with 1.8 V External Pull-up”), added DC I2C Specifications)), updated AC Electrical Specifications (Updated AC I2C Specifications *E 3085081 NJF 11/12/2010 (Updated Figure12 (No specific changed were made to I2C Timing Diagram. Updated for clearer understanding.)))). Updated Solder Reflow Specifications (Updated Table16). Added Reference Documents and Glossary. Updated in new template. Updated Layout Guidelines and Best Practices (Updated Table2 (Removed “Overlay thickness-buttons” category), added the following statement after Table2 – “The Recommended maximum overlay thickness is 5 mm (with external CS / 2 mm (without external CS ). For more details refer to the section Int) Int *F 3276234 ARVM 06/07/2011 “The Integrating Capacitor (Cint)” in AN53490. Note Some device packages does not have CS pin and external capacitor Int cannot be connected.”). Updated CapSense Constraints (Removed the parameter “Overlay thickness”). Updated Solder Reflow Specifications (Updated Table16). Document Number: 001-54606 Rev. *N Page 43 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Document History Page (continued) Document Title: CY8C20110/CY8C20180/CY8C20160/CY8C20140/CY8C20142, CapSense® Express™ Button Capacitive Controllers Document Number: 001-54606 Orig. of Submission Rev. ECN Description of Change Change Date Updated Pin Definitions (Updated description of XRES pin). Updated Pin Definitions (Updated description of XRES pin). Updated Typical Circuits (Updated Figure6 (Added Note 9 and referred the *G 3631370 VAIR / SLAN 05/31/2012 same Note in Figure6)). Updated Package Diagrams (spec 001-09116 (Changed revision from *E to *F), spec 51-85068 (Changed revision from *C to *D)). Updated in new template. Updated Device Operation Modes (Updated Periodic Sleep Mode (Updated description)). *H 3837914 SLAN 12/11/2012 Updated Package Diagrams (spec 001-09116 (Changed revision from *F to *G), spec 51-85068 (Changed revision from *D to *E)). Updated Package Diagrams: spec 001-09116 – Changed revision from *G to *H. *I 3992042 SLAN 05/06/2013 spec 51-85066 – Changed revision from *E to *F. Added Errata. Added CY8C20140/142/160/180/1A0. Added Errata Footnotes. *J 4033835 DCHE 06/19/2013 Updated in new template. Updated duration for which the device is not accessible after ACK timing for *K 4489897 PRIA 09/01/2014 the "Set Setup mode of operation" command." Added notes 17, 27, and 29. Updated I2C Clock Stretching. Updated hyperlinks in the document. Added reference to Getting Started with CapSense Design Guide in Layout *L 4873309 PRIA 08/25/2015 Guidelines and Best Practices. Updated Errata: Added Errata item 7 in Table19 and Errata item 6 in Table20. Updated Figure15 in Package Diagrams (spec 51-85066 *F to 51-85066 *G). Added “Not recommended for new designs” watermark. *M 5277446 PRIA 05/19/2016 Updated the template. *N 5733914 AESATMP7 05/12/2017 Updated Cypress Logo and Copyright. Document Number: 001-54606 Rev. *N Page 44 of 45

CY8C20110, CY8C20180, CY8C20160 CY8C20140, CY8C20142 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC®Solutions ARM® Cortex® Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP| PSoC 6 Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Forums | Projects | Video | Blogs | Training | Components Interface cypress.com/interface Technical Support Lighting & Power Control cypress.com/powerpsoc cypress.com/support Memory cypress.com/memory PSoC cypress.com/psoc Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless/RF cypress.com/wireless © Cypress Semiconductor Corporation, 2009-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-54606 Rev. *N Revised May 11, 2017 Page 45 of 45

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: C ypress Semiconductor: CY8C20160-LDX2I CY8C20140-LDX2I CY8C20110-SX2I CY8C20160-SX2I CY8C20140-SX2I CY8C20180-SX2I CY8C20180-LDX2I CY8C20142-SX1I CY8C20110-LDX2I CY7C69356-48LTXC