CY7C68003 MoBL-USB™ TX2UL USB 2.0 ULPI Transceiver MoBL-USB™ TX2UL USB 2.0 ULPI Transceiver Features ■UART pass through mode ■ESD compliance: The Cypress MoBL-USB™ TX2UL is a low voltage high speed (HS) USB 2.0 UTMI+ Low Pin Interface (ULPI) Transceiver. The ❐JESD22-A114D 8 kV Contact human body model (HBM) for DP, DM, and V pins TX2UL is specifically designed for mobile handset applications SS by offering tiny package options and low power consumption. ❐IEC61000 - 4-2 8 kV contact discharge ❐IEC61000 - 4-2 15 kV air discharge ■USB 2.0 Full Speed and High Speed compliant transceiver ■Support for industrial temperature range: (-40°C to 85°C) ■Multi range (1.8V to 3.3 V) I/O voltages ■Low power consumption for mobile applications: ■Fully compliant ULPI link interface ❐5 µA nominal sleep mode ■8-bit SDR ULPI data path ❐30 mA nominal active HS transfer ■UTMI+ level 0 support ■Small package for mobile applications: ❐2.14 x 1.76 mm 20-pin WLCSP 0.4 mm pitch ■Support USB device mode only ❐4 x 4 mm 24-pin QFN ■Integrated oscillator Applications ■Integrated phase locked loop (PLL) – 13, 19.2, 24, or 26 MHz reference ■Mobile phones ■Integrated USB pull-up and termination resistors ■PDAs ■3.0 V to 5.775V VBATT input ■Portable media players (PMPs) ■Chip select pin ■DTV applications ■Single ended device RESET input ■Portable GPS units TX2UL Block Diagram TX2UL ULPI Block CLOCK DATA[7:0] I/O Operational Control/ mode Tx/Rx DP DIR Data tracking Core USB Logic interrupt UTMI+ STP FS/HS Registers Level0 PHY NXT Block DM ULPI Wrapper RXD TXD Global Control Block RESET_N Reset / Clock / Power / 3.3 V CS_N Misc. Control Regulator (3.0 – VBATT Block 5.775 V) VCC POR (1.8 V) 1.8 V Bandgap 13/19.2/ XI PLL XOSC 24/26 MHz XO CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-15775 Rev. *O Revised May 30, 2017

CY7C68003 Contents Functional Overview ........................................................3 Configuration Mode ........................................................16 UTMI+ Low Pin Interface (ULPI) .................................3 Configuration Mode in 20-Pin CSP package .............16 Oscillator (OSC) ..........................................................3 Configuration Mode in 24-Pin QFN package .............16 Phase Locked Loop (PLL) ...........................................3 Power On Reset (POR) .............................................16 Power On Reset (POR) ...............................................3 Register .....................................................................16 Reset (RESET_N) .......................................................3 Register Map .............................................................16 DP and DM pins ..........................................................3 Immediate Register Set .............................................17 Chip Select (CS_N) .....................................................3 Function Control Register ..........................................17 USB2 Transceiver Macrocell Interface (UTMI+) ..........3 Interface Control Register .........................................18 Global Control .............................................................3 Debug Register .........................................................18 Full Speed Scratch Register ........................................................18 and High Speed USB Transceivers (FS/HS) ......................3 Carkit Control Register ..............................................18 USB Pull up and Intr Detect, Drive Strength Termination Resistors (Pull up/TERM) ...............................3 and Slew Rate Configuration Register .............................19 UART Pass Through Mode .........................................3 USB Interface Control Register .................................19 Clocking .......................................................................4 Absolute Maximum Ratings ..........................................20 Power Domains ...........................................................4 Operating Conditions .....................................................20 Operation Modes .........................................................5 DC Characteristics .........................................................21 VID and PID ................................................................6 AC Characteristics .........................................................21 Pinouts ..............................................................................7 Ordering Information ......................................................24 Synchronous Operation Modes ......................................9 Ordering Code Definitions .........................................24 ULPI Transmit Command Byte (TX CMD) ..................9 Package Diagrams ..........................................................25 ULPI Receive Command Byte (RX CMD) ...................9 Acronyms ........................................................................27 USB Data Transmit (NOPID) .....................................10 Document Conventions .................................................27 USB Data Transmit (PID) ..........................................11 Document History Page .................................................28 USB Packet Receive .................................................11 Sales, Solutions, and Legal Information ......................30 Immediate Register Read and Write .........................12 Worldwide Sales and Design Support .......................30 Immediate Register Read and Write Products ....................................................................30 Aborted by USB Receive ..................................................13 PSoC® Solutions ......................................................30 Back to Back Immediate Register Read and Write Cypress Developer Community .................................30 and USB Receive .............................................................14 Technical Support .....................................................30 Document Number: 001-15775 Rev. *O Page 2 of 30

CY7C68003 Functional Overview USB2 Transceiver Macrocell Interface (UTMI+) UTMI+ Low Pin Interface (ULPI) This block conforms to the UTMI+ Level 0 standard. It performs all the UTMI to USB translation. This block conforms to the ULPI specification. It supports the 8-bit wide SDR data path. The primary I/Os of this block support Global Control multi-range LVCMOS signaling from 1.8V to 3.3V (±5%). The This block is the digital control logic that ties the blocks of the level used is automatically selected by the voltage applied to device together. Its functions include pull up control, over current V and is set at any voltage between 1.8V and 3.3V. CCIO protect control, and more. Oscillator (OSC) Full Speed and High Speed USB Transceivers (FS/HS) This block meets the requirements of both the on-chip PLL and the USB-IF requirements for clock parameters. It is a The FS and HS Transceivers comply fully with the USB 2.0 fundamental mode parallel resonant oscillator with a maximum specifications. ESR of 60Ω. It supports the following: USB Pull up and Intr Detect, Termination Resistors ■Integrated Crystal Oscillator – 13, 19.2, 24, or 26 MHz crystal (Pull up/TERM) ■13, 19.2, 24, or 26 MHz LVCMOS single ended input clock on XI These blocks contain the USB pull-up and termination resistors Phase Locked Loop (PLL) as specified by the USB 2.0 specification. The PLL meets all clock stability requirements imposed by this UART Pass Through Mode device and the USB standard. It supports all requirements to make the device compliant to the USB 2.0 specifications. It also TX2UL supports Carkit UART Pass Through Mode. When the Carkit Mode bit in the Interface Control register is set, it enables has a fractional multiplier that enables it to supply the correct the Link to communicate through the DP/DM to a remote system frequency to the device when it is presented with a 13, 19.2, 24, or 26 MHz reference clock. using UART signaling. By default, the clock is powered down when the TX2UL enters Carkit Mode. Entering and exiting the Power On Reset (POR) Carkit Mode is identical to the Serial Mode. Table1, Table2, and Figure1 show the UART Signal Mapping between the DP/DM This block provides a POR signal (internal) based on the input and DATA[1:0] at ULPI interface. supply. An internal POR is generated when V input rises CC above VPOR(trip). Table 1. UART Signal Mapping at ULPI Interface Reset (RESET_N) Signal Maps to Direction Description The three major functions of RESET_N pin are as follows: txd DATA[0] IN UART TXD signal routed to DM pin ■Reset TX2UL rxd DATA[1] OUT UART RXD signal ■Place TX2UL into Sleep Mode routed to DP pin ■Place TX2UL into Configuration Mode Reserved DATA[7:2] - Reserved When the RESET_N pin is asserted (low) for tSTATE (tSTATE is specified in Table 21 on page 21), the TX2UL enters either Sleep Table 2. UART Signal Mapping at USB Interface Mode or Configuration Mode depending on the CS_N state. Signal Maps to Direction Description When RESET_N is asserted while CS_N is asserted, TX2UL enters Sleep Mode. When RESET_N is asserted for tSTATE TXD DM OUT UART TXD signal while CS_N is deasserted, TX2UL enters Configuration Mode. In RXD DP INT UART RXD signal these modes, all the pins in the ULPI interface are tristated. If the RESET_N pin is not used, it must be pulled high. For information about different modes of configuration, see Table 5 on page 5. Figure 1. UART Signal Mapping in Pass Through Mode DP and DM pins ULPI USB The DP and DM pins are the differential pins for the USB. They INTERFACE INTERFACE must be connected to the corresponding DP and DM pins of the TX2UL USB receptacle. txd DATA[0] DM TXD Chip Select (CS_N) rxd RXD DATA[1] DP This signal pin is available only in 24-pin QFN package. The two major functions of CS_N are as follows: ■Tristate the ULPI bus output pins ■Associate with RESET_N to place TX2UL in the Sleep mode When the CS_N pin is deasserted (high), all the pins in the ULPI interface are tristated. Document Number: 001-15775 Rev. *O Page 3 of 30

CY7C68003 Clocking TX2UL supports external crystal and clock inputs at the 13, 19.2, The selection between input clock source and frequency on the 24, and 26 MHz frequencies. The internal PLL applies the proper XI pin is determined by the Chip Configuration register loaded clock multiply option depending on the input frequency. For appli- through the RESET_N during Configuration Mode. The external cations that use an external clock source to drive XI, the XO pin clock source requirements are shown in Figure 3 on page 5. (in the 24-pin QFN package) is left floating. TX2UL has an on-chip oscillator circuit that uses an external 13, 19.2, 24, or Figure 2. Crystal Configuration 26MHz (±100 ppm) crystal with the following characteristics: ■Parallel resonant TX2UL ■Fundamental mode XI ■750 µW drive level XTAL ■12 pF (5 percent tolerance) load capacitors PLL XO ■150 ppm 12 pf 12 pf TX2UL operates on one of two primary clock sources: ■LVCMOS square wave clock input driven on the XI pin * 12 pF capacitor values assumes a trace capacitance of 3 pF per side on a four layer FR4 PCA ■Crystal generated sine wave clock on the XI and XO pins Table 3. External Clock Requirements Specification Parameter Description Unit Min Max Vn Supply voltage noise at frequencies < 50 MHz – 20 mV p-p PN_100 Input phase noise at 100 Hz – 75 dBc/Hz PN_1k Input phase noise at 1 kHz offset – 104 dBc/Hz PN_10k Input phase noise at 10 kHz offset – 120 dBc/Hz PN_100k Input phase noise at 100 kHz offset – 128 dBc/Hz PN_1M Input phase noise at 1 MHz offset – 130 dBc/Hz Duty cycle 30 70 % Maximum frequency deviation – 150 ppm Power Domains V BATT The TX2UL has three power supply domains: This is the battery input supply that powers the 3.3V regulator block. It can range anywhere from 3.0 to 5.775V during actual ■VCC operation. ■V IO Voltage Regulator ■VBATT The internal 3.3V regulator block regulates the VBATT supply to TX2UL has two grounds: the internal 3.3V supply for the USBIO and XOSC blocks. If the supply voltage at VBATT is below 3.3V, the regulator block ■VSS switches the VBATT supply directly for the USBIO and XOSC ■V blocks. SSBATT V Power Supply Sequence CC This is the core 1.8V power supply for the TX2UL. It can range TX2UL does not require a power supply sequence. All power anywhere from 1.7V to 1.9V during actual operation. supplies are independently sequenced without damaging the part. All supplies are up and stable for the device to function V properly. The analog block contains circuitry that senses the IO power supply to determine when all supplies are valid. This is the 1.8V to 3.3V multi range supply to the I/O ring. It can range anywhere from 1.7V to 3.6V during actual operation. Document Number: 001-15775 Rev. *O Page 4 of 30

CY7C68003 Operation Modes ULPI low power mode to Sleep mode, TX2UL changes to normal operation mode first, and then to Sleep mode. The Mode Change There are six operation modes available in TX2UL. They are: State diagram in Figure3 shows the mode change path of ■Normal operation mode TX2UL. The entries of the six operations modes (20-pin CSP package has five operation modes) are listed in Table4 and ■Configuration mode Table5. There are three mode change transactions that require ■ULPI low power mode the RESET_N assert or deassert with tSTATE (see Table 21 on page 21 for tSTATE). The three mode change transactions are: ■Sleep mode ■Change from normal operation mode to configuration mode; ■Carkit UART pass through mode RESET_N is required to assert with tSTATE ■Tristate ULPI interface output mode (only available in 24-pin ■Change from configuration mode to normal operation mode; QFN package) RESET_N is required to de-assert with tSTATE When changing the operation modes, if the current and changing ■Change from normal operation mode to sleep mode; RESET_N modes are not the normal operation Mode, TX2UL first changes is required to assert with tSTATE to the normal operation mode. For example, to change from Figure 3.Mode Change State Diagram Carkit UART Pass Through Tristate ULPI Interface Output Sleep Mode Mode Mode (available in 24-pin QFN package only) Normal Operation Mode Configuration Mode ULPI Low Power Mode Table 4. TX2UL 20-Pin CPS Package Operation Modes Table 5. TX2UL 24-Pin QFN Package Operation Modes RESET_N Mode CS_N RESET_N Mode 0 (Low) Sleep mode 0 (Low) 0 (Low) Sleep mode 1 (High) Normal operation mode 0 (Low) 1 (High) Normal operation mode 1 (High) Enter into ULPI low power mode by setting 0 (Low) 1 (High) Enter into ULPI low power mode by SuspendM register bit (in Function Control setting SuspendM register bit (in Register) to 0 during the normal operation mode. Function Control Register) to 0 during the normal operation mode. 1 (High) Enter into Carkit UART pass through mode by setting Carkit mode register bit (in Interface Control 0 (Low) 1 (High) Enter into Carkit UART pass Register) to 1 during the normal operation mode. through mode by setting Carkit Mode register bit (in Interface 0 (Low) Enter into Configuration Mode Control Register) to 1 during the when normal operation mode. Power On (VCC On) 1 (High) 0 (Low) Configuration mode 1 (High) 1 (High) Tristate ULPI interface output pins Document Number: 001-15775 Rev. *O Page 5 of 30

CY7C68003 The operation and configuration modes are described in the Table 21 on page 21 for tSTATE requirement) while CS_N is low, sections Operation Modes on page 5 and Configuration Mode on TX2UL enters Sleep Mode. VCC must remain supplied (ON) page 16 respectively. The ULPI low power mode and Sleep during the sleep mode. This mode powers down all internal mode are described in the following sections. circuitry except the RESET_N pin and the chip_config register. The ULPI interface bus is tristated. ULPI Low Power Mode During the Sleep Mode ensure that: In this mode, the link optionally places the TX2UL in low power mode when the USB is suspended. TX2UL powers down all the ■The ULPI interface I/Os are either floating or driven high by the circuitry except for the interface pins and full speed receiver. To link enter low power mode, the link must set SuspendM in the ■DP and DM are either floating or pull to 0V Function Control register to 0b. The TX2UL clock is stopped for a minimum of five cycles after TX2UL accepts the register write. ■Deassert RESET_N to exit the Sleep Mode To exit low power mode, the link signals TX2UL to exit the mode by asynchronously asserting a signal, STP. The TX2UL wakes up its internal circuitry and when it meets the ULPI timing require- ments, it deasserts DIR. The SuspendM register is set to 1b. Sleep Mode Sleep mode is entered by asserting RESET_N during the Normal Operation Mode. When RESET_N is driven low for tSTATE (see VID and PID The VID and PID are hard coded into Product ID and Vendor ID registers (read only) as shown in Table6. Table 6. Immediate Register Values for VID and PID Address (6 bits) Field Name Size (bit) Value Rd Wr Set Clr Vendor ID (VID) Low 8 00h - - - B4h Vendor ID (VID) High 8 01h - - - 04h Product ID (PID) Low 8 02h - - - 03h Product ID (PID) High 8 03h - - - 68h Document Number: 001-15775 Rev. *O Page 6 of 30

CY7C68003 Pinouts TX2UL is available in 20-ball WLCSP and 24-pin QFN package. The pin assignment is shown in Figure4 and Figure5 Figure 4.Pin Assignment - TX2UL 20-Ball WLCSP (Top View) 1 2 3 4 5 A A1 A2 A3 A4 A5 VCC XI DP DM VBATT B NBX1T RESBE2T_N VBS3S DABT4A[4] VBC5C C C1 C2 C3 C4 C5 DIR STP DATA[6] DATA[2] DATA[0] D D1 D2 D3 D4 D5 CLOCK DATA[7] DATA[5] DATA[3] DATA[1] Table 7. Pin Definitions - TX2UL 20-Ball WLCSP Name Ball No. Type Voltage Description ULPI Link Interface DATA[0] C5 I/O 1.8V ULPI data to/from link DATA[1] D5 I/O 1.8V ULPI data to/from link DATA[2] C4 I/O 1.8V ULPI data to/from link DATA[3] D4 I/O 1.8V ULPI data to/from link DATA[4] B4 I/O 1.8V ULPI data to/from link DATA[5] D3 I/O 1.8V ULPI data to/from link DATA[6] C3 I/O 1.8V ULPI data to/from link DATA[7] D2 I/O 1.8V ULPI data to/from link CLOCK D1 O 1.8V ULPI clock NXT B1 O 1.8V ULPI next signal STP C2 I 1.8V ULPI stop signal DIR C1 O 1.8V ULPI direction USB DP A3 I/O USB USB D-plus signal DM A4 I/O USB USB D-minus signal Miscellaneous RESET_N B2 I 1.8V Global reset. When RESET_N is asserted during the VCC power on, TX2UL enters configuration mode. During normal operation mode, asserting RESET_N resets the TX2UL and enter into the power saving mode. XI A2 I 1.8V LVCMOS single ended clock of frequency 13, 19.2, 24, or 26 MHz POWER and GROUND VCC B5, A1 Power 1.8V Low voltage supply for the digital core and I/O VBATT A5 Power 3.0 - 5.775V High voltage supply for USB VSS B3 GND 0V Common ground Document Number: 001-15775 Rev. *O Page 7 of 30

CY7C68003 Figure 5.Pin Assignment - TX2UL 24-Pin QFN (Top View) T VBAT DM DP XI XO VCC 24 23 22 21 20 19 VSSBATT 1 18 RESET_N VSS (GND) NC 2 Exposed die pad 17 NXT VCC 3 16 STP TX2UL DATA[0] 4 15 DIR DATA[1] 5 14 CLOCK DATA[2] 6 13 DATA[7] 7 8 9 10 11 12 S_N A[3] A[4] VIO A[5] A[6] C AT AT AT AT D D D D Table 8. Pin Definitions - TX2UL 24-Pin QFN Name Pin No. Type Voltage Description ULPI Link Interface DATA[0] 4 I/O 1.8 - 3.3V ULPI data to/from link DATA[1] 5 I/O 1.8 - 3.3V ULPI data to/from link DATA[2] 6 I/O 1.8 - 3.3V ULPI data to/from link DATA[3] 8 I/O 1.8 - 3.3V ULPI data to/from link DATA[4] 9 I/O 1.8 - 3.3V ULPI data to/from link DATA[5] 11 I/O 1.8 - 3.3V ULPI data to/from link DATA[6] 12 I/O 1.8 - 3.3V ULPI data to/from link DATA[7] 13 I/O 1.8 - 3.3V ULPI data to/from link CLOCK 14 O 1.8 - 3.3V ULPI clock NXT 17 O 1.8 - 3.3V ULPI next signal STP 16 I 1.8 - 3.3V ULPI stop signal DIR 15 O 1.8 - 3.3V ULPI direction USB DP 22 I/O USB USB D-plus signal DM 23 I/O USB USB D-minus signal Misc CS_N 7 I 1.8 - 3.3V When CS_N is de-asserted, all pins at ULPI interface are tristated RESET_N 18 I 1.8 - 3.3V Device chip global reset. When RESET_N is asserted, TX2UL is in reset and enters into the power saving mode. XI 21 I 1.8V Crystal or LVCMOS single ended clock of frequency 13, 19.2, 24, or 26 MHz XO 20 O 1.8 - 3.3V Crystal NC 2 - - No connect POWER and GROUND VCC 3, 19 Power 1.8V Low voltage supply for the digital core VIO 10 Power 1.8 - 3.3V Power for multi-range I/Os VBATT 24 Power 3.0 - 5.775V High voltage supply for USB VSSBATT 1 GND 0 USB ground VSS Die Paddle GND 0 Digital ground (core and I/O) Document Number: 001-15775 Rev. *O Page 8 of 30

CY7C68003 Synchronous Operation Modes This section describes the synchronous mode of TX2UL ULPI interface protocol. ULPI Transmit Command Byte (TX CMD) The Link initiates transfers to TX2UL by sending the Transmit Command Byte as shown in Table9. TX CMD byte consists of a 2-bit command code and a 6-bit payload. Table 9. Transmit Command (TX CMD) Byte Format Byte Name Command Code Data (7:6) Command Payload Data (5:0) Command Description Special 00b 000000b (NOOP) No operation. 00h is the idle value of the data bus. The Link drives NOOP by default. XXXXXXb (RSVD) Reserved command space. Values other than those mentioned give undefined behavior. Transmit 01b 000000b (NOPID) Transmit USB data that does not have a PID, such as chirp and resume signalling. The TX2UL starts transmitting on the USB beginning with the next byte. 00XXXXb (PID) Transmit USB packet. data (3:0) indicates USB packet identifier PID (3:0) XXXXXXb (RSVD) Reserved Command space. Values other than those mentioned give undefined behavior. RegWrite 10b 101111b (EXTW) Extended register write command. 8-bit address available in the next cycle. XXXXXXb (REGW) Register write command with 6-bit immediate address. RegRead 11b 101111b (EXTR) Extended register read command. 8-bit address available in the next cycle. XXXXXXb (REGR) Register read command with 6-bit immediate address. ULPI Receive Command Byte (RX CMD) The Receive Command Byte, as shown in Table10, is sent by TX2UL to update the link with LineState and USB receive information. The USB receive information includes LineState, RxActive, and RxError. After a USB transmit, TX2UL sends RX CMD with LineState indicating EOP to the link. For High Speed, EOP is the squelch to squelch transition on LineState. Figure 7 on page 10 shows how TX2UL sends RX CMD information to the link. The first packet shows a single RX CMD. If back to back changes are detected, TX2UL keeps DIR asserted and sends back to back RX CMDs as shown in the second packet. Table 10. Receive Command (RX CMD) Byte Format Data Name Description and Value 1:0 LineState ULPI LineState signals. DATA[0] = LineState (0) DATA[1] = LineState (1) 3:2 Reserved 5:4 RxEvent Encoded UTMI event signals Value RxActive RxError 00 0 0 01 1 0 11 1 1 10 X X 7:6 Reserved Document Number: 001-15775 Rev. *O Page 9 of 30

CY7C68003 Figure 6.Sending RX CMD CLOCK DATA[7:0] Turn around RX CMD Turn around Turn around RX CMD RX CMD Turn around DIR STP NXT USB Data Transmit (NOPID) In this mode, the Link transmits data on the USB without a Packet Identifier (PID) by sending a TX CMD byte of the NOPID type. TX2UL asserts NXT (see Figure 8 on page 11) in the first cycle of TX CMD and deasserts NXT when it detects STP to be high. Because this command does not contain PID data, TX2UL waits for the next data byte before beginning transmission on the USB. When the last byte is transferred by the TX2UL, the link asserts STP for one cycle and drives data to 00h if no transmit errors occur. The link does not assert STP before the first byte is transferred by the TX2UL. Figure 7.USB Data Transmit (NOPID) CLOCK DATA[7:0] TX CMD (NOPID) D0 D1 D2 DIR STP NXT Document Number: 001-15775 Rev. *O Page 10 of 30

CY7C68003 USB Data Transmit (PID) In this mode, the link transmits data on the USB with a PID. The link first drives a TX CMD byte as illustrated in Figure 9 on page 11 to transmit a USB packet. The link sets the Command Code to 01b (Transmit) and places the USB Packet Identifier (PID) on DATA[3:0] (see Table 9 on page 9). TX2UL throttles the data using NXT such that the link provides the next byte in the cycle after NXT is detected as high. Figure 8.USB Data Transmit (PID) CLOCK DATA[7:0] TX CMD (PID) D1 D2 D3 DIR STP NXT USB Packet Receive As shown in Figure 10 on page 12, when TX2UL receives the USB data it gains ownership of the data bus by asserting DIR. The DIR is previously either high or low. If DIR is low (see Figure9), TX2UL asserts both DIR and NXT so that the link knows immediately that this is a USB receive packet. If DIR is high (see Figure 10 on page 12), TX2UL deasserts NXT and drives an RX CMD with the RxEvent field set to the RxActive state. The TX2UL starts driving data in the following cycle or outputs RX CMD until USB data is available. Valid USB packet data is presented to the link by asserting NXT and placing a byte on the bus. When NXT is low, TX2UL drives the RX CMD byte. All RX CMD changes during the USB packet receive are signaled when NXT is low. If NXT is never low during the packet receive, all RX CMD changes are replaced with a single RX CMD update. This update is sent at the end of the USB packet receive, when the ULPI bus is available. The RX CMD update always conveys the current RX CMD values and not the previous one. Figure 9.USB Receive While DIR is Previously Low CLOCK DATA[7:0] Turn around RX CMD PID D1 RX CMD D2 D3 Turn around DIR STP NXT Document Number: 001-15775 Rev. *O Page 11 of 30

CY7C68003 Figure 10.USB Receive While DIR is Previously High CLOCK RX CMD DATA[7:0] Previous RX CMD PID D1 RX CMD D2 D3 Turn around (RxActive) DIR STP NXT Immediate Register Read and Write An immediate register is accessed by sending the TX CMD byte first (see Figure11 and Figure 12 on page 13). This byte is sent as a regread or regwrite command, depending on the intended operation. For a register write (see Figure11), the link first sends a register write TX CMD byte and waits for NXT to assert. After NXT asserts, the link sends the register write data and waits for NXT to assert again. After the second assertion is detected, the link asserts STP in the following cycle to complete the operation. The TX2UL detects this STP assertion before it can accept another transmit command. If the TX2UL aborts rewrite by asserting DIR, the link repeats the entire process again when the bus is idle. For a register read (see Figure 12 on page 13), the link sends a register read command and waits for NXT to assert. In the cycle after NXT asserts, the TX2UL asserts DIR to gain control of the data bus. In the cycle, after DIR asserts the TX2UL returns the register read data. The TX2UL does not assert NXT when DIR is asserted during the register read operation, even during the cycle when the register read data is returned. If the TX2UL aborts the regread by asserting DIR earlier than shown in Figure 12 on page 13, the link retries the regread when the bus is idle. Figure 11.Register Write CLOCK DATA[7:0] TX CMD Data (RegWrite) DIR STP NXT Document Number: 001-15775 Rev. *O Page 12 of 30

CY7C68003 Figure 12.Register Read CLOCK TX CMD DATA[7:0] Turn around Data Turn around (RegRead) DIR STP NXT Immediate Register Read and Write Aborted by USB Receive A register read is the only instance where ULPI does not use NXT to acquire data. The NXT signal is asserted only during USB receive to distinguish this type of receive from other types of data transfers. Register read and write operations are aborted when the TX2UL sends a RX CMD, except during the cycle where register read data is returned to the link. TX2UL asserts both DIR and NXT whenever a register read or write is aborted by a USB receive during the initial transmit command byte or in the same cycle that the register read data returned to the link. Figure 13.Register Read or Write Aborted by USB Receive During TX CMD Byte RegRead or RegWrite USB Receive CLOCK TX CMD DATA[7:0] Turn around RX CMD PID D1 D2 D3 (Reg) DIR STP NXT Document Number: 001-15775 Rev. *O Page 13 of 30

CY7C68003 Back to Back Immediate Register Read and Write and USB Receive When a USB receive occurs in the same cycle that the register read data is returned to the link, the TX2UL first returns the register read data, not a RX CMD byte (see Figure14). When a USB receive occurs in the cycle immediately after a register read completes, the TX2UL places the USB receive data back-to-back with the register read (see Figure15). The link accepts back-to-back packets where DIR does not deassert between packets. If DIR asserts during the same cycle that STP is asserted at the end of a register write, then the TX2UL considers the register write to have successfully executed (see Figure 16 on page 15). When a USB receive starts in the cycle after the register read data is returned to the link, it results in two cycles of bus turnaround when DIR deasserts for a single cycle (see Figure 17 on page 15). Figure 14.USB Receive in Same Cycle as Register Read Data. USB Receive is Delayed RegRead USB Receive CLOCK TX CMD RX CMD DATA[7:0] Turn around Reg Data PID D1 D2 (RegReg) (RxActive) DIR STP NXT Figure 15.Register Read Followed Immediately by a USB Receive RegRead USB Receive CLOCK TX CMD RX CMD DATA[7:0] (RegReg) Turn around Reg Data (RxActive) PID D1 D2 DIR STP NXT Document Number: 001-15775 Rev. *O Page 14 of 30

CY7C68003 Figure 16.Register Write Followed Immediately by a USB Receive During STP Assertion RegWrite USB Receive CLOCK TX CMD RX CMD DATA[7:0] Data Turn around PID D1 D2 (RegReg) (RxActive) DIR STP NXT Figure 17.Register Read Followed by a USB Receive RegRead USB Receive CLOCK TX CMD DATA[7:0] (RegReg) Turn around Reg Data Turn around Turn around PID D1 DIR STP NXT Document Number: 001-15775 Rev. *O Page 15 of 30

CY7C68003 Configuration Mode Table11. The TX2UL is defaulted to 26 MHz with single end clock input (to XI). TX2UL is configured in the input clock type and frequency for the XI and XO in Configuration Mode. The 20-pin CSP package and Table 11. TX2UL Configuration Options the 24-pin QFN package have different procedures to enter Number of Pulses at configuration mode. RESET_N Pin during Configuration Description Configuration Mode in 20-Pin CSP package Configuration Mode To enter configuration mode, keep the RESET_N low during V 0 pulses 26 MHz clock input on XI (default) CC Power On for tSTATE (see Figure 19 on page 22 for the timing 1 pulses 19.2 MHz clock input on XI diagraming and Table 21 on page 21 for the tSTATE timing 2 pulses 24.0 MHz clock input on XI requirement). When TX2UL enters configuration mode, the peripheral controller (link device) generates the pulses (falling 3 pulses 13.0 MHz clock input on XI edge) at the RESET_N pin to configure TX2UL. TX2UL 4 pulses 26 MHz crystal on XI/XO configures its internal oscillator base on number of received pulses at the RESET_N pin. When the configuration is 5 pulses 19.2 MHz crystal on XI/XO completed, deassert RESET_N (high) for tSTATE to exit the 6 pulses 24.0 MHz crystal on XI/XO Configuration. If the TX2UL needs to enter the Configuration 7 pulses 13.0 MHz crystal on XI/XO Mode again, it must go through the following power cycle: V Off ℜ→ RESET_N Low ℜ→ V On. CC CC Power On Reset (POR) Configuration Mode in 24-Pin QFN package TX2UL has an internal power on reset (POR) block that provides To enter configuration mode keep the RESET_N pin pulled low power on reset and power management control functionality. for tSTATE (see Figure 20 on page 22 for the timing diagraming This POR function complies with all the parameters required by and Table 21 on page 21 for the tSTATE timing requirement) the ULPI specification. while deasserting CS_N (high). When TX2UL enters configu- ration mode, the peripheral controller (link device) generates the Register pulses (falling edge) at the RESET_N pin to configure TX2UL. TX2UL provides an immediate register set that is defined by the TX2UL configures its internal oscillator base on number of ULPI specification for control and configuration functions. received pulses at the RESET_N pin. When the configuration is completed, assert the CS_N (low) for tSTATE (see Figure 21 on Register Map page 21 for the timing) to exit the configuration mode. Figure 19 on page 22 shows the timing diagram of entering and exiting The ULPI specifications define an immediate register set with a configuration mode. The configuration options are listed in 6-bit address that forms a part of the transmit command byte,as shown in shown in Table12. Table 12. Register Map Field Name Size (bits) Address (6bits) Rd Wr Set Clr Immediate Register Set Vendor ID Low 8 00h - - - Vendor ID High 8 01h - - - Product ID Low 8 02h - - - Product ID High 8 03h - - - Function Control 8 04-06h 04h 05h 06h Interface Control 8 07-09h 07h 08h 09h Debug 8 15h - - - Scratch Register 8 16-18h 16h 17h 18h Carkit Control (Optional) 8 19-1Bh 19h 1Ah 1Bh Vendor Specific Register Set Drive Strength and Slew Rate 8 31h 31h - - USB Interface Control Register 8 35h 35h - - Document Number: 001-15775 Rev. *O Page 16 of 30

CY7C68003 Table13 to Table 17 on page 18 define the read, write, set, and clear register options. The following are the conventions: ■Rd or rd = Read ■Wr or wr = Write ■Set or s = Set ■Clr or c = Clear Immediate Register Set The details of all immediate registers of TX2UL are shown in Table 6 on page 6, Table 18 on page 19, and Table 20 on page 21. Function Control Register Control ULPI Function Setting of TX2UL Table 13. Function Control Register (Address: 04h - 06h [read], 04h [write], 05h [set], 06h [clear]) Bit Field Name Description Access Reset Value 1:0 XcvrSelect Selects the required transceiver speed. rd/wr/s/c 01b 00b: Enable HS transceiver 01b: Enable FS transceiver 10b: Reserved 11b: Enable FS transceiver for LS packets. 2 TermSelect Controls the internal 1.5K pull up resistor and 45 HS terminations. rd/wr/s/c 0b 4:3 OpMode Selects the required bit encording style during transmit. rd/wr/s/c 00b 00b: Normal operation 01b: Non-driving 10b: Disable bit stuff and NRZI encoding 11b: Do not automatically add SYNC and EOP when transmitting. It is used only for HS packets. 5 Reset Active high transceiver reset. After the link sets this bit, TX2UL asserts DIR rd/wr/s/c 0b and resets ULPI core. When the reset is completed, DIR is de-asserted and automatically clears this bit. After de-asserting DIR, TX2UL re-asserts DIR and sends and RX CMD update to the link. The link waits for DIR to de-assert before using ULPI bus. It does not reset the ULPI interface or ULPI register set. 6 SuspendM Active low. Put TX2UL into Low Power Mode. TX2UL powers down all rd/wr/s/c 1b blocks except the full speed receiver and ULPI interface pins. TX2UL sets this bit to ‘1’ when it exits from low power mode. 0b: Enter into low power mode 1b: Normal operation mode 7 Reserved rd x Document Number: 001-15775 Rev. *O Page 17 of 30

CY7C68003 Interface Control Register This register enables alternative interface and TX2UL features. Table 14. Interface Control Register (Address: 07h - 09h [read], 07h [write], 08h [set], 09h [clear]) Bit Field Name Description Access Reset Value 1:0 Reserved rd xxb 2 CarkitMode Changes the ULPI interface to carkit interface that support UART pass rd/wr/s/c 0b through mode. This bit is cleared when it exits from carkit UART pass through mode. 0b: Disable serial carkit mode 1b: Enable serial carkit mode 6:3 Reserved rd xxxxb 7 Interface Protect Controls circuitry built into TX2UL for protecting the ULPI interface when rd/wr/s/c 0b Disable the link tristates STP and DATA[7:0]. Any pull ups or pull downs employed by this feature are disabled 0b: Enable the interface Protect Circuit 1b: Disable the Interface Protect Circuit Debug Register This register indicates the current value of various signals useful for debugging. Table 15. Debug Register (Address: 15h [read only]) Bit Field Name Description Access Reset Value 0 LineState0 Contains the current value of LineState(0) rd 0b 1 LineState1 Contains the current value of LineState(1) rd 0b 7:2 Reserved rd 000000b Scratch Register This register is for testing purpose only. The link can read, write, set and clear this register. Table 16. Scratch Register (Address: 16h - 18h [read], 16h [write], 17h [set], 18h [clear]) Bit Field Name Description Access Reset Value 7:0 Scratch Empty register byte for testing purposes. The link software reads, writes, rd/wr/s/c 00000000b sets, and clears this register. Carkit Control Register This register controls the TXD and RXD in carkit UART pass through mode. It has no control function if the CarkitMode bit in Interface Control Register is not set. Table 17. Carkit Control Register (Address: 19h - 1Bh [read], 19h [write], 1Ah [set], 1Bh [clear]) Bit Field Name Description Access Reset Value 1:0 Reserved rd xxb 2 TxdEn Routes TXD signal from DATA[0] pin to DM pin rd/wr/s/c 0b 3 RxdEn Routes RXD signal from DP pin to DATA[1] pin rd/wr/s/c 0b 7:4 Reserved rd xxxxb Document Number: 001-15775 Rev. *O Page 18 of 30

CY7C68003 Drive Strength and Slew Rate Configuration Register This register is mapped to the vendor specific registers address. This register configures the drive strength and slew rate of the outputs. Table 18. Drive Strength and Slew Rate Configuration Register (Address: 31h [read], 31h [write]) Bit Field Name Description Access Reset Value 1:0 DriveStrength Configure the drive strength on the output pins rd/wr 00b 00b: Full drive strength 01b: Three quarter drive strength 10b: half drive strength 11b: Quarter drive strength 2 SlewRate Configure the slew rate on the output pins rd/wr 0b 0b: slow slew rate 1b: fast slew rate 7:3 Reserved rd 00000b USB Interface Control Register This register is mapped to the vendor specific registers address. This register enables or disables the USB interface. Table 19. USB Interface Control Register (Address: 35h [read], 35h [write]) Bit Field Name Description Access Reset Value 1:0 Reserved When write to this register, this field must be filled in 0s rd 00b 2 UsbEnable USB interface control rd/wr 0b 0b: Disable USB interface 1b: Enable USB interface 7:3 Reserved When write to this register, this field must be filled in 0s rd 00000b Document Number: 001-15775 Rev. *O Page 19 of 30

CY7C68003 Absolute Maximum Ratings DC voltage applied to outputs in high Z state........................–0.5V to VCC + 0.5V Exceeding maximum ratings may shorten the useful life of the Static discharge voltage (ESD) device. User guidelines are not tested. from JESD22-A114..................................................> 2000V Storage temperature.................................–65°C to +150°C Latch up current......................................................> 200 mA Ambient temperature with Maximum output short circuit current power supplied (Industrial).........................–40°C to +85°C for all I/O configurations. (Vout = 0 V).....................–100 mA Supply voltage to ground potential Operating Conditions V ...............................................................–0.5V to +2.0V CC V ................................................................–0.5V to +4.0V Ambient temperature under bias (T ) IO A Industrial.....................................................–40°C to +85°C V ........................................................–0.5V to +5.775V BATT V supply voltage...........................................1.7V to 1.9V DC input voltage to any input pin....................1.89V to 3.6V CC V supply voltage............................................1.7V to 3.6V Depends on I/O supply voltage. Inputs are not over voltage IO tolerant. V supply voltage....................................3.0V to 5.775V BATT Document Number: 001-15775 Rev. *O Page 20 of 30

CY7C68003 DC Characteristics Table 20. DC Specifications for All Voltage Supplies Parameter Description Conditions Min Typ Max Unit VCC Core voltage supply 1.7 1.8 1.9 V VIO ULPI interface I/O voltage supply 1.7 1.8, 2.5, 3.6 V (this I/O supply is not available on 3.3 20-Ball WLCSP package) VBATT Crystal voltage supply 3.0 – 5.775 V V Power on reset trip voltage 1.0 – 1.5 V POR(trip) V Input HIGH voltage 1 All ports except USB, 0.625 × VIO – VIO + 0.3 V IH1 2.0 V < VIO < 3.6V V Input HIGH voltage 2 All ports except USB, VIO‚ 0.4 – VIO + 0.3 V IH2 1.7V < VIO < 2.0 V V Input LOW voltage –0.3 – 0.25 × VIO V IL V Output HIGH voltage I (MAX) = 0.1 mA 0.9 × VIO – – V OH OH V Output LOW voltage I (MIN) = 0.1 mA – – 0.1 × VIO V OL OL I Input leakage current All I/O signals held at VDDQ 1 – 1 μA IX I Output leakage current All I/O signals held at VDDQ 1 – 1 μA OZ ICC Supply current Continuous Receive – 30 65 mA Continuous Transmit – 30 65 mA ULPI Low Power Mode – 300 750 μA (Suspend) VCC = 1.8 V Sleep Mode – 5 40 μA - ULPI interface bus is either Hz or drive High - DP and DM must be Hz or pull low I Pull up current Interface protect enabled; –13 – –80 μA PU STP pin only; V = 0 V I I Pull down current Interface protect enabled; 16 – 90 μA PD DATA[7:0] only; V = VIO I AC Characteristics Table 21. ULPI Timing Parameters Parameter Description Min Max Unit tCS Setup time for control input 5.8 – ns tDS Setup time for data input 5.8 – ns tCH Hold time for control input 0 – ns tDH Hold time for data input 0 – ns tCD Output delay time for control output 7.6 9.0 ns tDD Output delay time for data output 7.6 9.0 ns tSTATE Mode state change time 500 – μs tPW Pulse width 200 10000 ns Document Number: 001-15775 Rev. *O Page 21 of 30

CY7C68003 Figure 18.ULPI Timing Diagram CLOCK tCS tCH Control In (STP) tDS tDH DATA[7:0] In tCD tCD Control out (DIR, NXT) tDD tDD DATA [7:0] Out Figure 19.20-Pin CSP Package Configuration Mode Entry Timing Diagram Entering into Exiting From Configuration Configuration Mode Configuration Mode Mode Normal Operation Mode tSTATE tSTATE VCC tPW tPW tPW RESET_N Configuration Pulses (falling edge) Figure 20.24-Pin QFN Package Configuration Mode Entry Timing Diagram VCC Entering into Exiting From Configuration Configuration Mode Configuration Mode Mode Normal Operation Mode tSTATE tSTATE CS_N tPW tPW RESET_N Configuration Pulses (falling edge) Document Number: 001-15775 Rev. *O Page 22 of 30

CY7C68003 Figure 21. AC Test Loads and Waveforms Figure 22.Connecting 20-Ball WLCSP Package TX2UL with a Standard Peripheral Controller with External Clock 1.8V 3.3 – 5.775V T T C A C B Peripheral V V Controller A1 B5 A5 CLOCK CLOCK D1 DATA[0] DATA[0] C5 DATA[1] DATA[1] D5 USB DATA[2] Connector DATA[2] C4 DATA[3] DM DM DATA[3] D4 A4 2 DATA[4] DP DP DATA[4] B4 A3 3 DATA[5] TX2UL DATA[5] D3 4 CSP Package DATA[6] DATA[6] C3 DATA[7] DATA[7] D2 DIR DIR C1 NXT NXT B1 STP XI 13/19.2/24/26 MHz STP C2 A2 External Clock RESET_N RESET_N B2 B3 S S V Document Number: 001-15775 Rev. *O Page 23 of 30

CY7C68003 Ordering Information Ordering Code Package Type Support Clock Input Frequencies (MHz) CY7C68003-20FNXIT 20-ball WLCSP – Tape and Reel 13, 19.2, 24, 26 CY7C68003-24LQXI 24-pin QFN 13, 19.2, 24, 26 CY7C68003-24LQXIT 24-pin QFN – Tape and Reel 13, 19.2, 24, 26 Ordering Code Definitions CY 7 C 68 XXX -FNX/LQX (I) (T) Tape and Reel Thermal Rating: I = Industrial Package type:FNX - WLCSP Pb-free LQX - QFN Pb-free Part Number Family Code: 68 = USB Technology Code: C = CMOS Marketing Code: 7 = Cypress Products Company ID: CY = Cypress Document Number: 001-15775 Rev. *O Page 24 of 30

CY7C68003 Package Diagrams Figure 23.20-Pin WLCSP Package Outline 001-13856 *D Document Number: 001-15775 Rev. *O Page 25 of 30

CY7C68003 Figure 24.24-pin QFN Package Outline 001-13937 *F Document Number: 001-15775 Rev. *O Page 26 of 30

CY7C68003 Acronyms Document Conventions Table 22. Acronyms Used in this Document Units of Measure Acronym Description Table 23. Units of Measure ASIC application specific integrated circuit Symbol Unit of Measure CPU central processing unit KHz kilohertz DID device identifier Mbytes megabytes DSP digital signal processor MHz megahertz µA microampere EEPROM electrically erasable programmable read only memory µs microseconds EPP enhanced parallel port µW microwatts ECC error correction code mA milliampere FIFO first in first out mW milliwatts ns nanoseconds GPIF general programmable interface ppm parts per million GPIO general purpose input / output pF picofarads HBM human body model V volts I/O input output PDA personal digital assistant PLL phase lock loop PID product identifier SIE serial interface engine SOF start of frame USB universal serial bus VID vendor identifier WLCSP wafer level chip scale package ULPI UTMI+ low pin interface Document Number: 001-15775 Rev. *O Page 27 of 30

CY7C68003 Document History Page Document Title: CY7C68003, MoBL-USB™ TX2UL USB 2.0 ULPI Transceiver Document Number: 001-15775 Orig. of Submission Revision ECN Description of Change Change Date ** 1094246 VSO / XVA See ECN Initial Release *A 1188703 VSO See ECN Update the tSTATE min requirement (from 200 us to 500us) in Table21 Section Sleep Mode add (see Table21 for tSTATE requirement) Section of Operating Conditions (page 19), the second VCC corrected to VIO. Table 19, the reference voltage for the V , V , V , V , and V has IH1 IH2 IL OH OL corrected from VCC to VIO. *B 1505863 VSO / See ECN Change in Ordering Information. AESA *C 2081867 VSO / See ECN Update the ESD description in the features list. AESA Updated the description of section ‚ÄúPower Supply Sequence‚Äù Updated the section of Chip Section (CS_N) Updated the section of Operation Modes - tri-state mode only available in 24-pin QFN package Updated Figure 3. Added Table 4. Updated Figure 4 and Table 7 (CSP pin assignment has been changed) Updated the section of Configuration Mode Correct the hyper link section of Immediate Register Set Correct the word of ‚ÄúReserved‚Äù in Table 14 Updated ULPI Timing Parameters table (table-21) Updated ULPI Timing Diagram (figure 18) Added Figure 19. Removed USB Interface Control Register section and table in page 19 Updated Figure 22. *D 2552066 VSO 08/13/2008 In the first page, feature list, update the CSP dimension from ‚Äú2.2 x 1.8 mm‚Äù to ‚Äú2.14 x 1.76 mm‚Äù. Updated Table 12 Add USB Interface Control Register section *E 2597682 VSO / 10/28/2008 Removed PRELIMINARY in master pages (turn into Final data sheet). AESA Updated data sheet template. Updated Ordering Information table. In the Clocking section, added a bullet ‚Äò150 ppm‚Äô. Table 3: ❐changed PN_DC to PN_100 ❐changed DC to 100 ❐change the unit of dB to dBc/Hz ❐added a row of ‚ÄúMaximum Frequency Deviation‚Äù *F 2671871 VSO / 03/13/2009 Updated Suspend current in Table20 (clarified VCC = 1.8V). PYRS Changed all TX3, TX3LP18 to TX2UL *G 2765711 TIK / RADH 09/18/2009 Posting to external web. *H 2920278 VSO / 04/21/2010 Added “Suport USB Device Mode only” in the Feature section. AESA Added table of conetnts. Updated links in Sales, Solutions, and Legal Information. *I 3035786 HBM 09/22/2010 Post to external web. *J 3305013 ODC 07/07/2011 Corrected crystal drive level requirement. Corrected V min value. IL Format updates based on the template and style guide. Added ordering code definition diagram. Added acronyms and units of measure. Document Number: 001-15775 Rev. *O Page 28 of 30

CY7C68003 Document History Page (continued) Document Title: CY7C68003, MoBL-USB™ TX2UL USB 2.0 ULPI Transceiver Document Number: 001-15775 Orig. of Submission Revision ECN Description of Change Change Date *K 3493857 VSO 01/17/2012 No technical updates. Completing Sunset Review. *L 3941477 KHIG 03/22/2013 Updated Absolute Maximum Ratings. Updated Package Diagrams: spec 001-13856 – Changed revision from *B to *C. spec 001-13937 – Changed revision from *C to *E. *M 4281294 SAMT 02/14/2014 Updated Ordering Information (Updated part numbers). Updated to new template. *N 4623579 NIKL 01/14/2015 No technical updates. Completing Sunset Review. *O 5755554 HPPC 05/30/2017 Updated Package Diagrams: spec 001-13856 – Changed revision from *C to *D. spec 001-13937 – Changed revision from *E to *F. Updated to new template. Document Number: 001-15775 Rev. *O Page 29 of 30

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