CY7C67300 EZ-Host™ Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support EZ-Host Features ■SPI support in both master and slave ■On-chip 16-bit DMA/mailbox data path interface ■Single chip programmable USB dual-role (Host/Peripheral) controller with two configurable Serial Interface Engines (SIEs) ■Supports 12 MHz external crystal or clock and four USB ports ■3.3V operation ■Support for USB On-The-Go (OTG) protocol ■Automotive AEC grade option (–40°C to 85°C) ■On-chip 48 MHz 16-bit processor with dynamically switchable clock speed ■Package option—100-pin TQFP ■Configurable IO block supporting a variety of IO options or up Typical Applications to 32 bits of General Purpose IO (GPIO) EZ-Host is a very powerful and flexible dual role USB controller ■4K x 16 internal masked ROM containing built in BIOS that that supports a wide variety of applications. It is primarily supports a communication ready state with access to I2C™ intended to enable host capability in applications such as: EEPROM Interface, external ROM, UART, or USB ■Set top boxes ■8K x 16 internal RAM for code and data buffering ■Printers ■Extended memory interface port for external SRAM and ROM ■KVM switches ■16-bit parallel Host Port Interface (HPI) with a DMA/mailbox data path for an external processor to directly access all of the ■Kiosks on-chip memory and control on-chip SIEs ■Automotive applications ■Fast serial port supports from 9600 baud to 2.0M baud ■Wireless access points Block Diagram CY7C67300 Timer 0 Timer 1 nRESET Control UART I/F I2C Watchdog EEPROM I/F S N CY16 PI 16-bit RISC CORE HSS I/F T U Vbus, ID P T D+,D- OTG USB-A PWM OU UT/ GPIO [31:0] SIE1 P SPI I/F N Host/ D+,D- USB-B ED I PUeSrBip Phoerratsl IDE I/F HAR D+,D- USB-A 4Kx16 8Kx16 S ROMBIOS RAM HPI I/F SIE2 D+,D- USB-B GPIO External MEM I/F X1 Mobile (SRAM/ROM) X2 PLL Power Booster SHARED INPUT/OUTPUT PINS A[15:0] D[15:0] CTRL[9:0] Errata: For information on silicon errata, see “Errata” on page107. Details include trigger conditions, devices affected, and proposed workaround. CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 38-08015 Rev. *P Revised January 18, 2018

CY7C67300 Contents Introduction .......................................................................3 HSS Registers ...........................................................62 Functional Overview ........................................................3 HPI Registers ............................................................68 Processor Core ...........................................................3 SPI Registers ............................................................72 Clocking .......................................................................3 UART Registers ........................................................80 Memory .......................................................................3 PWM Registers .........................................................82 Interrupts .....................................................................3 Pin Diagram ....................................................................86 General Timers and Watchdog Timer .........................3 Pin Descriptions .............................................................86 Power Management ....................................................3 Absolute Maximum Ratings ..........................................90 Interface Descriptions ......................................................3 Operating Conditions .....................................................90 USB Interface ..............................................................5 Crystal Requirements (XTALIN, XTALOUT) .................90 OTG Interface ..............................................................6 DC Characteristics ........................................................90 External Memory Interface ..........................................6 USB Transceiver .......................................................91 General Purpose IO Interface (GPIO) .........................9 AC Timing Characteristics .............................................92 UART Interface [3] .......................................................9 Reset Timing ...........................................................92 I2C EEPROM Interface [4] ..........................................9 Clock Timing .............................................................92 Serial Peripheral Interface ...........................................9 SRAM Read Cycle[24] ..............................................93 High-Speed Serial Interface ......................................10 SRAM Write Cycle [26] ..............................................94 Programmable Pulse/PWM Interface ........................10 I2C EEPROM Timing-Serial IO .................................95 Host Port Interface ....................................................11 HPI (Host Port Interface) Write Cycle Timing ...........96 IDE Interface .............................................................11 HPI (Host Port Interface) Read Cycle Timing ...........97 Charge Pump Interface .............................................12 IDE Timing .................................................................98 Booster Interface .......................................................13 HSS BYTE Mode Transmit ........................................98 Crystal Interface ........................................................13 HSS Block Mode Transmit ........................................98 Boot Configuration Interface ......................................14 HSS BYTE and BLOCK Mode Receive ....................98 Operational Modes ....................................................14 Hardware CTS/RTS Handshake ...............................99 Power Savings and Reset Description .........................15 Register Summary ..........................................................99 Power Saving Mode Description ...............................15 Ordering Information ....................................................104 Sleep .........................................................................15 Ordering Code Definitions .......................................104 External (Remote) Wakeup Source ...........................16 Package Diagram ..........................................................105 Power-On-Reset Description .....................................16 Acronyms ......................................................................106 Reset Pin ...................................................................16 Document Conventions ...............................................106 USB Reset .................................................................16 Units of Measure .....................................................106 Memory Map ....................................................................16 Errata .............................................................................107 Mapping .....................................................................16 Part Numbers Affected ............................................107 Registers .........................................................................18 CY7C67300 Qualification Status .............................107 Processor Control Registers .....................................18 CY7C67300 Errata Summary ..................................107 External Memory Registers .......................................25 Document History Page ...............................................117 Timer Registers .........................................................27 Sales, Solutions, and Legal Information ....................119 General USB Registers [10] ......................................29 Worldwide Sales and Design Support .....................119 USB Host Only Registers [11] ...................................32 Products ..................................................................119 USB Device Only Registers ......................................43 PSoC® Solutions ....................................................119 OTG Control Registers [13] .......................................54 Cypress Developer Community ...............................119 GPIO Registers .........................................................56 Technical Support ...................................................119 IDE Registers ............................................................59 Document Number: 38-08015 Rev. *P Page 2 of 119

CY7C67300 Introduction Interrupts EZ-Host provides 128 interrupt vectors. The first 48 vectors are EZ-Host™ (CY7C67300) is Cypress Semiconductor’s first full- hardware interrupts and the following 80 vectors are software speed, low cost multiport host/peripheral controller. EZ-Host is interrupts. designed to easily interface to most high performance CPUs to add USB host functionality. EZ-Host has its own 16-bit RISC General Timers and Watchdog Timer processor to act as a coprocessor or operate in standalone mode. EZ-Host also has a programmable IO interface block EZ-Host has two built in programmable timers and a Watchdog allowing a wide range of interface options. timer. All three timers can generate an interrupt to the EZ-Host. Functional Overview Power Management EZ-Host has one main power saving mode, Sleep. Sleep mode An overview of the processor core components are presented in pauses all operations and provides the lowest power state. this section. Interface Descriptions Processor Core EZ-Host has a general purpose 16-bit embedded RISC EZ-Host has a wide variety of interface options for connectivity. processor that runs at 48 MHz. With several interface options available, EZ-Host can act as a seamless data transport between many different types of Clocking devices. EZ-Host requires a 12 MHz source for clocking. Either an See Table1 and Table2on page4 to understand how the inter- external crystal or TTL level oscillator may be used. EZ-Host has faces share pins and which can coexist. Note that some inter- an internal PLL that produces a 48 MHz internal clock from the faces have more then one possible port location selectable 12 MHz source. through the GPIO control register [0xC006]. General guidelines for interfaces are as follows: Memory ■HPI and IDE interfaces are mutually exclusive. EZ-Host has a built in 4K × 16 masked ROM and an 8K × 16 internal RAM. The masked ROM contains the EZ-Host BIOS. ■If 16-bit external memory is required, then HSS and SPI default The internal RAM can be used for program code or data. locations must be used. ■I2C EEPROM and OTG do not conflict with any interfaces. Document Number: 38-08015 Rev. *P Page 3 of 119

CY7C67300 Table 1. Interface Options for GPIO Pins GPIO Pins HPI IDE PWM HSS SPI UART I2C OTG GPIO31 SCL/SDA GPIO30 SCL/SDA GPIO29 OTGID GPIO28 TX GPIO27 RX GPIO26 PWM3 CTS[1] GPIO25 GPIO24 INT IOREADY GPIO23 nRD IOR GPIO22 nWR IOW GPIO21 nCS GPIO20 A1 CS1 GPIO19 A0 CS0 GPIO18 A2 PWM2 RTS[1] GPIO17 A1 PWM1 RXD[1] GPIO16 A0 PWM0 TXD[1] GPIO15 D15 D15 GPIO14 D14 D14 GPIO13 D13 D13 GPIO12 D12 D12 GPIO11 D11 D11 MOSI[1] GPIO10 D10 D10 SCK[1] GPIO9 D9 D9 nSSI[1] GPIO8 D8 D8 MISO[1] GPIO7 D7 D7 GPIO6 D6 D6 GPIO5 D5 D5 GPIO4 D4 D4 GPIO3 D3 D3 GPIO2 D2 D2 GPIO1 D1 D1 GPIO0 D0 D0 Table 2. Interface Options for External Memory Bus Pins MEM Pins HPI IDE PWM HSS SPI UART I2C OTG D15 CTS[2] D14 RTS[2] D13 RXD[2] D12 TXD[2] D11 MOSI[2] D10 SCK[2] D9 nSSI[2] D8 MISO[2] D[7:0] A[18:0] CONTROL Notes 1. Default interface location. 2. Alternate interface location. Document Number: 38-08015 Rev. *P Page 4 of 119

CY7C67300 USB Interface EZ-Host has two built in Host/Peripheral SIEs and four USB transceivers that meet the USB 2.0 specification requirements for full and low speed (high speed is not supported). In Host mode, EZ-Host supports four downstream ports, each support control, interrupt, bulk, and isochronous transfers. In Peripheral mode, EZ-Host supports one peripheral port with eight endpoints for each of the two SIEs. Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints 1 though 7 support interrupt, bulk (up to 64 bytes/packet), or isochronous transfers (up to 1023 Bytes/packet size). EZ-Host also supports a combination of Host and Peripheral ports simultaneously as shown in Table 3 on page 5. Table 3. USB Port Configuration Options Port Configurations Port 1A Port 1B Port 2A Port 2B OTG OTG – – – OTG + 2 Hosts OTG – Host Host OTG + 1 Host OTG – Host – OTG + 1 Host OTG – – Host OTG + 1 Peripheral OTG – Peripheral – OTG + 1 Peripheral OTG – – Peripheral 4 Hosts Host Host Host Host 3 Hosts Any Combination of Ports 2 Hosts Any Combination of Ports 1 Host Any Port 2 Hosts + 1 Peripheral Host Host Peripheral – 2 Hosts + 1 Peripheral Host Host – Peripheral 2 Hosts + 1 Peripheral Peripheral – Host Host 2 Hosts + 1 Peripheral – Peripheral Host Host 1 Host + 1 Peripheral Host – Peripheral – 1 Host + 1 Peripheral Host – – Peripheral 1 Host + 1 Peripheral – Host – Peripheral 1 Host + 1 Peripheral – Host Peripheral – 1 Host + 1 Peripheral Peripheral – Host – 1 Host + 1 Peripheral Peripheral – – Host 1 Host + 1 Peripheral – Peripheral – Host 1 Host + 1 Peripheral – Peripheral Host – 2 Peripherals Peripheral – Peripheral – 2 Peripherals Peripheral – – Peripheral 2 Peripherals – Peripheral – Peripheral 2 Peripherals – Peripheral Peripheral – 1 Peripheral Any Port USB Features ■Up to eight available peripheral endpoints (one control endpoint) ■USB 2.0-compliant for full and low speed ■Supports control, interrupt, bulk, and isochronous transfers ■Up to four downstream USB host ports ■Internal DMA channels for each endpoint ■Up to two upstream USB peripheral ports ■Internal pull up and pull down resistors ■Configurable endpoint buffers (pointer and length), must reside in internal RAM ■Internal series termination resistors on USB data lines Document Number: 38-08015 Rev. *P Page 5 of 119

CY7C67300 USB Pins ■Two external memory mapped page registers Table 4. USB Interface Pins External Memory Access Strobes Pin Name Pin Number Access to external memory is sampled asynchronously on the rising edge of strobes with a minimum of one wait state cycle. Up DM1A 22 to seven wait state cycles may be inserted for external memory DP1A 23 access. Each additional wait state cycle stretches the external DM1B 18 memory access time by 21 ns (you must be running in internal memory when changing wait states). An external memory device DP1B 19 with 12 ns access time is necessary to support 48 MHz code DM2A 9 execution. DP2A 10 Page Registers DM2B 4 EZ-Host allows extended data or program code to be stored in DP2B 5 external SRAM, or ROM. The total size of extended memory can be up to 512K bytes. The CY16 processor can access extended OTG Interface memory via two address regions of 0x8000-0x9FFF and EZ-Host has one USB port that is compatible with the USB On- 0xA000-0xBFFF. The page register 0xC018 can be used to The-Go supplement to the USB 2.0 specification. The USB OTG control the address region 0x8000-0x9FFF and the page register port has a various hardware features to support Session 0xC01A controls the address region of 0xA000-0xBFFF. Request Protocol (SRP) and Host Negotiation Protocol (HNP). Figure1 illustrates that when the nXMEMSEL pin is asserted the OTG is only supported on USB PORT 1A. upper CPU address pins are driven by the contents of the Page x registers. OTG Features ■Internal charge pump to supply and control VBUS Figure 1. Page n Registers External Address Pins Logic ■VBUS valid status (above 4.4V) nXMEMSEL Pin ■VBUS status for 2.4V< VBUS <0.8V 0000 + PC[14:0] 1 ■ID pin status A[18:0] ■Switchable 2K ohm internal discharge resistor on VBUS PAGEx Register[5:0] + PC[12:0] 0 ■Switchable 500 ohm internal pull up resistor on VBUS ■Individually switchable internal pull up and pull down resistors Where: on the USB data lines x = 1 or 2 OTG Pins PC = Program Counter A = CPU Address Bus Table 5. OTG Interface Pins Pin Name Pin Number Note: PAGE 1 Register Active Range = 8000h to 9FFFh DM1A 22 PAGE 2 Register Active Range = A000h to BFFFh DP1A 23 nXMEMSEL Pin Active Range = 8000h to BFFFh OTGVBUS 11 OTGID 41 Merge Mode CSwitchA 13 CSwitchB 12 Merge modes enabled through the External Memory Control register [0xC03A] allow combining of external memory regions in External Memory Interface accordance with the following: EZ-Host provides a robust interface to a wide variety of external ■nXMEMSEL is active from 0x8000 to 0xBFFF memory arrays. All available external memory array locations ■nXRAMSEL is active from 0x4000 to 0x7FFF when RAM Merge can contain either code or data. The CY16 RISC processor is disabled; nXRAMSEL is active from 0x4000 to 0xBFFF when directly addresses a flat memory space from 0x0000 to 0xFFFF. RAM Merge is enabled External Memory Interface Features ■nXROMSEL is active from 0xC100 to 0xDFFF when ROM Merge is disabled; nXROMSEL is active from 0x8000 to ■Supports 8-bit or 16-bit SRAM or ROM 0xDFFF (excluding the 0xC000 to 0xC0FF area) when ROM ■SRAM or ROM can be used for code or data space Merge is enabled ■Direct addressing of SRAM or ROM Document Number: 38-08015 Rev. *P Page 6 of 119

CY7C67300 Program Memory Hole Description register must be written appropriately to enable A[18:15] for general addressing purposes. Code residing in the 0xC000-0xC0FF address space is not accessible by the CPU. ■47K ohm external pull up on pin A15 for 12 MHz crystal operation. DMA to External Memory Prohibited ■During the 3 ms BIOS boot procedure the CPU external EZ-Host supports an internal DMA engine to rapidly move data memory bus is active. between different functional blocks within the chip. This DMA engine is used for SIE1, SIE2, HPI, SPI, HSS, and IDE but it can ■ROM boot load value 0xC3B6 located at 0xC100. only transfer data between the specified block and internal RAM or ROM. Setting up the DMA engine to transfer to or from an ■HPI, HSS, SPI, SIE1, SIE2, and IDE cannot DMA to external external memory space might result in internal RAM data memory arrays. corruption because the hardware (for example, HSS/HPI/SIE1/ ■Page 1 banking is always enabled and is in effect from 0x8000 SIE2/IDE) does not explicitly check the address range. For to 0x9FFF. example, setting up a DMA transfer to external address 0x8000 might result in a DMA transfer into address 0x0000. ■Page 2 banking is always enabled and is in effect from 0xA000 to 0xBFFF. External Memory Related Resource Considerations: ■CPU memory bus strobes may wiggle when chip selects are ■By default A[18:15] are not available for general addressing inactive. and are driven high on power up. The Upper Address Enable Document Number: 38-08015 Rev. *P Page 7 of 119

CY7C67300 External Memory Interface Pins Table 6. External Memory Interface Pins (Continued) Table 6. External Memory Interface Pins Pin Name Pin Number Pin Name Pin Number D3 80 nWR 64 D2 81 nRD 62 D1 82 nXMEMSEL (optional nCS) 34 D0 83 nXROMSEL (ROM nCS) 35 nXRAMSEL (RAM nCS) 36 External Memory Interface Block Diagrams A18 95 Figure2 illustrates how to connect a 64k × 8 memory array (SRAM/ROM) to the EZ-Host external memory interface. A17 96 Figure 2. Interfacing to 64k × 8 Memory Array A16 97 A15 38 Interfacing to 64K x 8 External Memory Array A14 33 EZ-Host External Memory Array A13 32 CY7C67300 64K x 8 A12 31 A11 30 A10 27 A[15:0] A[15:0] D[7:0] D[7:0] A9 25 nXRAMSEL CE A8 24 nWR WE nRD OE A7 20 A6 17 A5 8 A4 7 Figure3 illustrates the interface for connecting a 16-bit ROM or A3 3 16-bit RAM to the EZ-Host external memory interface. In 16-bit A2 2 mode, up to 256K words of external ROM or RAM are supported. Note that the address lines do not map directly. A1 1 Figure 3. Interfacing up to 256k × 16 for External Code/Data nBEL/A0 99 nBEH 98 Up to 256k x 16 External Code/Data (Page Mode) D15 67 EZ-Host External Memory Array D14 68 CY7C67300 Up to 256k x 16 D13 69 D12 70 D11 71 A[18:1] A[17:0] D[15:0] D[15:0] D10 72 nXMEMSEL CE D9 73 nBEL BLE nBEH BHE D8 74 nWR WE D7 76 nRD OE D6 77 D5 78 D4 79 Document Number: 38-08015 Rev. *P Page 8 of 119

CY7C67300 Figure4 illustrates the interface for connecting an 8-bit ROM or I2C EEPROM Interface [4] 8-bit RAM to the EZ-Host external memory interface. In 8-bit EZ-Host provides a master-only I2C interface for external serial mode, up to 512K bytes of external ROM or RAM are supported. EEPROMs. The serial EEPROM can be used to store application Figure 4. Interfacing up to 512k × 8 for External Code/Data specific code and data. Use the I2C interface for loading code out of EEPROM, it is not a general I2C interface. The I2C EEPROM Up to 512k x 8 External Code/Data (Page Mode) interface is a BIOS implementation and is exposed through GPIO pins. Refer to the BIOS documentation for additional EZ-Host External Memory Array details on this interface. CY7C67300 Up to 512k x8 I2C EEPROM Features ■Supports EEPROMs up to 64 KB (512K bit) A[18:0] A[18:0] ■Auto-detection of EEPROM size D[7:0] D[7:0] nXMEMSEL CE I2C EEPROM Pins nWR WE Table 8. I2C EEPROM Interface Pins nRD OE Pin Name Pin Number GPIO Number SMALL EEPROM SCK 39 GPIO31 General Purpose IO Interface (GPIO) SDA 40 GPIO30 EZ-Host has up to 32 GPIO signals available. Several other LARGE EEPROM optional interfaces use GPIO pins as well and may reduce the SCK 40 GPIO30 overall number of available GPIOs. SDA 39 GPIO31 GPIO Description Serial Peripheral Interface All Inputs are sampled asynchronously with state changes occurring at a rate of up to two 48 MHz clock cycles. GPIO pins EZ-Host provides a SPI interface for added connectivity. EZ-Host are latched directly into registers, a single flip-flop. may be configured as either an SPI master or SPI slave. The SPI interface can be exposed through GPIO pins or the External Unused Pin Descriptions Memory port. Ensure to tristate unused USB pins with the D+ line pulled high SPI Features through the internal pull up resistor and the D– line pulled low through the internal pull down resistor. ■Master or slave mode operation Configure unused GPIO pins as outputs so they are driven low. ■DMA block transfer and PIO byte transfer modes UART Interface [3] ■Full duplex or half duplex data communication EZ-Host has a built in UART interface. The UART interface ■8-byte receive FIFO and 8-byte transmit FIFO supports data rates from 900 to 115.2K baud. It can be used as a development port or for other interface requirements. The ■Selectable master SPI clock rates from 250 kHz to 12 MHz UART interface is exposed through GPIO pins. ■Selectable master SPI clock phase and polarity UART Features ■Slave SPI signaling synchronization and filtering ■Supports baud rates of 900 to 115.2K ■Slave SPI clock rates up to 2 MHz ■8-N-1 ■Maskable interrupts for block and byte transfer modes UART Pins. ■Individual bit transfer for non-byte aligned serial communi- cation in PIO mode Table 7. UART Interface Pins ■Programmable delay timing for the active/inactive master SPI Pin Name Pin Number clock TX 42 ■Auto or manual control for master mode slave select signal RX 43 ■Complete access to internal memory Notes 3. Errata: The UART is not designed to recognize framing errors. When the UART is enabled, the GPIO Control Register still has control over GPIO 27 (UART RX pin). When enabled, the UART should override the GPIO Control Register, which defaults to setting the pin as an input. Please refer to Errata on page 107 for details and workaround. 4. Errata: If, while the BIOS is loading fi rmware, the part is reset and at that time the EEPROM is drivi ng the SDA line low, the BIOS will configure the part for co- processor mode instead of standalone mode. Please refer to Errata on page 107 for details and workaround. Document Number: 38-08015 Rev. *P Page 9 of 119

CY7C67300 SPI Pins HSS Pins The SPI port has a few different pin location options as shown in The HSS port has a few different pin location options as shown Table9. The port location is selectable via the GPIO control in Table10. The port location is selectable via the GPIO control register [0xC006]. register [0xC006]. Table 9. SPI Interface Pins Table 10. HSS Interface Pins Pin Name Pin Number Pin Name Pin Number Default Location Default Location nSSI 56 or 65 CTS 44 SCK 61 RTS 53 MOSI 60 RXD 54 MISO 66 TXD 55 Alternate Location Alternate Location nSSI 73 CTS 67 SCK 72 RTS 68 MOSI 71 RXD 69 MISO 74 TXD 70 Programmable Pulse/PWM Interface High-Speed Serial Interface EZ-Host has four built in PWM output channels. Each channel EZ-Host provides an HSS interface. The HSS interface is a provides a programmable timing generator sequence that can be programmable serial connection with baud rate from 9600 baud used to interface to various image sensors or other applications. to 2.0M baud. The HSS interface supports both byte and block The PWM interface is exposed through GPIO pins. mode operations and also hardware and software handshaking. Complete control of EZ-Host can be accomplished through this Programmable Pulse/PWM Features interface via an extensible API and communication protocol. The HSS interface can be exposed through GPIO pins or the External ■Four independent programmable waveform generators Memory port. ■Programmable predefined frequencies ranging from 5.90 KHz HSS Features to 48 MHz ■8 bits, no parity code ■Configurable polarity ■Programmable baud rate from 9600 baud to 2M baud ■Continuous and one-shot mode available ■Selectable 1- or 2-stop bit on transmit Programmable Pulse/PWM Pins. ■Programmable inter-character gap timing for Block Transmit Table 11. PWM Interface Pins ■8-byte receive FIFO Pin Name Pin Number ■Glitch filter on receive PWM3 44 ■Block mode transfer directly to/from EZ-Host internal memory PWM2 53 (DMA transfer) PWM1 54 ■Selectable CTS/RTS hardware signal handshake protocol PWM0 55 ■Selectable XON/XOFF software handshake protocol ■Programmable Receive interrupt, Block Transfer Done inter- rupts ■Complete access to internal memory Document Number: 38-08015 Rev. *P Page 10 of 119

CY7C67300 Host Port Interface Table 12. HPI Interface Pins (Continued)[5, 6] EZ-Host has an HPI interface. The HPI interface provides DMA D11 60 access to the EZ-Host internal memory by an external host, plus D10 61 a bidirectional mailbox register for supporting high level commu- nication protocols. This port is designed to be the primary D9 65 high-speed connection to a host processor. Complete control of D8 66 EZ-Host can be accomplished through this interface via an extensible API and communication protocol. Other than the D7 86 hardware communication protocols, a host processor has D6 87 identical control over EZ-Host whether connecting to the HPI or D5 89 HSS port. The HPI interface is exposed through GPIO pins. D4 90 HPI Features D3 91 ■16-bit data bus interface D2 92 ■16 MB/s throughput D1 93 ■Auto-increment of address pointer for fast block mode transfers D0 94 ■Direct memory access (DMA) to internal memory The two HPI address pins are used to address one of four ■Bidirectional Mailbox register possible HPI port registers as shown in Table13. ■Byte swapping Table 13. HPI Addressing ■Complete access to internal memory HPI A[1:0] A1 A0 ■Complete control of SIEs through HPI HPI Data 0 0 HPI Mailbox 0 1 ■Dedicated HPI status register HPI Address 1 0 HPI Pins HPI Status 1 1 Table 12. HPI Interface Pins[5, 6] IDE Interface Pin Name Pin Number EZ-Host has an IDE interface. The IDE interface supports PIO INT 46 mode 0-4 as specified in the Information Technology-AT nRD 47 Attachment–4 with Packet Interface Extension (ATA/ATAPI-4) nWR 48 Specification, T13/1153D Rev 18. There is no need for firmware to use programmable wait states. The CPU read/write cycle is nCS 49 automatically extended as needed for direct CPU to IDE read/ A1 50 write accesses. A0 52 The EZ-Host IDE interface also has a BLOCK transfer mode that allows EZ-Host to read/write large blocks of data to/from the IDE D15 56 data register and move it to/from the EZ-Host on-chip memory D14 57 directly without intervention of the CPU. The IDE interface is D13 58 exposed through GPIO pins. Table14on page12 lists the achieved throughput for maximum block mode data transfer rate D12 59 (with IDE_IORDY true) for the various IDE PIO modes. Notes 5. HPI_INT is for the Outgoing Mailbox interrupt. 6. HPI strobes are negative logic sampled on rising edge. Document Number: 38-08015 Rev. *P Page 11 of 119

CY7C67300 Table 14. IDE Throughput ATA/ATAPI-4 Actual ATA/ATPI-4 Actual Mode Min Cycle Time Min Cycle Time Max Transfer Rate Max Transfer Rate PIO Mode 0 600 ns 30T = 625 ns 3.33 MB/s 3.2 MB/s PIO Mode 1 383 ns 20T = 416.7 ns 5.22 MB/s 4.8 MB/s PIO Mode 2 240 13T = 270.8 ns 8.33 MB/s 7.38 MB/s PIO Mode 3 180 ns 10T = 208.3 ns 11.11 MB/s 9.6 MB/s PIO Mode 4 120 ns 8T = 166.7 ns 16.67 MB/s 12.0 MB/s T = System clock period = 1/48 MHz. IDE Features Charge Pump Interface ■Programmable IO mode 0–4 VBUS for the USB OTG port can be produced by EZ-Host using its built in charge pump and some external components. Ensure ■Block mode transfers the circuit connections look similar to the following diagram. ■Direct memory access to/from internal memory through the IDE Figure 5. Charge Pump data register IDE Pins D1 D2 Table 15. IDE Interface Pins CSWITCHA CY7C67300 Pin Name Pin Number CSWITCHB IORDY 46 C1 VBUS IOR 47 OTGVBUS C2 IOW 48 CS1 50 CS0 52 Component details: A2 53 ■D1 and D2: Schottky diodes with a current rating greater than 60 mA A1 54 ■C1: Ceramic capacitor with a capacitance of 0.1 µF A0 55 ■C2: Make capacitor value no more that 6.5 µF since that is the D15 56 maximum capacitance allowed by the USB OTG specifications D14 57 for a dual role device. The minimum value of C2 is 1µF. There are no restrictions on the type of capacitor for C2. D13 58 If the VBUS charge pump circuit is not to be used, CSWITCHA, D12 59 CSWITCHB, and OTGVBUS can be left unconnected. D11 60 Charge Pump Features D10 61 ■Meets OTG Supplement Requirements, see Table 134 on page D9 65 91 for details. D8 66 Charge Pump Pins D7 86 Table 16. Charge Pump Interface Pins D6 87 Pin Name Pin Number D5 89 OTGVBUS 11 D4 90 CSwitchA 13 D3 91 CSwitchB 12 D2 92 D1 93 D0 94 Document Number: 38-08015 Rev. *P Page 12 of 119

CY7C67300 Booster Interface Booster Pins EZ-Host has an on chip power booster circuit for use with power Table 17. Charge Pump Interface Pins supplies that range between 2.7V and 3.6V. The booster circuit boosts the power to 3.3V nominal to supply power for the entire Pin Name Pin Number chip. The booster circuit requires an external inductor, diode, and BOOSTVcc 16 capacitor. During power down mode, the circuit is disabled to save power. Figure6 shows how to connect the booster circuit. VSWITCH 14 Figure 6. Power Supply Connection With Booster Crystal Interface The recommended crystal circuit to be used with EZ-Host is shown in Figure8 If an oscillator is used instead of a crystal BOOSTVcc circuit, connect it to XTALIN and leave XTALOUT unconnected. For further information about the crystal requirements, see Table 2.7V to 3.6V 132 on page 90. L1 Power Supply Noted that the CLKSEL pin (pin 38) is sampled after reset to determine what crystal or clock source frequency is used. For normal operation, 12 MHz is required so the CLKSEL pin must VSWITCH have a 47K ohm pull up resistor to V . CC. D1 Figure 8. Crystal Interface 3.3V VCC C1 XTALIN AVCC CY7C67300 Y1 12MHz Parallel Resonant Component details: Fundamental Mode ■L1: Inductor with inductance of 10 µH and a current rating of at 500uW least 250 mA XTALOUT 20-33pf ±5% ■D1: Schottky diode with a current rating of at least 250 mA C1 = 22 pF C2 = 22 pF ■C1: Tantalum or ceramic capacitor with a capacitance of at least 2.2 µF Figure7 shows how to connect the power supply when the booster circuit is not being used. Figure 7. Power Supply Connection Without Booster Crystal Pins Table 18. Crystal Pins BOOSTVcc Pin Name Pin Number 3.0V to 3.6V XTALIN 29 Power Supply XTALOUT 28 VSWITCH VCC AVCC Document Number: 38-08015 Rev. *P Page 13 of 119

CY7C67300 Boot Configuration Interface Operational Modes EZ-Host can boot into any one of four modes. The mode it boots The operational modes are discussed in the following sections. into is determined by the TTL voltage level of GPIO[31:30] at the time nRESET is deasserted. Table19 shows the different boot Coprocessor Mode pin combinations possible. After a reset pin event occurs, the EZ-Host can act as a coprocessor to an external host processor. BIOS bootup procedure executes for up to 3 ms. GPIO[31:30] In this mode, an external host processor drives EZ-Host and is are sampled by the BIOS during bootup only. After bootup these the main processor rather then EZ-Host’s own 16-bit internal pins are available to the application as GPIOs. CPU. An external host processor may interface to EZ-Host through one of the following three interfaces in coprocessor Table 19. Boot Configuration Interface mode: GPIO31 GPIO30 (Pin 39) (Pin 40) Boot Mode ■HPI mode, a 16 bit parallel interface with up to 16 MB transfer rate 0 0 Host Port Interface (HPI) ■HSS mode, a serial interface with up to 2M baud transfer rate 0 1 High-Speed Serial (HSS) 1 0 Serial Peripheral Interface (SPI, ■SPI mode, a serial interface with up to 2 Mb/s transfer rate slave mode) At bootup GPIO[31:30] determine which of these three interfaces 1 1 I2C EEPROM (Standalone Mode) are used for coprocessor mode. See Table19 for details. Bootloading begins from the selected interface after POR + 3ms of BIOS bootup. Ensure that GPIO[31:30] is pulled high or low as needed using resistors tied to VCC or GND with resistor values between 5K Standalone Mode ohms and 15K ohms. Do not tie GPIO[31:30] directly to V or CC In standalone mode, there is no external processor connected to GND. Note that in standalone mode, the pull ups on those two EZ-Host. Instead, EZ-Host’s own internal 16-bit CPU is the main pins are used for the serial I2C EEPROM (if implemented). Make processor and firmware is typically downloaded from an sure that the resistors used for these pull ups conform to the EEPROM. Optionally, firmware may also be downloaded via serial EEPROM manufacturer's requirements. USB. See Table19 for booting into standalone mode. If any mode other then standalone is chosen, EZ-Host is in After booting into standalone mode (GPIO[31:30] = ‘11’), the coprocessor mode. The device powers up with the appropriate following pins are affected: communication interface enabled according to its boot pins and waits idle until a coprocessor communicates with it. See the ■GPIO[31:30] are configured as output pins to examine the BIOS documentation for greater detail of the boot process. EEPROM contents ■GPIO[28:27] are enabled for debug UART mode ■GPIO[29] is configured for as OTGID for OTG applications on PORT1A ❐If OTGID is logic 1 then PORT1A (OTG) is configured as a USB peripheral ❐If OTGID is logic 0 then PORT1A (OTG) is configured as a USB host ■Ports 1B, 2A, and 2B default as USB peripheral ports ■All other pins remain INPUT pins. Document Number: 38-08015 Rev. *P Page 14 of 119

CY7C67300 Minimum Hardware Requirements for Standalone Mode – Peripheral Only Figure 9. Minimum Standalone Hardware Configuration – Peripheral Only EZ-Host CY7C67300 Reset VReg VCC, AVCC, nRESET Logic BoostVCC VBus D+ DPlus Standard-B or Mini-B D- DMinus GND SHIELD VCC Bootstrap Options Vcc Vcc 47Kohm Pin 38 10k 10k GPIO[30] SCL* GPIO[31] SDA* Int. 16k x8 Code / Data Bootloading Firmware VCC A0 Up to 64k x8 VCC A1 EEPROM WP A2 SCL Reserved GND SDA 22pf XIN GND, AGND, 12MHz BoostGND XOUT 22pf *Bootloading begins after POR + 3ms BIOS bootup *Parallel Resonant Fundamental Mode *GPIO[31:30] 31 30 500uW Up to 2k x8 SCL SDA 20-33pf ±5% >2k x8 to 64k x8 SDA SCL Power Savings and Reset Description Sleep Sleep mode is the main chip power down mode and is also used This sections describes the different modes for resetting the chip for USB suspend. Sleep mode is entered by setting the Sleep and ways to save power. Enable (bit 1) of the Power control register [0xC00A]. During Sleep mode (USB Suspend) the following events and states are Power Saving Mode Description true: EZ-Host has one main power saving mode, Sleep. For detailed information about Sleep mode, see the Sleep section that ■GPIO pins maintain their configuration during sleep (in follows. suspend) Sleep mode is used for USB applications to support USB ■External Memory address pins are driven low suspend and non USB applications as the main chip power down ■XTALOUT is turned off mode. In addition, EZ-Host is capable of slowing down the CPU clock ■Internal PLL is turned off speed through the CPU Speed register [0xC008] without ■Ensure that firmware disables the charge pump (OTG Control affecting other peripheral timing. Reducing the CPU clock speed register [0xC098]) thereby causing OTGVBUS to drop below from 48 MHz to 24 MHz reduces the overall current draw by 0.2V. Otherwise OTGVBUS only drops to V – (2 schottky CC around 8 mA while reducing it from 48 MHz to 3 MHz reduces diode drops). the overall current draw by approximately 15 mA. ■Booster circuit is turned off ■USB transceivers is turned off ■CPU goes into suspend mode until a programmable wakeup event Document Number: 38-08015 Rev. *P Page 15 of 119

CY7C67300 External (Remote) Wakeup Source Memory Map There are several possible events available to wake EZ-Host The memory map is discussed in the following sections. from Sleep mode as shown in Table20. These may also be used as remote wakeup options for USB applications. See the Power Mapping Control Register [0xC00A] [R/W] on page 21 for details. The total memory space directly addressable by the CY16 Upon wakeup, code begins executing within 200 µs, the time it processor is 64K (0x0000-0xFFFF). Program, data, and IO are takes the PLL to stabilize. contained within this 64K space. This memory space is byte Table 20. Wakeup Sources [7, 8] addressable. Figure 10 on page 17 shows the various memory region address locations. Wakeup Source Event (if enabled) Internal Memory USB Resume D+/D– Signaling Of the internal memory, 15K bytes are allocated for user's program and data. The lower memory space from 0x0000 to OTGVBUS Level 0x04A2 is reserved for interrupt vectors, general purpose OTGID Any Edge registers, USB control registers, stack, and other BIOS variables. The upper internal memory space contains EZ-Host control HPI Read registers from 0xC000 to 0xC0FF and the BIOS ROM itself from HSS Read 0xE000 to 0xFFFF. For more information about the reserved SPI Read lower memory or the BIOS ROM, refer to the Programmer’s documentation and/or the BIOS documentation. IRQ1 (GPIO 25) Any Edge During development with the EZ-Host toolset, leave the lower IRQ0 (GPIO 24) Any Edge area of user's space (0x04A4 to 0x1000) available to load the GDB stub. The GDB stub is required to allow the toolset debug Power-On-Reset Description access into EZ-Host. The length of the power-on-reset event can be defined by (V The chip select pins are not active during accesses to internal CC ramp to valid) + (Crystal startup). A typical application might use memory. a 12 ms power-on-reset event = ~7 ms + ~5 ms, respectively. External Memory Reset Pin Up to 32 KB of external memory from 0x4000 - 0xBFFF is available via one chip select line (nXRAMSEL) with RAM Merge The Reset pin is active low and requires a minimum pulse enabled (BIOS default). Additionally, another 8KB region from duration of sixteen 12 MHz clock cycles (1.3 µs). A reset event 0xC100 - 0xDFFF is available via a second chip select line restores all registers to their default POR settings. Code (nXROMSEL) giving 40 KB of total available external memory. execution then begins 200 µs later at 0xFF00 with an immediate Together with the internal 15 KB, this gives a total of either ~48 jump to 0xE000, the start of BIOS. Refer to BIOS documentation KB (one chip select) or ~56 KB (two chip selects) of available for additional details. memory for either code or data. USB Reset Note that the memory map and pin names (nXRAMSEL/ A USB Reset affects registers 0xC090 and 0xC0B0, all other nXROMSEL) define specific memory regions for RAM vs. ROM. registers remain unchanged. This allows the BIOS to look in the upper external memory space at 0xC100 for SCAN vectors (enabling code to be loaded/ executed from ROM). If no SCAN vectors are required in the design (external memory is used exclusively for data), then all external memory regions can be used for RAM. Similarly, the external memory can be used exclusively for code space (ROM). If more external memory is required, EZ-Host has enough address lines to support up to 512 KB. However, this requires complex code banking/paging schemes via the Extended Page registers. For further information about setting up the external memory, see the External Memory Interface on page 6. Notes 7. Read data is discarded (dummy data). 8. HPI_INT asserts on a USB Resume. Document Number: 38-08015 Rev. *P Page 16 of 119

CY7C67300 Figure 10. Memory Map Internal Memory HW INT's 0x0000 - 0x00FF SW INT's 0x0100 - 0x011F Primary Registers 0x0120 - 0x013F Swap Registers 0x0140 - 0x0148 HPI Int / Mailbox 0x014A - 0x01FF LCP Variables 0x0200 - 0x02FF USB Registers 0x0300 - 0x030F Slave Setup Packet 0x0310 - 0x03FF BIOS Stack 0x0400 - 0x04A2 USB Slave & OTG USER SPACE 0x04A4 - 0x3FFF ~15K External Memory USER SPACE 0x4000 - 0x7FFF 16K Bank Selected Extended Page 1 0x8000 - 0x9FFF 01USER SPACE by 0xC018 Up to 64 8K Banks Bank Selected Extended Page 2 0xA000 - 0xBFFF by 01USER SPACE Up to 64 8K Banks 0xC01A 0xC000 - 0xC0FF Control Registers 0xC100 - 0xDFFF USER SPACE ~8K 0xE000 - 0xFFFF BIOS Document Number: 38-08015 Rev. *P Page 17 of 119

CY7C67300 Registers Table 21. Processor Control Registers Some registers have different functions for a read vs. a write Register Name Address R/W access or USB host vs. USB device mode. Therefore, registers CPU Flags Register 0xC000 R of this type have multiple definitions for the same address. Register Bank Register 0xC002 R/W The default register values listed in this data sheet may be Hardware Revision Register 0xC004 R altered to some other value during the BIOS initialization. Refer to the BIOS documentation for register initialization information. CPU Speed Register 0xC008 R/W Power Control Register 0xC00A R/W Processor Control Registers Interrupt Enable Register 0xC00E R/W There are nine registers dedicated to general processor control. Each of these registers are covered in this section and are Breakpoint Register 0xC014 R/W summarized in Table21. USB Diagnostic Register 0xC03C W Memory Diagnostic Register 0xC03E W CPU Flags Register [0xC000] [R] Table 22. CPU Flags Register Bit # 15 14 13 12 11 10 9 8 Field Reserved... Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 ...Reserved Global Negative Overflow Carry Zero Interrupt Flag Flag Flag Flag Field Enable Read/Write - - - R R R R R Default 0 0 0 X X X X X Register Description Overflow Flag (Bit 2) The CPU Flags register is a read only register that gives The Overflow Flag bit indicates if an overflow condition occurred. processor flags status. An overflow condition can occur if an arithmetic result was either larger than the destination operand size (for addition) or smaller Global Interrupt Enable (Bit 4) than the destination operand must allow for subtraction. The Global Interrupt Enable bit indicates if the Global Interrupts 1: Overflow occurred are enabled. 0: Overflow did not occur 1: Enabled Carry Flag (Bit 1) 0: Disabled The Carry Flag bit indicates if an arithmetic operation resulted in Negative Flag (Bit 3) a Carry for addition, or Borrow for subtraction. The Negative Flag bit indicates if an arithmetic operation results 1: Carry/Borrow occurred in a negative answer. 0: Carry/Borrow did not occur 1: MS result bit is ‘1’ Zero Flag (Bit 0) 0: MS result bit is not ‘1’ The Zero Flag bit indicates if an instruction execution resulted in a ‘0’. 1: Zero occurred 0: Zero did not occur Document Number: 38-08015 Rev. *P Page 18 of 119

CY7C67300 Bank Register [0xC002] [R/W] Table 23. Bank Register Bit # 15 14 13 12 11 10 9 8 Field Address... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 1 Bit # 7 6 5 4 3 2 1 0 Field ...Address Reserved Read/Write R/W R/W R/W - - - - - Default 0 0 0 X X X X X Register Description The Bank register maps registers R0–R15 into RAM. The eleven MSBs of this register are used as a base address for registers R0– R15. A register address is automatically generated by: 1.Shifting the four LSBs of the register address left by 1. 2.ORing the four shifted bits of the register address with the twelve MSBs of the Bank register. 3.Forcing the LSB to zero. For example, if the Bank register is left at its default value of 0x0100, and R2 is read, then the physical address 0x0102 is read. Refer to Table24 for details. Table 24. Bank Register Example Register Hex Value Binary Value Bank 0x0100 0000 0001 0000 0000 R14 0x000E << 1 = 0x001C 0000 0000 0001 1100 RAM Location 0x011C 0000 0001 0001 1100 Address (Bits [15:4]) The Address field is used as a base address for all register addresses to start from. Reserved Write all reserved bits with ’0’. Hardware Revision Register [0xC004] [R] Table 25. Revision Register Bit # 15 14 13 12 11 10 9 8 Field Revision... Read/Write R R R R R R R R Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 Field ...Revision Read/Write R R R R R R R R Default X X X X X X X X Register Description The Hardware Revision register is a read only register that indicates the silicon revision number. The first silicon revision is represented by 0x0101. This number is increased by one for each new silicon revision. Revision (Bits [15:0]) The Revision field contains the silicon revision number. Document Number: 38-08015 Rev. *P Page 19 of 119

CY7C67300 CPU Speed Register [0xC008] [R/W] Table 26. CPU Speed Register Bit # 15 14 13 12 11 10 9 8 Field Reserved... Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Reserved CPU Speed Read/Write - - - - R/W R/W R/W R/W Default 0 0 0 0 1 1 1 1 Register Description The CPU Speed register allows the processor to operate at a user selected speed. This register only affects the CPU, all other peripheral timing is still based on the 48 MHz system clock (unless otherwise noted). CPU Speed (Bits[3:0]) The CPU Speed field is a divisor that selects the operating speed of the processor as defined in Table27. Table 27. CPU Speed Definition CPU Speed [3:0] Processor Speed 0000 48 MHz/1 0001 48 MHz/2 0010 48 MHz/3 0011 48 MHz/4 0100 48 MHz/5 0101 48 MHz/6 0110 48 MHz/7 0111 48 MHz/8 1000 48 MHz/9 1001 48 MHz/10 1010 48 MHz/11 1011 48 MHz/12 1100 48 MHz/13 1101 48 MHz/14 1110 48 MHz/15 1111 48 MHz/16 Reserved Write all reserved bits with ’0’. Document Number: 38-08015 Rev. *P Page 20 of 119

CY7C67300 Power Control Register [0xC00A] [R/W] Table 28. Power Control Register Bit # 15 14 13 12 11 10 9 8 Host/Device Host/Device Host/Device Host/Device OTG Reserved HSS SPI 2B 2A 1B 1A Wake Wake Wake Wake Wake Wake Wake Enable Enable Enable Field Enable Enable Enable Enable Read/Write R/W R/W R/W R/W R/W - R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 HPI Reserved GPI Reserved Boost 3V Sleep Halt Wake Wake OK Enable Enable Field Enable Enable Read/Write R/W - - R/W - R R/W R/W Default 0 0 0 0 0 0 0 0 Register Description OTG Wake Enable (Bit 11) The Power Control register controls the power down and wakeup The OTG Wake Enable bit enables or disables a wakeup options. Either the sleep mode or the halt mode options can be condition to occur on either an OTG VBUS_Valid or OTG ID selected. All other writable bits in this register can be used as a transition (IRQ20). wakeup source while in sleep mode. 1: Enable wakeup on OTG VBUS valid or OTG ID transition Host/Device 2B Wake Enable (Bit 15) 0: Disable wakeup on OTG VBUS valid or OTG ID transition The Host/Device 2B Wake Enable bit enables or disables a HSS Wake Enable (Bit 9) wakeup condition to occur on a Host/Device 2B transition. This wakeup from the SIE port does not cause an interrupt to the on- The HSS Wake Enable bit enables or disables a wakeup chip CPU. condition to occur on an HSS Rx serial input transition. The processor may take several hundreds of microseconds before 1: Enable wakeup on Host/Device 2B transition being operational after wakeup. Therefore, the incoming data 0: Disable wakeup on Host/Device 2B transition byte that causes the wakeup is discarded. 1: Enable wakeup on HSS Rx serial input transition Host/Device 2A Wake Enable (Bit 14) 0: Disable wakeup on HSS Rx serial input transition The Host/Device 2A Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 2A transition. This SPI Wake Enable (Bit 8) wakeup from the SIE port does not cause an interrupt to the on- chip CPU. The SPI Wake Enable bit enables or disables a wakeup condition to occur on a falling SPI_nSS input transition. The processor 1: Enable wakeup on Host/Device 2A transition may take several hundreds of microseconds before being opera- 0: Disable wakeup on Host/Device 2A transition tional after wakeup. Therefore, the incoming data byte that causes the wakeup is discarded. Host/Device 1B Wake Enable (Bit 13) 1: Enable wakeup on falling SPI nSS input transition The Host/Device 1B Wake Enable bit enables or disables a 0: Disable SPI_nSS interrupt wakeup condition to occur on an Host/Device 1B transition. This wakeup from the SIE port does not cause an interrupt to the on- HPI Wake Enable (Bit 7) chip CPU. The HPI Wake Enable bit enables or disables a wakeup 1: Enable wakeup on Host/Device 1B transition condition to occur on an HPI interface read. 0: Disable wakeup on Host/Device 1B transition 1: Enable wakeup on HPI interface read Host/Device 1A Wake Enable (Bit 12) 0: Disable wakeup on HPI interface read The Host/Device 1A Wake Enable bit enables or disables a GPI Wake Enable (Bit 4) wakeup condition to occur on an Host/Device 1A transition. This wakeup from the SIE port does not cause an interrupt to the on- The GPI Wake Enable bit enables or disables a wakeup chip CPU. condition to occur on a GPIO(25:24) transition. 1: Enable wakeup on Host/Device 1A transition 1: Enable wakeup on GPIO(25:24) transition 0: Disable wakeup on Host/Device 1A transition 0: Disable wakeup on GPIO(25:24) transition Document Number: 38-08015 Rev. *P Page 21 of 119

CY7C67300 Boost 3V OK (Bit 2) Halt Enable (Bit 0) The Boost 3V OK bit is a read only bit that returns the status of Setting this bit to ‘1’ immediately initiates HALT mode. While in the OTG Boost circuit. HALT mode, only the CPU is stopped. The internal clock still runs and all peripherals still operate, including the USB engines. The 1: Boost circuit not ok and internal voltage rails are below 3.0V power saving using HALT in most cases is minimal, but in appli- 0: Boost circuit ok and internal voltage rails are at or above 3.0V cations that are very CPU intensive the incremental savings may provide some benefit. Sleep Enable (Bit 1) The HALT state is exited when any enabled interrupt is triggered. Setting this bit to ‘1’ immediately initiates SLEEP mode. While in Upon exiting the HALT state, one or two instructions immediately SLEEP mode, the entire chip is paused, achieving the lowest following the HALT instruction may be executed before the standby power state. All operations are paused, the internal waking interrupt is serviced (you may want to follow the HALT clock is stopped, the booster circuit and OTG VBUS charge instruction with two NOPs). pump are all powered down, and the USB transceivers are powered down. All counters and timers are paused but retain 1: Enable Halt mode their values; enabled PWM outputs freeze in their current states. 0: No function SLEEP mode exits by any activity selected in this register. When SLEEP mode ends, instruction execution resumes within 0.5 ms. Reserved 1: Enable Sleep mode Write all reserved bits with ’0’. 0: No function Interrupt Enable Register [0xC00E] [R/W] [9] Table 29. Interrupt Enable Register Bit # 15 14 13 12 11 10 9 8 Reserved OTG SPI Reserved Host/Device 2 Host/Device 1 Interrupt Interrupt Interrupt Interrupt Field Enable Enable Enable Enable Read/Write - - - R/W R/W - R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 HSS In Mailbox Out Mailbox Reserved UART GPIO Timer 1 Timer 0 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Field Enable Enable Enable Enable Enable Enable Enable Read/Write R/W R/W R/W - R/W R/W R/W R/W Default 0 0 0 1 0 0 0 0 Register Description Host/Device 2 Interrupt Enable (Bit 9) The Interrupt Enable register allows control of the hardware The Host/Device 2 Interrupt Enable bit enables or disables all of interrupt vectors. the following Host/Device 2 hardware interrupts: Host 2 USB Done, Host 2 USB SOF/EOP, Host 2 Wakeup/Insert/Remove, OTG Interrupt Enable (Bit 12) Device 2 Reset, Device 2 SOF/EOP or WakeUp from USB, The OTG Interrupt Enable bit enables or disables the OTG ID/ Device 2 Endpoint n. OTG4.4V Valid hardware interrupt. 1: Enable Host 2 and Device 2 interrupt 1: Enable OTG interrupt 0: Disable Host 2 and Device 2 interrupt 0: Disable OTG interrupt Host/Device 1 Interrupt Enable (Bit 8) SPI Interrupt Enable (Bit 11) The Host/Device 1 Interrupt Enable bit enables or disables all of The SPI Interrupt Enable bit enables or disables the following the following Host/Device 1 hardware interrupts: Host 1 USB three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA Done, Host 1 USB SOF/EOP, Host 1 Wakeup/Insert/Remove, Block Done. Device 1 Reset, Device 1 SOF/EOP or WakeUp from USB, Device 1Endpoint n. 1: Enable SPI interrupt 1: Enable Host 1 and Device 1 interrupt 0: Disable SPI interrupt 0: Disable Host 1 and Device 1 interrupt Note 9. Errata: Host/Device 1 SIE events will still trigger an interrupt when only the Host/Device 2 SIE Interrupt Enable is set and vise versa. Please refer to Errata on page 107 for details and workaround. Document Number: 38-08015 Rev. *P Page 22 of 119

CY7C67300 HSS Interrupt Enable (Bit 7) GPIO Interrupt Enable (Bit 2) The HSS Interrupt Enable bit enables or disables the following The GPIO Interrupt Enable bit enables or disables the General High-speed Serial Interface hardware interrupts: HSS Block Purpose IO pins interrupt (see the GPIO Control Register Done and HSS RX Full. [0xC006] [R/W] on page 56). When the GPIO bit is reset, all pending GPIO interrupts are also cleared 1: Enable HSS interrupt 1: Enable GPIO interrupt 0: Disable HSS interrupt 0: Disable GPIO interrupt In Mailbox Interrupt Enable (Bit 6) Timer 1 Interrupt Enable (Bit 1) The In Mailbox Interrupt Enable bit enables or disables the HPI: Incoming Mailbox hardware interrupt. The Timer 1 Interrupt Enable bit enables or disables the TImer1 Interrupt Enable. When this bit is reset, all pending Timer 1 inter- 1: Enable MBXI interrupt rupts are cleared. 0: Disable MBXI interrupt 1: Enable TM1 interrupt Out Mailbox Interrupt Enable (Bit 5) 0: Disable TM1 interrupt The Out Mailbox Interrupt Enable bit enables or disables the HPI: Timer 0 Interrupt Enable (Bit 0) Outgoing Mailbox hardware interrupt. The Timer 0 Interrupt Enable bit enables or disables the TImer0 1: Enable MBXO interrupt Interrupt Enable. When this bit is reset, all pending Timer 0 inter- 0: Disable MBXO interrupt rupts are cleared. UART Interrupt Enable (Bit 3) 1: Enable TM0 interrupt The UART Interrupt Enable bit enables or disables the following 0: Disable TM0 interrupt UART hardware interrupts: UART TX, and UART RX. Reserved 1: Enable UART interrupt Write all reserved bits with ’0’. 0: Disable UART interrupt Breakpoint Register [0xC014] [R/W] Table 30. Breakpoint Register Bit # 15 14 13 12 11 10 9 8 Field Address... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Address Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Address (Bits [15:0]) The Breakpoint register holds the breakpoint address. When the The Address field is a 16-bit field containing the breakpoint program counter matches this address, the INT127 interrupt address. occurs. To clear this interrupt, write a zero value to this register. Document Number: 38-08015 Rev. *P Page 23 of 119

CY7C67300 USB Diagnostic Register [0xC03C] [R/W] Table 31. USB Diagnostic Register Bit # 15 14 13 12 11 10 9 8 Port 2B Port 2A Port 1B Port 1A Reserved... Diagnostic Diagnostic Diagnostic Diagnostic Field Enable Enable Enable Enable Read/Write R/W R/W R/W R/W - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 ...Reserved Pull-down LS Pull-up FS Pull-up Reserved Force Select Field Enable Enable Enable Read/Write - R/W R/W R/W - R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Pull-down Enable (Bit 6) The USB Diagnostic register provides control of diagnostic The Pull-down Enable bit enables or disables full-speed pull modes. It is intended for use by device characterization tests, not down resistors (pull down on both D+ and D–) for testing. for normal operations. This register is read/write by the on-chip 1: Enable pull down resistors on both D+ and D– CPU but is write-only via the HPI port. 0: Disable pull down resistors on both D+ and D– Port 2B Diagnostic Enable (Bit 15) LS Pull-up Enable (Bit 5) The Port 2B Diagnostic Enable bit enables or disables Port 2B for the test conditions selected in this register. The LS Pull-up Enable bit enables or disables a low-speed pull up resistor (pull up on D–) for testing. 1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD 1: Enable low-speed pull up resistor on D– 0: Do not apply test conditions 0: Pull-up resistor is not connected on D– Port 2A Diagnostic Enable (Bit 14) FS Pull-up Enable (Bit 4) The Port 2A Diagnostic Enable bit enables or disables Port 2A The FS Pull-up Enable bit enables or disables a full-speed pull for the test conditions selected in this register. up resistor (pull up on D+) for testing. 1: Apply any of the following enabled test conditions: J/K, DCK, 1: Enable full-speed pull up resistor on D+ SE0, RSF, RSL, PRD 0: Pull up resistor is not connected on D+ 0: Do not apply test conditions Force Select (Bits [2:0]) Port 1B Diagnostic Enable (Bit 13) The Force Select field bit selects several different test condition The Port 1B Diagnostic Enable bit enables or disables Port 1B states on the data lines (D+/D–). Refer to Table32 for details. for the test conditions selected in this register. Table 32. Force Select Definition 1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD Force Select [2:0] Data Line State 0: Do not apply test conditions 1xx Assert SE0 01x Toggle JK Port 1A Diagnostic Enable (Bit 12) 001 Assert J The Port 1A Diagnostic Enable bit enables or disables Port 1A for the test conditions selected in this register. 000 Assert K 1: Apply any of the following enabled test conditions: J/K, DCK, Reserved SE0, RSF, RSL, PRD Write all reserved bits with ’0’. 0: Do not apply test conditions Document Number: 38-08015 Rev. *P Page 24 of 119

CY7C67300 Memory Diagnostic Register [0xC03E] [W] Table 33. Memory Diagnostic Register Bit # 15 14 13 12 11 10 9 8 Reserved Memory Arbitration Field Select Read/Write - - - - - W W W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Reserved Monitor Field Enable Read/Write - - - - - - - W Default 0 0 0 0 0 0 0 0 Register Description Reserved The Memory Diagnostic register provides control of diagnostic Write all reserved bits with ’0’. modes. External Memory Registers Memory Arbitration Select (Bits[10:8]) There are four registers dedicated to controlling the external The Memory Arbitration Select field is defined in Table34. memory interface. Each of these registers are covered in this section and are summarized in Table35. Table 34. Memory Arbitration Select Table 35. External Memory Control Registers Memory Arbitration Memory Arbitration Timing Select [3:0] Register Name Address R/W 111 1/8, 7 of every 8 cycles dead Extended Page 1 Map Register 0xC018 R/W 110 2/8, 6 of every 8 cycles dead Extended Page 2 Map Register 0xC01A R/W 101 3/8, 5 of every 8 cycles dead Upper Address Enable Register 0xC038 R/W 100 4/8, 4 of every 8 cycles dead External Memory Control Register 0xC03A R/W 011 5/8, 3 of every 8 cycles dead 010 6/8, 2 of every 8 cycles dead 001 7/8, 1 of every 8 cycles dead 000 8/8, all cycles available Monitor Enable (Bit 0) The Monitor Enable bit enables or disables monitor mode. In monitor mode the internal address bus is echoed to the external address pins. 1: Enable monitor mode 0: Disable monitor mode Document Number: 38-08015 Rev. *P Page 25 of 119

CY7C67300 Extended Page n Map Register [R/W] ■Extended Page 1 Map Register 0xC018 ■Extended Page 2 Map Register 0xC01A Table 36. Extended Page n Map Register Bit # 15 14 13 12 11 10 9 8 Field Address... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Address Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description reflect the content of this register when the CPU accesses the address 0x8000-0x9FFF. For the SRAM mode, the address pin The Extended Page n Map register contains the Page n high- on [4:0] (Page n address [17:13]) is used. order address bits. These bits are always appended to accesses to the Page n Memory mapped space. Set bit [8] (Page n address [21]) to ‘0’, so that Page n reads/ writes access external areas (SRAM, ROM or peripherals). Address (Bits [15:0]) nXMEMSEL is the external chip select for this space. The Address field contains the high-order bits 28 to 13 of the Page n address. The address pins [8:0] (Page n address [21:13]) Upper Address Enable Register [0xC038] [R/W] Table 37. External Memory Control Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Read/Write - - - - - - - - Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 Reserved Upper Reserved Address Field Enable Read/Write - - - - R/W Default X X X X 0 X X X Register Description Upper Address Enable (Bit 3) The Upper Address Enable register enables/disables the four The Upper Address Enable bit enables/disables the four most most significant bits of the external address A[18:15]. This significant bits of the external address A[18:15]. register defaults to having the Upper Address disabled. Note that 1: Enable A[18:15] of the external memory interface for general on power up, pins A[18:15] are driven high. addressing. 0: Disable A[18:15], not available. Reserved Write all reserved bits with ’0’. Document Number: 38-08015 Rev. *P Page 26 of 119

CY7C67300 External Memory Control Register [0xC03A] [R/W] Table 38. External Memory Control Register Bit # 15 14 13 12 11 10 9 8 Reserved XRAM Merge XROM Merge XMEM Width XMEM Wait Field Enable Enable Select Select Read/Write - - R/W R/W R/W R/W R/W R/W Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 XROM Width XROM Wait XRAM Width XRAM Wait Field Select Select Select Select Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X X X X X Register Description XROM Wait Select (Bits[6:4]) The External Memory Control register provides control of Wait The XROM Wait Select field selects the external ROM wait state States for the external SRAM or ROM. All wait states are based from 0 to 7. off of 48 MHz. XRAM Width Select (Bit 3) XRAM Merge Enable (Bit 13) The XRAM Width Select bit selects the external RAM width. The XRAM Merge Enable bit enables or disables the RAM merge 1: External memory = 8 feature. When the RAM merge feature is enabled, the nXRAMSEL is active whenever the nXMEMSEL is active. 0: External memory = 16 1: Enable RAM merge XRAM Wait Select (Bits[2:0]) 0: Disable RAM merge The XRAM Wait Select field selects the external RAM wait state from 0 to 7. XROM Merge Enable (Bit 12) The XROM Merge Enable bit enables or disables the ROM Reserved merge feature. When the ROM merge feature is enabled, the Write all reserved bits with ’0’. nXROMSEL is active whenever the nXMEMSEL is active. Timer Registers 1: Enable ROM merge 0: Disable ROM merge There are three registers dedicated to timer operations. Each of these registers are discussed in this section and are summarized XMEM Width Select (Bit 11) in Table39. The XMEM Width Select bit selects the extended memory width. Table 39. Timer Registers 1: Extended memory = 8 Register Name Address R/W 0: Extended memory = 16 Watchdog Timer Register 0xC00C R/W XMEM Wait Select (Bits [10:8]) Timer 0 Register 0xC010 R/W The XMEM Wait Select field selects the extended memory wait Timer 1 Register 0xC012 R/W state from 0 to 7. XROM Width Select (Bit 7) The XROM Width Select bit selects the external ROM width. 1: External memory = 8 0: External memory = 16 Document Number: 38-08015 Rev. *P Page 27 of 119

CY7C67300 Watchdog Timer Register [0xC00C] [R/W] Table 40. Watchdog Timer Register Bit # 15 14 13 12 11 10 9 8 Field Reserved... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 ...Reserved Timeout Period Lock WDT Reset Field Flag Select Enable Enable Strobe Read/Write R/W R/W R/W R/W R/W R/W R/W W Default 0 0 0 0 0 0 0 0 Register Description Lock Enable (Bit 2) The Watchdog Timer register provides status and control over The Lock Enable bit does not allow any writes to this register until the Watchdog timer. The Watchdog timer can also interrupt the a reset. In doing so the Watchdog timer can be set up and processor. enabled permanently so that it can only be cleared on reset (the WDT Enable bit is ignored). Timeout Flag (Bit 5) 1: Watchdog timer permanently set The Timeout Flag bit indicates if the Watchdog timer expired. The 0: Watchdog timer not permanently set processor can read this bit after exiting a reset to determine if a Watchdog timeout occurred. This bit is cleared on the next WDT Enable (Bit 1) external hardware reset. The WDT Enable bit enables or disables the Watchdog timer. 1: Watchdog timer expired. 1: Enable Watchdog timer operation 0: Watchdog timer did not expire. 0: Disable Watchdog timer operation Period Select (Bits [4:3]) Reset Strobe (Bit 0) The Period Select field is defined in Table41. If this time expires before the Reset Strobe bit is set, the internal processor is reset. The Reset Strobe is a write-only bit that resets the Watchdog timer count. Set this bit to ‘1’ before the count expires to avoid a Table 41. Period Select Definition Watchdog trigger Period Select[4:3] WDT Period Value 1: Reset Count 00 1.4 ms Reserved 01 5.5 ms Write all reserved bits with ’0’. 10 22.0 ms 11 66.0 ms Document Number: 38-08015 Rev. *P Page 28 of 119

CY7C67300 Timer n Register [R/W] ■Timer 0 Register 0xC010 ■Timer 1 Register 0xC012 Table 42. Timer n Register Bit # 15 14 13 12 11 10 9 8 Field Count... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 Bit # 7 6 5 4 3 2 1 0 Field ...Count Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 Register Description functions for both USB host and USB peripheral options and is covered in this section and summarized in Table43. USB Host The Timer n Register sets the Timer n count. Both Timer 0 and only registers are covered in UART Interface [3] on page 9, and Timer 1 decrement by one every 1 µs clock tick. Each can USB device only registers are covered in External Memory provide an interrupt to the CPU when the timer reaches zero. Registers on page 25. Count (Bits [15:0]) Table 43. General USB Registers The Count field sets the Timer count. Register Name Address (SIE1/SIE2) R/W General USB Registers [10] USB n Control Register 0xC08A/0xC0AA R/W There is one set of registers dedicated to general USB control. This set consists of two identical registers: one for Host/Device Port 1 and one for Host/Device Port 2. This register set has Note 10.Errata: Writing to the SIE2 Control register via HPI can corrupt the SIE1 Control register. Writing to the SIE1 Control register via HPI can corrupt the SIE2 Control register. Please refer to Errata on page 107 for details and workaround. Document Number: 38-08015 Rev. *P Page 29 of 119

CY7C67300 USB n Control Register [R/W] ■USB 1 Control Register 0xC08A ■USB 2 Control Register 0xC0AA Table 44. USB n Control Register Bit # 15 14 13 12 11 10 9 8 Port B Port B Port A Port A LOB LOA Mode Port B D+ D– D+ D– Select Resistors Field Status Status Status Status Enable Read/Write R R R R R/W R/W R/W R/W Default X X X X 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Port A Port B Port A Suspend Port B Port A Resistors Force D± Force D± Enable SOF/EOP SOF/EOP Field Enable State State Enable Enable Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Port B D+ Status (Bit 15) The USB n Control register is used in both host and device mode. The Port B D+ Status bit is a read only bit that indicates the value It monitors and controls the SIE and the data lines of the USB of DATA+ on Port B. ports. This register can be accessed by the HPI interface. 1: D+ is HIGH 0: D+ is LOW Document Number: 38-08015 Rev. *P Page 30 of 119

CY7C67300 Port B D– Status (Bit 14) When the Mode Select is set for Device mode, a single pull up resistor on either D+ or D–, determined by the LOA bit, is The Port B D– Status bit is a read only bit that indicates the value enabled. See Table45 for details. of DATA– on Port B. 1: Enable pull up/pull down resistors 1: D– is HIGH 0: Disable pull up/pull down resistors 0: D– is LOW Table 45. USB Data Line Pull Up and Pull Down Resistors Port A D+ Status (Bit 13) The Port A D+ Status bit is a read only bit that indicates the value L0A/ Mode Port n Resistors Function of DATA+ on Port A. L0B Select Enable 1: D+ is HIGH X X 0 Pull up/Pull down on D+ and 0: D+ is LOW D– Disabled Port A D– Status (Bit 12) X 1 1 Pull down on D+ and D– Enabled The Port A D– Status bit is a read only bit that indicates the value 1 0 1 Pull up on USB D– Enabled of DATA– on Port A. 0 0 1 Pull up on USB D+ Enabled 1: D– is HIGH 0: D– is LOW Port B Force D± State (Bits [6:5]) LOB (Bit 11) The Port B Force D± State field controls the forcing state of the The LOB bit selects the speed of Port B. D+ D– data lines for Port B. This field forces the state of the Port B data lines independent of the Port Select bit setting. See 1: Port B is set to low-speed mode Table46 for details. 0: Port B is set to full-speed mode Port A Force D± State (Bits [4:3]) LOA (Bit 10) The Port A Force D± State field controls the forcing state of the The LOA bit selects the speed of Port A. D+ D– data lines for Port A. This field forces the state of the Port A data lines independent of the Port Select bit setting. See 1: Port A is set to low-speed mode Table46 for details. 0: Port A is set to full-speed mode Table 46. Port A/B Force D± State Mode Select (Bit 9) Port A/B Force D± State Function The Mode Select bit sets the SIE for host or device operation. MSb LSb When set for device operation only one USB port is supported. The active port is selected by the Port Select bit in the Host n 0 0 Normal Operation Count register. 1 0 Force USB Reset, SE0 State 1: Host mode 0 1 Force J-State 0: Device mode 1 1 Force K-State Port B Resistors Enable (Bit 8) Suspend Enable (Bit 2) The Port B Resistors Enable bit enables or disables the pull up/ pull down resistors on Port B. When enabled, the Mode Select The Suspend Enable bit enables or disables the suspend feature bit and LOB bit of this register set the pull up/pull down resistors on both ports. When suspend is enabled the USB transceivers appropriately. When the Mode Select is set for Host mode, the are powered down and cannot transmit or received USB packets pull down resistors on the data lines (D+ and D–) are enabled. but can still monitor for a wakeup condition. When the Mode Select is set for Device mode, a single pull up 1: Enable suspend resistor on either D+ or D–, determined by the LOB bit, is 0: Disable suspend enabled. See Table45 for details. 1: Enable pull up/pull down resistors Port B SOF/EOP Enable (Bit 1) 0: Disable pull up/pull down resistors The Port B SOF/EOP Enable bit is only applicable in host mode. In device mode, this bit must be written as ‘0’. In host mode this Port A Resistors Enable (Bit 7) bit enables or disables SOFs or EOPs for Port B. Either SOFs or The Port A Resistors Enable bit enables or disables the pull up/ EOPs are generated depending on the LOB bit in the USB n pull down resistors on Port A. When enabled, the Mode Select Control register when Port B is active. bit and LOA bit of this register set the pull up/pull down resistors 1: Enable SOFs or EOPs appropriately. When the Mode Select is set for Host mode, the 0: Disable SOFs or EOPs pull down resistors on the data lines (D+ and D–) are enabled. Document Number: 38-08015 Rev. *P Page 31 of 119

CY7C67300 Port A SOF/EOP Enable (Bit 0) Reserved The Port A SOF/EOP Enable bit is only applicable in host mode. Write all reserved bits with ’0’. In device mode this bit must be written as ‘0’. In host mode this bit enables or disables SOFs or EOPs for Port A. Either SOFs or EOPs are generated depending on the LOA bit in the USB n Control register when Port A is active. 1: Enable SOFs or EOPs 0: Disable SOFs or EOPs USB Host Only Registers [11] There are twelve sets of dedicated registers for USB host only operation. Each set consists of two identical registers (unless otherwise noted), one for Host Port 1 and one for Host Port 2. These register sets are covered in this section and summarized in Table47. Table 47. USB Host Only Register Register Name Address (Host 1/Host 2) R/W Host n Control Register 0xC080/0xC0A0 R/W Host n Address Register 0xC082/0xC0A2 R/W Host n Count Register 0xC084/0xC0A4 R/W Host n Endpoint Status Register 0xC086/0xC0A6 R Host n PID Register 0xC086/0xC0A6 W Host n Count Result Register 0xC088/0xC0A8 R Host n Device Address Register 0xC088/0xC0A8 W Host n Interrupt Enable Register 0xC08C/0xC0AC R/W Host n Status Register 0xC090/0xC0B0 R/W Host n SOF/EOP Count Register 0xC092/0xC0B2 R/W Host n SOF/EOP Counter Register 0xC094/0xC0B4 R Host n Frame Register 0xC096/0xC0B6 R Note 11.Errata: The VBUS interrupt in the Host/Device Status Registers [0xC090 and 0xC0B0]] triggers multiple times whenever VBUS is turned on. It should only trigger once when VBUS rises above 4.4V and once when VBUS falls from above 4.4V to 0V. Please refer to Errata on page 107 for details and workaround. Document Number: 38-08015 Rev. *P Page 32 of 119

CY7C67300 Host n Control Register [R/W] ■Host 1 Control Register 0xC080 ■Host 2 Control Register 0xC0A0 Table 48. Host n Control Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Preamble Sequence Sync ISO Reserved Arm Field Enable Select Enable Enable Enable Read/Write R/W R/W R/W R/W - - - R/W Default 0 0 0 0 0 0 0 0 Register Description 1: The next enabled packet is transferred after the SOF or EOP packet is transmitted The Host n Control register allows high level USB transaction control. 0: The next enabled packet is transferred as soon as the SIE is free Preamble Enable (Bit 7) ISO Enable (Bit 4) The Preamble Enable bit enables or disables the transmission of The ISO Enable bit enables or disables an isochronous trans- a preamble packet before all low-speed packets. Set this bit only action. when communicating with a low-speed device. 1: Enable isochronous transaction 1: Enable Preamble packet 0: Disable isochronous transaction 0: Disable Preamble packet Arm Enable (Bit 0) Sequence Select (Bit 6) The Arm Enable bit arms an endpoint and starts a transaction. The Sequence Select bit sets the data toggle for the next packet. This bit is automatically cleared to ‘0’ when a transaction is This bit has no effect on receiving data packets; sequence complete. checking must be handled in firmware. 1: Arm endpoint and begin transaction 1: Send DATA1 0: Endpoint disarmed 0: Send DATA0 Reserved Sync Enable (Bit 5) Write all reserved bits with ’0’. The Sync Enable bit synchronizes the transfer with the SOF packet in full-speed mode and the EOP packet in low-speed mode. Document Number: 38-08015 Rev. *P Page 33 of 119

CY7C67300 Host n Address Register [R/W] ■Host 1 Address Register 0xC082 ■Host 2 Address Register 0xC0A2 Table 49. Host n Address Register Bit # 15 14 13 12 11 10 9 8 Field Address... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Address Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Address (Bits [15:0]) The Host n Address register is used as the base pointer into The Address field sets the address pointer into internal RAM or memory space for the current host transactions. ROM. Host n Count Register [R/W] ■Host 1 Count Register 0xC084. ■Host 2 Count Register 0xC0A4. Table 50. Host n Count Register Bit # 15 14 13 12 11 10 9 8 Reserved Port Reserved Count... Field Select Read/Write - R/W - - - - R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Count Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Table 51. Port Select Definition The Host n Count register is used to hold the number of bytes Host/Device 1 Host/Device 2 (packet length) for the current transaction. The maximum packet Port Select Active Port Active Port length is 1023 bytes in ISO mode. The Host Count value is used to determine how many bytes to transmit, or the maximum 0 A A number of bytes to receive. If the number of received bytes is 1 B B greater then the Host Count value then an overflow condition is flagged by the Overflow bit in the Host n Endpoint Status register. Count (Bits [9:0]) Port Select (Bit 14) The Count field sets the value for the current transaction data packet length. This value is retained when switching between The Port Select bit selects which of the two active ports is host and device mode, and back again. selected and is summarized in Table51. 1: Port 1B or Port 2B is enabled Reserved 0: Port 1A or Port 2A is enabled Write all reserved bits with ’0’. Document Number: 38-08015 Rev. *P Page 34 of 119

CY7C67300 Host n Endpoint Status Register [R] ■Host 1 Endpoint Status Register 0xC086 ■Host 2 Endpoint Status Register 0xC0A6 Table 52. Host n Endpoint Status Register Bit # 15 14 13 12 11 10 9 8 Reserved Overflow Underflow Reserved Field Flag Flag Read/Write - - - - R R - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Stall NAK Length Reserved Sequence Timeout Error ACK Flag Flag Exception Status Flag Flag Flag Field Flag Read/Write R R R - R R R R Default 0 0 0 0 0 0 0 0 Register Description Length Exception Flag (Bit 5) The Host n Endpoint Status register is a read only register that The Length Exception Flag bit indicates that the received data in provides status for the last USB transaction. the data stage of the last transaction does not equal the maximum Host Count specified in the Host n Count register. A Overflow Flag (Bit 11) Length Exception can either mean an overflow or underflow and The Overflow Flag bit indicates that the received data in the last the Overflow and Underflow flags (bits 11 and 10, respectively) data transaction exceeded the maximum length specified in the must be checked to determine which event occurred. Host n Count register. The Overflow Flag must be checked in 1: An overflow or underflow condition occurred response to a Length Exception signified by the Length 0: An overflow or underflow condition did not occur Exception Flag set to ‘1’. 1: Overflow condition occurred Sequence Status (Bit 3) 0: Overflow condition did not occur The Sequence Status bit indicates the state of the last received data toggle from the device. Firmware is responsible for Underflow Flag (Bit 10) monitoring and handling the sequence status. The Sequence bit The Underflow Flag bit indicates that the received data in the last is only valid if the ACK bit is set to ‘1’. The Sequence bit is set to data transaction was less than the maximum length specified in ‘0’ when an error is detected in the transaction and the Error bit the Host n Count register. The Underflow Flag must be checked is set. in response to a Length Exception signified by the Length 1: DATA1 Exception Flag set to ‘1’. 0: DATA0 1: Underflow condition occurred Timeout Flag (Bit 2) 0: Underflow condition did not occur The Timeout Flag bit indicates if a timeout condition occurred for Stall Flag (Bit 7) the last transaction. A timeout condition can occur when a device either takes too long to respond to a USB host request or takes The Stall Flag bit indicates that the peripheral device replied with too long to respond with a handshake. a Stall in the last transaction. 1: Timeout occurred 1: Device returned Stall 0: Timeout did not occur 0: Device did not return Stall Error Flag (Bit 1) NAK Flag (Bit 6) The Error Flag bit indicates a transaction failed for any reason The NAK Flag bit indicates that the peripheral device replied with other than the following: timeout, receiving a NAK, or receiving a NAK in the last transaction. a STALL. Overflow and Underflow are not considered errors and 1: Device returned NAK do not affect this bit. CRC5 and CRC16 errors result in an Error 0: Device did not return NAK flag along with receiving incorrect packet types. 1: Error detected 0: No error detected ACK Flag (Bit 0) Document Number: 38-08015 Rev. *P Page 35 of 119

CY7C67300 The ACK Flag bit indicates two different conditions depending on 0: For non-isochronous transfers, the transaction was not the transfer type. For non-isochronous transfers, this bit ACKed. For isochronous transfers, the transaction did not represents a transaction ending by receiving or sending an ACK complete successfully packet. For isochronous transfers, this bit represents a successful transaction that is not represented by an ACK packet. 1: For non-isochronous transfers, the transaction was ACKed. For isochronous transfers, the transaction was completed successfully Host n PID Register [W] ■Host 1 PID Register 0xC086 ■Host 2 PID Register 0xC0A6 Table 53. Host n PID Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field PID Select Endpoint Select Read/Write W W W W W W W W Default 0 0 0 0 0 0 0 0 Register Description Endpoint Select (Bits [3:0]) The Host n PID register is a write only register that provides the The Endpoint field allows addressing of up to 16 different PID and Endpoint information to the USB SIE to be used in the endpoints. next transaction. Reserved PID Select (Bits [7:4]) Write all reserved bits with ’0’. The PID Select field is defined in Table54. ACK and NAK tokens are automatically sent based on settings in the Host n Control register and do not need to be written in this register. Table 54. PID Select Definition PID TYPE PID Select [7:4] SETUP 1101 (D Hex) IN 1001 (9 Hex) OUT 0001 (1 Hex) SOF 0101 (5 Hex) PREAMBLE 1100 (C Hex) NAK 1010 (A Hex) STALL 1110 (E Hex) DATA0 0011 (3 Hex) DATA1 1011 (B Hex) Document Number: 38-08015 Rev. *P Page 36 of 119

CY7C67300 Host n Count Result Register [R] ■Host 1 Count Result Register 0xC088 ■Host 2 Count Result Register 0xC0A8 Table 55. Host n Count Result Register Bit # 15 14 13 12 11 10 9 8 Field Result... Read/Write R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Result Read/Write R R R R R R R R Default 0 0 0 0 0 0 0 0 Register Description Result (Bits [15:0]) The Host n Count Result register is a read only register that The Result field contains the differences in bytes between the contains the size difference in bytes between the Host Count received packet and the value specified in the Host n Count Value specified in the Host n Count register and the last packet register. If an overflow condition occurs, Result [15:10] is set to received. If an overflow or underflow condition occurs, that is the ‘111111’, a 2’s complement value indicating the additional byte received packet length differs from the value specified in the Host count of the received packet. If an underflow condition occurs, n Count register, the Length Exception Flag bit in the Host n Result [15:0] indicates the excess bytes count (number of bytes Endpoint Status register is set. The value in this register is only not used). value when the Length Exception Flag bit is set and the Error Flag bit is not set, both bits are in the Host n Endpoint Status Reserved register. Write all reserved bits with ’0’. Document Number: 38-08015 Rev. *P Page 37 of 119

CY7C67300 Host n Device Address Register [W] ■Host 1 Device Address Register 0xC088 ■Host 2 Device Address Register 0xC0A8 Table 56. Host n Device Address Register Bit # 15 14 13 12 11 10 9 8 Field Reserved... Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Reserved Address Read/Write - W W W W W W W Default 0 0 0 0 0 0 0 0 Register Description Address (Bits [6:0]) The Host n Device Address register is a write only register that The Address field contains the value of the USB address for the contains the USB Device Address that the host wants to commu- next device that the host is going to communicate with. This nicate with. value must be written by firmware. Reserved Write all reserved bits with ’0’. Document Number: 38-08015 Rev. *P Page 38 of 119

CY7C67300 Host n Interrupt Enable Register [R/W] ■Host 1 Interrupt Enable Register 0xC08C ■Host 2 Interrupt Enable Register 0xC0AC Table 57. Host n Interrupt Enable Register Bit # 15 14 13 12 11 10 9 8 VBUS ID Interrupt Reserved SOF/EOP Reserved Interrupt Enable Interrupt Field Enable Enable Read/Write R/W R/W - - - - R/W - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Port B Port A Port B Connect Port A Connect Reserved Done Wake Interrupt Wake Interrupt Change Change Interrupt Enable Enable Interrupt Interrupt Enable Field Enable Enable Read/Write R/W R/W R/W R/W - - - R/W Default 0 0 0 0 0 0 0 0 Register Description 0: Disable remote wakeup interrupt for Port B The Host n Interrupt Enable register enables control over host Port A Wake Interrupt Enable (Bit 6) related interrupts. The Port A Wake Interrupt Enable bit enables or disables the In this register a bit set to ‘1’ enables the corresponding interrupt remote wakeup interrupt for Port A while ‘0’ disables the interrupt. 1: Enable remote wakeup interrupt for Port A VBUS Interrupt Enable (Bit 15) 0: Disable remote wakeup interrupt for Port A The VBUS Interrupt Enable bit enables or disables the OTG VBUS interrupt. When enabled this interrupt triggers on both the Port B Connect Change Interrupt Enable (Bit 5) rising and falling edge of VBUS at the 4.4V status (only The Port B Connect Change Interrupt Enable bit enables or supported in Port 1A). This bit is only available for Host 1 and is disables the Port B Connect Change interrupt on Port B. This a reserved bit in Host 2. interrupt triggers when either a device is inserted (SE0 state to J 1: Enable VBUS interrupt state) or a device is removed (J state to SE0 state). 0: Disable VBUS interrupt 1: Enable Connect Change interrupt 0: Disable Connect Change interrupt ID Interrupt Enable (Bit 14) The ID Interrupt Enable bit enables or disables the OTG ID Port A Connect Change Interrupt Enable (Bit 4) interrupt. When enabled this interrupt triggers on both the rising The Port A Connect Change Interrupt Enable bit enables or and falling edge of the OTG ID pin (only supported in Port 1A). disables the Connect Change interrupt on Port A. This interrupt This bit is only available for Host 1 and is a reserved bit in Host 2. triggers when either a device is inserted (SE0 state to J state) or 1: Enable ID interrupt a device is removed (J state to SE0 state). 0: Disable ID interrupt 1: Enable Connect Change interrupt 0: Disable Connect Change interrupt SOF/EOP Interrupt Enable (Bit 9) Done Interrupt Enable (Bit 0) The SOF/EOP Interrupt Enable bit enables or disables the SOF/ The Done Interrupt Enable bit enables or disables the USB EOP timer interrupt Transfer Done interrupt. The USB Transfer Done triggers when either the host responds with an ACK, or a device responds with 1: Enable SOF/EOP timer interrupt any of the following: ACK, NAK, STALL, or Timeout. This 0: Disable SOF/EOP timer interrupt interrupt is used for both Port A and Port B. 1: Enable USB Transfer Done interrupt Port B Wake Interrupt Enable (Bit 7) 0: Disable USB Transfer Done interrupt The Port B Wake Interrupt Enable bit enables or disables the remote wakeup interrupt for Port B Reserved 1: Enable remote wakeup interrupt for Port B Write all reserved bits with ’0’. Document Number: 38-08015 Rev. *P Page 39 of 119

CY7C67300 Host n Status Register [R/W] ■Host 1 Status Register 0xC090 ■Host 2 Status Register 0xC0B0 Table 58. Host n Status Register Bit # 15 14 13 12 11 10 9 8 VBUS Interrupt ID Interrupt Reserved SOF/EOP Reserved Field Flag Flag Interrupt Flag Read/Write R/W R/W - - - - R/W - Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 Port B Port A Port B Connect Port A Connect Port B Port A Reserved Done Interrupt Wake Interrupt Wake Interrupt Change Change Interrupt SE0 SE0 Flag Field Flag Flag Interrupt Flag Flag Status Status Read/Write R/W R/W R/W R/W R/W R/W - R/W Default X X X X X X X X Register Description Port A Wake Interrupt Flag (Bit 6) The Host n Status register provides status information for host The Port A Wake Interrupt Flag bit indicates remote wakeup on operation. Pending interrupts can be cleared by writing a ‘1’ to PortA. the corresponding bit. This register can be accessed by the HPI 1: Interrupt triggered interface. 0: Interrupt did not trigger VBUS Interrupt Flag (Bit 15) Port B Connect Change Interrupt Flag (Bit 5) The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt (only for Port 1A). When enabled this interrupt The Port B Connect Change Interrupt Flag bit indicates the triggers on both the rising and falling edge of VBUS at 4.4V. This status of the Connect Change interrupt on Port B. This bit bit is only available for Host 1 and is a reserved bit in Host2. triggers ‘1’ on either a rising edge or falling edge of a USB Reset condition (device inserted or removed). Together with the Port B 1: Interrupt triggered SE0 Status bit, it can be determined whether a device was 0: Interrupt did not trigger inserted or removed. 1: Interrupt triggered ID Interrupt Flag (Bit 14) 0: Interrupt did not trigger The ID Interrupt Flag bit indicates the status of the OTG ID interrupt (only for Port 1A). When enabled this interrupt triggers Port A Connect Change Interrupt Flag (Bit 4) on both the rising and falling edge of the OTG ID pin. This bit is only available for Host 1 and is a reserved bit in Host2. The Port A Connect Change Interrupt Flag bit indicates the status of the Connect Change interrupt on Port A. This bit 1: Interrupt triggered triggers ‘1’ on either a rising edge or falling edge of a USB Reset 0: Interrupt did not trigger condition (device inserted or removed). Together with the Port A SE0 Status bit, it can be determined whether a device was SOF/EOP Interrupt Flag (Bit 9) inserted or removed. The SOF/EOP Interrupt Flag bit indicates the status of the SOF/ 1: Interrupt triggered EOP Timer interrupt. This bit triggers ‘1’ when the SOF/EOP 0: Interrupt did not trigger timer expires. 1: Interrupt triggered Port B SE0 Status (Bit 3) 0: Interrupt did not trigger The Port B SE0 Status bit indicates if Port B is in a SE0 state or not. Together with the Port B Connect Change Interrupt Flag bit, Port B Wake Interrupt Flag (Bit 7) it can be determined whether a device was inserted (non-SE0 The Port B Wake Interrupt Flag bit indicates remote wakeup on condition) or removed (SE0 condition). PortB. 1: SE0 condition 1: Interrupt triggered 0: Interrupt did not trigger 0: Non-SE0 condition Document Number: 38-08015 Rev. *P Page 40 of 119

CY7C67300 Port A SE0 Status (Bit 2) Done Interrupt Flag (Bit 0) The Port A SE0 Status bit indicates if Port A is in a SE0 state or The Done Interrupt Flag bit indicates the status of the USB not. Together with the Port A Connect change Interrupt Flag bit, Transfer Done interrupt. The USB Transfer Done triggers when it can be determined whether a device was inserted (non-SE0 either the host responds with an ACK, or a device responds with condition) or removed (SE0 condition). any of the following: ACK, NAK, STALL, or Timeout. This interrupt is used for both Port A and Port B. 1: SE0 condition 1: Interrupt triggered 0: Non-SE0 condition 0: Interrupt did not trigger Host n SOF/EOP Count Register [R/W] ■Host 1 SOF/EOP Count Register 0xC092 ■Host 2 SOF/EOP Count Register 0xC0B2 Table 59. Host n SOF/EOP Count Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Count... Read/Write - - R/W R/W R/W R/W R/W R/W Default 0 0 1 0 1 1 1 0 Bit # 7 6 5 4 3 2 1 0 Field ...Count Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 0 0 0 0 0 Register Description read, the value returned is the programmed SOF/EOP count value. The Host n SOF/EOP Count register contains the SOF/EOP Count Value that is loaded into the SOF/EOP counter. This value Count (Bits [13:0]) is loaded each time the SOF/EOP counter counts down to zero. The Count field sets the SOF/EOP counter duration. The default value set in this register at power up is 0x2EE0 which generates a 1 ms time frame. The SOF/EOP counter is a down Reserved counter decremented at a 12 MHz rate. When this register is Write all reserved bits with ’0’. Host n SOF/EOP Counter Register [R] ■Host 1 SOF/EOP Counter Register 0xC094 ■Host 2 SOF/EOP Counter Register 0xC0B4 Table 60. Host n SOF/EOP Counter Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Counter... Read/Write - - R R R R R R Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 Field ...Counter Read/Write R R R R R R R R Default X X X X X X X X Register Description Counter (Bits [13:0]) The Host n SOF/EOP Counter register contains the current value The Counter field contains the current value of the SOF/EOP of the SOF/EOP down counter. This value can be used to down counter. determine the time remaining in the current frame. Document Number: 38-08015 Rev. *P Page 41 of 119

CY7C67300 Host n Frame Register [R] ■Host 1 Frame Register 0xC096 ■Host 2 Frame Register 0xC0B6 Table 61. Host n Frame Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Frame... Read/Write - - - - - R R R Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Frame Read/Write R R R R R R R R Default 0 0 0 0 0 0 0 0 Register Description Frame (Bits [10:0]) The Host n Frame register maintains the next frame number to The Frame field contains the next frame number to be trans- be transmitted (current frame number + 1). This value is updated mitted. after each SOF transmission. This register resets to 0x0000 after each CPU write to the Host n SOF/EOP Count register (Host 1: Reserved 0xC092 Host 2: 0xC0B2). Write all reserved bits with ’0’. Document Number: 38-08015 Rev. *P Page 42 of 119

CY7C67300 USB Device Only Registers There are eleven sets of USB Device Only registers. All sets consist of at least two registers, one for Device Port 1 and one for Device Port 2. In addition, each Device port has eight possible endpoints. This gives each endpoint register set eight registers for each Device Port for a total of sixteen registers per set. The USB Device Only registers are covered in this section and summarized in Table62. Table 62. USB Device Only Registers Register Name Address (Device 1/Device 2) R/W Device n Endpoint n Control Register 0x02n0 R/W Device n Endpoint n Address Register 0x02n2 R/W Device n Endpoint n Count Register 0x02n4 R/W Device n Endpoint n Status Register 0x02n6 R/W Device n Endpoint n Count Result Register 0x02n8 R/W Device n Port Select Register 0xC084/0xC0A4 R/W Device n Interrupt Enable Register 0xC08C/0xC0AC R/W Device n Address Register 0xC08E/0xC0AE R/W Device n Status Register 0xC090/0xCB0 R/W Device n Frame Number Register 0xC092/0xC0B2 R Device n SOF/EOP Count Register 0xC094/0xC0B4 W Device n Endpoint n Control Register [R/W] ■Device n Endpoint 0 Control Register [Device 1: 0x0200 Device 2: 0x0280] ■Device n Endpoint 1 Control Register [Device 1: 0x0210 Device 2: 0x0290] ■Device n Endpoint 2 Control Register [Device 1: 0x0220 Device 2: 0x02A0] ■Device n Endpoint 3 Control Register [Device 1: 0x0230 Device 2: 0x02B0] ■Device n Endpoint 4 Control Register [Device 1: 0x0240 Device 2: 0x02C0] ■Device n Endpoint 5 Control Register [Device 1: 0x0250 Device 2: 0x02D0] ■Device n Endpoint 6 Control Register [Device 1: 0x0260 Device 2: 0x02E0] ■Device n Endpoint 7 Control Register [Device 1: 0x0270 Device 2: 0x02F0] Table 63. Device n Endpoint n Control Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Read/Write - - - - - - - - Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 IN/OUT Sequence Stall ISO NAK Direction Enable Arm Ignore Select Enable Enable Interrupt Select Enable Field Enable Enable Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X X X X X Register Description IN/OUT Ignore Enable (Bit 7) The Device n Endpoint n Control register provides control over a The IN/OUT Ignore Enable bit forces endpoint 0 (EP0) to ignore single EP in device mode. There are a total of eight endpoints for all IN and OUT requests. Set this bit so that EP0 only accepts each of the two ports. All endpoints have the same definition for Setup packets at the start of each transfer. Clear this bit to accept their Device n Endpoint n Control register. IN/OUT transactions. This bit only applies to EP0. 1: Ignore IN/OUT requests 0: Do not ignore IN/OUT requests Document Number: 38-08015 Rev. *P Page 43 of 119

CY7C67300 Sequence Select (Bit 6) Direction Select (Bit 2) The Sequence Select bit determines whether a DATA0 or a The Direction Select bit needs to be set according to the DATA1 is sent for the next data toggle. This bit has no effect on expected direction of the next data stage in the next transaction. receiving data packets; sequence checking must be handled in If the data stage direction is different from what is set in this bit, firmware. it gets NAKed and either the IN Exception Flag or the OUT 1: Send a DATA1 Exception Flag is set in the Device n Endpoint n Status register. If a setup packet is received and the Direction Select bit is set 0: Send a DATA0 incorrectly, the setup is ACKed and the Setup Status Flag is set (refer to the setup bit of the Device n Endpoint n Status Register Stall Enable (Bit 5) [R/W] on page 46 for details). The Stall Enable bit sends a Stall in response to the next request 1: OUT transfer (host to device) (unless it is a setup request, which are always ACKed). This is a sticky bit and continues to respond with Stalls until cleared by 0: IN transfer (device to host) firmware. Enable (Bit 1) 1: Send Stall Set the Enable bit to allow transfers to the endpoint. If Enable is 0: Do not send Stall set to ‘0’ then all USB traffic to this endpoint is ignored. If Enable ISO Enable (Bit 4) is set ‘1’ and Arm Enable (bit 0) is set ‘0’ then NAKs are automat- ically returned from this endpoint (except setup packets which The ISO Enable bit enables and disables an isochronous trans- are always ACKed as long as the Enable bit is set). action. This bit is only valid for EPs 1–7 and has no function for EP0. 1: Enable transfers to an endpoint 1: Enable isochronous transaction 0: Do not allow transfers to an endpoint 0: Disable isochronous transaction Arm Enable (Bit 0) NAK Interrupt Enable (Bit 3) The Arm Enable bit arms the endpoint to transfer or receive a packet. This bit is cleared to ‘0’ when a transaction is complete. The NAK Interrupt Enable bit enables and disables the gener- ation of an Endpoint n interrupt when the device responds to the 1: Arm endpoint host with a NAK. The Endpoint n Interrupt Enable bit in the 0: Endpoint disarmed Device n Interrupt Enable register must also be set. When a NAK is sent to the host, the corresponding EP Interrupt Flag in the Reserved Device n Status register is set. In addition, the NAK Flag in the Write all reserved bits with ’0’. Device n Endpoint n Status register is set. 1: Enable NAK interrupt 0: Disable NAK interrupt Device n Endpoint n Address Register [R/W] ■Device n Endpoint 0 Address Register [Device 1: 0x0202 Device 2: 0x0282] ■Device n Endpoint 1 Address Register [Device 1: 0x0212 Device 2: 0x0292] ■Device n Endpoint 2 Address Register [Device 1: 0x0222 Device 2: 0x02A2] ■Device n Endpoint 3 Address Register [Device 1: 0x0232 Device 2: 0x02B2] ■Device n Endpoint 4 Address Register [Device 1: 0x0242 Device 2: 0x02C2] ■Device n Endpoint 5 Address Register [Device 1: 0x0252 Device 2: 0x02D2] ■Device n Endpoint 6 Address Register [Device 1: 0x0262 Device 2: 0x02E2] ■Device n Endpoint 7 Address Register [Device 1: 0x0272 Device 2: 0x02F2] Table 64. Device n Endpoint n Address Register Bit # 15 14 13 12 11 10 9 8 Field Address... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 Field ...Address Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X X X X X Document Number: 38-08015 Rev. *P Page 44 of 119

CY7C67300 Register Description Address (Bits [15:0]) The Device n Endpoint n Address register is used as the base The Address field sets the base address for the current trans- pointer into memory space for the current Endpoint transaction. action on a signal endpoint. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Address register. Device n Endpoint n Count Register [R/W] ■Device n Endpoint 0 Count Register [Device 1: 0x0204 Device 2: 0x0284] ■Device n Endpoint 1 Count Register [Device 1: 0x0214 Device 2: 0x0294] ■Device n Endpoint 2 Count Register [Device 1: 0x0224 Device 2: 0x02A4] ■Device n Endpoint 3 Count Register [Device 1: 0x0234 Device 2: 0x02B4] ■Device n Endpoint 4 Count Register [Device 1: 0x0244 Device 2: 0x02C4] ■Device n Endpoint 5 Count Register [Device 1: 0x0254 Device 2: 0x02D4] ■Device n Endpoint 6 Count Register [Device 1: 0x0264 Device 2: 0x02E4] ■Device n Endpoint 7 Count Register [Device 1: 0x0274 Device 2: 0x02F4] Table 65. Device n Endpoint n Count Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Count... Read/Write - - - - - - R/W R/W Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 Field ...Count Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X X X X X Register Description Count (Bits [9:0]) The Device n Endpoint n Count register designates the The Count field sets the current transaction packet length for a maximum packet size that can be received from the host for OUT single endpoint. transfers for a single endpoint. This register also designates the packet size to be sent to the host in response to the next IN token Reserved for a single endpoint. The maximum packet length is 1023 bytes Write all reserved bits with ’0’. in ISO mode. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Count register. Document Number: 38-08015 Rev. *P Page 45 of 119

CY7C67300 Device n Endpoint n Status Register [R/W] ■Device n Endpoint 0 Status Register [Device 1: 0x0206 Device 2: 0x0286] ■Device n Endpoint 1 Status Register [Device 1: 0x0216 Device 2: 0x0296] ■Device n Endpoint 2 Status Register [Device 1: 0x0226 Device 2: 0x02A6] ■Device n Endpoint 3 Status Register [Device 1: 0x0236 Device 2: 0x02B6] ■Device n Endpoint 4 Status Register [Device 1: 0x0246 Device 2: 0x02C6] ■Device n Endpoint 5 Status Register [Device 1: 0x0256 Device 2: 0x02D6] ■Device n Endpoint 6 Status Register [Device 1: 0x0266 Device 2: 0x02E6] ■Device n Endpoint 7 Status Register [Device 1: 0x0276 Device 2: 0x02F6] Table 66. Device n Endpoint n Status Register Bit # 15 14 13 12 11 10 9 8 Reserved Overflow Underflow OUT IN Field Flag Flag Exception Flag Exception Flag Read/Write - - - - R/W R/W R/W R/W Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 Stall NAK Length Setup Sequence Timeout Error ACK Field Flag Flag Exception Flag Flag Flag Flag Flag Flag Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X X X X X Register Description OUT Exception Flag (Bit 9) The Device n Endpoint n Status register provides packet status The OUT Exception Flag bit indicates when the device received information for the last transaction received or transmitted. This an OUT packet when armed for an IN. register is updated in hardware and does not need to be cleared 1: Received OUT when armed for IN by firmware. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device 0: Received IN when armed for IN n Endpoint n Status register. IN Exception Flag (Bit 8) The Device n Endpoint n Status register is a memory based The IN Exception Flag bit indicates when the device received an register that must be initialized to 0x0000 before USB Device IN packet when armed for an OUT. operations are initiated. After initialization, do not write to this register again. 1: Received IN when armed for OUT 0: Received OUT when armed for OUT Overflow Flag (Bit 11) The Overflow Flag bit indicates that the received data in the last Stall Flag (Bit 7) data transaction exceeded the maximum length specified in the The Stall Flag bit indicates that a Stall packet was sent to the Device n Endpoint n Count register. The Overflow Flag must be host. checked in response to a Length Exception signified by the Length Exception Flag set to ‘1’. 1: Stall packet was sent to the host 1: Overflow condition occurred 0: Stall packet was not sent 0: Overflow condition did not occur NAK Flag (Bit 6) Underflow Flag (Bit 10) The NAK Flag bit indicates that a NAK packet was sent to the host. The Underflow Flag bit indicates that the received data in the last data transaction was less then the maximum length specified in 1: NAK packet was sent to the host the Device n Endpoint n Count register. The Underflow Flag must 0: NAK packet was not sent be checked in response to a Length Exception signified by the Length Exception Flag set to ‘1’. Length Exception Flag (Bit 5) 1: Underflow condition occurred The Length Exception Flag bit indicates the received data in the data stage of the last transaction does not equal the maximum 0: Underflow condition did not occur Endpoint Count specified in the Device n Endpoint n Count register. A Length Exception can either mean an overflow or Document Number: 38-08015 Rev. *P Page 46 of 119

CY7C67300 underflow and the Overflow and Underflow flags (bits 11 and 10 Timeout Flag (Bit 2) respectively) must be checked to determine which event The Timeout Flag bit indicates whether a timeout condition occurred. occurred on the last transaction. On the device side, a timeout 1: An overflow or underflow condition occurred can occur if the device sends a data packet in response to an IN request but then does not receive a handshake packet in a 0: An overflow or underflow condition did not occur predetermined time. It can also occur if the device does not Setup Flag (Bit 4) receive the data stage of an OUT transfer in time. The Setup Flag bit indicates that a setup packet was received. 1: Timeout occurred In device mode setup packets are stored at memory location 0: Timeout condition did not occur 0x0300 for Device 1 and 0x0308 for Device 2. Setup packets are always accepted regardless of the Direction Select and Arm Error Flag (Bit 2) Enable bit settings as long as the Device n EP n Control register The Error Flag bit is set if a CRC5 and CRC16 error occurs, or if Enable bit is set. an incorrect packet type is received. Overflow and underflow are 1: Setup packet was received not considered errors and do not affect this bit. 0: Setup packet was not received 1: Error occurred 0: Error did not occur Sequence Flag (Bit 3) The Sequence Flag bit indicates whether the last data toggle ACK Flag (Bit 0) received was a DATA1 or a DATA0. This bit has no effect on The ACK Flag bit indicates whether the last transaction was receiving data packets; sequence checking must be handled in ACKed. firmware. 1: ACK occurred 1: DATA1 was received 0: ACK did not occur 0: DATA0 was received Device n Endpoint n Count Result Register [R/W] ■Device n Endpoint 0 Count Result Register [Device 1: 0x0208 Device 2: 0x0288] ■Device n Endpoint 1 Count Result Register [Device 1: 0x0218 Device 2: 0x0298] ■Device n Endpoint 2 Count Result Register [Device 1: 0x0228 Device 2: 0x02A8] ■Device n Endpoint 3 Count Result Register [Device 1: 0x0238 Device 2: 0x02B8] ■Device n Endpoint 4 Count Result Register [Device 1: 0x0248 Device 2: 0x02C8] ■Device n Endpoint 5 Count Result Register [Device 1: 0x0258 Device 2: 0x02D8] ■Device n Endpoint 6 Count Result Register [Device 1: 0x0268 Device 2: 0x02E8] ■Device n Endpoint 7 Count Result Register [Device 1: 0x0278 Device 2: 0x02F8] Table 67. Device n Endpoint n Count Result Register Bit # 15 14 13 12 11 10 9 8 Field Result... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 Field ...Result Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X X X X X Register Description Endpoint n Count register, the Length Exception Flag bit in the Device n Endpoint n Status register is set. The value in this The Device n Endpoint n Count Result register contains the size register is only valued when the Length Exception Flag bit is set difference in bytes between the Endpoint Count specified in the and the Error Flag bit is not set; both bits are in the Device n Device n Endpoint n Count register and the last packet received. Endpoint n Status register. If an overflow or underflow condition occurs, that is, the received packet length differs from the value specified in the Device n Document Number: 38-08015 Rev. *P Page 47 of 119

CY7C67300 The Device n Endpoint n Count Result register is a memory- additional byte count of the received packet. If an underflow based register that must be initialized to 0x0000 before USB condition occurs, Result [15:0] indicates the excess bytes count Device operations are initiated. After initialization, do not write to (number of bytes not used). this register again. Reserved Result (Bits [15:0]) Write all reserved bits with ‘0’. The Result field contains the differences in bytes between the received packet and the value specified in the Device n Endpoint n Count register. If an overflow condition occurs, Result [15:10] is set to ‘111111’, a 2’s complement value indicating the Device n Port Select Register [R/W] ■Device n Port Select Register 0xC084 ■Device n Port Select Register 0xC0A4 Table 68. Device n Port Select Register Bit # 15 14 13 12 11 10 9 8 Reserved Port Reserved... Field Select Read/Write - R/W - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Reserved Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Register Description Port Select (Bit 14) The Device n Port Select register selects either port A or port B The Port Select bit selects which of the two ports is enabled. for the static device port. 1: Port 1B or Port 2B is enabled 0: Port 1A or Port 2A is enabled Document Number: 38-08015 Rev. *P Page 48 of 119

CY7C67300 Device n Interrupt Enable Register [R/W] ■Device 1 Interrupt Enable Register 0xC08C ■Device 2 Interrupt Enable Register 0xC0AC Table 69. Device n Interrupt Enable Register Bit # 15 14 13 12 11 10 9 8 VBUS ID Interrupt Reserved SOF/EOP Reserved SOF/EOP Reset Interrupt Enable Timeout Interrupt Interrupt Enable Interrupt Enable Enable Field Enable Read/Write R/W R/W - - R/W - R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 EP7 Interrupt EP6 Interrupt EP5 Interrupt EP4 Interrupt EP3 Interrupt EP2 Interrupt EP1 Interrupt EP0 Interrupt Field Enable Enable Enable Enable Enable Enable Enable Enable Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description [12] The SOF/EOP Interrupt Enable bit enables or disables the SOF/ EOP received interrupt. The Device n Interrupt Enable register provides control over device related interrupts including eight different endpoint inter- 1: Enable SOF/EOP received interrupt rupts. 0: Disable SOF/EOP received interrupt VBUS Interrupt Enable (Bit 15) Reset Interrupt Enable (Bit 8) The VBUS Interrupt Enable bit enables or disables the OTG The Reset Interrupt Enable bit enables or disables the USB VBUS interrupt. When enabled, this interrupt triggers on both the Reset Detected interrupt rising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Device 1 and 1: Enable USB Reset Detected interrupt is a reserved bit in Device 2. 0: Disable USB Reset Detected interrupt 1: Enable VBUS interrupt EP7 Interrupt Enable (Bit 7) 0: Disable VBUS interrupt The EP7 Interrupt Enable bit enables or disables endpoint seven ID Interrupt Enable (Bit 14) (EP7) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events The ID Interrupt Enable bit enables or disables the OTG ID occur in a transaction for the device’s supplied Endpoint: send/ interrupt. When enabled, this interrupt triggers on both the rising receive ACK, send STALL, Timeout occurs, IN Exception Error, and falling edge of the OTG ID pin (only supported in Port 1A). or OUT Exception Error. In addition, the NAK Interrupt Enable bit This bit is only available for Device 1 and is a reserved bit in in the Device n Endpoint Control register can also be set so that Device 2. NAK responses trigger this interrupt. 1: Enable ID interrupt 1: Enable EP7 Transaction Done interrupt 0: Disable ID interrupt 0: Disable EP7 Transaction Done interrupt SOF/EOP Timeout Interrupt Enable (Bit 11) EP6 Interrupt Enable (Bit 6) The SOF/EOP Timeout Interrupt Enable bit enables or disables The EP6 Interrupt Enable bit enables or disables endpoint six the SOF/EOP Timeout Interrupt. When enabled this interrupt (EP6) Transaction Done interrupt. An EPx Transaction Done triggers when the USB host fails to send a SOF or EOP packet interrupt triggers when any of the following responses or events within the time period specified in the Device n SOF/EOP Count occur in a transaction for the device’s supplied Endpoint: send/ register. In addition, the Device n Frame register counts the receive ACK, send STALL, Timeout occurs, IN Exception Error, number of times the SOF/EOP Timeout Interrupt triggers or OUT Exception Error. In addition, the NAK Interrupt Enable bit between receiving SOF/EOPs. in the Device n Endpoint Control register can also be set so that 1: SOF/EOP timeout occurred NAK responses trigger this interrupt. 0: SOF/EOP timeout did not occur 1: Enable EP6 Transaction Done interrupt 0: Disable EP6 Transaction Done interrupt SOF/EOP Interrupt Enable (Bit 9) Note 12.Errata: USB peripheral designs may miss endpoint interrupts when receiving Endpoint 0 (EP0) Control transfer requests mixed with other endpoint transfer type transactions. When an SIE is configured as a peripheral, data toggle corruption as specified in the USB 2.0 specification, section 8.6.4, does not work as specified. Please refer to Errata on page 107 for details and workaround. Document Number: 38-08015 Rev. *P Page 49 of 119

CY7C67300 EP5 Interrupt Enable (Bit 5) The EP2 Interrupt Enable bit enables or disables endpoint two (EP2) Transaction Done interrupt. An EPx Transaction Done The EP5 Interrupt Enable bit enables or disables endpoint five interrupt triggers when any of the following responses or events (EP5) Transaction Done interrupt. An EPx Transaction Done occur in a transaction for the device’s supplied Endpoint: send/ interrupt triggers when any of the following responses or events receive ACK, send STALL, Timeout occurs, IN Exception Error, occur in a transaction for the device’s supplied Endpoint: send/ or OUT Exception Error. In addition, the NAK Interrupt Enable bit receive ACK, send STALL, Timeout occurs, IN Exception Error, in the Device n Endpoint Control register can also be set so that or OUT Exception Error. In addition, the NAK Interrupt Enable bit NAK responses trigger this interrupt. in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt. 1: Enable EP2 Transaction Done interrupt 1: Enable EP5 Transaction Done interrupt 0: Disable EP2 Transaction Done interrupt 0: Disable EP5 Transaction Done interrupt EP1 Interrupt Enable (Bit 1) EP4 Interrupt Enable (Bit 4) The EP1 Interrupt Enable bit enables or disables endpoint one (EP1) Transaction Done interrupt. An EPx Transaction Done The EP4 Interrupt Enable bit enables or disables endpoint four interrupt triggers when any of the following responses or events (EP4) Transaction Done interrupt. An EPx Transaction Done occur in a transaction for the device’s supplied Endpoint: send/ interrupt triggers when any of the following responses or events receive ACK, send STALL, Timeout occurs, IN Exception Error, occur in a transaction for the device’s supplied Endpoint: send/ or OUT Exception Error. In addition, the NAK Interrupt Enable bit receive ACK, send STALL, Timeout occurs, IN Exception Error, in the Device n Endpoint Control register can also be set so that or OUT Exception Error. In addition, the NAK Interrupt Enable bit NAK responses trigger this interrupt. in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt. 1: Enable EP1 Transaction Done interrupt 1: Enable EP4 Transaction Done interrupt 0: Disable EP1 Transaction Done interrupt 0: Disable EP4 Transaction Done interrupt EP0 Interrupt Enable (Bit 0) EP3 Interrupt Enable (Bit 3) The EP0 Interrupt Enable bit enables or disables endpoint zero The EP3 Interrupt Enable bit enables or disables endpoint three (EP0) Transaction Done interrupt. An EPx Transaction Done (EP3) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events interrupt triggers when any of the following responses or events occur in a transaction for the device’s supplied Endpoint: send/ occur in a transaction for the device’s supplied Endpoint: send/ receive ACK, send STALL, Timeout occurs, IN Exception Error, receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt. NAK responses trigger this interrupt. 1: Enable EP0 Transaction Done interrupt 1: Enable EP3 Transaction Done interrupt 0: Disable EP0 Transaction Done interrupt 0: Disable EP3 Transaction Done interrupt Reserved EP2 Interrupt Enable (Bit 2) Write all reserved bits with ’0’. Device n Address Register [W] ■Device 1 Address Register 0xC08E ■Device 2 Address Register 0xC0AE Table 70. Device n Address Register Bit # 15 14 13 12 11 10 9 8 Field Reserved... Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Reserved Address Read/Write - W W W W W W W Default 0 0 0 0 0 0 0 0 Register Description The Device n Address register holds the device address assigned by the host. This register initializes to the default Document Number: 38-08015 Rev. *P Page 50 of 119

CY7C67300 address 0 at reset but must be updated by firmware when the The Address field contains the USB address of the device host assigns a new address. Only USB data sent to the address assigned by the host. contained in this register gets a respond—all others are ignored. Reserved Address (Bits [6:0]) Write all reserved bits with ’0’. Device n Status Register [R/W] ■Device 1 Status Register 0xC090 ■Device 2 Status Register 0xC0B0 Table 71. Device n Status Register Bit # 15 14 13 12 11 10 9 8 VBUS Inter- ID Interrupt Reserved SOF/EOP Reset Interrupt rupt Flag Interrupt Flag Flag Field Flag Read/Write R/W R/W - - - - R/W R/W Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 EP7 Interrupt EP6 Interrupt EP5 Interrupt EP4 Interrupt EP3 Interrupt EP2 Interrupt EP1 Interrupt EP0 Interrupt Field Flag Flag Flag Flag Flag Flag Flag Flag Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X X X X X Register Description The SOF/EOP Interrupt Flag bit indicates if the SOF/EOP received interrupt triggered. The Device n Status register provides status information for device operation. Pending interrupts can be cleared by writing a 1: Interrupt triggered ‘1’ to the corresponding bit. This register can be accessed by the 0: Interrupt did not trigger HPI interface. Reset Interrupt Flag (Bit 8) VBUS Interrupt Flag (Bit 15) The Reset Interrupt Flag bit indicates if the USB Reset Detected The VBUS Interrupt Flag bit indicates the status of the OTG interrupt triggered. VBUS interrupt (only for Port 1A). When enabled this interrupt triggers on both the rising and falling edge of VBUS at 4.4V. This 1: Interrupt triggered bit is only available for Device 1 and is a reserved bit in Device 2. 0: Interrupt did not trigger 1: Interrupt triggered EP7 Interrupt Flag (Bit 7) 0: Interrupt did not trigger The EP7 Interrupt Flag bit indicates if the endpoint seven (EP7) ID Interrupt Flag (Bit 14) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events The ID Interrupt Flag bit indicates the status of the OTG ID occur in a transaction for the device’s supplied EP: send/receive interrupt (only for Port 1A). When enabled this interrupt triggers ACK, send STALL, Timeout occurs, IN Exception Error, or OUT on both the rising and falling edge of the OTG ID pin. This bit is Exception Error. In addition, if the NAK Interrupt Enable bit in the only available for Device 1 and is a reserved bit in Device 2. Device n Endpoint Control register is set, this interrupt also 1: Interrupt triggered triggers when the device NAKs host requests. 0: Interrupt did not trigger 1: Interrupt triggered 0: Interrupt did not trigger SOF/EOP Interrupt Flag (Bit 9) Document Number: 38-08015 Rev. *P Page 51 of 119

CY7C67300 EP6 Interrupt Flag (Bit 6) Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests. The EP6 Interrupt Flag bit indicates if the endpoint six (EP6) Transaction Done interrupt triggered. An EPx Transaction Done 1: Interrupt triggered interrupt triggers when any of the following responses or events 0: Interrupt did not trigger occur in a transaction for the device’s supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT EP2 Interrupt Flag (Bit 2) Exception Error. In addition, if the NAK Interrupt Enable bit in the The EP2 Interrupt Flag bit indicates if the endpoint two (EP2) Device n Endpoint Control register is set, this interrupt also Transaction Done interrupt triggered. An EPx Transaction Done triggers when the device NAKs host requests. interrupt triggers when any of the following responses or events 1: Interrupt triggered occur in a transaction for the device’s supplied EP: send/receive 0: Interrupt did not trigger ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the EP5 Interrupt Flag (Bit 5) Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests. The EP5 Interrupt Flag bit indicates if the endpoint five (EP5) Transaction Done interrupt triggered. An EPx Transaction Done 1: Interrupt triggered interrupt triggers when any of the following responses or events 0: Interrupt did not trigger occur in a transaction for the device’s supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT EP1 Interrupt Flag (Bit 1) Exception Error. In addition, if the NAK Interrupt Enable bit in the The EP1 Interrupt Flag bit indicates if the endpoint one (EP1) Device n Endpoint Control register is set, this interrupt also Transaction Done interrupt triggered. An EPx Transaction Done triggers when the device NAKs host requests. interrupt triggers when any of the following responses or events 1: Interrupt triggered occur in a transaction for the device’s supplied EP: send/receive 0: Interrupt did not trigger ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the EP4 Interrupt Flag (Bit 4) Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests. The EP4 Interrupt Flag bit indicates if the endpoint four (EP4) Transaction Done interrupt triggered. An EPx Transaction Done 1: Interrupt triggered interrupt triggers when any of the following responses or events 0: Interrupt did not trigger occur in a transaction for the device’s supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT EP0 Interrupt Flag (Bit 0) Exception Error. In addition, if the NAK Interrupt Enable bit in the The EP0 Interrupt Flag bit indicates if the endpoint zero (EP0) Device n Endpoint Control register is set, this interrupt also Transaction Done interrupt triggered. An EPx Transaction Done triggers when the device NAKs host requests. interrupt triggers when any of the following responses or events 1: Interrupt triggered occur in a transaction for the device’s supplied EP: send/receive 0: Interrupt did not trigger ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the EP3 Interrupt Flag (Bit 3) Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests. The EP3 Interrupt Flag bit indicates if the endpoint three (EP3) Transaction Done interrupt triggered. An EPx Transaction Done 1: Interrupt triggered interrupt triggers when any of the following responses or events 0: Interrupt did not trigger occur in a transaction for the device’s supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Reserved Exception Error. In addition, if the NAK Interrupt Enable bit in the Write all reserved bits with ’0’. Document Number: 38-08015 Rev. *P Page 52 of 119

CY7C67300 Device n Frame Number Register [R] ■Device 1 Frame Number Register 0xC092 ■Device 2 Frame Number Register 0xC0B2 Table 72. Device n Frame Number Register Bit # 15 14 13 12 11 10 9 8 SOF/EOP SOF/EOP Reserved Frame... Field Timeout Flag Timeout Interrupt Counter Read/Write R R R R - R R R Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Frame Read/Write R R R R R R R R Default 0 0 0 0 0 0 0 0 Register Description SOF/EOP Timeout Interrupt Counter (Bits [14:12]) The Device n Frame Number register is a read only register that The SOF/EOP Timeout Interrupt Counter field increments by 1 contains the Frame number of the last SOF packet received. This from 0 to 7 for each SOF/EOP Timeout Interrupt. This field resets register also contains a count of SOF/EOP Timeout occurrences. to 0 when a SOF/EOP is received. This field is only updated when the SOF/EOP Timeout Interrupt Enable bit in the Device n SOF/EOP Timeout Flag (Bit 15) Interrupt Enable register is set. The SOF/EOP Timeout Flag bit indicates when an SOF/EOP Frame (Bits [10:0]) Timeout Interrupt occurs. The Frame field contains the frame number from the last 1: An SOF/EOP Timeout interrupt occurred received SOF packet in full-speed mode. This field no function 0: An SOF/EOP Timeout interrupt did not occur for low-speed mode. If a SOF Timeout occurs, this field contains the last received Frame number. Document Number: 38-08015 Rev. *P Page 53 of 119

CY7C67300 Device n SOF/EOP Count Register [W] ■Device 1 SOF/EOP Count Register 0xC094 ■Device 2 SOF/EOP Count Register 0xC0B4 Table 73. Device n SOF/EOP Count Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Count... Read/Write - - R R R R R R Default 0 0 1 0 1 1 1 0 Bit # 7 6 5 4 3 2 1 0 Field ...Count Read/Write R R R R R R R R Default 1 1 1 0 0 0 0 0 Register Description Reserved The Device n SOF/EOP Count register is written with the time Write all reserved bits with ’0’. expected between receiving a SOF/EOP. If the SOF/EOP counter expires before an SOF/EOP is received, an SOF/EOP OTG Control Registers [13] Timeout Interrupt can be generated. The SOF/EOP Timeout There is one register dedicated for On-The-Go operation. This Interrupt Enable and SOF/EOP Timeout Interrupt Flag are register is covered in this section and summarized in Table74. located in the Device n Interrupt Enable and Status registers respectively. Table 74. OTG Register Set the SOF/EOP count slightly greater than the expected SOF/ Register Name Address R/W EOP interval. The SOF/EOP counter decrements at a 12MHz OTG Control Register C098H R/W rate. Therefore, in the case of an expected 1ms SOF/EOP interval, the SOF/EOP count is set slightly greater than 0x2EE0. Count (Bits [13:0]) The Count field contains the current value of the SOF/EOP down counter. At power up and reset, this value is set to 0x2EE0 and for expected 1ms SOF/EOP intervals, this SOF/EOP count is increased slightly. Note 13.Errata: The VBUS interrupt in the OTG Control Register [0xC098] triggers multiple times whenever VBUS is turned on. It should only trigger once when VBUS rises above 4.4V and once when VBUS falls from above 4.4V to 0V. Please refer to Errata on page 107 for details and workaround. Document Number: 38-08015 Rev. *P Page 54 of 119

CY7C67300 OTG Control Register [0xC098] [R/W] Table 75. OTG Control Register Bit # 15 14 13 12 11 10 9 8 Reserved VBUS Receive Charge Pump VBUS D+ D– Field Pull-up Enable Disable Enable Discharge Enable Pull-up Enable Pull-up Enable Read/Write - - R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 D+ D– Reserved OTG Data ID VBUS Valid Field Pull-down Enable Pull-down Enable Status Status Flag Read/Write R/W R/W - - - R R R Default 0 0 0 0 0 X X X Register Description 1: OTG D– dataline pull up resistor enabled The OTG Control register allows control and monitoring over the 0: OTG D– dataline pull up resistor disabled OTG port on Port1A. Note that the D± pull up and pull down bits override the setting in the USB 0 Control register for this port. D+ Pull-down Enable (Bit 7) The D+ Pull-down Enable bit enables or disables a pull down VBUS Pull-up Enable (Bit 13) resistor on the OTG D+ data line. The VBUS Pull-up Enable bit enables or disables a 500 ohm pull 1: OTG D+ dataline pull down resistor enabled up resistor onto OTG VBus. 0: OTG D+ dataline pull down resistor disabled 1: 500 ohm pull up resistor enabled 0: 500 ohm pull up resistor disabled D– Pull-down Enable (Bit 6) The D– Pull-down Enable bit enables or disables a pull down Receive Disable (Bit 12) resistor on the OTG D– data line. The Receive Disable bit enables or powers down (disables) the 1: OTG D– dataline pull down resistor enabled OTG receiver section. 0: OTG D– dataline pull down resistor disabled 1: OTG receiver powered down and disabled 0: OTG receiver enabled OTG Data Status (Bit 2) The OTG Data Status bit is a read only bit and indicates the TTL Charge Pump Enable (Bit 11) logic state of the OTG VBus pin. The Charge Pump Enable bit enables or disables the OTG VBus 1: OTG VBus is greater then 2.4V charge pump. 0: OTG VBus is less then 0.8V 1: OTG VBus charge pump enabled 0: OTG VBus charge pump disabled ID Status (Bit 1) The ID Status bit is a read only bit that indicates the state of the VBUS Discharge Enable (Bit 10) OTG ID pin on Port A. The VBUS Discharge Enable bit enables or disables a 2K ohm 1: OTG ID Pin is not connected directly to ground (>10K ohm) discharge pull down resistor onto OTG VBus. 0: OTG ID Pin is connected directly ground (< 10 ohm) 1: 2K ohm pull down resistor enabled 0: 2K ohm pull down resistor disabled VBUS Valid Flag (Bit 0) The VBUS Valid Flag bit indicates whether OTG VBus is greater D+ Pull-up Enable (Bit 9) then 4.4V. After turning on VBUS, firmware must wait at least 10 The D+ Pull-up Enable bit enables or disables a pull up resistor µs before this reading this bit. on the OTG D+ data line. 1: OTG VBus is greater then 4.4V 1: OTG D+ dataline pull up resistor enabled 0: OTG VBus is less then 4.4V 0: OTG D+ dataline pull up resistor disabled Reserved D– Pull-up Enable (Bit 8) Write all reserved bits with ’0’. The D– Pull-up Enable bit enables or disables a pull up resistor on the OTG D– data line. Document Number: 38-08015 Rev. *P Page 55 of 119

CY7C67300 GPIO Registers Table 76. GPIO Registers There are seven registers dedicated for GPIO operations. These Register Name Address R/W seven registers are covered in this section and summarized in Table76. GPIO0 Direction Register 0xC022 R/W GPIO1 Output Data Register 0xC024 R/W Table 76. GPIO Registers GPIO1 Input Data Register 0xC026 R Register Name Address R/W GPIO1 Direction Register 0xC028 R/W GPIO Control Register 0xC006 R/W GPIO0 Output Data Register 0xC01E R/W GPIO0 Input Data Register 0xC020 R GPIO Control Register [0xC006] [R/W] Table 77. GPIO Control Register Bit # 15 14 13 12 11 10 9 8 Write Protect UD Reserved SAS Mode Field Enable Enable Select Read/Write R/W R/W - - R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 HSS HSS XD SPI SPI XD Interrupt 1 Interrupt 1 Interrupt 0 Interrupt 0 Field Enable Enable Enable Enable Polarity Select Enable Polarity Select Enable Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description 0: Leave SPI_nss on GPIO[9] The GPIO Control register configures the GPIO pins for various Mode Select (Bits [10:8]) interface options. It also controls the polarity of the GPIO interrupt on IRQ1 (GPIO25) and IRQ0 (GPIO24). The Mode Select field selects how GPIO[15:0] and GPIO[24:19] are used as defined in Table78. Write Protect Enable (Bit 15) Table 78. Mode Select Definition The Write Protect Enable bit enables or disables the GPIO write protect. When Write Protect is enabled, the GPIO Mode Select Mode Select GPIO Configuration [10:8] [15:8] field is read only until a chip reset. 111 Reserved 1: Enable Write Protect 110 SCAN — (HW) Scan diagnostic. For produc- 0: Disable Write Protect tion test only. Not for normal operation UD (Bit 14) 101 HPI — Host Port Interface 100 IDE — Integrated Drive Electronics or The UD bit routes the Host/Device 1A Port’s transmitter enable 011 Reserved status to GPIO[30]. This is for use with an external ESD protection circuit when needed. 010 Reserved 001 Reserved 1: Route the signal to GPIO[30] 000 GPIO — General Purpose Input Output 0: Do not route the signal to GPIO[30] HSS Enable (Bit 7) SAS Enable (Bit 11) The HSS Enable bit routes HSS to GPIO[26, 18:16]. If the HSS The SAS Enable bit, when in SPI mode, reroutes the SPI port XD Enable bit is set, it overrides this bit and HSS is routed to SPI_nSSI pin to GPIO[15] rather then GPIO[9] or XD[9] (per SG/ XD[15:12]. SX). 1: HSS is routed to GPIO 1: Reroute SPI_nss to GPIO[30] 0: HSS is not routed to GPIOs. GPIO[26, 18:16] are free for other Document Number: 38-08015 Rev. *P Page 56 of 119

CY7C67300 HSS XD Enable (Bit 6) Interrupt 1 Enable (Bit 2) The HSS XD Enable bit routes HSS to XD[15:12] (external The Interrupt 1 Enable bit enables or disables IRQ1. The GPIO memory data bus). This bit overrides the HSS Enable bit. bit on the interrupt Enable register must also be set in order for 1: HSS is routed to XD[15:12] this for this interrupt to be enabled. 0: HSS is not routed to XD[15:12] 1: Enable IRQ1 0: Disable IRQ1 SPI Enable (Bit 5) Interrupt 0 Polarity Select (Bit 1) The SPI Enable bit routes SPI to GPIO[11:8]. If the SAS Enable bit is set, it overrides the SPI Enable and routes SPI_nSSI to The Interrupt 0 Polarity Select bit selects the polarity for IRQ0. GPIO15. If the SPI XD Enable bit is set, it overrides both bits and 1: Sets IRQ0 to rising edge the SPI is routed to XD[11:8] (external memory data bus). 0: Sets IRQ0 to falling edge 1: SPI is routed to GPIO[11:8] Interrupt 0 Enable (Bit 0) 0: SPI is not routed to GPIO[11:8]. GPIO[11:8] are free for other purposes The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO bit on the interrupt Enable register must also be set in order for SPI XD Enable (Bit 4) this for this interrupt to be enabled. The SPI XD Enable bit routes SPI to XD[11:8] (external memory 1: Enable IRQ0 data bus). This bit overrides the SPI Enable bit. 0: Disable IRQ0 1: SPI is routed to XD[11:8] Reserved 0: SPI is not routed to XD[11:8] Write all reserved bits with ’0’. Interrupt 1 Polarity Select (Bit 3) The Interrupt 1 Polarity Select bit selects the polarity for IRQ1. 1: Sets IRQ1 to rising edge 0: Sets IRQ1 to falling edge GPIO n Output Data Register [R/W] ■GPIO 0 Output Data Register 0xC01E ■GPIO 1 Output Data Register 0xC024 Table 79. GPIO n Output Data Register Bit # 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Field Data... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 Field ...Data Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Data (Bits [15:0]) The GPIO n Output Data register controls the output data of the The Data field[15:0] writes to the corresponding GPIO 15–0 or GPIO pins. The GPIO 0 Output Data register controls GPIO15 to GPIO31–16 pins as output data. GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO16. When read, this register reads back the last data written, not the data on pins configured as inputs (see Input Data Register). Document Number: 38-08015 Rev. *P Page 57 of 119

CY7C67300 GPIO n Input Data Register [R] ■GPIO 0 Input Data Register 0xC020 ■GPIO 1 Input Data Register 0xC026 Table 80. GPIO n Input Data Register Bit # 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Field Data... Read/Write R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit # 23/7 22/6 21//5 20/4 19/3 18/2 17/1 16/0 Field ...Data Read/Write R R R R R R R R Default 0 0 0 0 0 0 0 0 Register Description Data (Bits [15:0]) The GPIO n Input Data register reads the input data of the GPIO The Data field[15:0] contains the voltage values on the corre- pins. The GPIO 0 Input Data register reads from GPIO15 to sponding GPIO15–0 or GPIO31–16 input pins. GPIO0 while the GPIO 1 Input Data register reads from GPIO31 to GPIO16. Document Number: 38-08015 Rev. *P Page 58 of 119

CY7C67300 GPIO n Direction Register [R/W] ■GPIO 0 Direction Register 0xC022 ■GPIO 1 Direction Register 0xC028 Table 81. GPIO n Direction Register Bit # 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Field Direction Select... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 Field ...Direction Select Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description IDE Registers The GPIO n Direction register controls the direction of the GPIO In addition to the standard IDE PIO Port registers, there are four data pins (input/output). The GPIO 0 Direction register controls registers dedicated to IDE operation. These registers are GPIO15 to GPIO0 while the GPIO 1 Direction register controls covered in this section and summarized in Table82. GPIO31 to GPIO16. Table 82. IDE Registers [14] Direction Select (Bits [15:0]) Register Name Address R/W The Direction Select field[15:0] configures the corresponding IDE Mode Register 0xC048 R/W GPIO15–0 or GPIO31–16 pins as either input or output. When any bit of this register is set to ‘1’, the corresponding GPIO data IDE Start Address Register 0xC04A R/W pin becomes an output. When any bit of this register is set to ‘0’, IDE Stop Address Register 0xC04C R/W the corresponding GPIO data pin becomes an input. IDE Control Register 0xC04E R/W IDE PIO Port Registers 0xC050-0xC06F R/W IDE Mode Register [0xC048] [R/W] Table 83. IDE Mode Register Bit # 15 14 13 12 11 10 9 8 Field Reserved... Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Reserved Mode Select Read/Write - - - - R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Mode Select (Bits [2:0]) The IDE Mode register allows the selection of IDE PIO Modes 0, The Mode Select field sets PIO Mode 0 to 4 in IDE mode. Refer 1, 2, 3, or 4. The default setting is zero which means IDE PIO to Table84on page60 for a definition of this field. Mode 0. Note 14.Errata: The part does not service USB ISRs when the GPIO24 pin (also labeled as HPI_INT and IORDY) is low and any IDE register is read. Please refer to Errata on page 107 for details and workaround. Document Number: 38-08015 Rev. *P Page 59 of 119

CY7C67300 Table 84. Mode Select Definition Mode Select [2:0] Mode 000 IDE PIO Mode 0 001 IDE PIO Mode 1 010 IDE PIO Mode 2 011 IDE PIO Mode 3 100 IDE PIO Mode 4 101 Reserved 110 Reserved 111 Disable IDE port operations Reserved Write all reserved bits with ’0’. IDE Start Address Register [0xC04A] [R/W] Table 85. IDE Start Address Register Bit # 15 14 13 12 11 10 9 8 Field Address... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Address Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description The hardware keeps an internal memory address counter. The two MSBs of the addresses are not modified by the address The IDE Start Address register holds the start address for an IDE counter. Therefore, the IDE Start Address and IDE Stop Address block transfer. This register is byte addressed and IDE block must reside within the same 16K byte block. transfers are 16-bit words, therefore the LSB of the start address is ignored. Block transfers begin at IDE Start Address and end Address (Bits [15:0]) with the final word at IDE Stop Address. When IDE Start Address equals IDE Stop Address, the block transfer moves one word of The Address field sets the start address for an IDE block transfer. data. Document Number: 38-08015 Rev. *P Page 60 of 119

CY7C67300 IDE Stop Address Register [0xC04C] [R/W] Table 86. IDE Stop Address Register Bit # 15 14 13 12 11 10 9 8 Field Address... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Address Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description The hardware keeps an internal memory address counter. The two MSBs of the addresses are not modified by the address The IDE Stop Address register holds the stop address for an IDE counter. Therefore the IDE Start Address and IDE Stop Address block transfer. This register is byte addressed and IDE block must reside within the same 16K byte block. transfers are 16-bit words, therefore the LSB of the stop address is ignored. Block transfers begin at IDE Start Address and end Address (Bits [15:0]) with the final word at IDE Stop Address. When IDE Start Address equals IDE Stop Address, the block transfer moves one word of The Address field sets the stop address for an IDE block transfer. data. IDE Control Register [0xC04E] [R/W] Table 87. IDE Control Register Bit # 15 14 13 12 11 10 9 8 Field Reserved... Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 ...Reserved Direction IDE Done IDE Select Interrupt Flag Enable Field Enable Read/Write - - - - R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Done Flag (Bit 1) The IDE Control register controls block transfers in IDE mode. The Done Flag bit is automatically set to ‘1’ by hardware when a block transfer is complete. The CPU clears this bit by writing a Direction Select (Bit 3) ‘0’ to it. When IDE Interrupt Enable is set this bit generates the The Direction Select bit sets the block mode transfer direction. signal for the cpuide_intr interrupt. 1: Data is written to the external device 1: Block transfer is complete 0: Data is read from the external device 0: Clears IDE Done Flag IDE Interrupt Enable (Bit 2) IDE Enable (Bit 0) The IDE Interrupt Enable bit enables or disables the block The IDE Enable bit starts a block transfer. It is reset to ‘0’ when transfer done interrupt. When enabled, the Done Flag is sent to the block transfer is complete the CPU as cpuide_intr interrupt. When disabled, the cpuide_intr 1: Start block transfer is set LOW. 0: Block transfer complete 1: Enable block transfer done interrupt Reserved 0: Disable block transfer done interrupt Write all reserved bits with ’0’. Document Number: 38-08015 Rev. *P Page 61 of 119

CY7C67300 IDE PIO Port Registers [0xC050 - 0xC06F] [R/W] All IDE PIO Port registers [0xC050 - 0xC06F] in Table88 are defined in detail in the Information Technology-AT Attachment -4 with Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18. The table Address column denotes the CY7C67300 register address for the corresponding ATA/ATAPI register. The IDE_nCS[1:0] field defines the ATA interface CS addressing bits and the IDE_A[2:0] field define the ATA interface address bits. The combination of IDE_nCS and IDE_A are the ATA interface register address. Table 88. IDE PIO Port Registers Address ATA/ATAPI Register IDE_nCS[1:0] IDE_A[2:0] 0xC050 DATA Register ‘10’ ‘000’ 0xC052 Read: Error Register ‘10’ ‘001’ Write: Feature Register 0xC054 Sector Count Register ‘10’ ‘010’ 0xC056 Sector Number Register ‘10’ ‘011’ 0xC058 Cylinder Low Register ‘10’ ‘100’ 0xC05A Cylinder High Register ‘10’ ‘101’ 0xC05C Device/Head Register ‘10’ ‘110’ 0xC05E Read: Status Register ‘10’ ‘111’ Write: Command Register 0xC060 Not Defined ‘01’ ‘000’ 0xC062 Not Defined ‘01’ ‘001’ 0xC064 Not Defined ‘01’ ‘010’ 0xC066 Not Defined ‘01’ ‘011’ 0xC068 Not Defined ‘01’ ‘100’ 0xC06A Not Defined ‘01’ ‘101’ 0xC06C Read: Alternate Status Register ‘01’ ‘110’ Write: Device Control Register 0xC06E Not Defined ‘01’ ‘111’ HSS Registers There are eight registers dedicated to HSS operation. Each of these registers are covered in this section and summarized in Table89. Table 89. HSS Registers Register Name Address R/W HSS Control Register 0xC070 R/W HSS Baud Rate Register 0xC072 R/W HSS Transmit Gap Register 0xC074 R/W HSS Data Register 0xC076 R/W HSS Receive Address Register 0xC078 R/W HSS Receive Length Register 0xC07A R/W HSS Transmit Address Register 0xC07C R/W HSS Transmit Length Register 0xC07E R/W Document Number: 38-08015 Rev. *P Page 62 of 119

CY7C67300 HSS Control Register [0xC070] [R/W] Table 90. HSS Control Register Bit # 15 14 13 12 11 10 9 8 HSS RTS CTS XOFF XOFF CTS Receive Done Enable Polarity Polarity Enable Enable Interrupt Interrupt Field Select Select Enable Enable Read/Write R/W R/W R/W R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Transmit Receive One Transmit Packet Receive Receive Receive Done Interrupt Done Interrupt Stop Bit Ready Mode Overflow Packet Ready Ready Field Enable Enable Select Flag Flag Flag Read/Write R/W R/W R/W R R/W R/W R R Default 0 0 0 0 0 0 0 0 Register Description Receive Interrupt Enable (Bit 9) The HSS Control register provides high level status and control The Receive Interrupt Enable bit enables or disables the Receive over the HSS port. Ready and Receive Packet Ready interrupts. 1: Enable the Receive Ready and Receive Packet Ready inter- HSS Enable (Bit 15) rupts The HSS Enable bit enables or disables HSS operation. 0: Disable the Receive Ready and Receive Packet Ready inter- 1: Enables HSS operation rupts 0: Disables HSS operation Done Interrupt Enable (Bit 8) RTS Polarity Select (Bit 14) The Done Interrupt Enable bit enables or disables the Transmit The RTS Polarity Select bit selects the polarity of RTS. Done and Receive Done interrupts. 1: RTS is true when LOW 1: Enable the Transmit Done and Receive Done interrupts 0: RTS is true when HIGH 0: Disable the Transmit Done and Receive Done interrupts CTS Polarity Select (Bit 13) Transmit Done Interrupt Flag (Bit 7) The CTS Polarity Select bit selects the polarity of CTS. The Transmit Done Interrupt Flag bit indicates the status of the Transmit Done Interrupt. It sets when a block transmit is finished. 1: CTS is true when LOW To clear the interrupt, write a ‘1’ to this bit. 0: CTS is true when HIGH 1: Interrupt triggered XOFF (Bit 12) 0: Interrupt did not trigger The XOFF bit is a read only bit that indicates if an XOFF was Receive Done Interrupt Flag (Bit 6) received. This bit is automatically cleared when an XON is received. The Receive Done Interrupt Flag bit indicates the status of the Receive Done Interrupt. It sets when a block transmit is finished. 1: XOFF received To clear the interrupt, write a ‘1’ to this bit. 0: XON received 1: Interrupt triggered XOFF Enable (Bit 11) 0: Interrupt did not trigger The XOFF Enable bit enables or disables XON/XOFF software One Stop Bit (Bit 5) handshaking. The One Stop Bit bit selects between one and two stop bits for 1: Enable XON/XOFF software handshaking transmit byte mode. In receive mode, the number of stop bits 0: Disable XON/XOFF software handshaking may vary and does not need to be fixed. 1: One stop bit CTS Enable (Bit 10) 0: Two stop bits The CTS Enable bit enables or disables CTS/RTS hardware handshaking. 1: Enable CTS/RTS hardware handshaking 0: Disable CTS/RTS hardware handshaking Document Number: 38-08015 Rev. *P Page 63 of 119

CY7C67300 Transmit Ready (Bit 4) 1: Overflow occurred The Transmit Ready bit is a read only bit that indicates if the HSS 0: Overflow did not occur Transmit FIFO is ready for the CPU to load new data for trans- mission. Receive Packet Ready Flag (Bit 1) 1: HSS transmit FIFO ready for loading The Receive Packet Ready Flag bit is a read only bit that indicates if the HSS receive FIFO is full with eight bytes or not. 0: HSS transmit FIFO not ready for loading 1: HSS receive FIFO is full Packet Mode Select (Bit 3) 0: HSS receive FIFO is not full The Packet Mode Select bit selects between Receive Packet Ready and Receive Ready as the interrupt source for the RxIntr Receive Ready Flag (Bit 0) interrupt. The Receive Ready Flag is a read only bit that indicates if the 1: Selects Receive Packet Ready as the source HSS receive FIFO is empty or not. 0: Selects Receive Ready as the source 1: HSS receive FIFO is not empty (one or more bytes is reading for reading) Receive Overflow Flag (Bit 2) 0: HSS receive FIFO is empty The Receive Overflow Flag bit indicates if the Receive FIFO overflowed when set. This flag can be cleared by writing a ‘1’ to this bit. HSS Baud Rate Register [0xC072] [R/W] Table 91. HSS Baud Rate Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Baud... Read/Write - - - R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Baud Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 1 0 1 1 1 Register Description Reserved The HSS Baud Rate register sets the HSS Baud Rate. At reset, Write all reserved bits with ’0’. the default value is 0x0017 which sets the baud rate to 2.0MHz. Baud (Bits [12:0]) The Baud field is the baud rate divisor minus one, in units of 1/ 48 MHz. Therefore the Baud Rate = 48 MHz/(Baud + 1). This puts a constraint on the Baud Value as follows: (24 – 1)  Baud  (5000 – 1) Document Number: 38-08015 Rev. *P Page 64 of 119

CY7C67300 HSS Transmit Gap Register [0xC074] [R/W] Table 92. HSS Transmit Gap Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field Transmit Gap Select Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 1 0 0 1 Register Description Reserved The HSS Transmit Gap register is only valid in block transmit Write all reserved bits with ’0’. mode. It allows for a programmable number of stop bits to be inserted, thus overwriting the One Stop Bit in the HSS Control register. The default reset value of this register is 0x0009, equiv- alent to two stop bits. Transmit Gap Select (Bits [7:0]) The Transmit Gap Select field sets the inactive time between transmitted bytes. The inactive time = (Transmit Gap Select –7) * bit time. Therefore a Transmit Gap Select Value of 8 is equal to having one Stop bit. HSS Data Register [0xC076] [R/W] Table 93. HSS Data Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Read/Write - - - - - - - - Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 Field Data Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X X X X X Register Description Data (Bits [7:0]) The HSS Data register contains data received on the HSS port The Data field contains the data received or to be transmitted on (not for block receive mode) when read. This receive data is valid the HSS port. when the Receive Ready bit of the HSS Control register is set to ‘1’. Writing to this register initiates a single byte transfer of data. Reserved The Transmit Ready Flag in the HSS Control register must read Write all reserved bits with ’0’. ‘1’ before writing to this register (this avoids disrupting the previous/current transmission). Document Number: 38-08015 Rev. *P Page 65 of 119

CY7C67300 HSS Receive Address Register [0xC078] [R/W] Table 94. HSS Receive Address Register Bit # 15 14 13 12 11 10 9 8 Field Address... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Address Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Address (Bits [15:0]) The HSS Receive Address register is used as the base pointer The Address field sets the base pointer address for the next HSS address for the next HSS block receive transfer. block receive transfer. HSS Receive Counter Register [0xC07A] [R/W] Table 95. HSS Receive Counter Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Counter... Read/Write - - - - - - R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Counter Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Counter (Bits [9:0]) The HSS Receive Counter register designates the block byte The Counter field value is equal to the word count minus one length for the next HSS receive transfer. Load this register with giving a maximum value of 0x03FF (1023) or 2048 bytes. When the word count minus one to start the block receive transfer. As the transfer is complete this register returns 0x03FF until each byte is received this register value is decremented. When reloaded. read, this register indicates the remaining length of the transfer. Reserved Write all reserved bits with ’0’. Document Number: 38-08015 Rev. *P Page 66 of 119

CY7C67300 HSS Transmit Address Register [0xC07C] [R/W] Table 96. HSS Transmit Address Register Bit # 15 14 13 12 11 10 9 8 Field Address... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Address Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Address (Bits [15:0]) The HSS Transmit Address register is used as the base pointer The Address field sets the base pointer address for the next HSS address for the next HSS block transmit transfer. block transmit transfer. HSS Transmit Counter Register [0xC07E] [R/W] Table 97. HSS Transmit Counter Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Counter... Read/Write - - - - - - R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Counter Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Counter (Bits [9:0]) The HSS Transmit Counter register designates the block byte The Counter field value is equal to the word count minus one length for the next HSS transmit transfer. Load this register with giving a maximum value of 0x03FF (1023) or 2048 bytes. When the word count minus one to start the block transmit transfer. As the transfer is complete this register returns 0x03FF until each byte is transmitted this register value is decremented. reloaded. When read, this register indicates the remaining length of the transfer. Reserved Write all reserved bits with ’0’. Document Number: 38-08015 Rev. *P Page 67 of 119

CY7C67300 HPI Registers Table 98. HPI Registers There are five registers dedicated to HPI operation. In addition, Register Name Address R/W there is an HPI status port which can be addressed over HPI. HPI Breakpoint Register 0x0140 R Each of these registers is covered in this section and are summa- rized in Table98. Interrupt Routing Register 0x0142 R SIE1msg Register 0x0144 W SIE2msg Register 0x0148 W HPI Mailbox Register 0xC0C6 R/W HPI Breakpoint Register [0x0140] [R] Table 99. HPI Breakpoint Register Bit # 15 14 13 12 11 10 9 8 Field Address... Read/Write R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Address Read/Write R R R R R R R R Default 0 0 0 0 0 0 0 0 Register Description When the program counter matches the Breakpoint Address, the INT127 interrupt triggers. To clear this interrupt, write a zero a to The HPI Breakpoint register is a special on-chip memory location this register. that the external processor can access using normal HPI memory read/write cycles. This register is read only by the CPU Address (Bits [15:0]) but is read/write by the HPI port. The contents of this register have the same effect as the Breakpoint register [0xC014]. This The Address field is a 16-bit field containing the breakpoint special Breakpoint register is used by software debuggers that address. interface through the HPI port instead of the serial port. Interrupt Routing Register [0x0142] [R] Table 100. Interrupt Routing Register Bit # 15 14 13 12 11 10 9 8 VBUS to HPI ID to HPI SOF/EOP2 to SOF/EOP2 to SOF/EOP1 to SOF/EOP1 to Reset2 to HPI HPI Swap 1 Field Enable Enable HPI Enable CPU Enable HPI Enable CPU Enable Enable Enable Read/Write - - - - - - - - Default 0 0 0 1 0 1 0 0 Bit # 7 6 5 4 3 2 1 0 Resume2 to Resume1 to Reserved Done2 to HPI Done1 to HPI Reset1 to HPI HPI Swap 0 Field HPI Enable HPI Enable Enable Enable Enable Enable Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Register Description where the interrupts are routed. The individual interrupt enable is handled in the SIE interrupt enable register. The Interrupt Routing register allows the HPI port to take over some or all of the SIE interrupts that usually go to the on-chip VBUS to HPI Enable (Bit 15) CPU. This register is read only by the CPU but is read/write by the HPI port. By setting the appropriate bit to ‘1’, the SIE interrupt The VBUS to HPI Enable bit routes the OTG VBUS interrupt to is routed to the HPI port to become the HPI_INTR signal and also the HPI port instead of the on-chip CPU. readable in the HPI Status register. The bits in this register select 1: Route signal to HPI port 0: Do not route signal to HPI port Document Number: 38-08015 Rev. *P Page 68 of 119

CY7C67300 ID to HPI Enable (Bit 14) Resume2 to HPI Enable (Bit 7) The ID to HPI Enable bit routes the OTG ID interrupt to the HPI The Resume2 to HPI Enable bit routes the USB Resume port instead of the on-chip CPU. interrupt that occurs on Host 2 to the HPI port instead of the on- chip CPU. 1: Route signal to HPI port 1: Route signal to HPI port 0: Do not route signal to HPI port 0: Do not route signal to HPI port SOF/EOP2 to HPI Enable (Bit 13) Resume1 to HPI Enable (Bit 6) The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2 interrupt to the HPI port. The Resume1 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 1 to the HPI port instead of the on- 1: Route signal to HPI port chip CPU. 0: Do not route signal to HPI port 1: Route signal to HPI port SOF/EOP2 to CPU Enable (Bit 12) 0: Do not route signal to HPI port The SOF/EOP2 to CPU Enable bit routes the SOF/EOP2 Done2 to HPI Enable (Bit 3) interrupt to the on-chip CPU. Since the SOF/EOP2 interrupt can be routed to both the on-chip CPU and the HPI port, the firmware The Done2 to HPI Enable bit routes the Done interrupt for Host/ must ensure only one of the two (CPU, HPI) resets the interrupt. Device 2 to the HPI port instead of the on-chip CPU. 1: Route signal to CPU 1: Route signal to HPI port 0: Do not route signal to CPU 0: Do not route signal to HPI port SOF/EOP1 to HPI Enable (Bit 11) Done1 to HPI Enable (Bit 2) The SOF/EOP1 to HPI Enable bit routes the SOF/EOP1 interrupt The Done1 to HPI Enable bit routes the Done interrupt for Host/ to the HPI port. Device 1 to the HPI port instead of the on-chip CPU. 1: Route signal to HPI port 1: Route signal to HPI port 0: Do not route signal to HPI port 0: Do not route signal to HPI port SOF/EOP1 to CPU Enable (Bit 10) Reset1 to HPI Enable (Bit 1) The SOF/EOP1 to CPU Enable bit routes the SOF/EOP1 The Reset1 to HPI Enable bit routes the USB Reset interrupt that interrupt to the on-chip CPU. Since the SOF/EOP1 interrupt can occurs on Device 1 to the HPI port instead of the on-chip CPU. be routed to both the on-chip CPU and the HPI port, the firmware 1: Route signal to HPI port must ensure only one of the two (CPU, HPI) resets the interrupt. 0: Do not route signal to HPI port 1: Route signal to CPU 0: Do not route signal to CPU HPI Swap 0 Enable (Bit 0) Both HPI Swap bits (bits 8 and 0) must be set to identical values. Reset2 to HPI Enable (Bit 9) When set to ‘00’, the most significant data byte goes to The Reset2 to HPI Enable bit routes the USB Reset interrupt that HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. occurs on Device 2 to the HPI port instead of the on-chip CPU. This is the default setting. By setting to ‘11’, the most significant data byte goes to HPI_D[7:0] and the least significant byte goes 1: Route signal to HPI port to HPI_D[15:8]. 0: Do not route signal to HPI port HPI Swap 1 Enable (Bit 8) Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to ‘00’, the most significant data byte goes to HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to ‘11’, the most significant data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8]. Document Number: 38-08015 Rev. *P Page 69 of 119

CY7C67300 SIEXmsg Register [W] ■SIE1msg Register 0x0144 [15] ■SIE2msg Register 0x0148 [15] Table 101. SIEXmsg Register Bit # 15 14 13 12 11 10 9 8 Field Data... Read/Write W W W W W W W W Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 Field ...Data Read/Write W W W W W W W W Default X X X X X X X X Register Description Data (Bits [15:0]) The SIEXmsg register allows an interrupt to be generated on the The Data field[15:0] simply needs to have any value written to it HPI port. Any write to this register causes the SIEXmsg flag in to cause SIExmsg flag in the HPI Status Port to go high. the HPI Status Port to go high and also causes an interrupt on the HPI_INTR pin. The SIEXmsg flag is automatically cleared when the HPI port reads from this register. HPI Mailbox Register [0xC0C6] [R/W] Table 102. HPI Mailbox Register Bit # 15 14 13 12 11 10 9 8 Field Message... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Message Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description In addition, when the CY7C67300 writes to this register, the HPI_INTR signal on the HPI port asserts, signaling the external The HPI Mailbox register provides a common mailbox between processor that there is data in the mailbox to read. The the CY7C67300 and the external host processor. HPI_INTR signal deasserts when the external host processor If enabled, the HPI Mailbox RX Full interrupt triggers when the reads from this register. external host processor writes to this register. When the CY7C67300 reads this register the HPI Mailbox RX Full interrupt Message (Bits [15:0]) is automatically cleared. The Message field contains the message that the host processor If enabled, the HPI Mailbox TX Empty interrupt triggers when the wrote to the HPI Mailbox register. external host processor reads from this register. The HPI Mailbox TX Empty interrupt automatically clears when the CY7C67300 writes to this register. Note 15.Errata: The SIE1msg and SIE2msg Registers [0x0144 and 0x0148] are not initialized at power up. Please refer to Errata on page 107 for details and workaround. Document Number: 38-08015 Rev. *P Page 70 of 119

CY7C67300 HPI Status Port [] [HPI: R] Table 103. HPI Status Port Bit # 15 14 13 12 11 10 9 8 VBUS ID Reserved SOF/EOP2 Reserved SOF/EOP1 Reset2 Mailbox In Field Flag Flag Flag Flag Flag Flag Read/Write R R - R - R R R Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 Resume2 Resume1 SIE2msg SIE1msg Done2 Done1 Reset1 Mailbox Out Field Flag Flag Flag Flag Flag Flag Read/Write R R R R R R R R Default X X X X X X X X Register Description Mailbox In Flag (Bit 8) The HPI Status Port provides the external host processor with The Mailbox In Flag bit is a read only bit that indicates if a the MailBox status bits plus several SIE status bits. This register message is ready in the incoming mailbox. This interrupt clears is not accessible from the on-chip CPU. The additional SIE status when the on-chip CPU reads from the HPI Mailbox register. bits are provided to aid external device driver firmware devel- 1: Interrupt triggered opment, and are not recommended for applications that do not have an intimate relationship with the on-chip BIOS. 0: Interrupt did not trigger Reading from the HPI Status Port does not result in a CPU HPI Resume2 Flag (Bit 7) interface memory access cycle. The external host may continu- The Resume2 Flag bit is a read only bit that indicates if a USB ously poll this register without degrading the CPU or DMA perfor- resume interrupt occurs on either Host/Device 2. mance. 1: Interrupt triggered VBUS Flag (Bit 15) 0: Interrupt did not trigger The VBUS Flag bit is a read only bit that indicates whether OTG VBus is greater than 4.4V. After turning on VBUS, firmware must Resume1 Flag (Bit 6) wait at least 10 µs before this reading this bit. The Resume1 Flag bit is a read only bit that indicates if a USB 1: OTG VBus is greater than 4.4V resume interrupt occurs on either Host/Device 1. 0: OTG VBus is less than 4.4V 1: Interrupt triggered 0: Interrupt did not trigger ID Flag (Bit 14) The ID Flag bit is a read only bit that indicates the state of the SIE2msg (Bit 5) OTG ID pin. The SIE2msg Flag bit is a read only bit that indicates if the CY7C67300 CPU wrote to the SIE2msg register. This bit is SOF/EOP2 Flag (Bit 12) cleared on an HPI read. The SOF/EOP2 Flag bit is a read only bit that indicates if a SOF/ 1: The SIE2msg register was written by the CY7C67300 CPU EOP interrupt occurs on either Host/Device 2. 0: The SIE2msg register was not written by the CY7C67300 CPU 1: Interrupt triggered SIE1msg (Bit 4) 0: Interrupt did not trigger The SIE1msg Flag bit is a read only bit that indicates if the SOF/EOP1 Flag (Bit 10) CY7C67300 CPU wrote to the SIE1msg register. This bit is The SOF/EOP1 Flag bit is a read only bit that indicates if a SOF/ cleared on an HPI read. EOP interrupt occurs on either Host/Device 1. 1: The SIE1msg register was written by the CY7C67300 CPU 1: Interrupt triggered 0: The SIE1msg register was not written by the CY7C67300 CPU 0: Interrupt did not trigger Done2 Flag (Bit 3) Reset2 Flag (Bit 9) In host mode the Done2 Flag bit is a read only bit that indicates The Reset2 Flag bit is a read only bit that indicates if a USB if a host packet done interrupt occurs on Host 2. In device mode Reset interrupt occurs on either Host/Device 2. this read only bit indicates if an any of the endpoint interrupts occur on Device 2. Firmware needs to determine which endpoint 1: Interrupt triggered interrupt occurred. 0: Interrupt did not trigger 1: Interrupt triggered 0: Interrupt did not trigger Document Number: 38-08015 Rev. *P Page 71 of 119

CY7C67300 Done1 Flag (Bit 2) The Reset1 Flag bit is a read only bit that indicates if a USB Reset interrupt occurs on either Host/Device 1. In host mode the Done 1 Flag bit is a read only bit that indicates if a host packet done interrupt occurs on Host 1. In device mode 1: Interrupt triggered this read only bit indicates if an any of the endpoint interrupts 0: Interrupt did not trigger occur on Device 1. Firmware needs to determine which endpoint interrupt occurred. Mailbox Out Flag (Bit 0) 1: Interrupt triggered The Mailbox Out Flag bit is a read only bit that indicates if a 0: Interrupt did not trigger message is ready in the outgoing mailbox. This interrupt clears when the external host reads from the HPI Mailbox register. Reset1 Flag (Bit 1) 1: Interrupt triggered 0: Interrupt did not trigger SPI Registers There are twelve registers dedicated to SPI operation. Each of these registers is covered in this section and summarized in Table104. Table 104. SPI Registers Register Name Address R/W SPI Configuration Register 0xC0C8 R/W SPI Control Register 0xC0CA R/W SPI Interrupt Enable Register 0xC0CC R/W SPI Status Register 0xC0CE R SPI Interrupt Clear Register 0xC0D0 W SPI CRC Control Register 0xC0D2 R/W SPI CRC Value 0xC0D4 R/W SPI Data Register 0xC0D6 R/W SPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/W SPI Receive Address Register 0xC0DC R/W SPI Receive Count Register 0xC0DE R/W Document Number: 38-08015 Rev. *P Page 72 of 119

CY7C67300 SPI Configuration Register [0xC0C8] [R/W] Table 105. SPI Configuration Register Bit # 15 14 13 12 11 10 9 8 3Wire Phase SCK Polarity Scale Select Reserved Field Enable Select Select Read/Write R/W R/W R/W R/W R/W R/W R/W - Default 1 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Master Master SS SS Delay Select Active Enable Enable Field Enable Read/Write R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 1 1 1 1 1 Register Description Table 106. Scale Select Field Definition for SCK Frequency The SPI Configuration register controls the SPI port. Fields apply Scale Select [12:9] SCK Frequency to both master and slave mode unless otherwise noted. 1001 500 KHz 3Wire Enable (Bit 15) 1010 375 KHz The 3Wire Enable bit indicates if the MISO and MOSI data lines 1011 250 KHz are tied together allowing only half duplex operation. 1100 375 KHz 1: MISO and MOSI data lines are tied together 1101 250 KHz 0: Normal MISO and MOSI Full Duplex operation (not tied 1110 375 KHz together) 1111 250 KHz Phase Select (Bit 14) Master Active Enable (Bit 7) The Phase Select bit selects advanced or delayed SCK phase. This field only applies to master mode. The Master Active Enable bit is a read only bit that indicates if the master state machine is active or idle. This field only applies 1: Advanced SCK phase to master mode. 0: Delayed SCK phase 1: Master state machine is active SCK Polarity Select (Bit 13) 0: Master state machine is idle This SCK Polarity Select bit selects the polarity of SCK. Master Enable (Bit 6) 1: Positive SCK polarity The Master Enable bit sets the SPI interface to master or slave. 0: Negative SCK polarity This bit is only writable when the Master Active Enable bit reads ‘0’, otherwise the value does not change. Scale Select (Bits [12:9]) 1: Master SPI interface The Scale Select field provides control over the SCK frequency, based on 48 MHz. Refer to Table106 for a definition of this field. 0: Slave SPI interface This field only applies to master mode. SS Enable (Bit 5) Table 106. Scale Select Field Definition for SCK Frequency The SS Enable bit enables or disables the master SS output. Scale Select [12:9] SCK Frequency 1: Enable master SS output 0000 12 MHz 0: Disable master SS output (three state master SS output, for 0001 8 MHz single SS line in slave mode) 0010 6 MHz SS Delay Select (Bits [4:0]) 0011 4 MHz When the SS Delay Select field is set to ‘00000’ this indicates 0100 3 MHz manual mode. In manual mode SS is controlled by the SS Manual bit of the SPI Control register. When the SS Delay Select 0101 2 MHz field is set between ‘00001’ to ‘11111’, this value indicates the 0110 1.5 MHz count in half bit times of auto transfer delay for: SS low to SCK 0111 1 MHz active, SCK inactive to SS high, SS high time. This field only applies to master mode. 1000 750 KHz Document Number: 38-08015 Rev. *P Page 73 of 119

CY7C67300 SPI Control Register [0xC0CA] [R/W] Table 107. SPI Control Register Bit # 15 14 13 12 11 10 9 8 SCK FIFO Byte Full Duplex SS Read Transmit Receive Strobe Init Mode Manual Enable Ready Data Field Ready Read/Write W W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 1 Bit # 7 6 5 4 3 2 1 0 Transmit Receive Transmit Bit Length Receive Bit Length Field Empty Full Read/Write R R R/W R/W R/W R/W R/W R/W Default 1 0 0 0 0 0 0 0 Register Description Read Enable (Bit 10) The SPI Control register controls the SPI port. Fields apply to The Read Enable bit initiates a read phase for a master mode both master and slave mode unless otherwise noted. transfer or sets the slave to receive (in slave mode). 1: Initiates a read phase for a master transfer or sets a slave to SCK Strobe (Bit 15) receive. In master mode this bit is sticky and remains set until the The SCK Strobe bit starts the SCK strobe at the selected read transfer begins. frequency and polarity (set in the SPI Configuration register), but 0: Initiates the write phase for slave operation not phase. This bit feature can only be enabled when in master mode and must be during a period of inactivity. This bit is self Transmit Ready (Bit 9) clearing. The Transmit Ready bit is a read only bit that indicates if the 1: SCK Strobe Enable transmit port is ready to empty and ready to be written. 0: No Function 1: Ready for data to be written to the port. The transmit FIFO is not full. FIFO Init (Bit 14) 0: Not ready for data to be written to the port The FIFO Init bit initializes the FIFO and clears the FIFO Error Status bit. This bit is self clearing. Receive Data Ready (Bit 8) 1: FIFO Init Enable The Receive Data Ready bit is a read only bit that indicates if the receive port has data ready. 0: No Function 1: Receive port has data ready to read Byte Mode (Bit 13) 0: Receive port does not have data ready The Byte Mode bit selects between PIO (byte mode) and DMA (block mode) operation. Transmit Empty (Bit 7) 1: Set PIO (byte mode) operation The Transmit Empty bit is a read only bit that indicates if the transmit FIFO is empty. 0: Set DMA (block mode) operation 1: Transmit FIFO is empty Full Duplex (Bit 12) 0: Transmit FIFO is not empty The Full Duplex bit selects between full duplex and half duplex operation. Receive Full (Bit 6) 1: Enable full duplex. Full duplex is not allowed and does not set The Receive Full bit is a read only bit that indicates if the receive if the 3Wire Enable bit of the SPI Configuration register is set to FIFO is full. ‘1’ 1: Receive FIFO is full 0: Enable half duplex operation 0: Receive FIFO is not full SS Manual (Bit 11) Transmit Bit Length (Bits [5:3]) The SS Manual bit activates or deactivates SS if the SS Delay The Transmit Bit Length field controls whether a full byte or Select field of the SPI Control register is all zeros and is partial byte is to be transmitted. If Transmit Bit Length is ‘000’ configured as master interface. This field only applies to master then a full byte is transmitted. If Transmit Bit Length is ‘001’ to mode. ‘111’, then the value indicates the number of bits that are be 1: Activate SS, master drives SS line asserted LOW transmitted. 0: Deactivate SS, master drives SS line deasserted HIGH Document Number: 38-08015 Rev. *P Page 74 of 119

CY7C67300 Receive Bit Length (Bits [2:0]) The Receive Bit Length field controls whether a full byte or partial byte is received. If Receive Bit Length is ‘000’ then a full byte is received. If Receive Bit Length is ‘001’ to ‘111’, then the value indicates the number of bits that are received. SPI Interrupt Enable Register [0xC0CC] [R/W] Table 108. SPI Interrupt Enable Register Bit # 15 14 13 12 11 10 9 8 Field Reserved... Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 ...Reserved Receive Transmit Transfer Interrupt Interrupt Interrupt Field Enable Enable Enable Read/Write - - - - - R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description 1: Enables byte mode transmit interrupt The SPI Interrupt Enable register controls the SPI port. 0: Disables byte mode transmit interrupt Receive Interrupt Enable (Bit 2) Transfer Interrupt Enable (Bit 0) The Receive Interrupt Enable bit enables or disables the byte The Transfer Interrupt Enable bit enables or disables the block mode receive interrupt (RxIntVal). mode interrupt (XfrBlkIntVal). 1: Enable byte mode receive interrupt 1: Enables block mode interrupt 0: Disable byte mode receive interrupt 0: Disables block mode interrupt Transmit Interrupt Enable (Bit 1) Reserved The Transmit Interrupt Enable bit enables or disables the byte Write all reserved bits with ’0’. mode transmit interrupt (TxIntVal). SPI Status Register [0xC0CE] [R] Table 109. SPI Status Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 FIFO Error Reserved Receive Transmit Transfer Flag Interrupt Interrupt Interrupt Field Flag Flag Flag Read/Write R - - - - R R R Default 0 0 0 0 0 0 0 0 Register Description bit of the SPI Control register is set to ‘1’, then a Tx FIFO underflow occurred. Similarly, when set with the Receive Full bit The SPI Status register is a read only register that provides of the SPI Control register, an Rx FIFO overflow occured.This bit status for the SPI port. automatically clears when the SPI FIFO Init Enable bit of the SPI FIFO Error Flag (Bit 7) Control register is set. The FIFO Error Flag bit is a read only bit that indicates if a FIFO 1: Indicates FIFO error error occurred. When this bit is set to ‘1’ and the Transmit Empty 0: Indicates no FIFO error Document Number: 38-08015 Rev. *P Page 75 of 119

CY7C67300 Receive Interrupt Flag (Bit 2) 1: Indicates a byte mode transmit interrupt triggered The Receive Interrupt Flag is a read only bit that indicates if a 0: Indicates a byte mode transmit interrupt did not trigger byte mode receive interrupt triggered. Transfer Interrupt Flag (Bit 0) 1: Indicates a byte mode receive interrupt triggered The Transfer Interrupt Flag is a read only bit that indicates a 0: Indicates a byte mode receive interrupt did not trigger block mode interrupt triggered. Transmit Interrupt Flag (Bit 1) 1: Indicates a block mode interrupt triggered The Transmit Interrupt Flag is a read only bit that indicates a byte 0: Indicates a block mode interrupt did not trigger mode transmit interrupt triggered. SPI Interrupt Clear Register [0xC0D0] [W] Table 110. SPI Interrupt Clear Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Reserved Transmit Transfer Interrupt Interrupt Field Clear Clear Read/Write - - - - - - W W Default 0 0 0 0 0 0 0 0 Register Description Transfer Interrupt Clear (Bit 0) The SPI Interrupt Clear register is a write only register that allows The Transfer Interrupt Clear bit is a write only bit that clears the the SPI Transmit and SPI Transfer Interrupts to be cleared. block mode interrupt. This bit is self clearing. 1: Clear the block mode interrupt Transmit Interrupt Clear (Bit 1) 0: No function The Transmit Interrupt Clear bit is a write only bit that clears the byte mode transmit interrupt. This bit is self clearing. Reserved 1: Clear the byte mode transmit interrupt Write all reserved bits with ’0’. 0: No function SPI CRC Control Register [0xC0D2] [R/W] Table 111. SPI CRC Control Register Bit # 15 14 13 12 11 10 9 8 CRC Mode CRC CRC Receive One in Zero in Reserved... Field Enable Clear CRC CRC CRC Read/Write R/W R/W R/W R/W R/W R R - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Reserved Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Register Description CRC Mode (Bits [15:14) The SPI CRC Control register provides control over the CRC The CRCMode field selects the CRC polynomial as defined in source and polynomial value. Table112on page77. Document Number: 38-08015 Rev. *P Page 76 of 119

CY7C67300 Table 112. CRC Mode Definition Receive CRC (Bit 11) The Receive CRC bit determines whether the receive bit stream CRCMode CRC Polynomial or the transmit bit stream is used for the CRC data input in full [15:14] duplex mode. This bit is a don’t care in half duplex mode. 00 MMC 16 bit: X^16 + X^12 + X^5 + 1(CCITT 1: Assigns the receive bit stream Standard) 0: Assigns the transmit bit stream 01 CRC7 7 bit: X^7+ X^3 + 1 10 MST 16 bit: X^16+ X^15 + X^2 + 1 One in CRC (Bit 10) The One in CRC bit is a read only bit that indicates if the CRC 11 Reserved, 16 bit polynomial 1 value is all zeros or not CRC Enable (Bit 13) 1: CRC value is not all zeros The CRC Enable bit enables or disables the CRC operation. 0: CRC value is all zeros 1: Enables CRC operation Zero in CRC (Bit 9) 0: Disables CRC operation The Zero in CRC bit is a read only bit that indicates if the CRC value is all ones or not. CRC Clear (Bit 12) 1: CRC value is not all ones The CRC Clear bit clears the CRC with a load of all ones. This bit is self clearing and always reads ‘0’. 0: CRC value is all ones 1: Clear CRC with all ones Reserved 0: No Function Write all reserved bits with ’0’. SPI CRC Value Register [0xC0D4] [R/W] Table 113. SPI CRC Value Register Bit # 15 14 13 12 11 10 9 8 Field CRC... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 Bit # 7 6 5 4 3 2 1 0 Field ...CRC Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 Register Description CRC (Bits [15:0]) The SPI CRC Value register contains the CRC value. The CRC field contains the SPI CRC. In CRC Mode CRC7, the CRC value is a seven bit value [6:0]. Therefore, bits [15:7] are invalid in CRC7 mode. Document Number: 38-08015 Rev. *P Page 77 of 119

CY7C67300 SPI Data Register [0xC0D6] [R/W] Table 114. SPI Data Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Read/Write - - - - - - - - Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 Field Data Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X X X X X Register Description Data (Bits [7:0]) The SPI Data register contains data received on the SPI port The Data field contains data received or to be transmitted on the when read. Reading it empties the eight byte receive FIFO in PIO SPI port. byte mode. This receive data is valid when the Receive Interrupt Bit of the SPI Status register is set to ‘1’ (RxIntVal triggers) or the Reserved Receive Data Ready bit of the SPI Control register is set to ‘1’. Write all reserved bits with ’0’. Writing to this register in PIO byte mode initiates a transfer of data, the number of bits defined by Transmit Bit Length field in the SPI Control register. SPI Transmit Address Register [0xC0D8] [R/W] Table 115. SPI Transmit Address Register Bit # 15 14 13 12 11 10 9 8 Field Address... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Address Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Address (Bits [15:0]) The SPI Transmit Address register is used as the base address The Address field sets the base address for the SPI transmit for the SPI transmit DMA. DMA. Document Number: 38-08015 Rev. *P Page 78 of 119

CY7C67300 SPI Transmit Count Register [0xC0DA] [R/W] Table 116. SPI Transmit Count Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Count... Read/Write - - - - - R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Count Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Reserved The SPI Transmit Count register designates the block byte Write all reserved bits with ’0’. length for the SPI transmit DMA transfer. Count (Bits [10:0]) The Count field sets the count for the SPI transmit DMA transfer. SPI Receive Address Register [0xC0DC [R/W] Table 117. SPI Receive Address Register Bit # 15 14 13 12 11 10 9 8 Field Address... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Address Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Address (Bits [15:0]) The SPI Receive Address register is issued as the base address The Address field sets the base address for the SPI receive for the SPI Receive DMA. DMA. SPI Receive Count Register [0xC0DE] [R/W] Table 118. SPI Receive Count Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Count... Read/Write - - - - - R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Count Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Document Number: 38-08015 Rev. *P Page 79 of 119

CY7C67300 Register Description UART Registers The SPI Receive Count register designates the block byte length There are three registers dedicated to UART operation. Each of for the SPI receive DMA transfer. these registers is covered in this section and summarized in Table119. Count (Bits [10:0]) Table 119. UART Registers The Count field sets the count for the SPI receive DMA transfer. Register Name Address R/W Reserved UART Control Register 0xC0E0 R/W Write all reserved bits with ’0’. UART Status Register 0xC0E2 R UART Data Register 0xC0E4 R/W UART Control Register [0xC0E0] [R/W] Table 120. UART Control Register Bit # 15 14 13 12 11 10 9 8 Field Reserved... Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Reserved Scale Select Baud Select UART Enable Read/Write - - - R/W R/W R/W R/W R/W Default 0 0 0 0 0 1 1 1 Register Description Table 121. UART Baud Select Definition The UART Control register enables or disables the UART, Baud Select allowing GPIO28 (UART_TXD) and GPIO27 (UART_RXD) to be Baud Rate w/ DIV8 = 0 Baud Rate w/ DIV8 = 1 [3:1] freed up for general use. This register must also be written to set the baud rate, which is based on a 48 MHz clock. 000 115.2 KBaud 14.4 KBaud 001 57.6 KBaud 7.2 KBaud Scale Select (Bit 4) 010 38.4 KBaud 4.8 KBaud The Scale Select bit acts as a prescaler that divide the baud rate by eight. 011 28.8 KBaud 3.6 KBaud 1: Enable prescaler 100 19.2 KBaud 2.4 KBaud 0: Disable prescaler 101 14.4 KBaud 1.8 KBaud 110 9.6 KBaud 1.2 KBaud Baud Select (Bits [3:1]) 111 7.2 KBaud 0.9 KBaud Refer to Table121 for a definition of this field. UART Enable (Bit 0) The UART Enable bit enables or disables the UART. 1: Enable UART 0: Disable UART. This allows GPIO28 and GPIO27 to be used for general use. Reserved Write all reserved bits with ’0’. Document Number: 38-08015 Rev. *P Page 80 of 119

CY7C67300 UART Status Register [0xC0E2] [R] Table 122. UART Status Register Bit # 15 14 13 12 11 10 9 8 Field Reserved... Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Reserved Receive Full Transmit Full Read/Write - - - - - - R R Default 0 0 0 0 0 0 0 0 Register Description Transmit Full (Bit 0) The UART Status register is a read only register that indicates The Transmit Full bit indicates whether the transmit buffer is full. the status of the UART buffer. It can be programmed to interrupt the CPU as interrupt #4 when the buffer is empty. This can be done though the UART bit of the Receive Full (Bit 1) Interrupt Enable register (0xC00E). This bit is automatically set The Receive Full bit indicates whether the receive buffer is full. to ‘1’ after data is written by EZ-Host to the UART Data register It can be programmed to interrupt the CPU as interrupt #5 when (to be transmitted). This bit is automatically cleared to ‘0’ after the buffer is full. This can be done though the UART bit of the the data is transmitted. Interrupt Enable register (0xC00E). This bit is automatically 1: Transmit buffer full (transmit busy) cleared when data is read from the UART Data register. 0: Transmit buffer is empty and ready for a new byte of data 1: Receive buffer full 0: Receive buffer empty UART Data Register [0xC0E4] [R/W] Table 123. UART Data Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field Data Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Data (Bits [7:0]) The UART Data register contains data to be transmitted or The Data field is where the UART data to be transmitted or received from the UART port. Data written to this register starts received is located. a data transmission and also causes the UART Transmit Full Flag of the UART Status register to set. When data received on Reserved the UART port is read from this register, the UART Receive Full Write all reserved bits with ’0’. Flag of the UART Status register is cleared. Document Number: 38-08015 Rev. *P Page 81 of 119

CY7C67300 PWM Registers There are eleven registers dedicated to PWM operation. Each of these registers are covered in this section and summarized in Table124. Table 124. PWM Registers Register Name Address R/W PWM Control Register 0xC0E6 R/W PWM Maximum Count Register 0xC0E8 R/W PWM0 Start Register 0xC0EA R/W PWM0 Stop Register 0xC0EC R/W PWM1 Start Register 0xC0EE R/W PWM1 Stop Register 0xC0F0 R/W PWM2 Start Register 0xC0F2 R/W PWM2 Stop Register 0xC0F4 R/W PWM3 Start Register 0xC0F6 R/W PWM3 Stop Register 0xC0F8 R/W PWM Cycle Count Register 0xC0FA R/W PWM Control Register [0xC0E6] [R/W] Table 125. PWM Control Register Bit # 15 14 13 12 11 10 9 8 PWM Reserved Prescale Mode Field Enable Select Select Read/Write R/W - - - R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 PWM 3 PWM 2 PWM 1 PWM 0 PWM 3 PWM 2 PWM 1 PWM 0 Polarity Polarity Polarity Polarity Enable Enable Enable Enable Field Select Select Select Select Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Table 126. Prescaler Select Definition The PWM Control register provides high level control over all four Prescale Select [11:9] Frequency of the PWM channels. 000 48.00 MHz PWM Enable (Bit 15) 001 24.00 MHz The PWM Enable bit starts and stops PWM operation. 010 06.00 MHz 1: Start operation 011 01.50 MHz 0: Stop operation 100 375 kHz Prescale Select (Bits [11:9]) 101 93.80 kHz The Prescale Select field sets the frequency of all the PWM 110 23.40 kHz channels as defined in Table126. 111 05.90 kHz Document Number: 38-08015 Rev. *P Page 82 of 119

CY7C67300 Mode Select (Bit 8) PWM 0 Polarity Select (Bit 4) The Mode Select bit selects between continuous PWM cycling The PWM 0 Polarity Select bit selects the polarity for PWM 0. and one shot mode. The default is continuous repeat. 1: Sets the polarity to active HIGH or rising edge pulse 1: Enable One Shot mode. The mode runs the number of counter 0: Sets the polarity to active LOW cycles set in the PWM Cycle Count register and then stops. 0: Enable Continuous mode. Runs in continuous mode and PWM 3 Enable (Bit 3) starts over after the PWM cycle count is reached. The PWM 3 Enable bit enables or disables PWM 3. PWM 3 Polarity Select (Bit 7) 1: Enable PWM 3 The PWM 3 Polarity Select bit selects the polarity for PWM 3. 0: Disable PWM 3 1: Sets the polarity to active HIGH or rising edge pulse PWM 2 Enable (Bit 2) 0: Sets the polarity to active LOW The PWM 2 Enable bit enables or disables PWM 2. PWM 2 Polarity Select (Bit 6) 1: Enable PWM 2 The PWM 2 Polarity Select bit selects the polarity for PWM 2. 0: Disable PWM 2 1: Sets the polarity to active HIGH or rising edge pulse PWM 1 Enable (Bit 1) 0: Sets the polarity to active LOW The PWM 1 Enable bit enables or disables PWM 1. PWM 1 Polarity Select (Bit 5) 1: Enable PWM 1 The PWM 1 Polarity Select bit selects the polarity for PWM 1. 0: Disable PWM 1 1: Sets the polarity to active HIGH or rising edge pulse PWM 0 Enable (Bit 0) 0: Sets the polarity to active LOW The PWM 0 Enable bit enables or disables PWM 0. 1: Enable PWM 0 0: Disable PWM 0 PWM Maximum Count Register [0xC0E8] [R/W] Table 127. PWM Maximum Count Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Count... Read/Write - - - - - - R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Count Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Count (Bits [9:0]) The PWM Maximum Count register designates the maximum The Count field sets the maximum cycle time. window for each pulse cycle. Each count tick is based on the clock frequency set in the PWM Control register. Reserved Write all reserved bits with ’0’. Document Number: 38-08015 Rev. *P Page 83 of 119

CY7C67300 PWM n Start Register [R/W] ■PWM 0 Start Register 0xC0EA ■PWM 1 Start Register 0xC0EE ■PWM 2 Start Register 0xC0F2 ■PWM 3 Start Register 0xC0F6 Table 128. PWM n Start Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Address... Read/Write - - - - - - R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Address Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Address (Bits [9:0]) The PWM n Start register designates where in the window The Address field designates when to start the PWM pulse. If this defined by the PWM Maximum Count register to start the PWM start value is equal to the Stop Count Value then the output stays pulse for a supplied channel. at false. Reserved Write all reserved bits with ’0’. PWM n Stop Register [R/W] ■PWM 0 Stop Register 0xC0EC ■PWM 1 Stop Register 0xC0F0 ■PWM 2 Stop Register 0xC0F4 ■PWM 3 Stop Register 0xC0F8 T able 129. PWM n Stop Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Address... Read/Write - - - - - - R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Address Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description stays at ‘0’. If the PWM Stop value is greater then the PWM Maximum Count value then the output stays at true. The PWM n Stop register designates where in the window defined by the PWM Maximum Count register to stop the PWM Reserved pulse for a supplied channel. Write all reserved bits with ’0’. Address (Bits [9:0]) The Address field designates when to stop the PWM pulse. If the PWM Start value is equal to the PWM Stop value then the output Document Number: 38-08015 Rev. *P Page 84 of 119

CY7C67300 PWM Cycle Count Register [0xC0FA] [R/W] Table 130. PWM Cycle Count Register Bit # 15 14 13 12 11 10 9 8 Field Count... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Count Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description Count (Bits [9:0]) The PWM Cycle Count register designates the number of cycles The Count field designates the number of cycles (plus one) to to run when in one shot mode. One shot mode is enabled by run when in one shot mode. For example, Cycles = PWM Cycle setting the Mode Select bit of the PWM Control register to ‘1’. Count + 1, therefore for two cycles set PWM Cycle Count = 1. Document Number: 38-08015 Rev. *P Page 85 of 119

CY7C67300 Pin Diagram Figure 11. EZ-Host Pin Diagram GND nBEL/A0 nBEH A16 A17 A18 GPIO0/D0 GPIO1/D1 GPIO2/D2 GPIO3/D3 GPIO4/D4 GPIO5/D5 VCC GPIO6/D6 GPIO7/D7 nRESET Reserved D0 D1 D2 D3 D4 D5 D6 D7 10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A1 1 75 GND A2 2 74 D8/MISO A3 3 73 D9/nSSI DM2B 4 72 D10/SCK DP2B 5 71 D11/MOSI AGND 6 70 D12/TXD A4 7 69 D13/RXD A5 8 68 D14/RTS DM2A 9 67 D15/CTS DP2A 10 66 GPIO8/D8/MISO OTGVBUS 11 65 GPIO9/D9/nSSI CSWITCHB 12 CY7C67300 64 nWR CSWITCHA 13 63 VCC VSWITCH 14 62 nRD BOOSTGND 15 61 GPIO10/D10/SCK BOOSTVCC 16 60 GPIO11/D11/MOSI A6 17 59 GPIO12/D12 DM1B 18 58 GPIO13/D13 DP1B 19 57 GPIO14/D14 A7 20 56 GPIO15/D15/nSSI AVCC 21 55 GPIO16/A0/TXD/PWM0 DM1A 22 54 GPIO17/A1/RXD/PWM1 DP1A 23 53 GPIO18/A2/RTS/PWM2 A8 24 52 GPIO19/A0/CS0 A9 25 51 GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND A10 XTALOUT XTALIN A11 A12 A13 A14 nXMEMSEL nXROMSEL nXRAMSEL VCC A15/CLKSEL GPIO31/SCL GPIO30/SDA GPIO29/OTGID GPIO28/TX GPIO27/RX GPIO26/CTS/PWM GPIO25/IRQ1 GPIO24/INT/IORD GPIO23/nRD/IOR GPIO22/nWR/IOW GPIO21/nCS GPIO20/A1/CS1 3 Y /IR Q 0 Pin Descriptions Table 131. Pin Descriptions Pin Name Type Description 67 D15/CTS IO D15: External Memory Data Bus CTS: HSS CTS 68 D14/RTS IO D14: External Memory Data Bus RTS: HSS RTS 69 D13/RXD IO D13: External Memory Data Bus RXD: HSS RXD (Data is received on this pin) 70 D12/TXD IO D12: External Memory Data Bus TXD: HSS TXD (Data is transmitted from this pin) Document Number: 38-08015 Rev. *P Page 86 of 119

CY7C67300 Table 131. Pin Descriptions (Continued) Pin Name Type Description 71 D11/MOSI IO D11: External Memory Data Bus MOSI: SPI MOSI 72 D10/SCK IO D10: External Memory Data Bus SCK: SPI SCK 73 D9/nSSI IO D9: External Memory Data Bus nSSI: SPI nSSI 74 D8/MISO IO D8: External Memory Data Bus MISO: SPI MISO 76 D7 IO External Memory Data Bus 77 D6 IO 78 D5 IO 79 D4 IO 80 D3 IO 81 D2 IO 82 D1 IO 83 D0 IO 33 A14 Output External Memory Address Bus 32 A13 Output 31 A12 Output 30 A11 Output 27 A10 Output 25 A9 Output 24 A8 Output 20 A7 Output 17 A6 Output 8 A5 Output 7 A4 Output 3 A3 Output 2 A2 Output 1 A1 Output 99 nBEL/A0 Output nBEL: Low Byte Enable for 16-bit memories A0: External Memory Address bit A0 for 0-8 bit memories 98 nBEH Output High Byte Enable for 16-bit memories 64 nWR Output External Memory Write pulse 62 nRD Output External Memory Read pulse 97 A16 Output A16: External SRAM A16 96 A17 Output A17: External SRAM A17 95 A18 Output A18: External SRAM A18 34 nXMEMSEL Output External Memory Select 0 35 nXROMSEL Output External Memory Select 1 36 nXRAMSEL Output External Memory Select 2 38 A15/CLKSEL IO A15: External SRAM A15 CLKSEL: Sampled directly after reset to determine what crystal or clock source frequency is being used. 12 MHz is required for normal operation so the CLKSEL pin must have a 47K ohm pull up to V CC. After reset this pin functions as A15. 39 GPIO31/SCK IO GPIO31: General Purpose IO SCK: I2C EEPROM SCK 40 GPIO30/SDA IO GPIO30: General Purpose IO SDA: I2C EEPROM SDA Document Number: 38-08015 Rev. *P Page 87 of 119

CY7C67300 Table 131. Pin Descriptions (Continued) Pin Name Type Description 41 GPIO29/OTGID IO GPIO29: General Purpose IO OTGID: Input for OTG ID pin. When used as OTGID, tie this pin high through an external pull up resistor. Assuming V = 3.0V, a 10K to CC 40K resistor must be used. 42 GPIO28/TX IO GPIO28: General Purpose IO TX: UART TX (Data is transmitted from this pin) 43 GPIO27/RX IO GPIO27: General Purpose IO RX: UART RX (Data is received on this pin) 44 GPIO26/CTS/PWM3 IO GPIO26: General Purpose IO CTS: HSS CTS PWM3: PWM channel 3 45 GPIO25/IRQ1 IO GPIO25: General Purpose IO IRQ1: Interrupt Request 1. See Register 0xC006. This pin is also one of two possible GPIO wakeup sources. 46 GPIO24/INT/ IO GPIO24: General Purpose IO IORDY/IRQ0 INT: HPI INT IORDY: IDE IORDY IRQ0: Interrupt Request 0. See Register 0xC006. This pin is also one of two possible GPIO wakeup sources. 47 GPIO23/nRD/IOR IO GPIO23: General Purpose IO nRD: HPI nRD IOR: IDE IOR 48 GPIO22/nWR/IOW IO GPIO22: General Purpose IO nWR: HPI nWR IOW: IDE IOW 49 GPIO21/nCS IO GPIO21: General Purpose IO nCS: HPI nCS 50 GPIO20/A1/CS1 IO GPIO20: General Purpose IO A1: HPI A1 CS1: IDE CS1 52 GPIO19/A0/CS0 IO GPIO19: General Purpose IO A0: HPI A0 CS0: IDE CS0 53 GPIO18/A2/RTS/ IO GPIO18: General Purpose IO PWM2 A2: IDE A2 RTS: HSS RTS PWM2: PWM channel 2 54 GPIO17/A1/RXD/ IO GPIO17: General Purpose IO PWM1 A1: IDE A1 RXD: HSS RXD (Data is received on this pin) PWM1: PWM channel 1 55 GPIO16/A0/TXD/ IO GPIO16: General Purpose IO PWM0 A0: IDE A0 TXD: HSS TXD (Data is transmitted from this pin) PWM0: PWM channel 0 56 GPIO15/D15/nSSI IO GPIO15: General Purpose IO D15: D15 for HPI or IDE nSSI: SPI nSSI 57 GPIO14/D14 IO GPIO14: General Purpose IO D14: D14 for HPI or IDE 58 GPIO13/D13 IO GPIO13: General Purpose IO D13: D13 for HPI or IDE 59 GPIO12/D12 IO GPIO12: General Purpose IO D12: D12 for HPI or IDE Document Number: 38-08015 Rev. *P Page 88 of 119

CY7C67300 Table 131. Pin Descriptions (Continued) Pin Name Type Description 60 GPIO11/D11/MOSI IO GPIO11: General Purpose IO D11: D11 for HPI or IDE MOSI: SPI MOSI 61 GPIO10/D10/SCK IO GPIO10: General Purpose IO D10: D10 for HPI or IDE SCK: SPI SCK 65 GPIO9/D9/nSSI IO GPIO9: General Purpose IO D9: D9 for HPI or IDE nSSI: SPI nSSI 66 GPIO8/D8/MISO IO GPIO8: General Purpose IO D8: D8 for HPI or IDE MISO: SPI MISO 86 GPIO7/D7 IO GPIO7: General Purpose IO D7: D7 for HPI or IDE 87 GPIO6/D6 IO GPIO6: General Purpose IO D6: D6 for HPI or IDE 89 GPIO5/D5 IO GPIO5: General Purpose IO D5: D5 for HPI or IDE 90 GPIO4/D4 IO GPIO4: General Purpose IO D4: D4 for HPI or IDE 91 GPIO3/D3 IO GPIO3: General Purpose IO D3: D3 for HPI or IDE 92 GPIO2/D2 IO GPIO2: General Purpose IO D2: D2 for HPI or IDE 93 GPIO1/D1 IO GPIO1: General Purpose IO D1: D1 for HPI or IDE 94 GPIO0/D0 IO GPIO0: General Purpose IO D0: D0 for HPI or IDE 22 DM1A IO USB Port 1A D– 23 DP1A IO USB Port 1A D+ 18 DM1B IO USB Port 1B D– 19 DP1B IO USB Port 1B D+ 9 DM2A IO USB Port 2A D– 10 DP2A IO USB Port 2A D+ 4 DM2B IO USB Port 2B D– 5 DP2B IO USB Port 2B D+ 29 XTALIN Input Crystal input or Direct Clock input 28 XTALOUT Output Crystal output. Leave floating if direct clock source is used. 85 nRESET Input Reset 84 Reserved - Tie to Gnd for normal operation. 16 BOOSTV Power Booster Power input: 2.7V to 3.6V CC 14 VSWITCH Analog Booster switching output Output 15 BOOSTGND Ground Booster Ground 11 OTGVBUS Analog IO USB OTG Vbus 13 CSWITCHA Analog Charge Pump Capacitor 12 CSWITCHB Analog Charge Pump Capacitor 21 AV Power USB Power CC 6 AGND Ground USB Ground 37, 63, 88 V Power Main V CC CC 26, 51, 75, GND Ground Main Ground 100 Document Number: 38-08015 Rev. *P Page 89 of 119

CY7C67300 Absolute Maximum Ratings This section lists the absolute maximum ratings. Stresses above Operating Conditions those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can T (Ambient Temperature Under Bias).........–40°C to +85°C A affect device operation and reliability. Supply Voltage (V , AV )...........................+3.0V to +3.6V CC CC Storage Temperature..................................–40°C to +125°C Supply Voltage (BoostV )[16]........................+2.7V to +3.6V CC Ambient Temperature with Power Supplied..–40°C to +85°C Ground Voltage..................................................................0V Supply Voltage to Ground Potential..................0.0V to +3.6V F (Oscillator or Crystal Frequency)....12 MHz ± 500 ppm OSC DC Input Voltage to Any General Purpose Input Pin..... 5.5V ...................................................................Parallel Resonant DC Voltage Applied to XTALIN............. –0.5V to V + 0.5V CC Static Discharge Voltage......................................... > 2000V Max Output Current, per IO.......................................... 4 mA Crystal Requirements (XTALIN, XTALOUT) Table 132. Crystal Requirements Crystal Requirements Min Typical Max Unit (XTALIN, XTALOUT) Parallel Resonant Frequency 12 MHz Frequency Stability –500 +500 PPM Load Capacitance 20 33 pF Driver Level 500 µW Startup Time 5 ms Mode of Vibration: Fundamental DC Characteristics Table 133. DC Characteristics[17] Parameter Description Conditions Min Typ. Max Unit V , AV Supply Voltage 3.0 3.3 3.6 V CC CC BoosV Supply Voltage 2.7 3.6 V CC V Input HIGH Voltage 2.0 5.5 V IH V Input LOW Voltage 0.8 V IL I Input Leakage Current 0< V < V –10.0 +10.0 A I IN CC V Output Voltage HIGH I = 4 mA 2.4 V OH OUT V Output LOW Voltage I = –4 mA 0.4 V OL OUT I Output Current HIGH 10 20 mA OH I Output Current LOW 10 20 mA OL C Input Pin Capacitance Except D+/D– 10 pF IN D+/D– 15 pF V Hysteresis on nReset Pin 250 mV HYS I [18, 19] Supply Current 4 transceivers powered 80 100 mA CC I [18, 19] Supply Current with Booster 4 transceivers powered 135 180 mA CCB Enabled Notes 16.The on-chip voltage booster circuit boosts BoostVCC to provide a nominal 3.3V VCC supply. 17.All tests were conducted with Charge pump off. Document Number: 38-08015 Rev. *P Page 90 of 119

CY7C67300 Table 133. DC Characteristics (Continued)[17] Parameter Description Conditions Min Typ. Max Unit I Sleep Current USB Peripheral: includes 1.5K 210 500 A SLEEP internal pull up Without 1.5K internal pull up 5 30 A I Sleep Current with Booster Enabled USB Peripheral: includes 1.5K 190 500 A SLEEPB internal pull up Without 1.5K internal pull up 5 30 A Table 134. DC Characteristics: Charge Pump Parameter Description Conditions Min Typ. Max Unit V Regulated OTGVBUS Voltage 8 mA< I < 10 mA 4.4 5.25 V A_VBUS_OUT LOAD T V Rise Time I = 10 mA 100 ms A_VBUS_RISE BUS LOAD I Maximum Load Current 8 10 mA A_VBUS_OUT C OUTVBUS Bypass Capacitance 4.4V< V < 5.25V 1.0 6.5 pF DRD_VBUS BUS V OTGVBUS Leakage Voltage OTGVBUS not driven 200 mV A_VBUS_LKG V Dataline Leakage Voltage 342 mV DRD_DATA_LKG I Charge Pump Current Draw I = 8 mA 20 20 mA CHARGE LOAD I = 0 mA 0 1 mA LOAD I Charge Pump Current Draw with I = 8 mA 30 45 mA CHARGEB LOAD Booster Active I = 0 mA 0 5 mA LOAD I B-Device (SRP Capable) Discharge 0V< V < 5.25V 8 mA B_DSCHG_IN BUS Current V A-Device VBUS Valid 4.4 V A_VBUS_VALID V A-Device Session Valid 0.8 2.0 V A_SESS_VALID V B-Device Session Valid 0.8 4.0 V B_SESS_VALID V B-Device Session End 0.2 0.8 V A_SESS_END E Efficiency When Loaded I = 8 mA, V = 3.3V 75 % LOAD CC R Data Line Pull Down 14.25 24.8  PD R A-device V Input Impedance to V is not being driven 40 100 k A_BUS_IN BUS BUS GND R B-device V SRP Pull Up Pull up voltage = 3.0V 281  B_SRP_UP BUS R B-device V SRP Pull Down 656  B_SRP_DWN BUS USB Transceiver USB 2.0 certified in full- and low-speed modes. Notes 18.ICC and ICCB values are the same regardless of USB host or peripheral configuration. 19.There is no appreciable difference in ICC and ICCB values when only two transceivers are powered. Document Number: 38-08015 Rev. *P Page 91 of 119

CY7C67300 AC Timing Characteristics Reset Timing t RESET nRESET t IOACT nRD or nWRL or nWRH Reset Timing Table 135. Reset Timing Parameters Parameter Description Min Typical Max Unit t nRESET Pulse Width 16 clocks[20] RESET t nRESET HIGH to nRD or nWRx active 200 µs IOACT Clock Timing t CLK t XTALIN LOW tHIGH tFALL tRISE Clock Timing Table 136. Clock Timing Parameters Parameter Description Min Typical Max Unit f Clock Frequency 12.0 MHz CLK v [21] Clock Input High 1.5 3.0 3.6 V XINH (XTALOUT left floating) t Clock Period 83.17 83.33 83.5 ns CLK t Clock High Time 36 44 ns HIGH t Clock Low Time 36 44 ns LOW t Clock Rise Time 5.0 ns RISE t Clock Fall Time 5.0 ns FALL Duty Cycle 45 55 % Notes 20.Clock is 12 MHz nominal. 21.vXINH is required to be 3.0 V to obtain an internal 50/50 duty cycle clock. Document Number: 38-08015 Rev. *P Page 92 of 119

CY7C67300 SRAM Read Cycle[24] Address CS t AR t CR t RPW RD t CDH tAC tRDH Din Data Valid Table 137. SRAM Read Cycle Parameters Parameter Description Min Typical Max Unit t CS LOW to RD LOW 1 ns CR t RD HIGH to Data Hold 0 ns RDH t CS HIGH to Data Hold 0 ns CDH t [22] RD LOW Time 38 45 ns RPW t RD LOW to Address Valid 0 ns AR t [23] RAM Access to Data Valid 12 ns AC Notes 22.0 wait state cycle. 23.tAC External SRAM access time = 12 ns for zero and one wait states. The External SRAM access time = 12 ns + (n – 1)*T for wait states = n, n > 1, T = 48 MHz clock period. 24.Read timing is applicable for nXMEMSEL, nXRAMSEL, and nXROMSEL. Document Number: 38-08015 Rev. *P Page 93 of 119

CY7C67300 SRAM Write Cycle [26] Address t AW t CSW CS t WC t WPW WE t DW t DH Dout Data Valid Table 138. SRAM Write Cycle Parameters Parameter Description Min Typical Max Unit t Write Address Valid to WE LOW 7 ns AW t CS LOW to WE LOW 7 ns CSW t Data Valid to WE HIGH 15 ns DW t [25] WE Pulse Width 15 ns WPW t Data Hold from WE HIGH 4.5 ns DH t WE HIGH to CS HIGH 13 ns WC Notes 25.tWPW The write pulse width = 18.8 ns min. for zero and one wait states. The write pulse = 18.8 ns + (n – 1)*T for wait states = n, n > 1, T = 48 MHz clock period. 26.Write timing is applicable for nXMEMSEL, nXRAMSEL and nXROMSEL. Document Number: 38-08015 Rev. *P Page 94 of 119

CY7C67300 I2C EEPROM Timing-Serial IO t t LOW HIGH t t R F SCL tSU.STA tHD.DAT tSU.DAT t tBUF t SU.STO HD.STA SDA IN tAA tDH SDA OUT Table 139. I2C EEPROM Timing Parameters Parameter Description Min Typical Max Unit f Clock Frequency 400 kHz SCL t Clock Pulse Width Low 1300 ns LOW t Clock Pulse Width High 600 ns HIGH t Clock Low to Data Out Valid 900 ns AA t Bus Idle Before New Transmission 1300 ns BUF t Start Hold Time 600 ns HD.STA t Start Setup Time 600 ns SU.STA t Data In Hold Time 0 ns HD.DAT t Data In Setup Time 100 ns SU.DAT t Input Rise Time 300 ns R t Input Fall Time 300 ns F t Stop Setup Time 600 ns SU.STO t Data Out Hold Time 0 ns DH Document Number: 38-08015 Rev. *P Page 95 of 119

CY7C67300 HPI (Host Port Interface) Write Cycle Timing t CYC t t t ASU WP AH ADDR [1:0] t t CSSU CSH nCS nWR nRD Dout [15:0] t t DSU WDH Table 140. HPI Write Cycle Timing Parameters Parameter Description Min Typical Max Unit t Address Setup –1 ns ASU t Address Hold –1 ns AH t Chip Select Setup –1 ns CSSU t Chip Select Hold –1 ns CSH t Data Setup 6 ns DSU t Write Data Hold 2 ns WDH t Write Pulse Width 2 T[27] WP t Write Cycle Time 6 T[27] CYC Notes 27.T = system clock period = 1/48 MHz. Document Number: 38-08015 Rev. *P Page 96 of 119

CY7C67300 HPI (Host Port Interface) Read Cycle Timing t CYC t t t ASU RP AH ADDR [1:0] t t CSSU CSH nCS nWR t RDH nRD Din [15:0] t t ACC RDH Table 141. HPI Read Cycle Timing Parameters Parameter Description Min Typical Max Unit t Address Setup –1 ns ASU t Address Hold –1 ns AH t Chip Select Setup –1 ns CSSU t Chip Select Hold –1 ns CSH t Data Access Time, from HPI_nRD falling 1 T[27] ACC t Read Data Hold, relative to the earlier of 1.5 7 ns RDH HPI_nRD rising or HPI_nCS rising t Read Pulse Width 2 T[27] RP t Read Cycle Time 6 T[27] CYC Document Number: 38-08015 Rev. *P Page 97 of 119

CY7C67300 IDE Timing The IDE interface supports PIO mode 0-4 as specified in the Information Technology-AT Attachment–4 with Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18. HSS BYTE Mode Transmit qt_clk CPU_A[2:0] CPU may start another BYTE transmit right after TxRdy goes high CPUHSS_cs CPU_wr BT BT TxRdy flag HSS_TxD start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit start bit start of last data bit to TxRdy high: TxRdy low to start bit delay: 0 min, 4 T max. programmable Byte transmit 0 min, BT max when starting from IDEL. 1 or 2 stop bits. triggered by a For back to back transmit, new START Bit (T is qt_clk period) 1 stop bit shown. CPU write to the begins immediately following previous STOP bit. HSS_TxData register (BT = bit period) qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate the relationship between CPU opera- tions and HSS port operations. Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value ‘1’. BT = bit time = 1/baud rate. HSS Block Mode Transmit BT HSS_TxD t GAP BLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value. The BLOCK mode STOP bit time, t = (HSS_GAP – 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS GAP Transmit Gap register [0xC074]. The default t is 2 BT. GAP BT = bit time = 1/baud rate. HSS BYTE and BLOCK Mode Receive BT +/- 5% received byte added to BT +/- 5% receive FIFO during the final data bit time HSS_RxD start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit start bit 10 BT +/- 5% Receive data arrives asynchronously relative to the internal clock. Incoming data bit rate may deviate from the programmed baud rate clock by as much as ±5% (with HSS_RATE value of 23 or higher). BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag. BLOCK mode received bytes are written directly to the memory system. Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value ‘1’. BT = bit time = 1/baud rate. Document Number: 38-08015 Rev. *P Page 98 of 119

CY7C67300 Hardware CTS/RTS Handshake tCTShold tCTShold tCTSsetup tCTSsetup HSS_RTS HSS_CTS HSS_TxD Start of transmission delayed until HSS_CTS goes high Start of transmission not delayed by HSS_CTS t : HSS_CTS setup time before HSS_RTS = 1.5T min. CTSsetup t : HSS_CTS hold time after START bit = 0 ns min. CTShold T = 1/48 MHz. When RTS/CTS hardware handshake is enabled, transmission can be help off by deasserting HSS_CTS at least 1.5T before HSS_RTS. Transmission resumes when HSS_CTS returns HIGH. HSS_CTS must remain HIGH until START bit. HSS_RTS is deasserted in the third data bit time. An application may choose to hold HSS_CTS until HSS_RTS is deasserted, which always occurs after the START bit. Register Summary Table 142. Register Summary R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low R 0x0140 HPI Breakpoint Address... 0000 0000 ...Address 0000 0000 R 0x0142 Interrupt Routing VBUS to HPI ID to HPI SOF/EOP2 to SOF/EOP2 to SOF/EOP1 to SOF/EOP1 to Reset2 to HPI HPI Swap 1 0001 0100 Enable Enable HPI Enable CPU Enable HPI Enable CPU Enable Enable Enable Resume2 to Resume1 to Reserved Done2 to HPIDone1 to HPI Reset1 to HPI HPI Swap 0 0000 0000 HPI Enable HPI Enable Enable Enable Enable Enable W 1: 0x0144 SIEXmsg Data... xxxx xxxx 2: 0x0148 ...Data xxxx xxxx R/W 0x02n0 Device n Endpoint n Control Reserved xxxx xxxx IN/OUT Sequence Stall ISO NAK InterruptDirection Enable ARM xxxx xxxx Ignore Enable Select Enable Enable Enable Select Enable R/W 0x02n2 Device n Endpoint n Address Address... xxxx xxxx ...Address xxxx xxxx R.W 0x02n4 Device n Endpoint n Count Reserved Count... xxxx xxxx ...Count xxxx xxxx R/W 0x02n6 Device n Endpoint n Status Reserved Overflow Underflow OUT IN xxxx xxxx Flag Flag Exception FlagException Flag Stall NAK Length Setup Sequence Timeout Error ACK xxxx xxxx Flag Flag Exception FlagFlag Status Flag Flag Flag R/W 0x02n8 Device n Endpoint n Count ResultResult... xxxx xxxx ...Result xxxx xxxx R 0xC000 CPU Flags Reserved... 0000 0000 ...Reserved Global Inter- Negative Overflow Carry Zero 000x xxxx rupt Enable Flag Flag Flag Flag R/W 0xC002 Bank Address... 0000 0001 ...Address Reserved 000x xxxx R 0xC004 Hardware Revision Revision... xxxx xxxx ...Revision xxxx xxxx R/W 0xC006 GPIO Control Write Protect UD Reserved SAS Mode 0000 0000 Enable Enable Select HSS HSS XD SPI SPI XD Interrupt 1 Interrupt 1 Interrupt 0 Interrupt 0 0000 0000 Enable Enable Enable Enable Polarity Enable Polarity Enable Select Select R/W 0xC008 CPU Speed Reserved... 0000 0000 .Reserved CPU Speed 0000 1111 R/W 0xC00A Power Control Host/Device Host/Device Host/Device Host/Device OTG Reserved HSS SPI 0000 0000 2B Wake 2A Wake 1B Wake 1A Wake Wake Wake Wake Enable Enable Enable Enable Enable Enable Enable HPI Reserved GPI Reserved Boost 3V Sleep Halt 0000 0000 Wake Enable Wake Enable OK Enable Enable Document Number: 38-08015 Rev. *P Page 99 of 119

CY7C67300 Table 142. Register Summary (Continued) R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low R/W 0xC00C Watchdog Timer Reserved... 0000 0000 ...Reserved Timeout Period Lock WDT Reset 0000 0000 Flag Select Enable Enable Strobe R/W 0xC00E Interrupt Enable Reserved OTG Interrupt SPI Interrupt Reserved Host/Device 2 Host/Device 1 0000 0000 Enable Enable Interrupt Interrupt Enable Enable HSS In Mailbox Out Mailbox Reserved UART GPIO Timer 1 Timer 0 0001 0000 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Enable Enable Enable Enable Enable Enable Enable R/W 0xC098 OTG Control Reserved VBUS Receive Charge PumpVBUS D+ D– 0000 0000 Pull-up Disable Enable Discharge Pull-up Pull-up Enable Enable Enable Enable D+ Pulldown D– Pull-down Reserved OTG Data ID VBUS Valid 0000 0xxx Enable Enable Status Status Flag R/W 0: 0xC010Timer n Count... 1111 1111 1: 0xC012 ...Count 1111 1111 R/W 0xC014 Breakpoint Address... 0000 0000 ...Address 0000 0000 R/W 1: 0xC018Extended Page n Map Address... 0000 0000 2: 0xC01A ...Address 0000 0000 R/W 0: 0xC01EGPIO n Output Data Data... 0000 0000 1: 0xC024 ...Data 0000 0000 R 0: 0xC020GPIO n Input Data Data... 0000 0000 1: 0xC026 ...Data 0000 0000 R/W 0: 0xC022GPIO n Direction Direction Select... 0000 0000 1: 0xC028 ...Direction Select 0000 0000 R/W 0xC038 Upper Address Enable Reserved xxxx xxxx Reserved Upper Reserved xxxx 0xxx Address Enable R/W 0xC03A External Memory Control Reserved XRAM XROM XMEM XMEM xxxx xxxx Merge Enable Merge Enable Width Select Wait Select XROM XROM XRAM XRAM xxxx xxxx Width Select Wait Select Width Select Wait Select R/W 0xC03C USB Diagnostic Port 2B Port 2A Port 1B Port 1A Reserved... 0000 0000 Diagnostic Diagnostic Diagnostic Diagnostic Enable Enable Enable Enable ...Reserved Pull-down LS Pull-up FS Pull-up Reserved Force Select 0000 0000 Enable Enable Enable W 0xC03E Memory Diagnostic Reserved Memory 0000 0000 Arbitration Select Reserved Monitor 0000 0000 Enable R/W 0xC048 IDE Mode Reserved... 0000 0000 ...Reserved Reserved Mode Select 0000 0000 R/W 0xC04A IDE Start Address Address... 0000 0000 ... Address 0000 0000 R/W 0xC04C IDE Stop Address Address... 0000 0000 ...Address 0000 0000 R/W 0xC04E IDE Control Reserved... 0000 0000 ...Reserved Direction IDE Interrupt Done IDE 0000 0000 Select Enable Flag Enable - 0xC050- IDE PIO Port 0xC06E R/W 0xC070 HSS Control HSS RTS CTS XOFF XOFF CTS Receive Done 0000 0000 Enable Polarity Polarity Enable Enable Interrupt Interrupt Select Select Enable Enable Transmit Done Receive Done One Transmit Packet Mode Receive Receive Pack-Receive 0000 0000 Interrupt Flag Interrupt Flag Stop Bit Ready Select Overflow Flag et Ready Flag Ready Flag R/W 0xC072 HSS Baud Rate Reserved HSS Baud... 0000 0000 ...Baud 0001 0111 R/W 0xC074 HSS Transmit Gap Reserved 0000 0000 Transmit Gap Select 0000 1001 R/W 0xC076 HSS Data Reserved xxxx xxxx Data xxxx xxxx R/W 0xC078 HSS Receive Address Address... 0000 0000 ...Address 0000 0000 R/W 0xC07A HSS Receive Counter Reserved Counter... 0000 0000 ...Counter 0000 0000 R/W 0xC07C HSS Transmit Address Address.. 0000 0000 ...Address 0000 0000 Document Number: 38-08015 Rev. *P Page 100 of 119

CY7C67300 Table 142. Register Summary (Continued) R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low R/W 0xC07E HSS Transmit Counter Reserved Counter... 0000 0000 ...Counter 0000 0000 R/W 0xC080 Host n Control Reserved 0000 0000 0xC0A0 Preamble Sequence Sync ISO Reserved Arm 0000 0000 Enable Select Enable Enable Enable R/W 0xC082 Host n Address Address... 0000 0000 0xC0A2 ...Address 0000 0000 R/W 0xC084 Host n Count Reserved Port Select Reserved Count... 0000 0000 0xC0A4 ...Count 0000 0000 R/W 0xC084 Device n Port Select Reserved Port Select Reserved... 0000 0000 0xC0A4 ...Reserved 0000 0000 R 0xC086 Host n PID Reserved Overflow Underflow Reserved 0000 0000 0xC0A6 Flag Flag Stall NAK Length Reserved Sequence Timeout Error ACK 0000 0000 Flag Flag Exception Flag Status Flag Flag Flag W 0xC086 Host n EP Status Reserved 0000 0000 0xC0A4 PID Select Endpoint Select 0000 0000 R 0xC088 Host n Count Result Result... 0000 0000 0xC0A8 ...Result 0000 0000 W 0xC088 Host n Device Address Reserved... 0000 0000 0xC0A8 ...Reserved Address 0000 0000 R/W 0xC08A USB n Control Port B Port B Port A Port A LOB LOA Mode Port B Resis- xxxx 0000 0xC0AA D+ Status D– Status D+ Status D– Status Select tors Enable Port A Port B Port A Suspend Port B Port A 0000 0000 Resistors Force D+/- Force D± Enable SOF/EOP SOF/EOP Enable State State Enable Enable R/W 0xC08C Host 1 Interrupt Enable VBUS ID Reserved SOF/EOP Reserved 0000 0000 Interrupt Interrupt Interrupt Enable Enable Enable Port B Port A Port B ConnectPort A Con- Reserved Done 0000 0000 Wake InterruptWake InterruptChange nect Change Interrupt Enable Enable Interrupt En- Interrupt Enable able Enable R/W 0xC08C Device 1 Interrupt Enable VBUS ID Reserved SOF/EOP Reserved SOF/EOP Reset 0000 0000 Interrupt Interrupt Timeout In- Interrupt Interrupt Enable Enable terrupt En- Enable Enable able EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 0000 0000 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Enable Enable Enable Enable Enable Enable Enable Enable R/W 0xC08E Device n Address Reserved... 0000 0000 0xC0AE ...Reserved Address 0000 0000 R/W 0xC090 Host 1 Status VBUS ID Reserved SOF/EOP Reserved xxxx xxxx Interrupt Flag Interrupt Flag Interrupt Flag Port B Port A Port B Connect Port A Con- Port B Port A Reserved Done xxxx xxxx Wake InterruptWake InterruptChange nect Change SE0 SE0 Interrupt Flag Flag Interrupt Flag Interrupt Flag Status Status Flag R/W 0xC090 Device 1 Status VBUS ID Reserved SOF/EOP Reset xxxx xxxx Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 xxxx xxxx Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt FlagInterrupt Flag Interrupt Flag Interrupt Flag R/W 0xC092 Host n SOF/EOP Count Reserved Count... 0010 1110 0xC0B2 ...Count 1110 0000 R 0xC092 Device n Frame Number SOF/EOP SOF/EOP Reserved Frame... 0000 0000 0xC0B2 Timeout Timeout Flag Interrupt Count ...Frame 0000 0000 R 0xC094 Host n SOF/EOP Counter Reserved Counter... xxxx xxxx 0xC0B4 ...Counter xxxx xxxx W 0xC094 Device n SOF/EOP Count Reserved Count... 0010 1110 0xC0B4 ...Count 1110 0000 R 0xC096 Host n Frame Reserved Frame... 0000 0000 0xC0B6 ...Frame 0000 0000 R/W 0xC0AC Host 2 Interrupt Enable Reserved SOF/EOP Reserved 0000 0000 Interrupt Enable Port B Port A Port B ConnectPort A Con- Reserved Done 0000 0000 Wake InterruptWake InterruptChange nect Change Interrupt Enable Enable Interrupt Interrupt Enable Enable Enable Document Number: 38-08015 Rev. *P Page 101 of 119

CY7C67300 Table 142. Register Summary (Continued) R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low R/W 0xC0AC Device 2 Interrupt Enable Reserved SOF/EOP Wake SOF/EOP Reset 0000 0000 Timeout Interrupt Interrupt Interrupt Interrupt Enable Enable Enable Enable EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 0000 0000 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Enable Enable Enable Enable Enable Enable Enable Enable R/W 0xC0B0 Host 2 Status Reserved SOF/EOP Reserved xxxx xxxx Interrupt Flag Port B Port A Port B Port A Port B Port A Reserved Done xxxx xxxx Wake InterruptWake InterruptConnect Connect SE0 SE0 Interrupt Flag Flag Change Change Status Status Flag Interrupt Flag Interrupt Flag R/W 0xC0B0 Device 2 Status Reserved SOF/EOP Wake SOF/EOP Reset xxxx xxxx Timeout Interrupt Interrupt Interrupt Interrupt Flag Flag Flag Enable EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 xxxx xxxx Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt FlagInterrupt Flag Interrupt Flag Interrupt Flag R/W 0xC0C6 HPI Mailbox Message... 0000 0000 ...Message 0000 0000 R/W 0xC0C8 SPI Configuration 3Wire Phase SCK Scale Select Reserved 1000 0000 Enable Select Polarity Select Master Master SS SS Delay Select 0001 1111 Active Enable Enable Enable R/W 0xC0CA SPI Control SCK FIFO Byte FullDuplex SS Read Transmit receive 0000 0001 Strobe Init Mode Manual Enable Ready Data Ready Transmit Receive Transmit Bit Length Receive Bit Length 1000 0000 Empty Full R/W 0xC0CC SPI Interrupt Enable Reserved... 0000 0000 ...Reserved Receive Inter- Transmit Inter-Transfer Inter- 0000 0000 rupt Enable rupt Enable rupt Enable R 0xC0CE SPI Status Reserved... 0000 0000 FIFO Error Reserved Receive Transmit Transfer 0000 0000 Flag Interrupt Flag Interrupt Flag Interrupt Flag W 0xC0D0 SPI Interrupt Clear Reserved... 0000 0000 ...Reserved Transmit Transmit 0000 0000 Interrupt Clear Interrupt Clear R/W 0xC0D2 SPI CRC Control CRC Mode CRC CRC Receive One in CRC Zero in CRC Reserved... 0000 0000 Enable Clear CRC ...Reserved 0000 0000 R/W 0xC0D4 SPI CRC Value CRC 1111 1111 ...CRC 1111 1111 R/W 0xC0D6 SPI Data Port t Reserved xxxx xxxx Data xxxx xxxx R/W 0xC0D8 SPI Transmit Address Address... 0000 0000 ...Address 0000 0000 R/W 0xC0DA SPI Transmit Count Reserved Count... 0000 0000 ...Count 0000 0000 R/W 0xC0DC SPI Receive Address Address... 0000 0000 ...Address 0000 0000 R/W 0xC0DE SPI Receive Count Reserved Count... 0000 0000 ...Count 0000 0000 R/W 0xC0E0 UART Control Reserved... 0000 0000 ...Reserved Scale Select Baud Select UART Enable 0000 0111 R 0xC0E2 UART Status Reserved... 0000 0000 ...Reserved Receive Transmit 0000 0000 Full Full R/W 0xC0E4 UART Data Reserved 0000 0000 Data 0000 0000 R/W 0xC0E6 PWM Control PWM Reserved Prescale Mode 0000 0000 Enable Select Select PWM3 PWM2 PWM1 PWM0 PWM3 PWM2 PWM1 PWM0 0000 0000 Polarity SelectPolarity SelectPolarity Select Polarity SelectEnable Enable Enable Enable R/W 0xC0E8 PWM Maximum Count Reserved Count... 0000 0000 ...Count 0000 0000 R/W 0: PWM n Start Reserved Address... 0000 0000 0xC0EA 1: ...Address 0000 0000 0xC0EE 2: 0xC0F2 3: 0xC0F6 Document Number: 38-08015 Rev. *P Page 102 of 119

CY7C67300 Table 142. Register Summary (Continued) R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low R/W 0: PWM n Stop Reserved Address... 0000 0000 0xC0EC 1: 0xC0F0 ...Address 0000 0000 2: 0xC0F4 3: 0xC0F8 R/W 0xC0FA PWM Cycle Count Count... 0000 0000 ...Count 0000 0000 R HPI Status Port VBUS ID Reserved SOF/EOP2 Reserved SOF/EOP1 Reset2 Mailbox In Flag Flag Flag Flag Flag Flag Resume2 FlagResume1 FlagSIE2msg SIE1msg Done2 Flag Done1 Flag Reset1 Flag Mailbox Out Flag Document Number: 38-08015 Rev. *P Page 103 of 119

CY7C67300 Ordering Information Table 143. Ordering Information Ordering Code Package Type AEC Pb-Free Temperature Range CY7C67300-100AXI 100-pin TQFP X –40 to 85°C CY7C67300-100AXA 100-pin TQFP X X –40 to 85°C CY7C67300-100AXIT 100-pin TQFP, tape and reel X –40 to 85°C CY7C67300-100AXAT 100-pin TQFP, tape and reel X X –40 to 85°C Ordering Code Definitions CY 67300 - xxx AX (I, A, E) T Tape and reel Temperature range: I = Industrial; A = Automotive; E= Extended TQFP Pb-free Pin count Part identifier Company Code: CY = Cypress Document Number: 38-08015 Rev. *P Page 104 of 119

CY7C67300 Package Diagram Figure 12. 100-pin TQFP(14 × 14 × 1.4 mm) A100SA 51-85048 *J Document Number: 38-08015 Rev. *P Page 105 of 119

CY7C67300 Acronyms Document Conventions Table 144. Acronyms Used in this Document Units of Measure Acronym Description Table 145. Units of Measure AC alternating current Symbol Unit of Measure AEC Automotive Electronics Council ns nanosecond CPU central processing unit V volt CRC cyclic redundancy check mV millivolt DC direct current µW microwatt DMA direct memory access µA microampere EEPROM electronically erasable programmable read only mA milliampere memory µs microsecond EOP end of packet ms millisecond XRAM external ram memory MHz megahertz FIFO first in first out µF microfarad GPIO general purpose input/output pF picofarad HSS high speed serial mW milliwatt HPI host port interface W watt IDE integrated device electronics ppm parts per million I2C inter-integrated circuit °C degree Celsius KVM keyboard-video-mouse OTG on-the-go protocol PLL phase locked loop POR power-on reset PIO programmed input/output PWM pulse width modulation RAM random access memory ROM read only memory SPI serial peripheral interface SIE serial-interface-engine SE0 single ended zero SOF start of frame SRAM static random access memory TQFP thin quad flat pack TTL transistor-transistor logic UART universal asynchronous receiver/transmitter USB universal serial bus WDT watchdog timer Document Number: 38-08015 Rev. *P Page 106 of 119

CY7C67300 Errata This document describes the errata for the EZ-Host™ Programmable Embedded USB Host/Peripheral Controller, CY7C67300 Product Family. Details include errata trigger conditions, available workaround, and silicon revision applicability. Compare this document to the device’s datasheet for a complete functional description. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number Device Characteristics CY7C67300 All Packages CY7C67300 Qualification Status Product status: In Production CY7C67300 Errata Summary The following table defines the errata applicability to available CY7C67300 family devices. An ‘X’ indicates that the errata pertains to the selected device. Note Click on the errata table items to view their descriptions. Silicon Items CY7C67300 Fix Status Revision 1. HPI write to SIE registers X A No silicon revision planned, use workaround. 2. Hub and low-speed device attached to a root hub of the X A No silicon revision planned, use workaround. EZ-Host chip 3. IDE register read when GPIO24 pin is low X A No silicon revision planned, use workaround. 4. UART Does Not Recognize Framing Errors X A No silicon revision planned, use workaround. 5. UART does not override GPIO Control Register X A No silicon revision planned, use workaround. 6. VBUS Interrupt (VBUS Valid) Requires Debouncing X A No silicon revision planned, use workaround. 7. Coupled SIE Interrupt Enable Bits X A No silicon revision planned, use workaround. 8. Un-Initialized SIExmsg Registers X A No silicon revision planned, use workaround. 9. BIOS USB Peripheral Mode: Descriptor Length X A No silicon revision planned, use workaround. 10. Peripheral short packet issue X A No silicon revision planned, use workaround. 11. Data toggle corruption issue X A No silicon revision planned, use workaround. 12. Code fails to load from EEPROM X A No silicon revision planned, use workaround. 13. ISOCH Endpoint Descriptor error X A No silicon revision planned, use workaround. 14. Missing Endpoint Interrupts in USB Peripheral Mode X A No silicon revision planned, use workaround. Document Number: 38-08015 Rev. *P Page 107 of 119

CY7C67300 1.HPI write to SIE registers ■Problem Definition Writing to the SIE2 Control register via HPI can corrupt the SIE1 Control register. Writing to the SIE1 Control register via HPI can corrupt the SIE2 Control register. ■Parameters Affected SIE Control registers. ■Trigger Condition(S) When an external processor accesses the SIE1 or SIE2 register at the same time the internal CY16 CPU is also accessing the opposite SIE, the SIE accessed by the CY16 CPU will be corrupted. For example, the external processor writes a value of 0x80 to the SIE2 register 0xC0B0 while the internal CY16 is doing a read/write to the SIE1 register 0xC08C, the SIE1 register 0xC08C, will be corrupted with the value 0x80. ■Scope of Impact If the internal CPU and the external CPU access the SIEs at the same time, contention will occur resulting in incorrect data in one of the SIE registers. ■Workaround 1. Use the LCP COMM_WRITE_CTRL_REG to handle the writing to SIE registers. 2. Use download code to handle SIE WRITE commands. 3. Avoid accessing SIE register from the external CPU. For example, route all the SIE interrupts to the software mailbox interrupt registers 0x144 and 0x148. This requires user to create download code. ■Fix Status No silicon revision planned, use workaround. An implementation example is included in the Cypress Windows CE driver. 2.Hub and low-speed device attached to a root hub of the EZ-Host chip ■Problem Definition When a hub and a low-speed device are connected to the same SIE, the hub does not pass the USB packets from the downstream to the upstream. ■Parameters Affected SOF timing. ■Trigger Condition(S) Connecting a hub and a low-speed device to the same root hub (SIE) of the EZ-Host chip. ■Scope of Impact The EZ-Host does not generate an accurate 1 ms SOF time frame to the hub. ■Workaround 1. Code can detect the condition and report a message to the user. 2. The low-speed device could be attached to one of the hub downstream ports. ■Fix Status No silicon revision planned, use workaround. Document Number: 38-08015 Rev. *P Page 108 of 119

CY7C67300 3.IDE register read when GPIO24 pin is low ■Problem Definition The part does not service USB ISRs when the GPIO24 pin (also labeled as HPI_INT and IORDY) is low and any IDE register is read. ■Parameters Affected USB ISRs do not get serviced. ■Trigger Condition(S) The IDE registers (0xC050 through 0xC06E) should not be read unless IDE is being used. Debuggers that read all memory locations while single stepping can cause this situation to manifest itself. ■Scope of Impact If you are debugging and using this pin, your application will appear to hang. ■Workaround When running in standalone mode, avoid using the GPIO24 pin if possible. ■Fix Status No silicon revision planned, use workaround. 4.UART Does Not Recognize Framing Errors ■Problem Definition The UART is not designed to recognize framing errors. ■Parameters Affected UART serial communications. ■Trigger Condition(S) Some platforms can cause EZ-Host to see a string of NULL characters and cause the UART to get out of sync. ■Scope of Impact This can cause the UART to lose connection with the host during serial communications. One example of this is if the UART is used as the debug port to the PC. This problem has occurred on, but is not limited to, Dell™ machines running Windows® XP or Windows® 2000. ■Workaround For general use, there is no workaround. If this problem is experienced while debugging, try running the debugger on a different host (PC/OS). Otherwise the USB port can be used for the debugging interface. ■Fix Status No silicon revision planned, use workaround. Document Number: 38-08015 Rev. *P Page 109 of 119

CY7C67300 5.UART does not override GPIO Control Register ■Problem Definition When the UART is enabled, the GPIO Control Register still has control over GPIO 27 (UART RX pin). When enabled, the UART should override the GPIO Control Register, which defaults to setting the pin as an input. ■Parameters Affected UART serial communications. ■Trigger Condition(S) Enabling UART. ■Scope of Impact GPIO 27 UART RX pin is controlled by GPIO Control Register and defaults to an input. The UART mode does not override the GPIO Control Register for this pin and can be inadvertently configured as an output. ■Workaround Ensure the GPIO Control Register is written appropriately to set GPIO27 as an input when the UART is enabled. ■Fix Status No silicon revision planned, use workaround. 6.VBUS Interrupt (VBUS Valid) Requires Debouncing ■Problem Definition The VBUS interrupt in the Host/Device Status Registers [0xC090 and 0xC0B0] and OTG Control Register [0xC098] triggers multiple times whenever VBUS is turned on. It should only trigger once when VBUS rises above 4.4V and once when VBUS falls from above 4.4V to 0V. ■Parameters Affected Electrical. ■Trigger Condition(S) VBUS turned on. ■Scope of Impact Host/Device Registers and OTG Control Register trigger multiple times. ■Workaround When reading the status of this interrupt, a software debounce should be implemented. ■Fix Status No silicon revision planned, use workaround. Examples are provided in the Development Kit Software. Document Number: 38-08015 Rev. *P Page 110 of 119

CY7C67300 7.Coupled SIE Interrupt Enable Bits ■Problem Definition Host/Device 1 SIE events will still trigger an interrupt when only the Host/Device 2 SIE Interrupt Enable is set and vise versa. ■Parameters Affected Host/Device SIE Interrupts. ■Trigger Condition(S) Setting only 1 Host/Device SIE Interrupt Enable. ■Scope of Impact The Host/Device global Interrupt Enable bits cannot be used to disable each Host/Device SIE independently. These bits are found in the Interrupt Enable Register (0xC00E). ■Workaround If an SIE Interrupt is desired, both Host/Device 1 and Host/Device 2 Interrupt Enable bits should be set in the Global Interrupt Enable Register (0xC00E). To properly mask an SIE Interrupt to a single SIE, the lower level Host/Device Interrupt Enable Registers (0xC08C and 0xC0AC) must be used. For example, setting the Host/Device 2 IE Register to 0x0000 will prevent any Host/Device 2 events from generating a Host/Device Interrupt. To disable all SIE interrupts, both Host/Device Interrupt Enable bits in the Interrupt Enable Register should be cleared. ■Fix Status No silicon revision planned, use workaround. 8.Un-Initialized SIExmsg Registers ■Problem Definition The SIE1msg and SIE2msg Registers [0x0144 and 0x0148] are not initialized at power up. ■Parameters Affected HPI interrupts. ■Trigger Condition(S) Power up initialization. ■Scope of Impact If you are using the HPI interface in co-processor mode, random data will be written to the SIE1msg and SIE2msg Registers [0x0144 and 0x0148] at power up. This will cause two improper HPI interrupts (HPI_INTR) to occur, one for each of the two SIExmsg Registers. ■Workaround The external processor should clear the SIExmsg Registers [0x0144 and 0x0148] shortly after nRESET is de-asserted and prior to the expected processing of proper HPI interrupts (generally 10 ms after nRESET is de-asserted). ■Fix Status No silicon revision planned, use workaround. Document Number: 38-08015 Rev. *P Page 111 of 119

CY7C67300 9.BIOS USB Peripheral Mode: Descriptor Length ■Problem Definition The BIOS will not properly return a descriptor or set of descriptors, if the length is a multiple of the control endpoint’s maximum packet size. ■Parameters Affected Control Endpoint maximum packet size. ■Trigger Condition(S) Get Descriptor requests. ■Scope of Impact If the descriptor length is a multiple of the maximum packet size, the BIOS will respond with a STALL instead of a zero-length data packet for the final IN request. ■Workaround If the requested descriptor length is a multiple of the maximum packet size, then either the maximum packet size or the descriptor length needs to change. A descriptor length can be increased by simply adding a padded byte to the end of a descriptor and increasing the descriptor Length byte by one. Section 9.5 (Descriptor) of the USB 2.0 specification allows a descriptor length to be larger than the value defined in the specification. ■Fix Status No silicon revision planned, use workaround. Document Number: 38-08015 Rev. *P Page 112 of 119

CY7C67300 10.Peripheral short packet issue ■Problem Definition When an SIE is configured as a peripheral, the SUSBx_RECEIVE function does not invoke the callback function when it receives a short packet. ■Parameters Affected SIEx Endpoint x Interrupt (Interrupt 32-47). ■Trigger Condition(S) This issue is seen when an SIE is configured as a peripheral during an OUT data transfer when the host sends a zero length or short packet. If this occurs, the BIOS will behave as if a full packet was received and will continue to accept data until the Device n Endpoint n Count Register value is satisfied. ■Scope of Impact All peripheral functions are susceptible to this, as it is a normal occurrence with USB traffic. ■Workaround To fix this problem, the SIEx Endpoint x Interrupt must be replaced for any peripheral endpoint that is configured as an OUT endpoint. 1. Acquire the file called susb1.s from Cypress Support or download a newer version of the frameworks that has this fix applied and includes susb1.s. 2. Modify fwxcfg.h in your project to have the following flags and define/undef the fix for the endpoints you are using: #define FIX_USB1_EP1 #define FIX_USB1_EP2 #undef FIX_USB1_EP3 #undef FIX_USB1_EP4 #undef FIX_USB1_EP5 #undef FIX_USB1_EP6 #undef FIX_USB1_EP7 #undef FIX_USB2_EP1 #undef FIX_USB2_EP2 #undef FIX_USB2_EP3 #undef FIX_USB2_EP4 #undef FIX_USB2_EP5 #undef FIX_USB2_EP6 #undef FIX_USB2_EP7 3. Add the new susb1.s to the included assembly source files in the make file. For example : ASM_SRC := startup.s isrs.s susb1.s 4. Add usb_init somewhere in the startup code. This will likely be in fwxmain.c as demonstrated below: void fwx_program_init(void) { void usb_init();/* define the prototype */ usb_init(); fwx_init();/* Initialize everything in the base framework. */ } 5. Build the project using the modified make file. ■Fix Status No silicon revision planned, use workaround. Document Number: 38-08015 Rev. *P Page 113 of 119

CY7C67300 11.Data toggle corruption issue ■Problem Definition When an SIE is configured as a peripheral, data toggle corruption as specified in the USB 2.0 specification, section 8.6.4, does not work as specified. ■Parameters Affected SIEx Endpoint x Interrupt (Interrupt 32-47). ■Trigger Condition(S) This issue is seen when an SIE is configured as a peripheral and the host sends an incorrect data toggle. According to the USB specification, when an incorrect data toggle is seen from the host, the peripheral should throw away the data but increment the data toggle bit to re-synchronize the data toggle bits. In the current ROM BIOS, the SIEx Endpoint x Interrupt will ignore the data toggle error and accept the data. ■Scope of Impact All peripheral functions are susceptible to this as it is a normal occurrence with USB traffic. ■Workaround To fix this problem, the SIEx Endpoint x Interrupt must be replaced for any endpoint that is configured as an OUT endpoint. 1. Acquire the file called susb1.s from Cypress Support or download a newer version of the frameworks that has this included. 2. Modify fwxcfg.h in your project to have the following flags and define/undef the fix for the endpoints you are using: #define FIX_USB1_EP1 #define FIX_USB1_EP2 #undef FIX_USB1_EP3 #undef FIX_USB1_EP4 #undef FIX_USB1_EP5 #undef FIX_USB1_EP6 #undef FIX_USB1_EP7 #undef FIX_USB2_EP1 #undef FIX_USB2_EP2 #undef FIX_USB2_EP3 #undef FIX_USB2_EP4 #undef FIX_USB2_EP5 #undef FIX_USB2_EP6 #undef FIX_USB2_EP7 3. Add the new susb1.s to the included assembly source files in the make file. For example : ASM_SRC := startup.s isrs.s susb1.s 4. Add usb_init somewhere in the startup code. This will likely be in fwxmain.c as demonstrated below: void fwx_program_init(void) { void usb_init(); /* define the prototype */ usb_init(); fwx_init(); /* Initialize everything in the base framework. */ } 5. Build the project using the modified make file. ■Fix Status No silicon revision planned, use workaround. Document Number: 38-08015 Rev. *P Page 114 of 119

CY7C67300 12.Code fails to load from EEPROM ■Problem Definition If, while the BIOS is loading firmware, the part is reset and at that time the EEPROM is driving the SDA line low, the BIOS will configure the part for co-processor mode instead of standalone mode. ■Parameters Affected Initialization. ■Trigger Condition(S) Reset the part while firmware is being loaded from the EEPROM. ■Scope of Impact The firmware download process will not finish, leaving the part configured in co-processor mode. ■Workaround There is no workaround. Cycle power to the EEPROM to download firmware. ■Fix Status No silicon revision planned, use workaround. 13.ISOCH Endpoint Descriptor error ■Problem Definition Setting any bit other than 1:0 in the bmAttributes field will cause the ISOCH Endpoint Descriptors to be reported incorrectly. ■Parameters Affected Isochronous transfers. ■Trigger Condition(S) Setting any bit other than 1:0 in the bmAttributes field. ■Scope of Impact If the bmAttributes field in the Endpoint Descriptor is using bits 5...2, the BIOS will not correctly parse the endopoint and set up the part correctly for ISO transfers. ■Workaround There are two methods that can be used. A.Mask these bits before the BIOS parses the descriptros using the SET_INTERFACE handler. An example of this is given in the “Using Multiple Interfaces to Implement a USB Isochronous Composite Peripheral with EZ-Host™ and EZ-OTG™.” B.Replace the BIOS delta config interrupt and modify the USB-parse code to mask off all but the lower two bits of the bmAttribute. A possilble solution might look like this. @@test b[r8+bEPAttribute], 0x01 ; check ISO rz test b[r8+bEPAttribute], 0x02 rnz ;if we get here, then the lower two bits ;of bEPAttribute = 01 meaning it is ISO or r2,EP_ISO ret ■Fix Status No silicon revision planned, use workaround. Document Number: 38-08015 Rev. *P Page 115 of 119

CY7C67300 14.Missing Endpoint Interrupts in USB Peripheral Mode ■Problem Definition USB peripheral designs may miss endpoint interrupts when receiving Endpoint 0 (EP0) Control transfer requests mixed with other endpoint transfer type transactions. ■Parameters Affected All USB peripheral mode endpoint communication may potentially be affected. ■Trigger Condition(S) An endpoint interrupt may be missed when a non-EP0 transaction completes (with ACK) during an EP0 Control transfer or within ~200 s before or after the EP0 Control transfer. Other processor activity and interrupts may influence the likelihood of this failure occurring. ■Scope of Impact This errata item applies to USB peripheral mode only. All USB peripheral designs that mix Standard, Vendor, or Class EP0 requests with other transfer types are potential candidates for this issue. If this problem occurs and an endpoint interrupt is missed, the endpoint will likely not be rearmed and therefore endpoint communication will be halted and the host system may reset the device. ■Workaround A.The PC Application and/or driver must be developed to ensure at least ~200 s of idle time is given before and after any EP0 transfers. The driver must ensure that no other transfer type transactions occur during the EP0 transfer or during this idle time before and after the EP0 transfer. Therefore, the driver cannot submit asynchronous Control transfers. The driver must submit Control transfer requests synchronously with other transfer requests. In addition, the driver must be aware of any interrupt endpoint scheduling (which is under control of the host controller driver) when submitting Control transfers. This generally means that a vendor-specific driver is required. B.USB endpoint communication stress testing of any USB peripheral designs that mix EP0 Control transfers with other transfer types is recommended. ■Fix Status No silicon revision planned, use workaround. Document Number: 38-08015 Rev. *P Page 116 of 119

CY7C67300 Document History Page Document Title: CY7C67300, EZ-Host™ Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Document Number: 38-08015 Orig. of Submission Revision ECN Description of Change Change Date ** 111872 MUL 03/22/02 New Data Sheet *A 116989 MUL 08/23/02 Preliminary Data Sheet *B 125262 MUL 04/10/03 Added Memory Map Section and Ordering Information Section Moved Functional Register Map Tables into Register section General Clean-up *C 126210 MUL 05/23/03 Added Interface Description Section and Power Savings and Reset Section Added Char Data General Clean-up *D 127335 KKV 05/29/03 Corrected font to enable correct symbol display *E 129395 MUL 10/01/03 Final Data Sheet Changed Memory Map Section and added CLKSEL to Pin Description Added USB OTG Logo General Clean-up *F 443992 VCS See ECN Title changed indicating AEC Grade Added information for AEC qualified including part number Fixed misc. errors including: Table 4-1: UART does not have alternate location Section 4.3.4 had incorrect register address Table 4-10 had incorrect pin definitions Section 4.16.2 changed GPIO[31:20] to GPIO[31:30] Corrected Table 7-6 and 7-14 *G 566465 KKVTMP See ECN Added the lead free information on the Ordering Information Section. Imple- mented the new template with no numbers on the headings. *H 1063560 ARI See ECN Changed Ordering Information table to reflect Automotive Qualification and to meet the MPN Part Number changes reflected in ECN 884880. Changed the EZ-Host Pin Diagram figure to reflect the pin changes. Edited. *I 2514867 PYRS See ECN To publish in Web *J 2544823 BHA/AESA 07/28/08 Updated template. Corrected A18 and A17 pin assignments in Tables 6 and 131. *K 3302644 NMMA 07/05/11 Added CY4640 Reference Design entry in Ordering Information Table. Included table of contents. Added ordering code definitions, acronyms, and units of measure. Updated package diagram from *C to *E *L 3997633 PRJI 05/11/2013 Updated Package Diagram: spec 51-85048 – Changed revision from *E to *G. Added Errata. Document Number: 38-08015 Rev. *P Page 117 of 119

CY7C67300 Document History Page (Continued) Document Title: CY7C67300, EZ-Host™ Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Document Number: 38-08015 Orig. of Submission Revision ECN Description of Change Change Date *M 4080334 PRJI 07/29/2013 Added Errata footnotes (Note 3, 4, 9, 10, 11, 12, 13, 14, 15). Updated Interface Descriptions: Updated UART Interface [3]: Added Note 3 and referred the same note in the heading. Updated I2C EEPROM Interface [4]: Added Note 4 and referred the same note in the heading. Updated Registers: Updated Processor Control Registers: Updated Interrupt Enable Register [0xC00E] [R/W] [9]: Added Note 9 and referred the same note in the heading. Updated General USB Registers [10]: Added Note 10 and referred the same note in the heading. Updated USB Host Only Registers [11]: Added Note 11 and referred the same note in the heading. Updated USB Device Only Registers: Updated Device n Interrupt Enable Register [R/W]: Added Note 12 and referred the same note in “Register Description”. Updated OTG Control Registers [13]: Added Note 13 and referred the same note in the heading. Updated IDE Registers: Added Note 14 and referred the same note in Table82. Updated HPI Registers: Updated SIEXmsg Register [W]: Added Note 15 and referred the same note in “SIE1msg Register 0x0144” and “SIE2msg Register 0x0148”. Updated in new template. *N 5391844 RAJV 08/05/2016 Document migrated to new template. Updated package diagram. Removed obsolete Development kit CY3663 from the ordering information. *O 5708844 AESATMP7 04/27/2017 Updated Logo and Copyright. *P 6037062 RAJV 01/18/2018 Removed “CY4640” from the Ordering Information. Document Number: 38-08015 Rev. *P Page 118 of 119

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