CY7C6431x CY7C6434x CY7C6435x enCoRe™ V Full Speed USB Controller enCoRe™ V Full Speed USB Controller Features ■Programmable pin configurations ❐Up to 36 general purpose I/O (GPIO) depending on package. ■Powerful Harvard-architecture processor ❐25 mA sink current on all GPIO ❐M8C processor speeds running up to 24 MHz • 60mA total sink current on Even port pins and 60 mA total ❐Low power at high processing speeds sink current on Odd port pins ❐Interrupt controller • 120 mA total sink current on all GPIOs ❐3.0V to 5.5V operating voltage without USB ❐Pull-up, High Z, open drain, CMOS drive modes on all GPIO ❐Operating voltage with USB enabled: ❐CMOS drive mode A -5 mA source current on ports 0 and 1 • 3.15V to 3.45V when supply voltage is around 3.3V and 1 mA on ports 2, 3, and 4 • 4.35V to 5.25V when supply voltage is around 5.0V • 20 mA total source current on all GPIOs ❐Commercial temperature range: 0°C to +70°C ❐Low dropout voltage regulator for Port 1 pins: ❐Industrial temperature range: –40°C to +85°C • Programmable to output 3.0, 2.5, or 1.8 V ■Flexible on-chip memory ❐Selectable, regulated digital I/O on Port 1 ❐Up to 32 KB flash program storage: ❐Configurable input threshold for Port 1 • 50,000 erase and write cycles ❐Hot-swappable Capability on Port 1 • Flexible protection modes ■Full-Speed USB (12 Mbps) ❐Up to 2048 bytes SRAM data storage ❐Eight unidirectional endpoints ❐In-system serial programming (ISSP) ❐One bidirectional control endpoint ■Complete development tools ❐USB 2.0-compliant: TID# 40000893 ❐Free development tool PSoC Designer™ ❐Dedicated 512 bytes buffer ❐Full-featured, in-circuit emulator and programmer ❐No external crystal required ❐Full-speed emulation ■Additional system resources ❐Complex breakpoint structure ❐Configurable communication speeds ❐128-KB trace memory ❐I2C slave: ■Precision, programmable clocking • Selectable to 50 kHz, 100 kHz, or 400 kHz ❐Crystal-less oscillator with support for an external crystal or • Implementation requires no clock stretching resonator • Implementation during sleep modes with less than 100 A ❐Internal ±5.0% 6, 12, or 24 MHz main oscillator (IMO): • Hardware address detection • 0.25% accuracy with oscillator lock to USB data, no ❐SPI master and SPI slave: external components required • Configurable between 46.9 kHz and 12 MHz • Internal low-speed oscillator (ILO) at 32 kHz for watchdog ❐Three 16-bit timers and sleep. The frequency range is 19 to 50 kHz with a ❐10-bit ADC used to monitor battery voltage or other signals 32-kHz typical value with external components ❐Watchdog and sleep timers ❐Integrated supervisory circuit enCoRe V Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 Prog. LDO enCoRe V CORE System Bus SRAM 2048 Bytes SROM 8K/16K/32K Flash Interrupt CPU Core(M8C) SWleaetcph adnodg Controller 6/12/24 MHz Internal Main Oscillator ADC 3T i1m6e-Brsit IM2Cas Stelar-vSel/aSvPeI SPyOsRte man Rd eLsVeDts SUFpSeuBell d SYSTEM RESOURCES Errata: For information on silicon errata, see “Errata” on page35. Details include trigger conditions, devices affected, and proposed workaround. CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-12394 Rev. *U Revised April 27, 2017

CY7C6431x CY7C6434x CY7C6435x Contents Functional Overview ........................................................3 Register Conventions ....................................................13 The enCoRe V Core ....................................................3 Register Mapping Tables ...............................................13 Full-Speed USB ...........................................................3 Electrical Specifications ................................................16 10-bit ADC ...................................................................4 Absolute Maximum Ratings .......................................17 SPI ...............................................................................4 Operating Temperature .............................................17 I2C Slave .....................................................................5 DC Electrical Characteristics .....................................18 Additional System Resources .....................................6 AC Electrical Characteristics .....................................22 Getting Started ..................................................................6 Package Diagram ............................................................29 Application Notes ........................................................6 Packaging Dimensions ..............................................29 Development Kits ........................................................6 Package Handling .....................................................31 Training .......................................................................6 Thermal Impedances .................................................31 CYPros Consultants ....................................................6 Capacitance on Crystal Pins .....................................31 Solutions Library ..........................................................6 Solder Reflow Peak Temperature .............................31 Technical Support .......................................................6 Ordering Information ......................................................32 Development Tools ..........................................................7 Ordering Code Definitions .........................................33 PSoC Designer Software Subsystems ........................7 Acronyms ........................................................................34 Designing with PSoC Designer .......................................8 Document Conventions .................................................34 Select User Modules ...................................................8 Units of Measure .......................................................34 Configure User Modules ..............................................8 Numeric Naming ........................................................34 Organize and Connect ................................................8 Errata ...............................................................................35 Generate, Verify, and Debug .......................................8 CY7C643xx Errata Summary ....................................35 Pin Information .................................................................9 Document History Page .................................................37 16-pin part pinout ........................................................9 Sales, Solutions, and Legal Information ......................41 Pin Definitions .............................................................9 Worldwide Sales and Design Support .......................41 32-pin part pinout ......................................................10 Products ....................................................................41 Pin Definitions ...........................................................10 PSoC® Solutions ......................................................41 48-pin Part Pinout ......................................................11 Cypress Developer Community .................................41 Pin Definitions ...........................................................11 Technical Support .....................................................41 Register Reference .........................................................13 Document Number: 001-12394 Rev. *U Page 2 of 41

CY7C6431x CY7C6434x CY7C6435x Functional Overview Figure 1. USB Transceiver Regulator The enCoRe V family of devices are designed to replace multiple traditional full-speed USB microcontroller system components VOLTAGE PS2 Pull Up with one, low cost single-chip programmable component. REGULATOR Communication peripherals (I2C/SPI), a fast CPU, Flash 5V 3.3V program memory, SRAM data memory, and configurable I/O are 1.5K 5K included in a range of convenient pinouts. The architecture for this device family, as illustrated in the enCoRe V Block Diagram on page 1, consists of two main areas: TEN DP the CPU core and the system resources. Depending on the TD DM enCoRe V package, up to 36 GPIO are also included. This product is an enhanced version of Cypress’s successful full RECEIVERS TRANSMITTER speed-USB peripheral controllers. Enhancements include faster PDN CPU at lower voltage operation, lower current consumption, twice the RAM and Flash, hot-swappable I/Os, I2C hardware RD address recognition, new very low current sleep mode, and new package options. DPO RSE0 The enCoRe V Core DMO The enCoRe V Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO and ILO. The CPU core, called the M8C, is a powerful processor with At the enCoRe V system level, the full-speed USB system speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard resource interfaces to the rest of the enCoRe V by way of the architecture microprocessor. M8C’s register access instructions and to the outside world by way of the two USB pins. The SIE supports nine endpoints During USB operation, the CPU speed can be set to any setting. including a bidirectional control endpoint (endpoint 0) and eight Be aware that USB throughput decreases with a decrease in unidirectional data endpoints (endpoints 1 to 8). The CPU speed. For maximum throughput, the CPU clock should be unidirectional data endpoints are individually configurable as made equal to the system clock. The system clock must be either IN or OUT. 24MHz for USB operation. Low value series resistors R (22 Ω) must be added externally System resources provide additional capability, such as a EXT to the D+ and D– lines to meet the driving impedance configurable I2C slave and SPI master-slave communication requirement for full-speed USB. interface and various system resets supported by the M8C. The USB Serial Interface Engine (SIE) allows the enCoRe V Full-Speed USB device to communicate with the USB host at full speed data rates (12 Mb/s). The SIE simplifies the interface to USB traffic by The enCoRe V USB system resource adheres to the USB 2.0 automatically handling the following USB processing tasks Specification for full speed devices operating at 12 Mb/second without firmware intervention: with one upstream port and one USB address. enCoRe V USB consists of these components: ■Translates the encoded received data and formats the data to be transmitted on the bus. ■Serial interface engine (SIE) block. ■Generates and checks cyclical redundancy checks (CRCs). ■PSoC memory arbiter (PMA) block. Incoming packets failing checksum verification are ignored. ■512 bytes of dedicated SRAM. ■Checks addresses. Ignores all transactions not addressed to ■A full-speed USB Transceiver with internal regulator and two the device. dedicated USB pins. ■Sends appropriate ACK/NAK/Stall handshakes. ■Identifies token type (SETUP, IN, OUT) and sets the appropriate token bit once a valid token in received. ■Identifies Start-of-Frame (SOF) and saves the frame count. ■Sends data to or retrieves data from the USB SRAM, by way of the PSoC Memory Arbiter (PMA). Document Number: 001-12394 Rev. *U Page 3 of 41

CY7C6431x CY7C6434x CY7C6435x Firmware is required to handle various parts of the USB input mux or the temperature sensor with an input voltage range interface. The SIE issues interrupts after key USB events to of 0 V to V . REFADC direct firmware to appropriate tasks: In the ADC only configuration (the ADC MUX selects the Analog ■Fill and empty the USB data buffers in USB SRAM. mux bus, not the default temperature sensor connection), an external voltage can be connected to the input of the modulator ■Enable PMA channels appropriately. for voltage conversion. The ADC is run for a number of cycles set by the timer, depending upon the desired resolution of the ■Coordinate enumeration by decoding USB device requests. ADC. A counter counts the number of trips by the comparator, ■Suspend and resume coordination. which is proportional to the input voltage. The Temp Sensor block clock speed is 36 MHz and is divided down to 1 to 12 MHz for ■Verify and select data toggle values. ADC operation. 10-bit ADC SPI The ADC on enCoRe V device is an independent block with a The serial peripheral interconnect (SPI) 3-wire protocol uses state machine interface to control accesses to the block. The both edges of the clock to enable synchronous communication ADC is housed together with the temperature sensor core and without the need for stringent setup and hold requirements. can be connected to this or the Analog mux bus. As a default operation, the ADC is connected to the temperature sensor Figure 3. Basic SPI Configuration diodes to give digital values of the temperature. SPI Master SPI Slave Figure 2. ADC System Performance Block Diagram Data is output by both the Master Data is registered at the VIN and Slave on input of both devices on the one edge of the opposite edge of the clock. clock. SCLK TEMP SENSOR/ADC MOSI MISO A device can be a master or slave. A master outputs clock and data to the slave device and inputs slave data. A slave device TEMP inputs clock and data from the master device and outputs data DIODES ADC for input to the master. Together, the master and slave are essentially a circular Shift register, where the master generates the clocking and initiates data transfers. A basic data transfer occurs when the master sends eight bits of data, along with eight clocks. In any transfer, both master and SYSTEM BUS slave transmit and receive simultaneously. If the master only sends data, the received data from the slave is ignored. If the master wishes to receive data from the slave, the master must send dummy bytes to generate the clocking for the slave to send data back. INTERFACE BLOCK COMMAND/STATUS Figure 4. SPI Block Diagram SPI Block MOSI, MOSI, MISO MISO DATA_IN DATA_OUT SCLK SCLK CLK_IN CLK_OUT SYSCLK INT Interface to the M8C SS_ ( Processor) Core Registers The ADC User Module contains an integrator block and one CONFIGURATION[7:0] CONTROL[7:0] comparator with positive and negative input set by the MUXes. TRANSMIT[7:0] RECEIVE[7:0] The input to the integrator stage comes from the analog global Document Number: 001-12394 Rev. *U Page 4 of 41

CY7C6431x CY7C6434x CY7C6435x SPI configuration register (SPI_CFG) sets master/slave ■Interrupt or polling CPU interface. functionality, clock speed, and interrupt select. SPI control ■Support for clock rates of up to 400 kHz. register (SPI_CR) provides four control bits and four status bits for device interfacing and synchronization. ■7- or 10-bit addressing (through firmware support). The SPIM hardware has no support for driving the Slave Select ■SMBus operation (through firmware support). (SS_) signal. The behavior and use of this signal is dependent on the application and enCoRe V device and, if required, must Enhanced features of the I2C Slave Enhanced Module include: be implemented in firmware. ■Support for 7-bit hardware address compare. There is an additional data input in the SPIS, Slave Select (SS_), ■Flexible data buffering schemes. which is an active low signal. SS_ must be asserted to enable the SPIS to receive and transmit. SS_ has two high level ■A “no bus stalling” operating mode. functions: ■A low power bus monitoring mode. ■To allow for the selection of a given slave in a multi-slave The I2C block controls the data (SDA) and the clock (SCL) to the environment. external I2C interface through direct connections to two ■To provide additional clocking for TX data queuing in SPI modes dedicated GPIO pins. When I2C is enabled, these GPIO pins are 0 and 1. not available for general purpose use. The enCoRe V CPU firmware interacts with the block through I/O register reads and I2C Slave writes, and firmware synchronization is implemented through The I2C slave enhanced communications block is a polling and/or interrupts. serial-to-parallel processor, designed to interface the enCoRe V In the default operating mode, which is firmware compatible with device to a two-wire I2C serial communications bus. To eliminate previous versions of I2C slave modules, the I2C bus is stalled the need for excessive CPU intervention and overhead, the block upon every received address or byte, and the CPU is required to provides I2C-specific support for status detection and generation read the data or supply data as required before the I2C bus of framing bits. By default, the I2C slave enhanced module is continues. However, this I2C Slave Enhanced module provides firmware compatible with the previous generation of I2C slave new data buffering capability as an enhanced feature. In the functionality. However, this module provides new features that EZI2C buffering mode, the I2C slave interface appears as a are configurable to implement significant flexibility for both 32-byte RAM buffer to the external I2C master. Using a simple internal and external interfacing. The basic I2C features include: predefined protocol, the master controls the read and write pointers into the RAM. When this method is enabled, the slave ■Slave, transmitter, and receiver operation. never stalls the bus. In this protocol, the data available in the ■Byte processing for low CPU overhead. RAM (this is managed by the CPU) is valid. Figure 5. I2C Block Diagram I2C Plus Slave I2C Core Buffer Module CPU Port S SDA_IN I2C Basic I2C_BUF ys To/From SCL_IN Configuration tem GPPinIOs SDA_OUT II22CC__SCCFGR 32 Byte RAM Bus SCL_OUT I2C_DR I2C_EN HW Addr Cmp Buffer Ctl I2C_ADDR I2C_BP SYSCLK Plus Features I2C_CP I2C_XCFG MCU_BP STANDBY I2C_XSTAT MCU_CP Document Number: 001-12394 Rev. *U Page 5 of 41

CY7C6431x CY7C6434x CY7C6435x Additional System Resources Application Notes System resources, some of which have been previously listed, Application notes are an excellent introduction to the wide variety provide additional capability useful to complete systems. of possible PSoC designs and are available at Additional resources include low voltage detection and power on http://www.cypress.com. reset. The following statements describe the merits of each system resource. Development Kits ■Low voltage detection (LVD) interrupts can signal the PSoC development kits are available online from Cypress at application of falling voltage levels, while the advanced POR http://www.cypress.com and through a growing number of (power on reset) circuit eliminates the need for a system regional and global distributors, including Arrow, Avnet, Digi-Key, supervisor. Farnell, Future Electronics, and Newark. ■The 5 V maximum input, 1.8, 2.5, or 3 V selectable output, LDO Training regulator provides regulation for I/Os. A register controlled Free PSoC technical training (on demand, webinars, and bypass mode enables the user to disable the LDO. workshops) is available online at http://www.cypress.com. The ■Standard Cypress PSoC IDE tools are available for debugging training covers a wide variety of topics and skill levels to assist the enCoRe V family of parts. you in your designs. Getting Started CYPros Consultants Certified PSoC Consultants offer everything from technical The quickest path to understanding the enCoRe V silicon is by assistance to completed PSoC designs. To contact or become a reading this data sheet and using the PSoC Designer Integrated PSoC Consultant, go to http://www.cypress.com and look for Development Environment (IDE). This datasheet is an overview CYPros Consultants. of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with Solutions Library detailed programming information, see the enCoRe™ V Visit our growing library of solution-focused designs at CY7C643xx, enCoRe™ V LV CY7C604xx Technical Reference http://www.cypress.com. Here you can find various application Manual (TRM) for this PSoC device. designs that include firmware and hardware design files that For up-to-date ordering, packaging, and electrical specification enable you to complete your designs quickly. information, see the latest PSoC device data sheets on the web at http://www.cypress.com. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at http://www.cypress.com. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Document Number: 001-12394 Rev. *U Page 6 of 41

CY7C6431x CY7C6434x CY7C6435x Development Tools Code Generation Tools The code generation tools work seamlessly within the PSoC Designer™ is the revolutionary Integrated Design PSoCDesigner interface and have been tested with a full range Environment (IDE) that you can use to customize PSoC to meet of debugging tools. You can develop your design in C, assembly, your specific application requirements. PSoC Designer software or a combination of the two. accelerates system design and time to market. Develop your Assemblers. The assemblers allow you to merge assembly applications using a library of precharacterized analog and digital code seamlessly with C code. Link libraries automatically use peripherals (called user modules) in a drag-and-drop design absolute addressing or are compiled in relative mode, and linked environment. Then, customize your design by leveraging the with other software modules to get absolute addressing. dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the C Language Compilers. C language compilers are available integrated debug environment, including in-circuit emulation and that support the PSoC family of devices. The products allow you standard software debug features. PSoC Designer includes: to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored ■Application editor graphical user interface (GUI) for device and to the PSoC architecture. They come complete with embedded user module configuration and dynamic reconfiguration libraries providing port and bus operations, standard keypad and ■Extensive user module catalog display support, and extended math functionality. ■Integrated source-code editor (C and assembly) Debugger ■Free C compiler with no size restrictions or time limits PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in ■Built-in debugger a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and ■In-circuit emulation read and write data memory, and read and write I/O registers. ■Built-in support for communication interfaces: You can read and write CPU registers, set and clear breakpoints, ❐Hardware and software I2C slaves and masters and provide program run, halt, and step control. The debugger ❐Full-speed USB 2.0 also allows you to create a trace buffer of registers and memory locations of interest. ❐Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and Online Help System wireless PSoC Designer supports the entire library of PSoC 1 devices and The online help system displays online, context-sensitive help. runs on Windows XP, Windows Vista, and Windows 7. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also PSoC Designer Software Subsystems provides tutorials and links to FAQs and an Online Support Forum to aid the designer. Design Entry In-Circuit Emulator In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use A low-cost, high-functionality In-Circuit Emulator (ICE) is the PSoC blocks, which are called user modules. Examples of available for development support. This hardware can program user modules are analog-to-digital converters (ADCs), single devices. digital-to-analog converters (DACs), amplifiers, and filters. The emulator consists of a base unit that connects to the PC Configure the user modules for your chosen application and using a USB port. The base unit is universal and operates with connect them to each other and to the proper pins. Then all PSoC devices. Emulation pods for each device family are generate your project. This prepopulates your project with APIs available separately. The emulation pod takes the place of the and libraries that you can use to program your application. PSoC device in the target board and performs full-speed The tool also supports easy development of multiple (24-MHz) operation. configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC’s resources for a given application. Document Number: 001-12394 Rev. *U Page 7 of 41

CY7C6431x CY7C6434x CY7C6435x Designing with PSoC Designer data sheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes The development process for the PSoC device differs from that the use of each user module parameter, and other information of a traditional fixed-function microprocessor. The configurable that you may need to successfully implement your design. analog and digital hardware blocks give the PSoC architecture a Organize and Connect unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These Build signal chains at the chip level by interconnecting user configurable resources, called PSoC blocks, have the ability to modules to each other and the I/O pins. Perform the selection, implement a wide variety of user-selectable functions. The PSoC configuration, and routing so that you have complete control over development process is: all on-chip resources. 1.Select user modules. Generate, Verify, and Debug 2.Configure user modules. When you are ready to test the hardware configuration or move 3.Organize and connect. on to developing code for the project, perform the “Generate 4.Generate, verify, and debug. Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to Select User Modules your specification and provides the software for the system. The PSoC Designer provides a library of prebuilt, pretested hardware generated code provides APIs with high-level functions to control peripheral components called user modules. User modules and respond to hardware events at run time, and interrupt make selecting and implementing peripheral devices, both service routines that you can adapt as needed. analog and digital, simple. A complete code development environment allows you to develop and customize your applications in C, assembly Configure User Modules language, or both. Each user module that you select establishes the basic register The last step in the development process takes place inside settings that implement the selected function. They also provide PSoC Designer’s Debugger (accessed by clicking the Connect parameters and properties that allow you to tailor their precise icon). PSoC Designer downloads the HEX image to the ICE configuration to your particular application. For example, a Pulse where it runs at full speed. PSoC Designer debugging width modulator (PWM) user module configures one or more capabilities rival those of systems costing many times more. In digital PSoC blocks, one for each eight bits of resolution. Using addition to traditional single-step, run-to-breakpoint, and these parameters, you can establish the pulse width and duty watch-variable features, the debug interface provides a large cycle. Configure the parameters and properties to correspond to trace buffer. It allows you to define complex breakpoint events your chosen application. Enter values directly or by selecting that include monitoring address and data bus values, memory values from drop-down menus. All of the user modules are locations, and external signals. documented in datasheets that may be viewed directly in PSoCDesigner or on the Cypress website. These user module Document Number: 001-12394 Rev. *U Page 8 of 41

CY7C6431x CY7C6434x CY7C6435x Pin Information The enCoRe V USB device is available in a variety of packages which are listed and illustrated in the subsequent tables. 16-pin part pinout Figure 6. CY7C64315/CY7C64316 16-pin enCoRe V USB Device 5] 1] 3] 7] 2[ 0[ 0[ 0[ P P P P 6 5 4 3 1 1 1 1 P2[3] 1 12 P0[4] P1[7] 2 QFN 11 XRES P1[5] 3 (Top View) 10 P1[4] P1[1] 4 9 P1[0] 5 6 7 8 S + – D VS D D VD Pin Definitions 16-pin part pinout (QFN) Pin No. Type Name Description 1 I/O P2[3] Digital I/O, crystal input (Xin) 2 I/OHR P1[7] Digital I/O, SPI SS, I2C SCL 3 I/OHR P1[5] Digital I/O, SPI MISO, I2C SDA 4 I/OHR P1[1][1, 2] Digital I/O, ISSP CLK, I2C SCL, SPI MOSI 5 Power V Ground connection SS 6 USB line D+ USB PHY 7 USB line D– USB PHY 8 Power V Supply DD 9 I/OHR P1[0][1, 2] Digital I/O, ISSP DATA, I2C SDA, SPI CLK 10 I/OHR P1[4] Digital I/O, optional external clock input (EXTCLK) 11 Input XRES Active high external reset with internal pull-down 12 I/OH P0[4] Digital I/O 13 I/OH P0[7] Digital I/O 14 I/OH P0[3] Digital I/O 15 I/OH P0[1] Digital I/O 16 I/O P2[5] Digital I/O, crystal output (Xout) LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output Notes 1. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered. 2. These are the in-system serial programming (ISSP) pins that are not High Z at power on reset (POR). Document Number: 001-12394 Rev. *U Page 9 of 41

CY7C6431x CY7C6434x CY7C6435x 32-pin part pinout Figure 7. CY7C64343/CY7C64345/CY7C64346 32-pin enCoRe V USB Device VSS P0[3] P0[5] P0[7] VDDP0[6] P0[4] P0[2] 21 0 9 87 6 5 33 3 2 22 2 2 P0[1] 1 24 P0[0] P2[5] 2 23 P2[6] P2[3] 3 22 P2[4] P2[1] 4 QFN 21 P2[2] P1[7] 5 (Top View) 20 P2[0] P1[5] 6 19 P3[2] P1[3] 7 18 P3[0] P1[1] 8910 11 12 1314 15 1617 XRES VSS D+ D–VDD 1[0] 1[2] 1[4] 1[6] P P P P Pin Definitions 32-pin part pinout (QFN) Pin No. Type Name Description 1 I/OH P0[1] Digital I/O 2 I/O P2[5] Digital I/O, crystal output (Xout) 3 I/O P2[3] Digital I/O, crystal Input (Xin) 4 I/O P2[1] Digital I/O 5 I/OHR P1[7] Digital I/O, I2C SCL, SPI SS 6 I/OHR P1[5] Digital I/O, I2C SDA, SPI MISO 7 I/OHR P1[3] Digital I/O, SPI CLK 8 I/OHR P1[1][3, 4] Digital I/O, ISSP CLK, I2C SCL, SPI MOSI 9 Power V Ground SS 10 I/O D+ USB PHY 11 I/O D– USB PHY 12 Power V Supply voltage DD 13 I/OHR P1[0][3, 4] Digital I/O, ISSP DATA, I2C SDA, SPI CLK 14 I/OHR P1[2] Digital I/O 15 I/OHR P1[4] Digital I/O, optional external clock input (EXTCLK) 16 I/OHR P1[6] Digital I/O 17 Reset XRES Active high external reset with internal pull down 18 I/O P3[0] Digital I/O 19 I/O P3[2] Digital I/O 20 I/O P2[0] Digital I/O 21 I/O P2[2] Digital I/O 22 I/O P2[4] Digital I/O 23 I/O P2[6] Digital I/O 24 I/OH P0[0] Digital I/O 25 I/OH P0[2] Digital I/O 26 I/OH P0[4] Digital I/O 27 I/OH P0[6] Digital I/O 28 Power V Supply voltage DD 29 I/OH P0[7] Digital I/O 30 I/OH P0[5] Digital I/O 31 I/OH P0[3] Digital I/O 32 Power V Ground SS CP Power V Ensure the center pad is connected to ground SS LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output Notes 3. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered. 4. These are the in-system serial programming (ISSP) pins that are not High Z at power on reset (POR). Document Number: 001-12394 Rev. *U Page 10 of 41

CY7C6431x CY7C6434x CY7C6435x 48-pin Part Pinout Figure 8. CY7C64355/CY7C64356 48-pin enCoRe V USB Device P0[1]VSSP0[3] P0[5] P0[7] NCNC VDDP0[6] P0[4] P0[2] P0[0] NC 148 47 46 4544 43 424140 39 383736 P2[6] P2[7] 2 35 P2[4] P2[5] 3 34 P2[2] P2[3] 4 33 P2[0] P2[1] 5 32 P4[2] P4[3] 6 QFN 31 P4[0] P4[1] 7 (Top View) 30 P3[6] P3[7] 8 29 P3[4] P3[5] 9 28 P3[2] P3[3] 10 27 P3[0] P3[1] 11 26 XRES P1[7] 121314 15 16 17 18 192021 22232425 P1[6] P1[5] NCNC P1[3] P1[1] VSS D+ D-VDD P1[0] P1[2] P1[4] Pin Definitions 48-pin Part Pinout (QFN) Pin No. Type Pin Name Description 1 NC NC No connection 2 I/O P2[7] Digital I/O 3 I/O P2[5] Digital I/O, crystal out (Xout) 4 I/O P2[3] Digital I/O, crystal in (Xin) 5 I/O P2[1] Digital I/O 6 I/O P4[3] Digital I/O 7 I/O P4[1] Digital I/O 8 I/O P3[7] Digital I/O 9 I/O P3[5] Digital I/O 10 I/O P3[3] Digital I/O 11 I/O P3[1] Digital I/O 12 I/OHR P1[7] Digital I/O, I2C SCL, SPI SS 13 I/OHR P1[5] Digital I/O, I2C SDA, SPI MISO 14 NC NC No connection 15 NC NC No connection 16 I/OHR P1[3] Digital I/O, SPI CLK 17 I/OHR P1[1][5, 6] Digital I/O, ISSP CLK, I2C SCL, SPI MOSI 18 Power V Supply ground SS 19 I/O D+ USB 20 I/O D– USB 21 Power V Supply voltage DD 22 I/OHR P1[0][5, 6] Digital I/O, ISSP DATA, I2C SDA, SPI CLK 23 I/OHR P1[2] Digital I/O Notes 5. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered. 6. These are the in-system serial programming (ISSP) pins that are not High Z at power on reset (POR). Document Number: 001-12394 Rev. *U Page 11 of 41

CY7C6431x CY7C6434x CY7C6435x Pin Definitions 48-pin Part Pinout (QFN) Pin No. Type Pin Name Description 24 I/OHR P1[4] Digital I/O, optional external clock input (EXTCLK) 25 I/OHR P1[6] Digital I/O 26 XRES Ext Reset Active high external reset with internal pull down 27 I/O P3[0] Digital I/O 28 I/O P3[2] Digital I/O 29 I/O P3[4] Digital I/O 30 I/O P3[6] Digital I/O 31 I/O P4[0] Digital I/O 32 I/O P4[2] Digital I/O 33 I/O P2[0] Digital I/O 34 I/O P2[2] Digital I/O 35 I/O P2[4] Digital I/O 36 I/O P2[6] Digital I/O 37 I/OH P0[0] Digital I/O 38 I/OH P0[2] Digital I/O 39 I/OH P0[4] Digital I/O 40 I/OH P0[6] Digital I/O 41 Power V Supply voltage DD 42 NC NC No connection 43 NC NC No connection 44 I/OH P0[7] Digital I/O 45 I/OH P0[5] Digital I/O 46 I/OH P0[3] Digital I/O 47 Power V Supply ground SS 48 I/OH P0[1] Digital I/O CP Power V Ensure the center pad is connected to ground SS LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output Document Number: 001-12394 Rev. *U Page 12 of 41

CY7C6431x CY7C6434x CY7C6435x Register Reference The section discusses the registers of the enCoRe V device. It lists all the registers in mapping tables, in address order. Register Conventions Register Mapping Tables The register conventions specific to this section are listed in the The enCoRe V device has a total register address space of following table. 512bytes. The register space is also referred to as I/O space and is broken into two parts: Bank 0 (user space) and Bank 1 Table 1. Register Conventions (configuration space). The XIO bit in the Flag register (CPU_F) Convention Description determines which bank the user is currently in. When the XIO bit is set, the user is said to be in the “extended” address space or R Read register or bits the “configuration” registers. W Write register or bits L Logical register or bits C Clearable register or bits # Access is bit specific Document Number: 001-12394 Rev. *U Page 13 of 41

CY7C6431x CY7C6434x CY7C6435x Table 2. Register Map Bank 0 Table: User Space Name Addr (0, Hex) Access Name Addr (0, Hex) Access Name Addr (0, Hex) Access Name Addr (0, Hex) Access PRT0DR 00 RW EP1_CNT0 40 # 80 C0 PRT0IE 01 RW EP1_CNT1 41 RW 81 C1 02 EP2_CNT0 42 # 82 C2 03 EP2_CNT1 43 RW 83 C3 PRT1DR 04 RW EP3_CNT0 44 # 84 C4 PRT1IE 05 RW EP3_CNT1 45 RW 85 C5 06 EP4_CNT0 46 # 86 C6 07 EP4_CNT1 47 RW 87 C7 PRT2DR 08 RW EP5_CNT0 48 # 88 I2C_XCFG C8 RW PRT2IE 09 RW EP5_CNT1 49 RW 89 I2C_XSTAT C9 R 0A EP6_CNT0 4A # 8A I2C_ADDR CA RW 0B EP6_CNT1 4B RW 8B I2C_BP CB R PRT3DR 0C RW EP7_CNT0 4C # 8C I2C_CP CC R PRT3IE 0D RW EP7_CNT1 4D RW 8D CPU_BP CD RW 0E EP8_CNT0 4E # 8E CPU_CP CE R 0F EP8_CNT1 4F RW 8F I2C_BUF CF RW PRT4DR 10 RW 50 90 CUR_PP D0 RW PRT4IE 11 RW 51 91 STK_PP D1 RW 12 52 92 D2 13 53 93 IDX_PP D3 RW 14 54 94 MVR_PP D4 RW 15 55 95 MVW_PP D5 RW 16 56 96 I2C_CFG D6 RW 17 57 97 I2C_SCR D7 # 18 PMA0_DR 58 RW 98 I2C_DR D8 RW 19 PMA1_DR 59 RW 99 D9 1A PMA2_DR 5A RW 9A INT_CLR0 DA RW 1B PMA3_DR 5B RW 9B INT_CLR1 DB RW 1C PMA4_DR 5C RW 9C INT_CLR2 DC RW 1D PMA5_DR 5D RW 9D DD 1E PMA6_DR 5E RW 9E INT_MSK2 DE RW 1F PMA7_DR 5F RW 9F INT_MSK1 DF RW 20 60 A0 INT_MSK0 E0 RW 21 61 A1 INT_SW_EN E1 RW 22 62 A2 INT_VC E2 RC 23 63 A3 RES_WDT E3 W 24 PMA8_DR 64 RW A4 E4 25 PMA9_DR 65 RW A5 E5 26 PMA10_DR 66 RW A6 E6 27 PMA11_DR 67 RW A7 E7 28 PMA12_DR 68 RW A8 E8 SPI_TXR 29 W PMA13_DR 69 RW A9 E9 SPI_RXR 2A R PMA14_DR 6A RW AA EA SPI_CR 2B # PMA15_DR 6B RW AB EB 2C TMP_DR0 6C RW AC EC 2D TMP_DR1 6D RW AD ED 2E TMP_DR2 6E RW AE EE 2F TMP_DR3 6F RW AF EF 30 70 PT0_CFG B0 RW F0 USB_SOF0 31 R 71 PT0_DATA1 B1 RW F1 USB_SOF1 32 R 72 PT0_DATA0 B2 RW F2 USB_CR0 33 RW 73 PT1_CFG B3 RW F3 USBIO_CR0 34 # 74 PT1_DATA1 B4 RW F4 USBIO_CR1 35 # 75 PT1_DATA0 B5 RW F5 EP0_CR 36 # 76 PT2_CFG B6 RW F6 EP0_CNT0 37 # 77 PT2_DATA1 B7 RW CPU_F F7 RL EP0_DR0 38 RW 78 PT2_DATA0 B8 RW F8 EP0_DR1 39 RW 79 B9 F9 EP0_DR2 3A RW 7A BA FA EP0_DR3 3B RW 7B BB FB EP0_DR4 3C RW 7C BC FC EP0_DR5 3D RW 7D BD FD EP0_DR6 3E RW 7E BE CPU_SCR1 FE # EP0_DR7 3F RW 7F BF CPU_SCR0 FF # Gray fields are reserved; do not access these fields. # Access is bit specific. Document Number: 001-12394 Rev. *U Page 14 of 41

CY7C6431x CY7C6434x CY7C6435x Table 3. Register Map Bank 1 Table: Configuration Space Name Addr (1, Hex) Access Name Addr (1, Hex) Access Name Addr (1, Hex) Access Name Addr (1, Hex) Access PRT0DM0 00 RW PMA4_RA 40 RW 80 C0 PRT0DM1 01 RW PMA5_RA 41 RW 81 C1 02 PMA6_RA 42 RW 82 C2 03 PMA7_RA 43 RW 83 C3 PRT1DM0 04 RW PMA8_WA 44 RW 84 C4 PRT1DM1 05 RW PMA9_WA 45 RW 85 C5 06 PMA10_WA 46 RW 86 C6 07 PMA11_WA 47 RW 87 C7 PRT2DM0 08 RW PMA12_WA 48 RW 88 C8 PRT2DM1 09 RW PMA13_WA 49 RW 89 C9 0A PMA14_WA 4A RW 8A CA 0B PMA15_WA 4B RW 8B CB PRT3DM0 0C RW PMA8_RA 4C RW 8C CC PRT3DM1 0D RW PMA9_RA 4D RW 8D CD 0E PMA10_RA 4E RW 8E CE 0F PMA11_RA 4F RW 8F CF PRT4DM0 10 RW PMA12_RA 50 RW 90 D0 PRT4DM1 11 RW PMA13_RA 51 RW 91 D1 12 PMA14_RA 52 RW 92 ECO_ENBUS D2 RW 13 PMA15_RA 53 RW 93 ECO_TRIM D3 RW 14 EP1_CR0 54 # 94 D4 15 EP2_CR0 55 # 95 D5 16 EP3_CR0 56 # 96 D6 17 EP4_CR0 57 # 97 D7 18 EP5_CR0 58 # 98 MUX_CR0 D8 RW 19 EP6_CRO 59 # 99 MUX_CR1 D9 RW 1A EP7_CR0 5A # 9A MUX_CR2 DA RW 1B EP8_CR0 5B # 9B MUX_CR3 DB RW 1C 5C 9C IO_CFG1 DC RW 1D 5D 9D OUT_P1 DD RW 1E 5E 9E IO_CFG2 DE RW 1F 5F 9F MUX_CR4 DF RW 20 60 A0 OSC_CR0 E0 RW 21 61 A1 ECO_CFG E1 # 22 62 A2 OSC_CR2 E2 RW 23 63 A3 VLT_CR E3 RW 24 64 A4 VLT_CMP E4 R 25 65 A5 E5 26 66 A6 E6 27 67 A7 E7 28 68 A8 IMO_TR E8 W SPI_CFG 29 RW 69 A9 ILO_TR E9 W 2A 6A AA EA 2B 6B AB SLP_CFG EB RW 2C TMP_DR0 6C RW AC SLP_CFG2 EC RW 2D TMP_DR1 6D RW AD SLP_CFG3 ED RW 2E TMP_DR2 6E RW AE EE 2F TMP_DR3 6F RW AF EF USB_CR1 30 # 70 B0 F0 31 71 B1 F1 32 72 B2 F2 33 73 B3 F3 PMA0_WA 34 RW 74 B4 F4 PMA1_WA 35 RW 75 B5 F5 PMA2_WA 36 RW 76 B6 F6 PMA3_WA 37 RW 77 B7 CPU_F F7 RL PMA4_WA 38 RW 78 B8 F8 PMA5_WA 39 RW 79 B9 F9 PMA6_WA 3A RW 7A BA IMO_TR1 FA RW PMA7_WA 3B RW 7B BB FB PMA0_RA 3C RW 7C BC FC PMA1_RA 3D RW 7D USB_MISC_CR BD RW FD PMA2_RA 3E RW 7E BE FE PMA3_RA 3F RW 7F BF FF Gray fields are reserved; do not access these fields. # Access is bit specific. Document Number: 001-12394 Rev. *U Page 15 of 41

CY7C6431x CY7C6434x CY7C6435x Electrical Specifications This section presents the DC and AC electrical specifications of the enCoRe V USB devices. For the most up-to-date electrical specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com Figure 9. Voltage versus CPU Frequency Figure 10. IMO Frequency Trim Options 5.5V 5.5V ROperValid Voltage egionating oltage SM=Lo I0Md1eO SM=Lo I0Md0Oe SM=Lo I1Md0eO dd d V V d V 3.0V 3.0V 5.7 MHz 24 MHz 750 kHz 3 MHz 6 MHz 12 MHz24 MHz CPU Frequency IMO Frequency Document Number: 001-12394 Rev. *U Page 16 of 41

CY7C6431x CY7C6434x CY7C6435x Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 4. Absolute Maximum Ratings Symbol Description Conditions Min Typ Max Units T Storage temperature[10] Higher storage temperatures reduces data –55 +25 +125 °C STG retention time. Recommended Storage Temperature is +25°C ± 25°C. Extended duration storage temperatures above 85C degrades reliability. V Supply voltage relative to V –0.5 – +6.0 V DD SS V DC input voltage V – 0.5 – V + 0.5 V IO SS DD V DC voltage applied to tristate V – 0.5 – V + 0.5 V IOZ SS DD I Maximum current into any port pin –25 – +50 mA MIO ESD Electrostatic discharge voltage Human body model ESD 2000 – – V LU [8] Latch up current In accordance with JESD78 standard – – 200 mA Operating Temperature Table 5. Operating Temperature Symbol Description Conditions Min Typ Max Units T Ambient industrial temperature –40 – +85 °C AI T Ambient commercial temperature 0 – +70 °C AC T Operational industrial die The temperature rise from ambient to junction JI temperature [11] is package specific. Refer the table Thermal Impedances per Package on page 31. The –40 – +100 °C user must limit the power consumption to comply with this requirement. T Operational commercial die The temperature rise from ambient to junction JC temperature is package specific. Refer the table Thermal Impedances per Package on page 31. The 0 – +85 °C user must limit the power consumption to comply with this requirement. Notes 7. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 µsec, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be slower than 1 V/500 µsec to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter. 8. Errata: For Port 1 pins P1[1], P1[4], and P1[5] 300 Ohm external resistor is needed to meet this spec. Refer to “Errata” on page35 for more details. 9. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken: • Bring the device out of sleep before powering down. • Assure that VDD falls below 100 mV before powering back up. • Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep. • Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register. For the referenced registers, refer to the enCoRe V Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows VDD brown out conditions to be detected for edge rates slower than 1 V/ms. Document Number: 001-12394 Rev. *U Page 17 of 41

CY7C6431x CY7C6434x CY7C6435x DC Electrical Characteristics DC Chip Level Specifications Table6 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 6. DC Chip Level Specifications Symbol Description Conditions Min Typ Max Units V Operating voltage [7, 9] No USB activity. 3.0 – 5.5 V DD I Supply current, CPU = 24 MHz Conditions are V = 3.0 V, T = 25C, – 2.9 4.0 mA DD24,3 DD A CPU = 24 MHz, No USB/I2C/SPI. I Supply current, CPU = 12 MHz Conditions are V = 3.0 V, T = 25C, – 1.7 2.6 mA DD12,3 DD A CPU = 12 MHz, No USB/I2C/SPI. I Supply current, CPU = 6 MHz Conditions are V = 3.0 V, T = 25C, – 1.2 1.8 mA DD6,3 DD A CPU = 6 MHz, No USB/I2C/SPI. I Standby current with POR, LVD, and sleep V = 3.0 V, T = 25C, I/O regulator – 1.1 1.5 A SB1,3 DD A timer turned off. I Deep sleep current V = 3.0 V, T = 25C, I/O regulator – 0.1 – A SB0,3 DD A turned off. V Operating voltage USB activity, USB regulator enabled 4.35 – 5.25 V DDUSB I Supply current, CPU = 24 MHz Conditions are V = 5.0 V, T = 25C, – 7.1 – mA DD24,5 DD A CPU = 24 MHz, IMO = 24 MHz USB Active, No I2C/SPI. I Supply current, CPU = 12 MHz Conditions are V = 5.0 V, T = 25C, – 6.2 – mA DD12,5 DD A CPU = 12 MHz, IMO = 24 MHz USB Active, No I2C/SPI. I Supply current, CPU = 6 MHz Conditions are V = 5.0 V, T = 25C, – 5.8 – mA DD6,5 DD A CPU = 6 MHz, IMO = 24 MHz USB Active, No I2C/SPI I Standby current with POR, LVD, and sleep V = 5.0 V, T = 25C, I/O regulator – 1.1 – A SB1,5 DD A timer turned off. I Deep sleep current V = 5.0 V, T = 25C, I/O regulator – 0.1 – A SB0,5 DD A turned off. V Operating voltage USB activity, USB regulator bypassed 3.15 3.3 3.60 V DDUSB Notes 10.Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 85°C degrade reliability. 11.The temperature rise from ambient to junction is package specific. See Package Handling on page 31. The user must limit the power consumption to comply with this requirement. Document Number: 001-12394 Rev. *U Page 18 of 41

CY7C6431x CY7C6434x CY7C6435x Table 7. DC Characteristics – USB Interface Symbol Description Conditions Min Typ Max Units Rusbi USB D+ pull-up resistance With idle bus 0.900 – 1.575 k Rusba USB D+ pull-up resistance While receiving traffic 1.425 – 3.090 k Vohusb Static output high 2.8 – 3.6 V Volusb Static output low – – 0.3 V Vdi Differential input sensitivity 0.2 – – V Vcm Differential input common mode range 0.8 – 2.5 V Vse Single-ended receiver threshold 0.8 – 2.0 V Cin Transceiver capacitance – 50 pF Iio High Z state data Line Leakage On D+ or D– line –10 – +10 A Rps2 PS/2 Pull Up Resistance 3 5 7 k Rext External USB Series Resistor In series with each USB pin 21.78 22.0 22.22  ADC Electrical Specifications Table 8. ADC User Module Electrical Specifications Symbol Description Conditions Min Typ Max Units Input V Input voltage range 0 – VREFADC V IN C Input capacitance – – 5 pF IIN R Input resistance Equivalent switched cap input 1/(500fF* 1/(400fF* 1/(300fF*  IN resistance for 8-, 9-, or 10-bit Data Clock) Data Clock) Data Clock) resolution Reference V ADC reference voltage 1.14 – 1.26 V REFADC Conversion Rate F Data clock Source is chip’s internal main 2.25 – 6 MHz CLK oscillator. See AC Chip-Level Specifications for accuracy S8 8-bit sample rate Data Clock set to 6 MHz. – 23.4375 – ksps Sample Rate = 0.001/ (2^Resolution/Data Clock) S10 10-bit sample rate Data Clock set to 6 MHz. – 5.859 – ksps Sample Rate = 0.001/ (2^Resolution/Data Clock) DC Accuracy RES Resolution Can be set to 8-, 9-, or 10-bit 8 – 10 bits DNL Differential nonlinearity –1 – +2 LSB INL Integral nonlinearity –2 – +2 LSB E Offset error 8-bit resolution 0 3.2 19.2 LSB Offset 10-bit resolution 0 12.8 76.8 LSB E Gain error For any resolution –5 – +5 %FSR gain Power I Operating current – 2.1 2.6 mA ADC PSRR Power supply rejection ratio PSRR (V > 3.0 V) – 24 – dB DD PSRR (V < 3.0 V) – 30 – dB DD Document Number: 001-12394 Rev. *U Page 19 of 41

CY7C6431x CY7C6434x CY7C6435x DC General Purpose I/O Specifications Table9 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and package specific temperature range. Typical parameters apply to 5 V and 3.3 V at 25 °C. These are for design guidance only. Table 9. 3.0 V and 5.5 V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units R Pull-up resistor 4 5.6 8 k PU V High output voltage I < 10 µA, maximum of 10 mA source V – 0.2 – – V OH1 OH DD Port 2 or 3 pins current in all I/Os. V High output voltage I = 1 mA, maximum of 20 mA source V – 0.9 – – V OH2 OH DD Port 2 or 3 Pins current in all I/Os. V High output voltage I < 10 µA, maximum of 10 mA source V – 0.2 – – V OH3 OH DD Port 0 or 1 pins with LDO regulator current in all I/Os. disabled V High output voltage I = 5 mA, maximum of 20 mA source V – 0.9 – – V OH4 OH DD Port 0 or 1 pins with LDO regulator current in all I/Os. disabled V High output voltage I < 10 A, V > 3.1 V, maximum of 2.85 3.00 3.3 V OH5 OH DD Port 1 pins with LDO regulator enabled 4 I/Os all sourcing 5 mA for 3 V Out V High output voltage I = 5 mA, V > 3.1 V, maximum of 2.20 – – V OH6 OH DD Port 1 pins with LDO regulator enabled 20 mA source current in all I/Os for 3 V out V High output voltage I < 10 A, V > 3.0 V, maximum of 2.35 2.50 2.75 V OH7 OH DD Port 1 pins with LDO enabled for 2.5V 20 mA source current in all I/Os out V High output voltage I = 2 mA, V > 3.0 V, maximum of 1.90 – – V OH8 OH DD Port 1 pins with LDO enabled for 2.5V 20 mA source current in all I/Os out V High output voltage I < 10 A, V > 3.0 V, maximum of 1.60 1.80 2.1 V OH9 OH DD Port 1 pins with LDO enabled for 1.8V 20 mA source current in all I/Os out V High output voltage I = 1 mA, V > 3.0 V, maximum of 1.20 – – V OH10 OH DD Port 1 pins with LDO enabled for 1.8V 20 mA source current in all I/Os out V Low output voltage I = 25 mA, V > 3.3 V, maximum of – – 0.75 V OL OL DD 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]). V Input low voltage – – 0.8 V IL V Input high voltage 2.0 – – V IH V Input hysteresis voltage – 80 – mV H I Input leakage (absolute value) – 0.001 1 µA IL C Pin capacitance Package and pin dependent. 0.5 1.7 5 pF PIN Temp = 25C. Document Number: 001-12394 Rev. *U Page 20 of 41

CY7C6431x CY7C6434x CY7C6435x DC POR and LVD Specifications Table10 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 10. DC POR and LVD Specifications Symbol Description Conditions Min Typ Max Units V V value for PPOR trip[12] PPOR DD PORLEV[1:0] = 10b – 2.82 2.95 V V value for LVD trip DD V VM[2:0] = 000b – – – V LVD0 V VM[2:0] = 001b – – – V LVD1 V VM[2:0] = 010b 2.85 2.92 2.99 V LVD2 V VM[2:0] = 011b 2.95 3.02 3.09 V LVD3 V VM[2:0] = 100b 3.06 3.13 3.20 V LVD4 V VM[2:0] = 101b –- – – V LVD5 V VM[2:0] = 110b – – – V LVD6 V VM[2:0] = 111b 4.62 4.73 4.83 V LVD7 DC Programming Specifications Table11 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 11. DC Programming Specifications Symbol Description Conditions Min Typ Max Units V Supply voltage for flash write 1.71 – 5.25 V DDIWRITE operations I Supply current during programming – 5 25 mA DDP or verify V Input low voltage during See appropriate DC – – V V ILP IL programming or verify General Purpose I/O Specifications table V Input high voltage during 1.71 – V + 0.3 V IHP DDIWRITE programming or verify I Input current when applying Vilp to – – 0.2 mA ILP P1[0] or P1[1] during programming or verify[13] I Input current when applying Vihp to – – 1.5 mA IHP P1[0] or P1[1] during programming or verify[13] V Output low voltage during – – V + 0.75 V OLP SS programming or verify V Output high voltage during V – 0.9 – V V OHP DDIWRITE DDIWRITE programming or verify Flash Flash write endurance[14] 50,000 – – Cycles ENPB Flash Flash data retention[15] 10 20 – Years DR Notes 12.Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply. 13.Driving internal pull down resistor. 14.Erase/write cycles per block. 15.Following maximum Flash write cycles at Tamb = 55 °C and Tj = 70 °C. Document Number: 001-12394 Rev. *U Page 21 of 41

CY7C6431x CY7C6434x CY7C6435x AC Electrical Characteristics AC Chip Level Specifications The following tables list guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 12. AC Chip Level Specifications Symbol Description Conditions Min Typ Max Units F Processing frequency[16] 5.7 – 25.2 MHz CPU F Internal low-speed oscillator (ILO) frequency Trimmed[17] 19 32 50 kHz 32K1 F ILO untrimmed frequency) 13 32 82 kHz 32K_U F ILO frequency Untrimmed 13 32 82 kHz 32K2 F Internal main oscillator (IMO) stability for 22.8 24 25.2 MHz IMO24 24MHz ± 5%(12) F IMO stability for 12 MHz[17] 11.4 12 12.6 MHz IMO12 F IMO stability for 6 MHz[17] 5.7 6.0 6.3 MHz IMO6 DC Duty cycle of IMO 40 50 60 % IMO DC ILO duty cycle 40 50 60 % ILO SR Power supply slew rate – – 250 V/ms POWER_UP T External reset pulse width at power-up After supply voltage 1 – – ms XRST is valid T External reset pulse width after power-up[18] Applies after part 10 – – s XRST2 has booted Table 13. AC Characteristics – USB Data Timings Symbol Description Conditions Min Typ Max Units Tdrate Full speed data rate Average bit rate 11.97 12 12.03 MHz Tdjr1 Receiver data jitter tolerance To next transition –18.5 – 18.5 ns Tdjr2 Receiver data jitter tolerance To pair transition –9 – 9 ns Tudj1 Driver differential jitter To next transition –3.5 – 3.5 ns Tudj2 Driver differential jitter To pair transition –4.0 – 4.0 ns Tfdeop Source jitter for differential transition To SE0 transition –2 – 5 ns Tfeopt Source SE0 interval of EOP 160 – 175 ns Tfeopr Receiver SE0 interval of EOP 82 – – ns Tfst Width of SE0 interval during differential – – 14 ns transition Table 14. AC Characteristics – USB Driver Symbol Description Conditions Min Typ Max Units Tr Transition rise time 50 pF 4 – 20 ns Tf Transition fall time 50 pF 4 – 20 ns TR [19] Rise/fall time matching 90.00 – 111.1 % Vcrs Output signal crossover voltage 1.3 – 2.0 V Notes 16.VDD = 3.0 V and TJ = 85 C, CPU speed. 17.Trimmed for 3.3 V operation using factory trim values. 18.The minimum required XRES pulse length is longer when programming the device (see Table17 on page24). 19.Errata: Rising to falling rate matching of the USB D+ and D- lines has a corner case issue when operating voltage is below 3.3 V. Refer to “Errata” on page35 for more details. Document Number: 001-12394 Rev. *U Page 22 of 41

CY7C6431x CY7C6434x CY7C6435x AC General Purpose I/O Specifications Table15 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 15. AC GPIO Specifications Symbol Description Conditions Min Typ Max Units F GPIO operating frequency Normal strong mode, – – 12 MHz GPIO Ports 0, 1 TRise23 Rise time, strong mode V = 3.0 to 3.6 V, 15 – 80 ns DD Ports 2, 3 10% - 90% TRise01 Rise time, strong mode V = 3.0 to 3.6 V, 10 – 50 ns DD Ports 0, 1 10% - 90% TFall Fall time, strong mode V = 3.0 to 3.6 V, 10 – 50 ns DD All Ports 10% - 90% Figure 11. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRise23 TFall TRise01 AC External Clock Specifications Table16 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 16. AC External Clock Specifications Symbol Description Conditions Min Typ Max Units F Frequency 0.750 – 25.2 MHz OSCEXT – High period 20.6 – 5300 ns – Low period 20.6 – – ns – Power-up IMO to switch 150 – – s Document Number: 001-12394 Rev. *U Page 23 of 41

CY7C6431x CY7C6434x CY7C6435x AC Programming Specifications Table17 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 17. AC Programming Specifications Symbol Description Conditions Min Typ Max Units T Rise time of SCLK 1 – 20 ns RSCLK T Fall time of SCLK 1 – 20 ns FSCLK T Data setup time to falling edge of SCLK 40 – – ns SSCLK T Data hold time from falling edge of SCLK 40 – – ns HSCLK F Frequency of SCLK 0 – 8 MHz SCLK T Flash erase time (Block) – – 18 ms ERASEB T Flash block write time – – 25 ms WRITE T Data out delay from falling edge of SCLK, V > 3.6 V – – 60 ns DSCLK1 DD T Data out delay from falling edge of SCLK 3.0 V < V < 3.6 V – – 85 ns DSCLK2 DD T External reset pulse width after power-up Required to enter programming 263 – – s XRST3 mode when coming out of sleep Figure 12. Timing Diagram - AC Programming Cycle Document Number: 001-12394 Rev. *U Page 24 of 41

CY7C6431x CY7C6434x CY7C6435x AC I2C Specifications Table18 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 18. AC Characteristics of the I2C SDA and SCL Pins Standard Mode Fast Mode Symbol Description Units Min Max Min Max F SCL clock frequency 0 100 0 400 kHz SCLI2C T Hold time (repeated) START condition. After this period, the first 4.0 – 0.6 – s HDSTAI2C clock pulse is generated T LOW period of the SCL clock 4.7 – 1.3 – s LOWI2C T HIGH period of the SCL clock 4.0 – 0.6 – s HIGHI2C T Setup time for a repeated START condition 4.7 – 0.6 – s SUSTAI2C T Data hold time 0 – 0 – s HDDATI2C T Data setup time 250 – 100[20] – ns SUDATI2C T Setup time for STOP condition 4.0 – 0.6 – s SUSTOI2C T Bus free time between a STOP and START condition 4.7 – 1.3 – s BUFI2C T Pulse width of spikes are suppressed by the input filter – – 0 50 ns SPI2C Figure 13. Definition of Timing for Fast/Standard Mode on the I2C Bus SDA T T SPI2C LOWI2C T T T SUDATI2C HDSTAI2C BUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S Note 20.A Fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tSUDAT  250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSUDAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released. Document Number: 001-12394 Rev. *U Page 25 of 41

CY7C6431x CY7C6434x CY7C6435x Table 19. SPI Master AC Specifications Symbol Description Conditions Min Typ Max Units F SCLK clock frequency – – 6 MHz SCLK DC SCLK duty cycle – 50 – % T MISO to SCLK setup time 60 – – ns SETUP T SCLK to MISO hold time 40 – – ns HOLD T SCLK to MOSI valid time – – 40 ns OUT_VAL T SCLK to MOSI hold time 40 – – ns OUT_H Figure 14. SPI Master Mode 0 and 2 SPI Master, modes 0 and 2 1/FSCLK TLOW THIGH SCLK (mode 0) SCLK (mode 2) TSETUP THOLD MISO MSb LSb (input) TOUT_SU TOUT_H MOSI (output) Figure 15. SPI Master Mode 1 and 3 SPI Master, modes 1 and 3 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TSETUP THOLD MISO MSb LSb (input) TOUT_SU TOUT_H MOSI MSb LSb (output) Document Number: 001-12394 Rev. *U Page 26 of 41

CY7C6431x CY7C6434x CY7C6435x Table 20. SPI Slave AC Specifications Symbol Description Conditions Min Typ Max Units F SCLK clock frequency 0.0469 – 12 MHz SCLK T SCLK low time 41.67 – – ns LOW T SCLK high time 41.67 – – ns HIGH T MOSI to SCLK setup time 30 – – ns SETUP T SCLK to MOSI hold time 50 – – ns HOLD T SS low to MISO valid – – 153 ns SS_MISO T SCLK to MISO valid – – 125 ns SCLK_MISO T SS high time 50 – – ns SS_HIGH T Time from SS low to first SCLK 2/F – – ns SS_CLK SCLK T Time from last SCLK to SS high 2/F – – ns CLK_SS SCLK Figure 16. SPI Slave Mode 0 and 2 SPI Slave, modes 0 and 2 TSS_CLK TCLK_SS TSS_HIGH /SS 1/FSCLK TLOW THIGH SCLK (mode 0) SCLK (mode 2) TSS_MISO TOUT_H MISO (output) TSETUP THOLD MOSI (input) MSb LSb Document Number: 001-12394 Rev. *U Page 27 of 41

CY7C6431x CY7C6434x CY7C6435x Figure 17. SPI Slave Mode 1 and 3 SPI Slave, modes 1 and 3 TSS_CLK TCLK_SS /SS 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TOUT_H TSS_MISO TSCLK_MISO MISO MSb LSb (output) TSETUP THOLD MOSI (input) MSb LSb Document Number: 001-12394 Rev. *U Page 28 of 41

CY7C6431x CY7C6434x CY7C6435x Package Diagrams This section illustrates the packaging specifications for the enCoRe V USB device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the enCoRe V emulation tools and their dimensions, refer to the development kit. Packaging Dimensions Figure 18. 16-pin Chip On Lead (3 × 3 × 0.6 mm) LG16A/LD16A (Sawn) Package Outline, 001-09116 001-09116 *J Document Number: 001-12394 Rev. *U Page 29 of 41

CY7C6431x CY7C6434x CY7C6435x Figure 19. 32-pin QFN (5 × 5 × 0.55 mm) LQ32 3.5 × 3.5 E-Pad (Sawn) Package Outline, 001-42168 001-42168 *E Figure 20. 48-pin QFN (7 × 7 × 1.00 mm) LT48A 5.1 × 5.1 E-Pad (Sawn) Package Outline, 001-13191 001-13191 *H Document Number: 001-12394 Rev. *U Page 30 of 41

CY7C6431x CY7C6434x CY7C6435x Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. A label on the package has details about the actual bake temperature and the minimum bake time to remove this moisture. The maximum bake time is the aggregate time that the parts exposed to the bake temperature. Exceeding this exposure may degrade device reliability. Table 21. Package Handling Parameter Description Minimum Typical Maximum Unit TBAKETEMP Bake temperature – 125 See package label C TBAKETIME Bake time See package label – 72 hours Thermal Impedances Table 22. Thermal Impedances per Package Package Typical  [21] JA 16-pin QFN 32.69C / W 32-pin QFN[22] 19.51C / W 48-pin QFN[22] 17.68C / W Capacitance on Crystal Pins Table 23. Typical Package Capacitance on Crystal Pins Package Package Capacitance 32-pin QFN 3.2 pF 48-pin QFN 3.3 pF Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 24. Solder Reflow Peak Temperature Package Minimum Peak Temperature [23] Maximum Peak Temperature 16-pin QFN 240C 260C 32-pin QFN 240C 260C 48-pin QFN 240C 260C Notes 21.TJ = TA + Power x JA. 22.To achieve the thermal impedance specified for the package, solder the center thermal pad to the PCB ground plane. 23.Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-12394 Rev. *U Page 31 of 41

CY7C6431x CY7C6434x CY7C6435x Ordering Information Table 25. Ordering Code - Commercial Parts Flash SRAM Ordering Code Package Information No. of GPIOs Target Applications (KB) (KB) Mid-tier Full-Speed USB dongle, CY7C64315-16LKXC 16-pin QFN (3 × 3 mm) 16 1 11 Remote Control Host Module, Various 16-pin QFN (Tape and Reel), Mid-tier Full-Speed USB dongle, CY7C64315-16LKXCT 16 1 11 (3×3 mm) Remote Control Host Module, Various Feature-rich Full-Speed USB dongle, CY7C64316-16LKXC 16-pin QFN (3 × 3 mm) 32 2 11 Remote Control Host Module, Various 16-pin QFN (Tape and Reel), Feature-rich Full-Speed USB dongle, CY7C64316-16LKXCT 32 2 11 (3×3 mm) Remote Control Host Module, Various CY7C64343-32LQXC 32-pin QFN (5 × 5 mm) 8 1 25 Full-Speed USB mouse, Various 32-pin QFN (Tape and Reel), CY7C64343-32LQXCT 8 1 25 Full-Speed USB mouse, Various (5×5 mm) CY7C64345-32LQXC 32-pin QFN (5×5 mm) 16 1 25 Full-Speed USB mouse, Various 32-pin QFN (Tape and Reel), CY7C64345-32LQXCT 16 1 25 Full-Speed USB mouse, Various (5×5 mm) 32-pin QFN (Tape and Reel), CY7C64346-32LQXCT 32 1 25 Full-Speed USB keyboard, Various (5×5 mm) CY7C64355-48LTXC 48-pin QFN (7 × 7 mm) 16 1 36 Full-Speed USB keyboard, Various 48-pin QFN (Tape and Reel), CY7C64355-48LTXCT 16 1 36 Full-Speed USB keyboard, Various (7×7 mm) Feature-rich Full-Speed USB CY7C64356-48LTXC 48-pin QFN (7×7 mm) 32 2 36 keyboard, Various 48-pin QFN (Tape and Reel), Feature-rich Full-Speed USB CY7C64356-48LTXCT 32 2 36 (7×7 mm) keyboard, Various Table 26. Ordering Code - Industrial Parts Flash SRAM Ordering Code Package Information No. of GPIOs Target Applications (KB) (KB) 16-pin QFN, Industrial Mid-tier Full-Speed USB dongle, CY7C64315-16LKXI 16 1 11 (3×3mm) Remote Control Host Module, Various 16-pin QFN, Industrial (Tape Mid-tier Full-Speed USB dongle, CY7C64315-16LKXIT 16 1 11 and Reel), (3 × 3 mm) Remote Control Host Module, Various Document Number: 001-12394 Rev. *U Page 32 of 41

CY7C6431x CY7C6434x CY7C6435x Ordering Code Definitions CY 7C64 XXX- XX XXX C/I (T) Tape and reel Temperature range: Commercial/Industrial Package type: LK/LQ/LT: QFN Pb-free Pin count: 16 = 16 pins, 32 = 32 pins, 48 = 48 pins Base part number Marketing Code: 7C64 = enCoRe Full-Speed USB Controller Company ID: CY = Cypress Document Number: 001-12394 Rev. *U Page 33 of 41

CY7C6431x CY7C6434x CY7C6435x Acronyms Document Conventions Units of Measure Acronym Description API Application Programming Interface Symbol Unit of Measure CPU Central Processing Unit C degree Celsius GPIO General Purpose I/O dB decibel ICE In-Circuit Emulator fF femtofarad ILO Internal Low speed Oscillator Hz hertz IMO Internal Main Oscillator KB 1024 bytes I/O Input/Output Kbit 1024 bits LSb Least Significant Bit kHz kilohertz LVD Low Voltage Detect k kilohm MSb Most Significant Bit MHz megahertz POR Power On Reset M megaohm PPOR Precision Power On Reset A microampere F microfarad PSoC Programmable System-on-Chip H microhenry SLIMO Slow IMO s microsecond SRAM Static Random Access Memory V microvolt Vrms microvolts root-mean-square W microwatt mA milliampere ms milli-second mV millivolt nA nanoampere ns nanosecond nV nanovolt W ohm pA picoampere pF picofarad pp peak-to-peak ppm parts per million ps picosecond sps samples per second  sigma: one standard deviation V volt Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are decimal. Document Number: 001-12394 Rev. *U Page 34 of 41

CY7C6431x CY7C6434x CY7C6435x Errata This section describes the errata for the enCoRe V – CY7C643xx. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. CY7C643xx Errata Summary The following Errata item applies to the CY7C643xx data sheets. 1.Latch up susceptibility when maximum I/O sink current exceeded ■PROBLEM DEFINITION P1[3], P1[6], and P1[7] pins are susceptible to latch up when the I/O sink current exceeds 25 mA per pin on these pins. ■PARAMETERS AFFECTED LU – Latch up current. Per JESD78A, the maximum allowable latch up current per pin is 100 mA. Cypress internal specification is 200 mA latch up current limit. ■TRIGGER CONDITIONS Latch up occurs when both the following conditions are met: A.The offending I/O is externally connected to a voltage higher than the I/O high state, causing a current to flow into the pin that exceeds 25 mA. B.A Port1 I/O (P1[1], P1[4], and P1[5] respectively) adjacent to the offending I/O is connected to a voltage lower than the I/O low state. This causes a signal that drops below Vss (signal undershoot) and a current greater than 200 mA to flow out of the pin. ■SCOPE OF IMPACT The trigger conditions outlined in this item exceed the maximum ratings specified in the CY7C643xx data sheets. ■WORKAROUND Add a series resistor > 300  to P1[3], P1[6], and P1[7] pins to restrict current to within latch up limits. ■FIX STATUS This issue will be corrected in the next new silicon revision. 2.Does not meet USB 2.0 specification for D+ and D- rise/fall matching when supply voltage is under 3.3 V ■PROBLEM DEFINITION Rising to falling rate matching of the USB D+ and D- lines has a corner case at lower supply voltages, such as those under 3.3 V. ■PARAMETERS AFFECTED Rising to falling rate matching of the USB data lines. ■TRIGGER CONDITION(S) Operating the VCC supply voltage at the low end of the chip’s specification (under 3.3 V) may cause a mismatch in the rising to falling rate. ■SCOPE OF IMPACT This condition does not affect USB communications but could cause corner case issues with USB lines’ rise/fall matching specification. Signal integrity tests were run using the Cypress development kit and excellent eye was observed with supply voltage of 3.15 V. Document Number: 001-12394 Rev. *U Page 35 of 41

CY7C6431x CY7C6434x CY7C6435x Figure 21. Eye Diagram ■WORKAROUND Avoid the trigger condition by using lower tolerance voltage regulators. ■FIX STATUS This issue will not be corrected in the next new silicon revision. Document Number: 001-12394 Rev. *U Page 36 of 41

CY7C6431x CY7C6434x CY7C6435x Document History Page Document Title: CY7C6431x/CY7C6434x/CY7C6435x, enCoRe™ V Full Speed USB Controller Document Number: 001-12394 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 626256 TYJ See ECN New data sheet. Filled in TBDs, added new block diagram, and corrected some values. Part *A 735718 TYJ / ARI See ECN numbers updated as per new specifications. Corrected the block diagram and Figure 3, which is the 16-pin enCoRe V device. Corrected the description to pin 29 on Table 2, the Typ/Max values for I on the DC chip-level specifications, the current value for the latch-up SB0 current in the Electrical Characteristics section, and corrected the 16 QFN package information in the Thermal Impedance table. Corrected some of the bulleted items on the first page. Added DC Characteristics–USB Interface table. Added AC Characteristics–USB Data Timings table. Added AC Characteristics–USB Driver table. *B 1120404 ARI See ECN Corrected Flash Write Endurance minimum value in the DC Programming Specifications table. Corrected the Flash Erase Time max value and the Flash Block Write Time max value in the AC Programming Specifications table. Implemented new latest template. Include parameters: Vcrs, Rpu (USB, active), Rpu (USB suspend), Tfdeop, Tfeopr2, Tfeopt, Tfst. Added register map tables. Corrected a value in the DC Chip-Level Specifications table. *C 1241024 TYJ / ARI See ECN Corrected Idd values in Table 6 - DC Chip-Level Specifications. *D 1639963 AESA See ECN Post to www.cypress.com Updated Ordering Code table: - Ordering code changed for 32-QFN package: From -32LKXC to -32LTXC - Added a new package type – “LTXC” for 48-QFN - Included Tape and Reel ordering code for 32-QFN and 48-QFN packages Changed active current values at 24, 12 and 6MHz in table “DC Chip-Level *E 2138889 TYJ / PYRS See ECN Specifications” - IDD24: 2.15 to 3.1mA - IDD12: 1.45 to 2.0mA - IDD6: 1.1 to 1.5mA Added information on using P1[0] and P1[1] as the I2C interface during POR or reset events Document Number: 001-12394 Rev. *U Page 37 of 41

CY7C6431x CY7C6434x CY7C6435x Document History Page (continued) Document Title: CY7C6431x/CY7C6434x/CY7C6435x, enCoRe™ V Full Speed USB Controller Document Number: 001-12394 Orig. of Submission Rev. ECN No. Description of Change Change Date Converted from Preliminary to Final Added operating voltage ranges with USB ADC resolution changed from 10-bit to 8-bit Rephrased battery monitoring clause in page 1 to include “with external components” Included ADC specifications table Included Voh7, Voh8, Voh9, Voh10 specs Flash data retention – condition added to Note [11] Input leakage spec changed to 25 nA max TYJ / PYRS / Under AC Char, Frequency accuracy of ILO corrected *F 2583853 10/10/08 HMT GPIO rise time for ports 0,1 and ports 2,3 made common AC Programming specifications updated Included AC Programming cycle timing diagram AC SPI specification updated Spec change for 32-QFN package Input Leakage Current maximum value changed to 1 A Updated V parameter in Table 13 OHV Updated thermal impedances for the packages Update Development Tools, add Designing with PSoC Designer. Edit, fix links and table format. Update TMs. Updated Features, Functional Overview, Development Tools, and Designing with PSoC Designer sections with edits. Removed ‘GUI - graphical user interface’ from Document Conventions acronym table. *G 2653717 DVJA / PYRS 02/04/09 Removed ‘O - Only a read/write register or bits’ in Table 4 Edited Table 8: removed 10-bit resolution information and corrected units column. Added package handling section Added 8K part ‘CY7C64343-32LQXC’ to Ordering Information. Updated Block Diagram. Added Full Speed USB, 10-bit ADC, SPI, and I2C Slave sections. ADC Resolution changed from 8-bit to 10-bit Updated Table 9 DC Chip Level Specs Updated Table10 DC Char - USB Interface Updated Table 12 DC POR and LDV Specs *H 2714694 DVJA / AESA 06/04/2009 Changed operating temperature from Commercial to Industrial Changed Temperature Range to Industrial: –40 to 85°C Figure 9: Changed minimum CPU Frequency from 750 kHz to 5.7 MHz Table 14: Removed “Maximum” from the F description CPU Ordering Information: Replaced ‘C’ with ‘I’ in all part numbers to denote Industrial Temp Range Changed Table 12: ADC Specs Added F (Untrimmed) spec to Table 16: AC Chip level Specs *I 2764460 DVJA / AESA 09/16/2009 32K2 Changed T spec to SR in Table 16: AC Chip Level Specs RAMP POWER_UP Added Table 27: Typical Package Capacitance on Crystal Pins Added USB-IF TID number in Features on page 1. Added Note 5 on page *J 2811903 DVJA 11/20/2009 18. Changed V in Table 12 on page 22. IHP Document Number: 001-12394 Rev. *U Page 38 of 41

CY7C6431x CY7C6434x CY7C6435x Document History Page (continued) Document Title: CY7C6431x/CY7C6434x/CY7C6435x, enCoRe™ V Full Speed USB Controller Document Number: 001-12394 Orig. of Submission Rev. ECN No. Description of Change Change Date On page 4, changed the input voltage range from ‘0 V to 1.3 V’ to ‘0 V to V ’. REFADC Added note for Operating Voltage in Table6. Updated Register Map. Added SPI slave and master mode diagrams; in Table19, changed *K 2874274 KKU / PYRS 02/05/10 T parameter to T and modified description; in Table20, OUT_HIGH OUT_H updated T and T min values to 2/F and changed SS_CLK CLK_SS SCLK description of T . SS_MISO Added Vdd parameter in Table6. USB Updated package diagrams. Removed HPOR bit reference from DC POR and LVD Specifications Updated Development Tools and Designing with PSoC Designer. *L 3028310 XUT 09/13/2010 Added Ordering Code Definitions Moved Acronyms and Document Conventions to end of document. Updated Features section as furnished in the CDT 74890 *M 3048308 NXZ 10/06/2010 Updated datasheet as per new template All footnotes updated sequentially Updated Getting Started. *N 3557631 CSAI 03/21/2012 Updated Package Diagrams. Updated in new template. Updated Functional Overview (Updated The enCoRe V Core (Updated contents in the section), updated Full-Speed USB (Updated contents in the section)). Updated Register Mapping Tables (Updated Table3 (Replaced “EC0_ENBUS” with “ECO_ENBUS” and replaced “EC0_TRIM” with *O 3912957 NXZ 03/06/2013 “ECO_TRIM”)). Updated Package Diagrams: spec 001-09116 – Changed revision from *F to *H. spec 001-42168 – Changed revision from *D to *E. spec 001-13191 – Changed revision from *F to *G. *P 3979449 ANKC 04/23/2013 Added Errata. Added Errata footnotes (Note 8, 19). Updated Electrical Specifications: Updated Absolute Maximum Ratings: Added Note 8 and referred the same note in LU parameter. *Q 4074443 ANKC 07/23/2013 Updated AC Electrical Characteristics Updated AC Chip Level Specifications: Added Note 19 and referred the same note in TR parameter in Table14. Updated to new template. Updated Package Diagrams: spec 001-09116 – Changed revision from *H to *I. *R 4197134 ANKC 11/20/2013 Completing Sunset Review. Document Number: 001-12394 Rev. *U Page 39 of 41

CY7C6431x CY7C6434x CY7C6435x Document History Page (continued) Document Title: CY7C6431x/CY7C6434x/CY7C6435x, enCoRe™ V Full Speed USB Controller Document Number: 001-12394 Orig. of Submission Rev. ECN No. Description of Change Change Date Updated Pin Information: Updated 32-pin part pinout: Updated Figure7 (No change in figure, included CY7C64346 in figure caption). *S 4578605 GINS 12/11/2014 Updated Package Diagrams: spec 001-09116 – Changed revision from *I to *J. Updated Ordering Information: Updated Table25: Updated part numbers. Updated Cypress Logo, Sales Page and Disclaimer. Updated Figure20 (spec 001-13191 *G to *H) in Package Diagrams. *T 5548557 ANKC 12/12/2016 Removed the following obsolete part numbers (Table26) in Ordering Information: CY7C64343-32LQXI, CY7C64343-32LQXIT, CY7C64345-32LQXI, CY7C64345-32LQXIT, CY7C64356-48LTXI, CY7C64356-48LTXIT. *U 5715963 AESATMP7 04/27/2017 Updated Cypress Logo and Copyright. Document Number: 001-12394 Rev. *U Page 40 of 41

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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-12394 Rev. *U Revised April 27, 2017 Page 41 of 41

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: C ypress Semiconductor: CY7C64315-16LKXC CY7C64316-16LKXC CY7C64345-32LKXC CY7C64356-48LFXC CY7C64345-32LQXCT CY7C64356-48LTXCT CY7C64355-48LTXC CY7C64315-16LKXCT CY7C64316-16LKXCT CY7C64345-32LQXC CY7C64355-48LTXCT CY7C64356-48LTXC CY7C64343-32LQXC CY7C64343-32LQXCT CY7C64316-WAFC