CY7C64215 enCoRe™ III Full-Speed USB Controller enCoRe™ III Full-Speed USB Controller Features ■Additional system resources ❐Inter-integrated circuit (I2C) slave, master, and multimaster ■Powerful Harvard-architecture processor to 400 kHz ❐M8C processor speeds up to 24 MHz ❐Watchdog and sleep timers ❐Two 8 × 8 multiply, 32-bit accumulate ❐User-configurable low-voltage detection (LVD) ❐3.15 to 5.25-V operating voltage ❐Integrated supervisory circuit ❐USB 2.0 USB-IF certified. TID# 40000110 ❐On-chip precision voltage reference ❐Commercial operating temperature range: 0°C to +70°C ■Complete development tools ❐Industrial operating temperature range: –40°C to +85°C ❐Free development software (PSoC® Designer) ■Advanced peripherals (enCoRe™ III blocks) ❐Full-featured, in-circuit emulator and programmer ❐Six analog enCoRe III blocks provide: ❐Full-speed emulation • Up to 14-bit incremental and delta sigma analog-to-digital ❐Complex breakpoint structure converters (ADCs) ❐128 KB trace memory ❐Programmable threshold comparator ❐Four digital enCoRe III blocks provide: Block Diagram • 8-bit and 16-bit pulse width modulators (PWMs), timers, and counters • I2C master • SPI master or slave • Full-duplex universal asynchronous receiver-transmitter (UART) • CYFISNP modules to talk to Cypress CYFI™ radio ■Complex peripherals by combining blocks enCoRe III Core ■Full-speed USB (12 Mbps) ❐Four unidirectional endpoints ❐One bidirectional control endpoint ❐Dedicated 256-byte buffer ❐No external crystal required ❐Operational at 3.15V to 3.5V or 4.35V to 5.25V ■Flexible on-chip memory ❐16 KB flash program storage 50,000 erase/write cycles ❐1 KB SRAM data storage ❐In-system serial programming (ISSP) ❐Partial flash updates ❐Flexible protection modes ❐EEPROM emulation in flash ■Programmable pin configurations ❐25 mA sink on all general purpose I/Os (GPIOs) ❐Pull-up, Pull-down, high Z, strong, or open drain drive modes on all GPIOs ❐Configurable interrupt on all GPIOs ■Precision, programmable clocking ❐Internal ±4% 24- and 48-MHz oscillator with support for external clock oscillator ❐Internal oscillator for watchdog and sleep ❐.25% accuracy for USB with no external components Errata: For information on silicon errata, see “Errata” on page40. Details include trigger conditions, devices affected, and proposed workaround. CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 38-08036 Rev. *N Revised May 19, 2017

CY7C64215 Contents Applications ......................................................................3 Operating Temperature .............................................13 enCoRe III Functional Overview ......................................3 DC Electrical Characteristics .....................................14 enCoRe III Core ..........................................................3 AC Electrical Characteristics .....................................24 The Digital System ......................................................3 Packaging Information ...................................................30 The Analog System .....................................................4 Package Diagrams ....................................................30 Additional System Resources .....................................4 Thermal Impedance ..................................................32 enCoRe III Device Characteristics ..............................4 Solder Reflow Peak Temperature .............................32 Getting Started ..................................................................5 Ordering Information ......................................................33 Application Notes ........................................................5 Ordering Code Definitions .........................................33 Development Kits ........................................................5 Acronyms ........................................................................34 Training .......................................................................5 Acronyms Used .........................................................34 CYPros Consultants ....................................................5 Reference Documents ....................................................34 Solutions Library ..........................................................5 Document Conventions .................................................35 Technical Support .......................................................5 Units of Measure .......................................................35 Development Tools ..........................................................5 Numeric Conventions ................................................35 PSoC Designer Software Subsystems ........................5 Glossary ..........................................................................35 Designing with PSoC Designer .......................................6 Errata ...............................................................................40 Select Components .....................................................6 Part Numbers Affected ..............................................40 Configure Components ...............................................6 CY7C64215 Qualification Status ...............................40 Organize and Connect ................................................6 CY7C64215 Errata Summary ....................................40 Generate, Verify, and Debug .......................................6 Document History Page .................................................43 Pin Information .................................................................7 Sales, Solutions, and Legal Information ......................45 56-Pin Part Pinout .......................................................7 Worldwide Sales and Design Support .......................45 28-Pin Part Pinout .......................................................8 Products ....................................................................45 Register Reference ...........................................................9 PSoC® Solutions ......................................................45 Register Mapping Tables ............................................9 Cypress Developer Community .................................45 Register Map Bank 0 Table: User Space .................10 Technical Support .....................................................45 Register Map Bank 1 Table: Configuration Space ...11 Electrical Specifications ................................................12 Absolute Maximum Ratings .......................................13 Document Number: 38-08036 Rev. *N Page 2 of 45

CY7C64215 Applications The 24-MHz IMO is doubled to 48 MHz for use by the digital system, if needed. The 48-MHz clock is required to clock the ■PC human interface devices USB block and must be enabled for communication. A low-power 32-kHz internal low-speed oscillator (ILO) is provided for the ❐Mouse (optomechanical, optical, trackball) sleep timer and WDT. The clocks, together with programmable ❐Keyboards clock dividers (system resource), provide flexibility to integrate ❐Joysticks almost any timing requirement into enCoRe III. In USB systems, ■Gaming the IMO self-tunes to ±0.25% accuracy for USB communication. ❐Game pads The extended temperature range for the industrial operating ❐Console keyboards range (–40°C to +85°C) requires the use of an ECO, which is ■General purpose only available on the 56-pin QFN package. ❐Barcode scanners enCoRe III GPIOs provide connection to the CPU, digital and ❐POS terminal analog resources of the device. Each pin’s drive mode may be ❐Consumer electronics selected from eight options, enabling great flexibility in external ❐Toys interfacing. Every pin also has capability to generate a system ❐Remote controls interrupt on high-level, low-level, and change from last read. ❐USB to serial The Digital System enCoRe III Functional Overview The digital system is composed of four digital enCoRe III blocks. The enCoRe III is based on the flexible PSoC architecture and Each block is an 8-bit resource that is used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, is a full-featured, full-speed (12-Mbps) USB part. Configurable analog, digital, and interconnect circuitry enable a high level of which are called user module references. integration in a host of consumer, and communication Figure 1. Digital System Block Diagram applications. Port 7 Port 5 Port 3 Port 1 This architecture enables the user to create customized Port 4 Port 2 Port 0 peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included Digital Clocks To System Bus To Analog in both 28-pin SSOP and 56-pin QFN packages. From Core System enCoRe III architecture, as illustrated in the “Block Diagram” on page1, is comprised of four main areas: enCoRe III core, digital DIGITAL SYSTEM system, analog system, and system resources including a full-speed USB port. Configurable global busing enables all the Digital enCoRe III Block Array device resources to combine into a complete custom system. Tcaochcneen esenscC tt otoo Rf otehu erII Idg CliogYibta7alCl bd6lio4gc2itka1sl5 a acnnaddn a shniaxav laoeng ua iplno ttgeo r bscleoovncenknse .cI/tOs, pporortvsi dthinagt 8 8 Row InputConfiguration DBB00 DBB0R1owD 0CB02 DCB0344 ConfigurationRow Output 8 8 enCoRe III Core The enCoRe III Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and GIE[7:0] GlobalD igital GOE[7:0] configurable GPIOs. GIO[7:0] Interconnect GOO[7:0] The M8C CPU core is a powerful processor with speeds up to 24MHz, providing a four-million instructions per second (MIPS) 8-bit Harvard-architecture microprocessor. The CPU uses an interrupt controller with up to 20 vectors, to simplify programming The following digital configurations can be built from the blocks: of real-time embedded events. Program execution is timed and ■PWMs, timers, and counters (8-bit and 16-bit) protected using the included sleep and watchdog timers (WDT). Memory encompasses 16 KB of flash for program storage, 1KB ■UART 8-bit with selectable parity of SRAM for data storage, and up to 2 KB of EEPROM emulated ■SPI master and slave using the flash. Program flash uses four protection levels on blocks of 64 bytes, enabling customized software IP protection. ■I2C master enCoRe III incorporates flexible internal clock generators, ■RF interface: Interface to Cypress CYFI radio including a 24-MHz internal main oscillator (IMO) accurate to 8% The digital blocks are connected to any GPIO through a series over temperature and voltage as well as an option for an external of global buses that can route any signal to any pin. The buses clock oscillator (ECO). USB operation requires the OSC LOCK also enable signal multiplexing and performing logic operations. bit of the USB_CR0 register to be set to obtain IMO accuracy This configurability frees your designs from the constraints of a to.25%. fixed peripheral controller. Document Number: 38-08036 Rev. *N Page 3 of 45

CY7C64215 The Analog System The Analog Multiplexer System The analog system is composed of six configurable blocks, The analog mux bus can connect to every GPIO pin in ports 0 to comprised of an opamp circuit enabling the creation of complex 5. Pins are connected to the bus individually or in any analog signal flows. Analog peripherals are very flexible and are combination. The bus also connects to the analog system for customized to support specific application requirements. analysis with comparators and analog-to-digital converters. It is enCoRe III analog function supports the Analog-to-digital split into two sections for simultaneous dual-channel processing. converters (with 6- to 14-bit resolution, selectable as An additional 8:1 analog input multiplexer provides a second incremental, and delta-sigma) and programmable threshold path to bring Port 0 pins to the analog array. comparator). Additional System Resources Analog blocks are arranged in two columns of three, with each column comprising one continuous time (CT) - AC B00 or AC System resources provide additional capability useful to B01 - and two switched capacitor (SC) - ASC10 and ASD20 or complete systems. Additional resources include a multiplier, ASD11 and ASC21 - blocks, as shown in Figure2. decimator, low voltage detection, and power-on reset. Brief statements describing the merits of each resource follow. Figure 2. Analog System Block Diagram ■Full-speed USB (12 Mbps) with five configurable endpoints and All IO 256 bytes of RAM. No external components required except (Except Port 7) two series resistors. Industrial temperature operating range for P0[7] P0[6] USB requires an external clock oscillator. ■Two multiply accumulates (MACs) provide fast 8-bit multipliers P0[5] P0[4] with 32-bit accumulate, to assist in both general math and digital filters. P0[3] P0[2] ■The decimator provides a custom hardware filter for digital P0[1] P0[0] signal processing applications including the creation of n delta-sigma ADCs. P2[3] AnalogMux Bus RefIDIn P2[6] ■Dfreigqiutael nccileosc kfo r duivsied einrs appprloicvaidtieo nsth. rTehee ccluosctkosm aizraeb rloeu tecldo ctok N P2[4] G both the digital and analog systems. A P2[1] P2[2] ■The I2C module provides 100- and 400-kHz communication over two wires. Slave, master, and multimaster modes are all P2[0] supported. ■LVD interrupts can signal the application of falling voltage levels, while the advanced power-on reset (POR) circuit eliminates the need for a system supervisor. enCoRe III Device Characteristics enCoRe III devices have four digital blocks and six analog blocks. The following table lists the resources available for ACI0[1:0] ACI1[1:0] specific enCoRe III devices. Array Input Configuration Table 1. enCoRe III Device Characteristics BArlroacyk ACB00 ACB01 NuPmarbter Digital I/O Digital Rows Digital Blocks Analog Inputs Analog Outputs Analog Columns Analog Blocks SRAMSize Flash Size ASC10 ASD11 CY7C64215 up to 1 4 22 2 2 6 1K 16K 28 Pin 22 ASD20 ASC21 CY7C64215 up to 1 4 48 2 2 6 1K 16K 56 Pin 50 Analog Reference Interface to RefHi Reference AGNDIn Digital System RefLo Generators RefIn AGND Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 38-08036 Rev. *N Page 4 of 45

CY7C64215 Getting Started ■Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration The quickest path to understanding the enCoRe III silicon is by ■Extensive user module catalog reading this datasheet and using the PSoC Designer Integrated Development Environment (IDE). This datasheet is an overview ■Integrated source-code editor (C and assembly) of the enCoRe V integrated circuit and presents specific pin, register, and electrical specifications. ■Free C compiler with no size restrictions or time limits For in-depth information, along with detailed programming ■Built-in debugger details, see the PSoC® Technical Reference Manual. ■In-circuit emulation For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web. ■Built-in support for communication interfaces: ❐Hardware and software I2C slaves and masters Application Notes ❐Full-speed USB 2.0 Cypress application notes are an excellent introduction to the ❐Up to four full-duplex universal asynchronous wide variety of possible PSoC designs. receiver/transmitters (UARTs), SPI master and slave, and wireless Development Kits PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Development Kits are available online from and through a growing number of regional and global distributors, which PSoC Designer Software Subsystems include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Design Entry Training In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use Free PSoC technical training (on demand, webinars, and the PSoC blocks, which are called user modules. Examples of workshops), which is available online via www.cypress.com, user modules are ADCs, DACs, amplifiers, and filters. Configure covers a wide variety of topics and skill levels to assist you in the user modules for your chosen application and connect them your designs. to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you CYPros Consultants can use to program your application. Certified PSoC consultants offer everything from technical The tool also supports easy development of multiple assistance to completed PSoC designs. To contact or become a configurations and dynamic reconfiguration. Dynamic PSoC consultant go to the CYPros Consultants web site. reconfiguration makes it possible to change configurations at run Solutions Library time. In essence, this allows you to use more than 100 percent of PSoC’s resources for an application. Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and Code Generation Tools hardware design files that enable you to complete your designs The code generation tools work seamlessly within the quickly. PSoCDesigner interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, Technical Support or a combination of the two. Technical support – including a searchable Knowledge Base Assemblers. The assemblers allow you to merge assembly articles and technical forums – is also available online. If you code seamlessly with C code. Link libraries automatically use cannot find an answer to your question, call our Technical absolute addressing or are compiled in relative mode, and are Support hotline at 1-800-541-4736. linked with other software modules to get absolute addressing. Development Tools C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you PSoC Designer™ is the revolutionary integrated design to create complete C programs for the PSoC family devices. The environment (IDE) that you can use to customize PSoC to meet optimizing C compilers provide all of the features of C, tailored your specific application requirements. PSoC Designer software to the PSoC architecture. They come complete with embedded accelerates system design and time to market. Develop your libraries providing port and bus operations, standard keypad and applications using a library of precharacterized analog and digital display support, and extended math functionality. peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the Debugger dynamically generated application programming interface (API) PSoC Designer has a debug environment that provides libraries of code. Finally, debug and test your designs with the hardware in-circuit emulation, allowing you to test the program in integrated debug environment, including in-circuit emulation and a physical system while providing an internal view of the PSoC standard software debug features. PSoC Designer includes: device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, Document Number: 38-08036 Rev. *N Page 5 of 45

CY7C64215 and provide program run, halt, and step control. The debugger precise configuration to your particular application. For example, also allows you to create a trace buffer of registers and memory a PWM User Module configures one or more locations of interest. digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and Online Help System duty cycle. Configure the parameters and properties to The online help system displays online, context-sensitive help. correspond to your chosen application. Enter values directly or Designed for procedural and quick reference, each functional by selecting values from drop-down menus. All the user modules subsystem has its own context-sensitive help. This system also are documented in datasheets that may be viewed directly in provides tutorials and links to FAQs and an online support Forum PSoC Designer or on the Cypress website. These user module to aid the designer. datasheets explain the internal operation of the User Module and provide performance specifications. Each datasheet describes In-Circuit Emulator the use of each user module parameter, and other information A low-cost, high-functionality in-circuit emulator (ICE) is you may need to successfully implement your design. available for development support. This hardware can program Organize and Connect single devices. The emulator consists of a base unit that connects to the PC You build signal chains at the chip level by interconnecting user using a USB port. The base unit is universal and operates with modules to each other and the I/O pins. You perform the all PSoC devices. Emulation pods for each device family are selection, configuration, and routing so that you have complete available separately. The emulation pod takes the place of the control over all on-chip resources. PSoC device in the target board and performs full-speed Generate, Verify, and Debug (24 MHz) operation. When you are ready to test the hardware configuration or move Designing with PSoC Designer on to developing code for the project, you perform the "Generate Configuration Files" step. This causes PSoC Designer to The development process for the PSoC device differs from that generate source code that automatically configures the device to of a traditional fixed function microprocessor. The configurable your specification and provides the software for the system. The analog and digital hardware blocks give the PSoC architecture a generated code provides application programming interfaces unique flexibility that pays dividends in managing specification (APIs) with high-level functions to control and respond to change during development and by lowering inventory costs. hardware events at run time and interrupt service routines that These configurable resources, called PSoC Blocks, have the you can adapt as needed. ability to implement a wide variety of user-selectable functions. A complete code development environment allows you to The PSoC development process can be summarized in the develop and customize your applications in C, assembly following four steps: language, or both. 1.Select User Modules The last step in the development process takes place inside 2.Configure User Modules PSoC Designer's Debugger (access by clicking the Connect 3.Organize and Connect icon). PSoC Designer downloads the HEX image to the ICE 4.Generate, Verify, and Debug where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In Select Components addition PSoC Designer provides a library of pre-built, pre-tested to traditional single-step, run-to-breakpoint and watch-variable hardware peripheral components called “user modules”. User features, the debug interface provides a large trace buffer and modules make selecting and implementing peripheral devices, allows you to define complex breakpoint events that include both analog and digital, simple. monitoring address and data bus values, memory locations and external signals. Configure Components Each of the User Modules you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their Document Number: 38-08036 Rev. *N Page 6 of 45

CY7C64215 Pin Information 56-Pin Part Pinout The CY7C64215 enCoRe III device is available in a 56-pin package which is listed and illustrated in the following table. Every port pin (labeled “P”) is capable of digital I/O. However, V and V are not capable of digital I/O. SS DD Table 2. 56-Pin Part Pinout (QFN-MLF SAWN)[1] Pin Type Figure 3. CY7C64215 56-Pin enCoRe III Device Name Description No. Digital Analog 1 I/O I, M P2[3] Direct switched capacitor block input. M M 2345 IIII////OOOO I,MMM M PPPP2444[[[[1753]]]] Direct switched capacitor block input. P2[5], MP2[7], MP0[1], A, I, MP0[3], A, IO, P0[5], A, IO, P0[7], A, I, MVSSVDDP0[6], A, I, MP0[4], A, I, MP0[2], A, I, MP0[0], A, I, M P2[6], MP2[4], M 6 I/O M P4[1] 7 I/O M P3[7] A, I, M, P2[3] 1 56555453 5251504948474645 444342 P2[2], A, I, M 8 I/O M P3[5] A, I, M, P2[1] 2 41 P2[0], A, I, M 9 I/O M P3[3] M, P4[7] 3 40 P4[6], M 10 I/O M P3[1] M, P4[5] 4 39 P4[4], M 11 I/O M P5[7] M, P4[3] 5 38 P4[2], M M, P4[1] 6 37 P4[0], M 12 I/O M P5[5] M, P3[7] 7 QFN-MLF 36 P3[6], M 13 I/O M P5[3] M, P3[5] 8 (Top View) 35 P3[4], M 14 I/O M P5[1] M, P3[3] 9 34 P3[2], M 15 I/O M P1[7] I2C serial clock (SCL). M, P3[1] 10 33 P3[0], M 16 I/O M P1[5] I2C serial data (SDA). M, P5[7] 11 32 P5[6], M 17 I/O M P1[3] M, P5[5] 12 31 P5[4], M 18 I/O M P1[1] I2C SCL, ISSP-SCLK. M, P5[3] 13 30 P5[2], M 19 Power VSS Ground connection. M, P5[1] 141516 1718192021222324 2526272829 P5[0], M 20 USB D+ 222123 I/OPUoSwBer PVD7D[-7D] Supply voltage. CL, P1[7]DA, P1[5] M, P1[3]CL, P1[1]VssD+D-VDDP7[7]P7[0] DA, P1[0]M, P1[2]M, P1[4]M, P1[6] 24 I/O P7[0] C SC S C S C S 2256 II//OO MM PP11[[02]] I2C SDA, ISSP-SDATA. M, I2M, I2 M, I2 M, I2 27 I/O M P1[4] Optional external clock input EXTCLK. 28 I/O M P1[6] 29 I/O M P5[0] Pin Type Name Description 30 I/O M P5[2] No. Digital Analog 31 I/O M P5[4] 44 I/O M P2[6] External voltage reference (VREF) input. 32 I/O M P5[6] 45 I/O I, M P0[0] Analog column mux input. 33 I/O M P3[0] 46 I/O I, M P0[2] Analog column mux input and column output. 34 I/O M P3[2] 47 I/O I, M P0[4] Analog column mux input and column output. 35 I/O M P3[4] 48 I/O I, M P0[6] Analog column mux input. 36 I/O M P3[6] 49 Power V Supply voltage. DD 37 I/O M P4[0] 50 Power VSS Ground connection. 38 I/O M P4[2] 51 I/O I, M P0[7] Analog column mux input. 39 I/O M P4[4] 52 I/O I/O, M P0[5] Analog column mux input and column output 40 I/O M P4[6] 53 I/O I/O, M P0[3] Analog column mux input and column output. 41 I/O I, M P2[0] Direct switched capacitor block input. 54 I/O I, M P0[1] Analog column mux input. 42 I/O I, M P2[2] Direct switched capacitor block input. 55 I/O M P2[7] 43 I/O M P2[4] External analog ground (AGND) input. 56 I/O M P2[5] LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. Note 1. The center pad on the QFN-MLF package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. Document Number: 38-08036 Rev. *N Page 7 of 45

CY7C64215 28-Pin Part Pinout The CY7C64215 enCoRe III device is available in a 28-pin package which is listed and illustrated in the following table. Every port pin (labeled with a “P”) is capable of digital I/O. However, V and V are not capable of digital I/O. SS DD Table 3. 28-Pin Part Pinout (SSOP) Pin Type Figure 4. CY7C64215 28-Pin enCoRe III Device Name Description No. Digital Analog 1 Power GND Ground connection. 2 I/O I, M P0[7] Analog column mux input. Vss 1 28 VVdDdD 3 I/O I/O,M P0[5] Analog column mux input and column output. AI, P0[7] 2 27 P0[6], AI 4 I/O I/O,M P0[3] Analog column mux input and column output. AIO, P0[5] 3 26 P0[4], AI 5 I/O I,M P0[1] Analog column mux input. AIO, P0[3] 4 25 P0[2], AI 6 I/O M P2[5] AI, P0[1] 5 24 P0[0], AI 7 I/O M P2[3] Direct switched capacitor block input. P2[5] 6 23 P2[4] 8 I/O M P2[1] Direct switched capacitor block input. AI, P2[3] 7 SSOP 22 P2[2], AI 9 I/O M P1[7] I2C SCL AI, P2[1] 8 21 P2[0], AI 10 I/O M P1[5] I2C SDA I2C SCL, P1[7] 9 20 P1[6] 11 I/O M P1[3] I2C SDA, P1[5] 10 19 P1[4] 12 I/O M P1[1] I2C SCL, ISSP-SCLK. P1[3] 11 18 P1[2] 13 Power GND Ground connection. I2C SCL, P1[1] 12 17 P1[0], I2C SDA 14 USB D+ Vss 13 16 VVdDdD 15 USB D- D+ 14 15 D- 16 Power V Supply voltage. DD 17 I/O M P1[0] I2C SCL, ISSP-SDATA. 18 I/O M P1[2] 19 I/O M P1[4] 20 I/O M P1[6] 21 I/O M P2[0] Direct switched capacitor block input. 22 I/O M P2[2] Direct switched capacitor block input. 23 I/O M P2[4] External analog ground (AGND) input. 24 I/O M P0[0] Analog column mux input. 25 I/O M P0[2] Analog column mux input and column output. 26 I/O M P0[4] Analog column mux input and column output. 27 I/O M P0[6] Analog column mux input. 28 Power V Supply voltage. DD LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. Document Number: 38-08036 Rev. *N Page 8 of 45

CY7C64215 Register Reference Register Mapping Tables The register conventions specific to this section are listed in the following table. The enCoRe III device has a total register address space of 512 bytes. The register space is referred to as I/O space and is Table 4. Register Conventions divided into two banks, bank 0 and bank 1. The XOI bit in the Flag register (CPU_F) determines which bank the user is Convention Description currently in. When the XOI bit is set to ‘1’, the user is in bank 1. R Read register or bit(s) Note In the following register mapping tables, blank fields are W Write register or bit(s) reserved and should not be accessed. L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific Document Number: 38-08036 Rev. *N Page 9 of 45

CY7C64215 Register Map Bank 0 Table: User Space Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access PRT0DR 00 RW PMA0_DR 40 RW ASC10CR0 80 RW C0 PRT0IE 01 RW PMA1_DR 41 RW ASC10CR1 81 RW C1 PRT0GS 02 RW PMA2_DR 42 RW ASC10CR2 82 RW C2 PRT0DM2 03 RW PMA3_DR 43 RW ASC10CR3 83 RW C3 PRT1DR 04 RW PMA4_DR 44 RW ASD11CR0 84 RW C4 PRT1IE 05 RW PMA5_DR 45 RW ASD11CR1 85 RW C5 PRT1GS 06 RW PMA6_DR 46 RW ASD11CR2 86 RW C6 PRT1DM2 07 RW PMA7_DR 47 RW ASD11CR3 87 RW C7 PRT2DR 08 RW USB_SOF0 48 R 88 C8 PRT2IE 09 RW USB_SOF1 49 R 89 C9 PRT2GS 0A RW USB_CR0 4A RW 8A CA PRT2DM2 0B RW USBIO_CR0 4B # 8B CB PRT3DR 0C RW USBIO_CR1 4C RW 8C CC PRT3IE 0D RW 4D 8D CD PRT3GS 0E RW EP1_CNT1 4E # 8E CE PRT3DM2 0F RW EP1_CNT 4F RW 8F CF PRT4DR 10 RW EP2_CNT1 50 # ASD20CR0 90 RW CUR_PP D0 RW PRT4IE 11 RW EP2_CNT 51 RW ASD20CR1 91 RW STK_PP D1 RW PRT4GS 12 RW EP3_CNT1 52 # ASD20CR2 92 RW D2 PRT4DM2 13 RW EP3_CNT 53 RW ASD20CR3 93 RW IDX_PP D3 RW PRT5DR 14 RW EP4_CNT1 54 # ASC21CR0 94 RW MVR_PP D4 RW PRT5IE 15 RW EP4_CNT 55 RW ASC21CR1 95 RW MVW_PP D5 RW PRT5GS 16 RW EP0_CR 56 # ASC21CR2 96 RW I2C_CFG D6 RW PRT5DM2 17 RW EP0_CNT 57 # ASC21CR3 97 RW I2C_SCR D7 # 18 EP0_DR0 58 RW 98 I2C_DR D8 RW 19 EP0_DR1 59 RW 99 I2C_MSCR D9 # 1A EP0_DR2 5A RW 9A INT_CLR0 DA RW 1B EP0_DR3 5B RW 9B INT_CLR1 DB RW PRT7DR 1C RW EP0_DR4 5C RW 9C INT_CLR2 DC RW PRT7IE 1D RW EP0_DR5 5D RW 9D INT_CLR3 DD RW PRT7GS 1E RW EP0_DR6 5E RW 9E INT_MSK3 DE RW PRT7DM2 1F RW EP0_DR7 5F RW 9F INT_MSK2 DF RW DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW DBB00DR1 21 W AMUXCFG 61 RW A1 INT_MSK1 E1 RW DBB00DR2 22 RW 62 A2 INT_VC E2 RC DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW DCB02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W DCB02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W DCB02DR2 2A RW 6A MUL1_DH AA R MUL0_DH EA R DCB02CR0 2B # 6B MUL1_DL AB R MUL0_DL EB R DCB03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW DCB03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW DCB03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW DCB03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW 30 ACB00CR3 70 RW RDI0RI B0 RW F0 31 ACB00CR0 71 RW RDI0SYN B1 RW F1 32 ACB00CR1 72 RW RDI0IS B2 RW F2 33 ACB00CR2 73 RW RDI0LT0 B3 RW F3 34 ACB01CR3 74 RW RDI0LT1 B4 RW F4 35 ACB01CR0 75 RW RDI0RO0 B5 RW F5 36 ACB01CR1 76 RW RDI0RO1 B6 RW F6 37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD DAC_D FD RW 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF # Blank fields are Reserved and should not be accessed. # Access is bit specific. Document Number: 38-08036 Rev. *N Page 10 of 45

CY7C64215 Register Map Bank 1 Table: Configuration Space Addr Addr Addr Addr Name Access Name Access Name Access Name Access (1,Hex) (1,Hex) (1,Hex) (1,Hex) PRT0DM0 00 RW PMA0_WA 40 RW ASC10CR0 80 RW USBIO_CR2 C0 RW PRT0DM1 01 RW PMA1_WA 41 RW ASC10CR1 81 RW USB_CR1 C1 # PRT0IC0 02 RW PMA2_WA 42 RW ASC10CR2 82 RW PRT0IC1 03 RW PMA3_WA 43 RW ASC10CR3 83 RW PRT1DM0 04 RW PMA4_WA 44 RW ASD11CR0 84 RW EP1_CR0 C4 # PRT1DM1 05 RW PMA5_WA 45 RW ASD11CR1 85 RW EP2_CR0 C5 # PRT1IC0 06 RW PMA6_WA 46 RW ASD11CR2 86 RW EP3_CR0 C6 # PRT1IC1 07 RW PMA7_WA 47 RW ASD11CR3 87 RW EP4_CR0 C7 # PRT2DM0 08 RW 48 88 C8 PRT2DM1 09 RW 49 89 C9 PRT2IC0 0A RW 4A 8A CA PRT2IC1 0B RW 4B 8B CB PRT3DM0 0C RW 4C 8C CC PRT3DM1 0D RW 4D 8D CD PRT3IC0 0E RW 4E 8E CE PRT3IC1 0F RW 4F 8F CF PRT4DM0 10 RW PMA0_RA 50 RW 90 GDI_O_IN D0 RW PRT4DM1 11 RW PMA1_RA 51 RW ASD20CR1 91 RW GDI_E_IN D1 RW PRT4IC0 12 RW PMA2_RA 52 RW ASD20CR2 92 RW GDI_O_OU D2 RW PRT4IC1 13 RW PMA3_RA 53 RW ASD20CR3 93 RW GDI_E_OU D3 RW PRT5DM0 14 RW PMA4_RA 54 RW ASC21CR0 94 RW D4 PRT5DM1 15 RW PMA5_RA 55 RW ASC21CR1 95 RW D5 PRT5IC0 16 RW PMA6_RA 56 RW ASC21CR2 96 RW D6 PRT5IC1 17 RW PMA7_RA 57 RW ASC21CR3 97 RW D7 18 58 98 MUX_CR0 D8 RW 19 59 99 MUX_CR1 D9 RW 1A 5A 9A MUX_CR2 DA RW 1B 5B 9B MUX_CR3 DB RW PRT7DM0 1C RW 5C 9C DC PRT7DM1 1D RW 5D 9D OSC_GO_EN DD RW PRT7IC0 1E RW 5E 9E OSC_CR4 DE RW PRT7IC1 1F RW 5F 9F OSC_CR3 DF RW DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW 23 AMD_CR0 63 RW A3 VLT_CR E3 RW DBB01FN 24 RW CMP_GO_EN 64 RW A4 VLT_CMP E4 R DBB01IN 25 RW 65 RW A5 E5 DBB01OU 26 RW AMD_CR1 66 RW A6 E6 27 ALT_CR0 67 RW A7 E7 DCB02FN 28 RW 68 A8 IMO_TR E8 W DCB02IN 29 RW 69 A9 ILO_TR E9 W DCB02OU 2A RW 6A AA BDG_TR EA RW 2B 6B AB ECO_TR EB W DCB03FN 2C RW TMP_DR0 6C RW AC MUX_CR4 EC RW DCB03IN 2D RW TMP_DR1 6D RW AD MUX_CR5 ED RW DCB03OU 2E RW TMP_DR2 6E RW AE EE 2F TMP_DR3 6F RW AF EF 30 ACB00CR3 70 RW RDI0RI B0 RW F0 31 ACB00CR0 71 RW RDI0SYN B1 RW F1 32 ACB00CR1 72 RW RDI0IS B2 RW F2 33 ACB00CR2 73 RW RDI0LT0 B3 RW F3 34 ACB01CR3 74 RW RDI0LT1 B4 RW F4 35 ACB01CR0 75 RW RDI0RO0 B5 RW F5 36 ACB01CR1 76 RW RDI0RO1 B6 RW F6 37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD DAC_CR FD RW 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF # Blank fields are Reserved and should not be accessed. # Access is bit specific. Document Number: 38-08036 Rev. *N Page 11 of 45

CY7C64215 Electrical Specifications This section presents the DC and AC electrical specifications of the CY7C64215 enCoRe III. For the most up-to-date electrical specifications, confirm that you have the most recent datasheet by going to the web at http://www.cypress.com/go/usb. Specifications are valid for –40°C < T < 85°C and T < 100°C, except where noted. Specifications for devices running at greater A J than 12 MHz are valid for –40°C < T < 70°C and T < 82°C. A J Figure 5. Voltage versus CPU Frequency 5.25 Valid Operating Region 4.75 V) 4.35 e ( [2] g a Valid Operating Region olt V d 3.50 d V Valid Operating Region 3.15 93 kHz 12 MHz 24 MHz CPU Frequency Note 2. This is a valid operating region for the CPU, but USB hardware is non functional in the voltage range from 3.50 V to 4.35 V. Document Number: 38-08036 Rev. *N Page 12 of 45

CY7C64215 Absolute Maximum Ratings Table 5. Absolute Maximum Ratings Parameter Description Min Typ Max Unit Notes T Storage temperature –55 – +100 °C Higher storage temperatures STG reduces data retention time. T Bake temperature – 125 See °C – BAKETEMP package label T Bake time See – 72 Hours – BAKETIME package label T Ambient temperature with power applied 0 – +70 °C – A V Supply voltage on V relative to V –0.5 – +6.0 V – DD DD SS V DC input voltage V – 0.5 – V + 0.5 V – IO SS DD V DC voltage applied to tristate V – 0.5 – V + 0.5 V – IO2 SS DD I Maximum current into any port pin –25 – +50 mA – MIO I Maximum current into any port pin –50 – +50 mA – MAIO configured as an analog driver ESD Electrostatic discharge voltage 2000 – – V Human body model ESD. LU Latch up current – – 200 mA – Operating Temperature Table 6. Operating Temperature Parameter Description Min Typ Max Unit Notes T Commercial ambient temperature 0 – +70 °C – AC T Industrial ambient temperature –40 – +85 °C USB operation requires the AI use of an external clock oscillator and the 56-pin QFN package. T Junction temperature –40 – +100 °C The temperature rise from J ambient to junction is package specific. See “Thermal Impedance” on page32. The user must limit the power consumption to comply with this requirement. Document Number: 38-08036 Rev. *N Page 13 of 45

CY7C64215 DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V and 3.3V at 25°C A A and are for design guidance only. Table 7. DC Chip-Level Specifications Parameter Description Min Typ Max Unit Notes V Supply voltage 3.0 – 5.25 V See DC POR and LVD specifications, DD Table 15 on page 22. USB hardware is not functional when V is between 3.5V to DD 4.35V. I Supply current, IMO = 24 MHz (5 V) – 14 27 mA Conditions are V = 5.0 V, T = 25°C, DD5 DD A CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. I Supply current, IMO = 24 MHz (3.3 V) – 8 14 mA Conditions are V = 3.3 V, T = 25°C, DD3 DD A CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz, analog power = off. I Sleep [3] (mode) current with POR, LVD, – 3 6.5 A Conditions are with internal slow speed SB sleep timer, and WDT [4]. oscillator, V = 3.3 V, 0°C < T < 55°C, DD A analog power = off. I Sleep (mode) current with POR, LVD, sleep – 4 25 A Conditions are with internal slow speed SBH timer, and WDT at high temperature [4] . oscillator, V = 3.3 V, 55°C < T < 70°C, DD A analog power = off. Notes 3. Errata: When the device operates at4.75 V to 5.25 V and the 3.3-V regulator is enabled, a short low pulse may be created on the DP signal line during device wakeup. The 15- to 20-µs low pulse of the DP line may be interpreted by the host computer as a deattach or the beginning of a wakeup. For more details refer to Errata on page 40. 4. Standby current includes all functions (POR, LVD, WDT, sleep time) needed for reliable system operation. This should be compared with devices that have similar functions enabled. Document Number: 38-08036 Rev. *N Page 14 of 45

CY7C64215 DC GPIO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C A A and are for design guidance only. Table 8. DC GPIO Specifications Parameter Description Min Typ Max Unit Notes R Pull-up resistor 4 5.6 8 k – PU R Pull-down resistor 4 5.6 8 k – PD V High output level V – 1.0 – – V I = 10 mA, V = 4.75 to 5.25 V (8 total OH DD OH DD loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined I budget. OH V Low output level – – 0.75 V I = 25 mA, V = 4.75 to 5.25 V (8 total OL OL DD loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined I budget. OL I High-level source current 10 – – mA – OH I Low-level sink current 25 – – mA – OL V Input low level – – 0.8 V V = 3.15 to 5.25. IL DD V Input high level 2.1 – V V = 3.15 to 5.25. IH DD V Input hysteresis – 60 – mV – H I Input leakage (absolute value) – 1 – nA Gross tested to 1 A. IL C Capacitive load on pins as input – 3.5 10 pF Package and pin dependent. IN Temp = 25°C. C Capacitive load on pins as output – 3.5 10 pF Package and pin dependent. OUT Temp = 25°C. DC Full-Speed USB Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges when the IMO is selected as system clock: 4.75 V to 5.25 V and 0°C < T < 70°C, or 3.15 V to 3.5 V and 0°C < T < 70°C, respectively. A A The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges when an external clock is selected as the system clock: 4.75 V to 5.25 V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C. A A Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Table 9. DC Full Speed (12 Mbps) USB Specifications Parameter Description Min Typ Max Unit Notes USB Interface V Differential input sensitivity 0.2 – – V | (D+) – (D–) | DI V Differential input common mode range 0.8 – 2.5 V – CM V Single-ended receiver threshold 0.8 – 2.0 V – SE C Transceiver capacitance – – 20 pF – IN I High Z state data line leakage –10 – 10 A 0 V < V < 3.3 V. IO IN R External USB series resistor 23 – 25  In series with each USB pin. EXT V Static output high, driven 2.8 – 3.6 V 15 k ± 5% to ground. Internal pull-up UOH enabled. V Static output high, idle 2.7 – 3.6 V 15 k ± 5% to ground. Internal pull-up UOHI enabled. V Static output low – – 0.3 V 15 k ± 5% to ground. Internal pull-up UOL enabled. Z USB driver output impedance 28 – 44  Including R resistor. O EXT V D+/D– crossover voltage 1.3 – 2.0 V – CRS Document Number: 38-08036 Rev. *N Page 15 of 45

CY7C64215 DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C A A and are for design guidance only. Table 10. 5 V DC Analog Output Buffer Specifications Parameter Description Min Typ Max Unit Notes C Load Capacitance – – 200 pF This specification applies to the L external circuit that is being driven by the analog output buffer. V Input offset voltage (absolute value) – 3 12 mV – OSOB TCV Average input offset voltage drift – +6 – V/°C – OSOB V Common mode input voltage range 0.5 – V – 1.0 V – CMOB DD R Output resistance – OUTOB Power = low – 0.6 – W Power = high – 0.6 – W V High output voltage swing – OHIGHOB (Load = 32 ohms to V /2) DD Power = low 0.5 × V + 1.1 – – V DD Power = high 0.5 × V + 1.1 – – V DD V Low output voltage swing – OLOWOB (Load = 32 ohms to V /2) DD Power = low – – 0.5 × V – 1.3 V DD Power = high – – 0.5 × V – 1.3 V DD I Supply current including bias cell (no load) – SOB Power = low – 1.1 5.1 mA Power = high – 2.6 8.8 mA PSRR Supply voltage rejection ratio 53 64 – dB (0.5 × V – 1.3) < V < (V OB DD OUT DD – 2.3). Table 11. 3.3 V DC Analog Output Buffer Specifications Parameter Description Min Typ Max Unit Notes C Load Capacitance – – 200 pF This specification applies to the L external circuit that is being driven by the analog output buffer. V Input offset voltage (absolute value) – 3 12 mV – OSOB TCV Average input offset voltage drift – +6 – V/°C – OSOB V Common mode input voltage range 0.5 - V – 1.0 V – CMOB DD R Output resistance – OUTOB Power = low – 1 – W Power = high – 1 – W V High output voltage swing – OHIGHOB (Load = 1 K to V /2) DD Power = low 0.5 × V + 1.0 – – V DD Power = high 0.5 × V + 1.0 – – V DD V Low output voltage swing – OLOWOB (Load = 1 K to V /2) DD Power = low – – 0.5 × V – 1.0 V DD Power = high – – 0.5 × V – 1.0 V DD I Supply current including bias cell (no – SOB load) Power = low 0.8 2.0 mA Power = high – 2.0 4.3 mA PSRR Supply voltage rejection ratio 34 64 – dB (0.5 × V – 1.0) < V < (0.5 OB DD OUT × V + 0.9). DD Document Number: 38-08036 Rev. *N Page 16 of 45

CY7C64215 DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40 °C < T < 85 °C, or 3.15 V to 3.5 V and –40 °C < T < 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C A A and are for design guidance only. The guaranteed specifications are measured through the analog continuous time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 12. 5-V DC Analog Reference Specifications Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b000 RefPower = high V Ref High V /2 + Bandgap V /2 + 1.229 V /2 + 1.290 V /2 + 1.346 V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.038 V /2 V /2 + 0.040 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.356 V /2 – 1.295 V /2 – 1.218 V REFLO DD DD DD DD RefPower = high V Ref High V /2 + Bandgap V /2 + 1.220 V /2 + 1.292 V /2 + 1.348 V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.036 V /2 V /2 + 0.036 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.357 V /2 – 1.297 V /2 – 1.225 V REFLO DD DD DD DD RefPower = medium V Ref High V /2 + Bandgap V /2 + 1.221 V /2 + 1.293 V /2 + 1.351 V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.036 V /2 V /2 + 0.036 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.357 V /2 – 1.298 V /2 – 1.228 V REFLO DD DD DD DD RefPower = medium V Ref High V /2 + Bandgap V /2 + 1.219 V /2 + 1.293 V /2 + 1.353 V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.037 V /2 – 0.001 V /2 + 0.036 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.359 V /2 – 1.299 V /2 – 1.229 V REFLO DD DD DD DD 0b001 RefPower = high V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = high V /2, P2[6] = 1.3 V) 0.092 0.011 0.064 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 1.3 V) 0.031 0.007 0.056 DD RefPower = high V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = low V /2, P2[6] = 1.3 V) 0.078 0.008 0.063 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 1.3 V) 0.031 0.004 0.043 DD RefPower = medium V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = high V /2, P2[6] = 1.3 V) 0.073 0.006 0.062 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 1.3 V) 0.032 0.003 0.038 DD RefPower = medium V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = low V /2, P2[6] = 1.3 V) 0.073 0.006 0.062 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 1.3 V) 0.034 0.002 0.037 DD Document Number: 38-08036 Rev. *N Page 17 of 45

CY7C64215 Table 12. 5-V DC Analog Reference Specifications (continued) Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b010 RefPower = high V Ref High V V – 0.037 V – 0.007 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.036 V /2 – 0.001 V /2 + 0.036 V AGND DD DD DD DD V Ref Low V V V + 0.005 V + 0.029 V REFLO SS SS SS SS RefPower = high V Ref High V V – 0.034 V – 0.006 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.036 V /2 – 0.001 V /2 + 0.035 V AGND DD DD DD DD V Ref Low V V V + 0.004 V + 0.024 V REFLO SS SS SS SS RefPower = medium V Ref High V V – 0.032 V – 0.005 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.036 V /2 – 0.001 V /2 + 0.035 V AGND DD DD DD DD V Ref Low V V V + 0.003 V + 0.022 V REFLO SS SS SS SS RefPower = medium V Ref High V V – 0.031 V – 0.005 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.037 V /2 – 0.001 V /2 + 0.035 V AGND DD DD DD DD V Ref Low V V V + 0.003 V + 0.020 V REFLO SS SS SS SS 0b011 RefPower = high V Ref High 3 × Bandgap 3.760 3.884 4.006 V REFHI Opamp bias = high V AGND 2 × Bandgap 2.522 2.593 2.669 V AGND V Ref Low Bandgap 1.252 1.299 1.342 V REFLO RefPower = high V Ref High 3 × Bandgap 3.766 3.887 4.010 V REFHI Opamp bias = low V AGND 2 × Bandgap 2.523 2.594 2.670 V AGND V Ref Low Bandgap 1.252 1.297 1.342 V REFLO RefPower = medium V Ref High 3 × Bandgap 3.769 3.888 4.013 V REFHI Opamp bias = high V AGND 2 × Bandgap 2.523 2.594 2.671 V AGND V Ref Low Bandgap 1.251 1.296 1.343 V REFLO RefPower = medium V Ref High 3 × Bandgap 3.769 3.889 4.015 V REFHI Opamp bias = low V AGND 2 × Bandgap 2.523 2.595 2.671 V AGND V Ref Low Bandgap 1.251 1.296 1.344 V REFLO 0b100 RefPower = high V Ref High 2 × Bandgap + P2[6] 2.483 – P2[6] 2.582 – P2[6] 2.674 – P2[6] V REFHI Opamp bias = high (P2[6] = 1.3 V) V AGND 2 × Bandgap 2.522 2.593 2.669 V AGND V Ref Low 2 × Bandgap – P2[6] 2.524 – P2[6] 2.600 – P2[6] 2.676 – P2[6] V REFLO (P2[6] = 1.3 V) RefPower = high V Ref High 2 × Bandgap + P2[6] 2.490 – P2[6] 2.586 – P2[6] 2.679 – P2[6] V REFHI Opamp bias = low (P2[6] = 1.3 V) V AGND 2 × Bandgap 2.523 2.594 2.669 V AGND V Ref Low 2 × Bandgap – P2[6] 2.523 – P2[6] 2.598 – P2[6] 2.675 – P2[6] V REFLO (P2[6] = 1.3 V) RefPower = medium V Ref High 2 × Bandgap + P2[6] 2.493 – P2[6] 2.588 – P2[6] 2.682 – P2[6] V REFHI Opamp bias = high (P2[6] = 1.3 V) V AGND 2 × Bandgap 2.523 2.594 2.670 V AGND V Ref Low 2 × Bandgap – P2[6] 2.523 – P2[6] 2.597 – P2[6] 2.675 – P2[6] V REFLO (P2[6] = 1.3 V) RefPower = medium V Ref High 2 × Bandgap + P2[6] 2.494 – P2[6] 2.589 – P2[6] 2.685 – P2[6] V REFHI Opamp bias = low (P2[6] = 1.3 V) V AGND 2 × Bandgap 2.523 2.595 2.671 V AGND V Ref Low 2 × Bandgap – P2[6] 2.522 – P2[6] 2.596 – P2[6] 2.676 – P2[6] V REFLO (P2[6] = 1.3 V) Document Number: 38-08036 Rev. *N Page 18 of 45

CY7C64215 Table 12. 5-V DC Analog Reference Specifications (continued) Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b101 RefPower = high V Ref High P2[4] + Bandgap P2[4] + 1.218 P2[4] + 1.291 P2[4] + 1.354 V REFHI Opamp bias = high (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.335 P2[4] – 1.294 P2[4] – 1.237 V REFLO (P2[4] = V /2) DD RefPower = high V Ref High P2[4] + Bandgap P2[4] + 1.221 P2[4] + 1.293 P2[4] + 1.358 V REFHI Opamp bias = low (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.337 P2[4] – 1.297 P2[4] – 1.243 V REFLO (P2[4] = V /2) DD RefPower = medium V Ref High P2[4] + Bandgap P2[4] + 1.222 P2[4] + 1.294 P2[4] + 1.360 V REFHI Opamp bias = high (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.338 P2[4] – 1.298 P2[4] – 1.245 V REFLO (P2[4] = V /2) DD RefPower = medium V Ref High P2[4] + Bandgap P2[4] + 1.221 P2[4] + 1.294 P2[4] + 1.362 V REFHI Opamp bias = low (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.340 P2[4] – 1.298 P2[4] – 1.245 V REFLO (P2[4] = V /2) DD 0b110 RefPower = high V Ref High 2 × Bandgap 2.513 2.593 2.672 V REFHI Opamp bias = high V AGND Bandgap 1.264 1.302 1.340 V AGND V Ref Low V V V + 0.008 V + 0.038 V REFLO SS SS SS SS RefPower = high V Ref High 2 × Bandgap 2.514 2.593 2.674 V REFHI Opamp bias = low V AGND Bandgap 1.264 1.301 1.340 V AGND V Ref Low V V V + 0.005 V + 0.028 V REFLO SS SS SS SS RefPower = medium V Ref High 2 × Bandgap 2.514 2.593 2.676 V REFHI Opamp bias = high V AGND Bandgap 1.264 1.301 1.340 V AGND V Ref Low V V V + 0.004 V + 0.024 V REFLO SS SS SS SS RefPower = medium V Ref High 2 × Bandgap 2.514 2.593 2.677 V REFHI Opamp bias = low V AGND Bandgap 1.264 1.300 1.340 V AGND V Ref Low V V V + 0.003 V + 0.021 V REFLO SS SS SS SS 0b111 RefPower = high V Ref High 3.2 × Bandgap 4.028 4.144 4.242 V REFHI Opamp bias = high V AGND 1.6 × Bandgap 2.028 2.076 2.125 V AGND V Ref Low V V V + 0.008 V + 0.034 V REFLO SS SS SS SS RefPower = high V Ref High 3.2 × Bandgap 4.032 4.142 4.245 V REFHI Opamp bias = low V AGND 1.6 × Bandgap 2.029 2.076 2.126 V AGND V Ref Low V V V + 0.005 V + 0.025 V REFLO SS SS SS SS RefPower = medium V Ref High 3.2 × Bandgap 4.034 4.143 4.247 V REFHI Opamp bias = high V AGND 1.6 × Bandgap 2.029 2.076 2.126 V AGND V Ref Low V V V + 0.004 V + 0.021 V REFLO SS SS SS SS RefPower = medium V Ref High 3.2 × Bandgap 4.036 4.144 4.249 V REFHI Opamp bias = low V AGND 1.6 × Bandgap 2.029 2.076 2.126 V AGND V Ref Low V V V + 0.003 V + 0.019 V REFLO SS SS SS SS Document Number: 38-08036 Rev. *N Page 19 of 45

CY7C64215 Table 13. 3.3-V DC Analog Reference Specifications Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b000 RefPower = high V Ref High V /2 + Bandgap V /2 + 1.200 V /2 + 1.290 V /2 + 1.365 V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.030 V /2 V /2 + 0.034 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.346 V /2 – 1.292 V /2 – 1.208 V REFLO DD DD DD DD RefPower = high V Ref High V /2 + Bandgap V /2 + 1.196 V /2 + 1.292 V /2 + 1.374 V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.029 V /2 V /2 + 0.031 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.349 V /2 – 1.295 V /2 – 1.227 V REFLO DD DD DD DD RefPower = medium V Ref High V /2 + Bandgap V /2 + 1.204 V /2 + 1.293 V /2 + 1.369 V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.030 V /2 V /2 + 0.030 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.351 V /2 – 1.297 V /2 – 1.229 V REFLO DD DD DD DD RefPower = medium V Ref High V /2 + Bandgap V /2 + 1.189 V /2 + 1.294 V /2 + 1.384 V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.032 V /2 V /2 + 0.029 V AGND DD DD DD DD V Ref Low V /2 – Bandgap V /2 – 1.353 V /2 – 1.297 V /2 – 1.230 V REFLO DD DD DD DD 0b001 RefPower = high V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = high V /2, P2[6] = 0.5 V) 0.105 0.008 0.095 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) 0.035 0.006 0.053 DD RefPower = high V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = low V /2, P2[6] = 0.5 V) 0.094 0.005 0.073 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) 0.033 0.002 0.042 DD RefPower = medium V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = high V /2, P2[6] = 0.5 V) 0.094 0.003 0.075 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) 0.035 0.038 DD RefPower = medium V Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + V REFHI Opamp bias = low V /2, P2[6] = 0.5 V) 0.095 0.003 0.080 DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] P2[4] – P2[6] + V REFLO V /2, P2[6] = 0.5 V) 0.038 0.038 DD 0b010 RefPower = high V Ref High V V – 0.119 V – 0.005 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.028 V /2 V /2 + 0.029 V AGND DD DD DD DD V Ref Low V V V + 0.004 V + 0.022 V REFLO SS SS SS SS RefPower = high V Ref High V V – 0.131 V – 0.004 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.028 V /2 V /2 + 0.028 V AGND DD DD DD DD V Ref Low V V V + 0.003 V + 0.021 V REFLO SS SS SS SS RefPower = medium V Ref High V V – 0.111 V – 0.003 V V REFHI DD DD DD DD Opamp bias = high V AGND V /2 V /2 – 0.029 V /2 V /2 + 0.028 V AGND DD DD DD DD V Ref Low V V V + 0.002 V + 0.017 V REFLO SS SS SS SS RefPower = medium V Ref High V V – 0.128 V – 0.003 V V REFHI DD DD DD DD Opamp bias = low V AGND V /2 V /2 – 0.029 V /2 V /2 + 0.029 V AGND DD DD DD DD V Ref Low V V V + 0.002 V + 0.019 V REFLO SS SS SS SS 0b011 All power settings. – – – – – – – Not allowed for 3.3 V. Document Number: 38-08036 Rev. *N Page 20 of 45

CY7C64215 Table 13. 3.3-V DC Analog Reference Specifications (continued) Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units Settings [5:3] 0b100 All power settings. – – – – – – – Not allowed for 3.3 V. 0b101 RefPower = high V Ref High P2[4] + Bandgap P2[4] + 1.214 P2[4] + 1.291 P2[4] + 1.359 V REFHI Opamp bias = high (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.335 P2[4] – 1.292 P2[4] – 1.200 V REFLO (P2[4] = V /2) DD RefPower = high V Ref High P2[4] + Bandgap P2[4] + 1.219 P2[4] + 1.293 P2[4] + 1.357 V REFHI Opamp bias = low (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.335 P2[4] – 1.295 P2[4] – 1.243 V REFLO (P2[4] = V /2) DD RefPower = medium V Ref High P2[4] + Bandgap P2[4] + 1.222 P2[4] + 1.294 P2[4] + 1.356 V REFHI Opamp bias = high (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.337 P2[4] – 1.296 P2[4] – 1.244 V REFLO (P2[4] = V /2) DD RefPower = medium V Ref High P2[4] + Bandgap P2[4] + 1.224 P2[4] + 1.295 P2[4] + 1.355 V REFHI Opamp bias = low (P2[4] = V /2) DD V AGND P2[4] P2[4] P2[4] P2[4] – AGND V Ref Low P2[4] – Bandgap P2[4] – 1.339 P2[4] – 1.297 P2[4] – 1.244 V REFLO (P2[4] = V /2) DD 0b110 RefPower = high V Ref High 2 × Bandgap 2.510 2.595 2.655 V REFHI Opamp bias = high V AGND Bandgap 1.276 1.301 1.332 V AGND V Ref Low V V V + 0.006 V + 0.031 V REFLO SS SS SS SS RefPower = high V Ref High 2 × Bandgap 2.513 2.594 2.656 V REFHI Opamp bias = low V AGND Bandgap 1.275 1.301 1.331 V AGND V Ref Low V V V + 0.004 V + 0.021 V REFLO SS SS SS SS RefPower = medium V Ref High 2 × Bandgap 2.516 2.595 2.657 V REFHI Opamp bias = high V AGND Bandgap 1.275 1.301 1.331 V AGND V Ref Low V V V + 0.003 V + 0.017 V REFLO SS SS SS SS RefPower = medium V Ref High 2 × Bandgap 2.520 2.595 2.658 V REFHI Opamp bias = low V AGND Bandgap 1.275 1.300 1.331 V AGND V Ref Low V V V + 0.002 V + 0.015 V REFLO SS SS SS SS 0b111 All power settings. – – – – – – – Not allowed for 3.3 V. DC Analog enCoRe III Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C A A and are for design guidance only. Table 14. DC Analog enCoRe III Block Specifications Parameter Description Min Typ Max Unit Notes R Resistor unit value (CT) – 12.2 – k – CT C Capacitor unit value (SC) – 80 – fF – SC Document Number: 38-08036 Rev. *N Page 21 of 45

CY7C64215 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V or 3.3 V at 25°C A A and are for design guidance only. Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC® Technical Reference Manual for more information on the VLT_CR register. Table 15. DC POR and LVD Specifications Parameter Description Min Typ Max Unit Notes V value for PPOR trip (positive ramp) – DD V [5] PORLEV[1:0] = 00b 2.91 V PPOR0R V [5] PORLEV[1:0] = 01b – 4.39 – V PPOR1R V [5] PORLEV[1:0] = 10b 4.55 V PPOR2R V value for PPOR trip (negative ramp) – DD V PORLEV[1:0] = 00b 2.82 V PPOR0 V PORLEV[1:0] = 01b – 4.39 – V PPOR1 V PORLEV[1:0] = 10b 4.55 V PPOR2 PPOR hysteresis – V PORLEV[1:0] = 00b – 92 – mV PH0 V PORLEV[1:0] = 01b – 0 – mV PH1 V PORLEV[1:0] = 10b – 0 – mV PH2 V value for LVD trip – DD V VM[2:0] = 000b 2.86 2.92 2.98[6] V LVD0 V VM[2:0] = 001b 2.96 3.02 3.08 V LVD1 V VM[2:0] = 010b 3.07 3.13 3.20 V LVD2 V VM[2:0] = 011b 3.92 4.00 4.08 V LVD3 V VM[2:0] = 100b 4.39 4.48 4.57 V LVD4 V VM[2:0] = 101b 4.55 4.64 4.74[7] V LVD5 V VM[2:0] = 110b 4.63 4.73 4.82 V LVD6 V VM[2:0] = 111b 4.72 4.81 4.91 V LVD7 Notes 5. Errata: When VDD of the device is pulled below ground just before power on, the first read from each 8K Flash page may be corrupted. This issue does not affect Flash page 0 because it is the selected page upon reset. For more details in Errata on page 40. 6. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 7. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. Document Number: 38-08036 Rev. *N Page 22 of 45

CY7C64215 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C A A and are for design guidance only. Table 16. DC Programming Specifications Parameter Description Min Typ Max Unit Notes V V for programming and erase 4.5 5.0 5.5 V This specification applies to the DDP DD functional requirements of external programmer tools V Low V for verify 3.0 3.1 3.2 V This specification applies to the DDLV DD functional requirements of external programmer tools V High V for verify 5.1 5.2 5.3 V This specification applies to the DDHV DD functional requirements of external programmer tools V Supply voltage for flash write operation 3.15 – 5.25 V This specification applies to this DDIWRITE device when it is executing internal flash writes I Supply current during programming or verify – 15 30 mA – DDP V Input low voltage during programming or verify – – 0.8 V – ILP V Input high voltage during programming or Verify 2.1 – – V – IHP I Input current when applying Vilp to P1[0] or – – 0.2 mA Driving internal pull-down resistor. ILP P1[1] during programming or verify I Input current when applying Vihp to P1[0] or – – 1.5 mA Driving internal pull-down resistor. IHP P1[1] during programming or verify V Output low voltage during programming or verify – – V + 0.75 V – OLV SS V Output high voltage during programming or V – 1.0 – V V – OHV DD DD verify Flash Flash endurance (per block) 50,000[8] – – – Erase/write cycles per block. ENPB Flash Flash endurance (total)[9] 1,800,000 – – – Erase/write cycles. ENT Flash Flash data retention 10 – – Years – DR DC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C A A and are for design guidance only. Table 17. DC I2C Specifications [10] Symbol Description Min Typ Max Units Notes V Input low level – – 0.3 × V V 3.15 V V 3.6 V ILI2C DD DD – – 0.25 × V V 4.75 V V 5.25 V DD DD V Input high level 0.7 × V – – V 3.15 V V 5.25 V IHI2C DD DD Notes 8. The 50,000 cycle Flash endurance per block will only be guaranteed if the Flash is operating within one voltage range. Voltage ranges are 3.0V to 3.6V and 4.75V to 5.25V. 9. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs application note AN2015 for more information. 10.All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the mentioned specifications. Document Number: 38-08036 Rev. *N Page 23 of 45

CY7C64215 AC Electrical Characteristics AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C A A and are for design guidance only. Table 18. AC Chip-Level Specifications Parameter Description Min Typ Max Unit Notes F IMO frequency for 24 MHz (5 V) 23.04 24 24.96[11, 12] MHz Trimmed for 5 V operation using factory IMO245V trim values. F IMO frequency for 24 MHz (3.3 V) 22.08 24 25.92[11,13] MHz Trimmed for 3.3 V operation using IMO243V factory trim values. F IMO frequency with USB frequency locking 23.94 24 24.06[12] MHz USB operation for system clock IMOUSB enabled and USB traffic present source from the IMO is limited to 0°C < T < 70°C. A F CPU frequency (5 V nominal) 0.090 24 24.96[11,12] MHz SLIMO mode = 0. CPU1 F CPU frequency (3.3 V nominal) 0.086 12 12.96[12,13] MHz SLIMO mode = 0. CPU2 F Digital PSoC block frequency 0 48 49.92[11,12,14] MHz Refer to the AC Digital Block Specifica- BLK5 (5 V nominal) tions on page 26. F Digital PSoC block frequency 0 24 25.92[12,14] MHz – BLK3 (3.3 V nominal) F ILO frequency 15 32 64 kHz – 32K1 F ILO untrimmed frequency 5 – 100 kHz After a reset and before the M8C 32K_U starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on this timing. DC ILO duty cycle 20 50 80 % – ILO DC 24-MHz duty cycle 40 50 60 % – 24M Step24M 24-MH trim step size – 50 – kHz – Fout48M 48-MHz output frequency 46.08 48.0 49.92[11,13] MHz Trimmed. Utilizing factory trim values. F Maximum frequency of signal on row input – – 12.96 MHz – MAX or row output SR Power supply slew rate – – 250 V/ms – POWER_UP T Time from end of POR to CPU executing – 16 100 ms – POWERUP code T [15] 24 MHz IMO cycle-to-cycle jitter (RMS) – 200 1200 ps jit_IMO 24 MHz IMO long term N cycle-to-cycle jitter – 900 6000 ps N = 32. (RMS) 24 MHz IMO period jitter (RMS) – 200 900 ps Notes 11.4.75 V < VDD < 5.25 V. 12.Accuracy derived from Internal Main Oscillator with appropriate trim for VDD range. 13.3.0 V < VDD < 3.6 V. See application note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3 V. 14.See the individual user module data sheets for information on maximum frequencies for user modules. 15.Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information. Document Number: 38-08036 Rev. *N Page 24 of 45

CY7C64215 AC GPIO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C A A and are for design guidance only. Table 19. AC GPIO Specifications Parameter Description Min Typ Max Unit Notes F GPIO operating frequency 0 – 12 MHz Normal Strong Mode GPIO TRiseF Rise time, normal strong mode, Cload = 50 pF 3 – 18 ns V = 4.5 to 5.25 V, 10%–90% DD TFallF Fall time, normal strong mode, Cload = 50 pF 2 – 18 ns V = 4.5 to 5.25 V, 10%–90% DD TRiseS Rise time, slow strong mode, Cload = 50 pF 10 27 – ns V = 3 to 5.25 V, 10%–90% DD TFallS Fall time, slow strong mode, Cload = 50 pF 10 22 – ns V = 3 to 5.25 V, 10%–90% DD Figure 6. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TFallF TRiseS TFallS AC Full Speed USB Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C A A and are for design guidance only. Table 20. AC Full-Speed (12 Mbps) USB Specifications Parameter Description Min Typ Max Unit Notes T Transition rise time 4 – 20 ns For 50-pF load. RFS T Transition fall time 4 – 20 ns For 50-pF load. FSS T Rise/fall time matching: (T /T ) 90 – 111 % For 50-pF load. RFMFS R F T Full-speed data rate 12 – 0.25% 12 12 + 0.25% Mbps – DRATEFS Document Number: 38-08036 Rev. *N Page 25 of 45

CY7C64215 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C A A and are for design guidance only. Table 21. AC Digital Block Specifications Function Description Min Typ Max Unit Notes All functions Block input clock frequency V  4.75 V – – 49.92 MHz DD V < 4.75 V – – 25.92 MHz DD Timer Input clock frequency No capture, V 4.75 V – – 49.92 MHz DD No capture, V < 4.75 V – – 25.92 MHz DD With capture – – 25.92 MHz Capture pulse width 50[16] – – ns Counter Input clock frequency No enable input, V  4.75 V – – 49.92 MHz DD No enable input, V < 4.75 V – – 25.92 MHz DD With enable input – – 25.92 MHz Enable input pulse width 50[16] – – ns Kill pulse width Asynchronous restart mode 20 – – ns Synchronous restart mode 50[16] – – ns Disable mode 50[16] – – ns Input clock frequency V  4.75 V – – 49.92 MHz DD V < 4.75 V – – 25.92 MHz DD CRCPRS Input clock frequency (PRS V  4.75 V – – 49.92 MHz Mode) DD V < 4.75 V – – 25.92 MHz DD CRCPRS Input clock frequency – – 24.6 MHz (CRC Mode) SPIM Input clock frequency – – 8.2 MHz The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. SPIS Input clock (SCLK) frequency – – 4.1 MHz The input clock is the SPI SCLK in SPIS mode. Width of SS_negated between 50[16] – – ns transmissions Transmitter Input clock frequency The baud rate is equal to the input clock frequency divided by 8. V  4.75 V, 2 stop bits – – 49.92 MHz DD V  4.75 V, 1 stop bit – – 24.6 MHz DD V < 4.75 V – – 24.6 MHz DD Receiver Input clock frequency The baud rate is equal to the input clock frequency divided by 8. V  4.75 V, 2 stop bits – – 49.92 MHz DD V  4.75 V, 1 stop bit – – 24.6 MHz DD V < 4.75 V – – 24.6 MHz DD Note 16.50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 38-08036 Rev. *N Page 26 of 45

CY7C64215 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C A A and are for design guidance only. Table 22. AC External Clock Specifications Parameter Description Min Typ Max Unit Notes F Frequency for USB applications 23.94 24 24.06 MHz USB operation in the extended Industrial OSCEXT temperature range (–40°C < T < 85°C) A requires that the system clock is sourced from an external clock oscillator. – Duty cycle 47 50 53 % – – Power-up to IMO switch 150 – – s – AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C A A and are for design guidance only. Table 23. 5 V AC Analog Output Buffer Specifications Parameter Description Min Typ Max Unit Notes T Rising settling time to 0.1%, 1 V Step, 100-pF load – ROB Power = low – – 2.5 s Power = high – – 2.5 s T Falling settling time to 0.1%, 1 V Step, 100-pF load – SOB Power = low – – 2.2 s Power = high – – 2.2 s SR Rising slew rate (20% to 80%), 1 V Step, 100-pF load – ROB Power = low 0.65 – – V/s Power = high 0.65 – – V/s SR Falling slew rate (80% to 20%), 1 V Step, 100-pF load – FOB Power = low 0.65 – – V/s Power = high 0.65 – – V/s BW Small signal bandwidth, 20mV , 3-dB BW, 100-pF load – OBSS pp Power = low 0.8 – – MHz Power = high 0.8 – – MHz BW Large signal bandwidth, 1 V , 3-dB BW, 100-pF load – OBLS pp Power = low 300 – – kHz Power = high 300 – – kHz Table 24. 3.3 V AC Analog Output Buffer Specifications Parameter Description Min Typ Max Unit Notes T Rising settling time to 0.1%, 1 V Step, 100-pF load – ROB Power = low – – 3.8 s Power = high – – 3.8 s T Falling settling time to 0.1%, 1 V Step, 100-pF load – SOB Power = low – – 2.6 s Power = high – – 2.6 s SR Rising slew rate (20% to 80%), 1 V Step, 100-pF load – ROB Power = low 0.5 – – V/s Power = high 0.5 – – V/s SR Falling slew rate (80% to 20%), 1 V Step, 100-pF load – FOB Power = low 0.5 – – V/s Power = high 0.5 – – V/s BW Small signal bandwidth, 20mV , 3dB BW, 100-pF load – OBSS pp Power = low 0.7 – – MHz Power = high 0.7 – – MHz BW Large signal bandwidth, 1 V , 3dB BW, 100-pF load – OBLS pp Power = low 200 – – kHz Power = high 200 – – kHz Document Number: 38-08036 Rev. *N Page 27 of 45

CY7C64215 AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C A A and are for design guidance only. Table 25. AC Programming Specifications Parameter Description Min Typ Max Unit Notes T Rise time of SCLK 1 – 20 ns – RSCLK T Fall time of SCLK 1 – 20 ns – FSCLK T Data setup time to falling edge of SCLK 40 – – ns – SSCLK T Data hold time from falling edge of SCLK 40 – – ns – HSCLK F Frequency of SCLK 0 – 8 MHz – SCLK T Flash erase time (block) – 10 – ms – ERASEB T Flash block write time – 40 – ms – WRITE T Data out delay from falling edge of SCLK – – 45 ns V  3.6 DSCLK DD T Data out delay from falling edge of SCLK – – 50 ns 3.15 < V < 3.5 DSCLK3 DD T Flash erase time (bulk) – 40 – ms Erase all blocks and protection ERASEALL fields at once. T Flash block erase + flash block write time – – 100 ms 0°C  T  100°C PROGRAM_HOT J T Flash block erase + flash block write time – – 200 ms –40°C  T  0°C PROGRAM_COLD J Document Number: 38-08036 Rev. *N Page 28 of 45

CY7C64215 AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and –40°C < T < 85°C, or 3.15 V to 3.5 V and –40°C < T < 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C A A and are for design guidance only. Table 26. AC Characteristics of the I2C SDA and SCL Pins for V DD Standard-Mode Fast-Mode Parameter Description Unit Notes Min Max Min Max F SCL clock frequency 0 100 0 400 kHz – SCLI2C T Hold time (repeated) START condition. After 4.0 – 0.6 – s – HDSTAI2C this period, the first clock pulse is generated. T LOW period of the SCL clock 4.7 – 1.3 – s – LOWI2C T HIGH period of the SCL clock 4.0 – 0.6 – s – HIGHI2C T Setup time for a repeated START condition 4.7 – 0.6 – s – SUSTAI2C T Data hold time 0 – 0 – s – HDDATI2C T Data setup time 250 – 100[17] – ns – SUDATI2C T Setup time for STOP condition 4.0 – 0.6 – s – SUSTOI2C T Bus free time between a STOP and START 4.7 – 1.3 – s – BUFI2C condition T Pulse width of spikes are suppressed by the – – 0 50 ns – SPI2C input filter. Figure 7. Definition for Timing for Fast-/Standard-Mode on the I2C Bus I2C_SDA T TSUDATI2C THDDATI2CTSUSTAI2C TSPI2C TBUFI2C HDSTAI2C I2C_SCL T T T HIGHI2C LOWI2C SUSTOI2C P S S Sr START Condition Repeated START Condition STOP Condition Note 17.A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement TSUDATI2C  250 ns must then be met. This automatically is the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + TSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 38-08036 Rev. *N Page 29 of 45

CY7C64215 Packaging Information This section illustrates the package specification for the CY7C64215 enCoRe III, along with the thermal impedance for the package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com. Package Diagrams Figure 8. 56-pin QFN (8 × 8 × 1.0 mm) 4.5 × 5.21 E-Pad (Subcon Punch Type Package) Package Outline, 001-12921 001-12921 *C Document Number: 38-08036 Rev. *N Page 30 of 45

CY7C64215 Figure 9. 56-pin QFN (8 × 8 × 1.0 mm) 4.5 × 5.2 E-Pad (Sawn) Package Outline, 001-53450 001-53450 *D Figure 10. 28-pin SSOP (210 Mils) Package Outline, 51-85079 51-85079 *F Document Number: 38-08036 Rev. *N Page 31 of 45

CY7C64215 Thermal Impedance Table 27. Thermal Impedance for the Package Package Typical  [18] JA 56-pin QFN[19] 20 oC/W 28-pin SSOP 96 oC/W Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 28. Solder Reflow Peak Temperature Package Maximum Peak Temperature Time at Maximum Peak Temperature 56-pin QFN 260°C 20 s 28-pin SSOP 260°C 20 s Notes 18.TJ = TA + POWER x JA 19.To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane. Document Number: 38-08036 Rev. *N Page 32 of 45

CY7C64215 Ordering Information Package Ordering Code Flash Size SRAM (Bytes) Temperature Range 28-pin SSOP CY7C64215-28PVXC 16K 1K Commercial, 0°C to 70°C 28-pin SSOP (Tape and Reel) CY7C64215-28PVXCT 16K 1K Commercial, 0°C to 70°C 28-pin SSOP CY7C64215-28PVXI 16 K 1K Industrial, –40 °C to 85 °C 28-pin SSOP (Tape and Reel) CY7C64215-28PVXIT 16 K 1K Industrial, –40 °C to 85 °C 56-pin QFN (Sawn) CY7C64215-56LTXC 16K 1K Commercial, 0°C to 70°C 56-pin QFN (Sawn) (Tape and Reel) CY7C64215-56LTXCT 16K 1K Commercial, 0°C to 70°C 56-pin QFN (Sawn) CY7C64215-56LTXI 16K 1K Industrial, –40°C to 85°C 56-pin QFN (Sawn) (Tape and Reel) CY7C64215-56LTXIT 16K 1K Industrial, –40°C to 85°C Ordering Code Definitions CY 7C64 XXX- XX XXX C/I (T) Tape and reel Temperature range: Commercial/Industrial Package type: PVX: SSOP LTX: QFN Pin count: 28 = 28 pins, 56 = 56 pins Base part number Marketing Code: 7C64 = enCoRe Full-Speed USB Controller Company ID: CY = Cypress Document Number: 38-08036 Rev. *N Page 33 of 45

CY7C64215 Acronyms Acronyms Used The following table lists the acronyms that are used in this document. Acronym Description Acronym Description AC alternating current MIPS million instructions per second ADC analog-to-digital converter PCB printed circuit board API application programming interface PGA programmable gain amplifier CPU central processing unit POR power-on reset CRC cyclic redundancy check PPOR precision power-on reset CT continuous time PSoC® Programmable System-on-Chip™ DAC digital-to-analog converter PWM pulse-width modulator DC direct current QFN quad flat no leads EEPROM electrically erasable programmable read-only RF radio frequency memory GPIO general purpose I/O SC switched capacitor ICE in-circuit emulator SLIMO slow IMO IDE integrated development environment SPI™ serial peripheral interface ILO internal low speed oscillator SRAM static random-access memory IMO internal main oscillator SROM supervisory read-only memory I/O input/output SSOP shrink small-outline package ISSP In-System Serial Programming UART universal asynchronous receiver / transmitter LVD low voltage detect USB universal serial bus MAC multiply-accumulate WDT watchdog timer Reference Documents CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34, CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical Reference Manual (TRM) (001-14463) Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459) Document Number: 38-08036 Rev. *N Page 34 of 45

CY7C64215 Document Conventions Units of Measure Symbol Unit of Measure Symbol Unit of Measure °C degree Celsius ms milli-second dB decibels mV milli-volts fF femto farad nA nanoampere kHz kilohertz ns nanosecond k kilohm  ohm MHz megahertz pF picofarad A microampere ps picosecond s microsecond % percent V microvolts V volts mA milli-ampere W watts mm milli-meter Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal. active high 5.A logic signal having its asserted state as the logic 1 state. 6.A logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. analog-to-digital A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts (ADC) a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. API (Application A series of software routines that comprise an interface between a computer application and lower level services Programming and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create Interface) software applications. asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. Bandgap A stable voltage reference design that matches the positive temperature coefficient of VT with the negative reference temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. bandwidth 1.The frequency range of a message or information processing system measured in hertz. 2.The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. bias 1.A systematic deviation of a value from a reference value. 2.The amount by which the average of a set of values departs from a reference value. 3.The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1.A functional unit that performs a single function, such as an oscillator. 2.A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. Document Number: 38-08036 Rev. *N Page 35 of 45

CY7C64215 buffer 1.A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written. 2.A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3.An amplifier used to lower the output impedance of a system. bus 1.A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2.A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3.One or more conductors that serve as a common connection for a group of related devices. clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler A program that translates a high level language, such as C, into machine language. configuration In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. space crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. debugger A hardware and software system that allows the user to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition. digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. digital-to-analog A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC) (DAC) converter performs the reverse operation. duty cycle The relationship of a clock period high time to its low time, expressed as a percent. emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop (XRES) and return to a pre-defined state. Document Number: 38-08036 Rev. *N Page 36 of 45

CY7C64215 flash An electrically programmable and erasable, non-volatile technology that provides users with the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is off. Flash block The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. frequency The number of cycles or events per unit of time, for a periodic function. gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ICE The in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many routine (ISR) interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. jitter 1.A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2.The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. low-voltage detect A circuit that senses V and provides an interrupt to the system when V falls lower than a selected threshold. DD DD (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal The reference to a circuit containing both analog and digital techniques and components. modulator A device that imposes a signal on a carrier. Document Number: 38-08036 Rev. *N Page 37 of 45

CY7C64215 noise 1.A disturbance that affects a signal and that may distort the information carried by the signal. 2.The random variations of one or more characteristics of any entity such as voltage, current, or data. oscillator A circuit that may be crystal controlled and is used to generate a clock frequency. parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference loop (PLL) signal. pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. port A group of pins, usually eight. power on reset A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is one type of (POR) hardware reset. PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark of Cypress. PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. register A storage device with a specific capacity, such as a bit or byte. reset A means of bringing a system back to a know state. See hardware reset and software reset. ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. serial 1.Pertaining to a process in which all events occur one after the other. 2.Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. SRAM An acronym for static random access memory. A memory device allowing users to store and retrieve data at a high rate of speed. The term static is used because, after a value has been loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. Document Number: 38-08036 Rev. *N Page 38 of 45

CY7C64215 SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. stop bit A signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1.A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2.A system whose operation is synchronized by a clock signal. tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. V A name for a power net meaning “voltage drain.” The most positive power supply signal. Usually 5 V or 3.3 V. DD V A name for a power net meaning “voltage source.” The most negative power supply signal. SS watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. Document Number: 38-08036 Rev. *N Page 39 of 45

CY7C64215 Errata This section describes the errata for the enCoRe III CY7C64215 device. The information in this document describes hardware issues associated with Silicon Revision A. Contact your local Cypress sales representative if you have questions. Part Numbers Affected Part Number Silicon Revision CY7C64215 A CY7C64215 Qualification Status Product Status: In Production CY7C64215 Errata Summary This table defines the errata applicability to available enCoRe III CY7C64215 family devices. Items Part Number Silicon Revision Fix Status USB interface DP line pulses low when the CY7C64215 A No silicon fix planned. Use enCoRe III device wakes from sleep. workaround. Invalid flash reads may occur if V is pulled to CY7C64215 A DD –0.5 V just before power on. PMA Index Register fails to auto-increment with CY7C64215 A CPU_Clock set to SysClk/1 (24 MHz). 1.USB interface DP line pulses low when the enCoRe III device wakes from sleep ■Problem Definition When the device operates at 4.75 V to 5.25 V and the 3.3-V regulator is enabled, a short low pulse may be created on the DP signal line during device wakeup. The 15- to 20-µs low pulse of the DP line may be interpreted by the host computer as a deattach or the beginning of a wakeup. ■Parameters Affected The bandgap reference voltage used by the 3.3-V regulator decreases during sleep due to leakage. Upon device wakeup, the bandgap is re-enabled and, after a delay for settling, the 3.3-V regulator is enabled. On some devices the 3.3-V regulator used to generate the USB DP signal may be enabled before the bandgap is fully stabilized. This can cause a low pulse on the regulator output and DP signal line until the bandgap stabilizes. In applications where V is 3.3 V, the regulator is not used and, therefore, the DP low pulse DD is not generated. ■Trigger Condition N/A ■Scope of Impact N/A ■Workaround To prevent the DP signal from pulsing low, keep the bandgap enabled during sleep. The most efficient method is to set the No Buzz bit in the OSC_CR0 register. The No Buzz bit keeps the bandgap powered and output stable during sleep. Setting the No Buzz bit results in a nominal 100 µA increase in sleep current. Leaving the analog reference block enabled during sleep also resolves this issue because it forces the bandgap to remain enabled. The following example shows how to disable the No Buzz bit: Assembly M8C_SetBank1 or reg[OSC_CR0], 0x20 M8C_SetBank0 C OSC_CR0 |= 0x20; Document Number: 38-08036 Rev. *N Page 40 of 45

CY7C64215 ■Fix Status There is no planned silicon fix; use workaround. 2.Invalid flash reads may occur if V is pulled to –0.5 V just before power on DD ■Problem Definition When V of the device is pulled below ground just before power on, the first read from each 8-KB flash page may be corrupted. This DD issue does not affect flash page 0 because it is the selected page upon reset. ■Parameters Affected When V is pulled below ground before power on, an internal flash reference may deviate from its nominal voltage. The reference DD deviation tends to result in the first flash read from that page returning 0xFF. During the first read from each page, the reference is reset resulting in all future reads returning the correct value. A short delay of 5 µs before the first real read provides time for the reference voltage to stabilize. ■Trigger Condition N/A ■Scope of Impact N/A ■Workaround To prevent an invalid flash read, a dummy read from each flash page must occur before use of the pages. A delay of 5 µs must occur after the dummy read and before a real read. The dummy reads occur as soon as possible and must be located in flash page 0 before a read from any other flash page. An example for reading a byte of memory from each flash page is listed below. Place it in boot.tpl and boot.asm immediately after the ‘start:’ label. // dummy read from each 8K Flash page // page 1 movA, 0x20 // MSB movX, 0x00 // LSB romx // wait at least 5 µs movX, 14 loop1: decX jnzloop1 ■Fix Status There is no planned silicon fix; use workaround. 3.PMA Index Register fails to auto-increment with CPU_Clock set to SysClk/1 (24 MHz) ■Problem Definition When the device operates at 4.75 V to 5.25 V and the CPU_Clock is set to SysClk/1 (24 MHz), the USB PMA Index Register may fail to increment automatically when used in an OUT endpoint configuration at full-speed. When the application program attempts to use the bReadOutEP() function, the first byte in the PMA buffer is always returned. ■Parameters Affected An internal flip-flop hold problem is associated with the index register increment function. All reads of the associated RAM originate from the first byte. The hold problem has no impact on other circuits or functions within the device. ■Trigger Condition N/A ■Scope of Impact N/A Document Number: 38-08036 Rev. *N Page 41 of 45

CY7C64215 ■WORKAROUND To make certain that the index register properly increments, set the CPU_Clock to SysClk/2 (12 MHz) during the read of the PMA buffer. An example for the clock adjustment method follows: PSoC Designer 4.3 User Module workaround: PSoC Designer Release 4.3 and subsequent releases include a revised full-speed USB User Module with the revised firmware workaround included (see the following example). 24-Mhz read PMA workaround ;; M8C_SetBank1 mov A, reg[OSC_CR0] push A and A, 0xf8 ;clear the clock bits (briefly chg the cpu_clk to 3Mhz) or A, 0x02 ;will set clk to 12Mhz mov reg[OSC_CR0],A ;clk is now set at 12Mhz M8C_SetBank0 .loop: mov A, reg[PMA0_DR] ; Get the data from the PMA space mov [X], A ; save it in data array inc X ; increment the pointer dec [USB_APITemp+1] ; decrement the counter jnz .loop ; wait for count to zero out ;; ;; 24Mhz read PMA workaround (back to previous clock speed) ;; pop A ;recover previous reg[OSC_CR0] value M8C_SetBank1 mov reg[OSC_CR0],A ;clk is now set at previous value M8C_SetBank0 ;; ;; end 24Mhz read PMA workaround ■Fix Status There is no planned silicon fix; use workaround. Document Number: 38-08036 Rev. *N Page 42 of 45

CY7C64215 Document History Page Description Title: CY7C64215, enCoRe™ III Full-Speed USB Controller Document Number: 38-08036 Submission Orig. of Rev. ECN No. Description of Change Date Change ** 131325 See ECN XGR New data sheet. *A 385256 See ECN BHA Changed status from Advance Information to Preliminary. Added standard data sheet items. Changed Part number from CY7C642xx to CY7C64215. *B 2547630 08/04/2008 AZIEL / Operational voltage range for USB specified under “Full Speed USB PYRS (12Mbps)”. CMP_GO_EN1 register removed as it has no functionality on Radon. Figure “CPU Frequency” adjusted to show invalid operating region for USB with footnote describing reason. DC electrical characteristic, V . Note added describing where USB hardware DD is non-functional. *C 2620679 12/12/2008 CMCC / Added Package Handling information. PYRS Deleted note regarding link to amkor.com for MLF package dimensions. *D 2717887 06/11/2009 DPT Added 56 -Pin Sawn QFN (8 X 8 mm) package diagram and added CY7C64215-56LTXC part information in the Ordering Information table. *E 2852393 01/15/2010 BHA / XUT ■Added Table of Contents. ■Added external clock oscillator option and Industrial Temperature information to the Features, Pin Information, Electrical Specifications, Operating Temperature, DC Electrical Characteristics, AC Electrical Characteristics, and Ordering Information sections. ■Updated DC GPIO, AC Chip, and AC Programming Specifications follows: ❐Replaced TRAMP (time) with SRPOWER_UP (slew rate) specification. ❐Added I , I , DCILO, F32K_U, TPOWERUP, TERASEALL, OH OL TPROGRAM_HOT, and TPROGRAM_COLD specifications. ❐Updated V ranges on Figure 5 and Table 8. DD ❐Added notes for VM and VDI on Table 10. ❐Removed TR/TF from Table 20. ■Update Ordering Information for: CY7C64215-56LFXCT, CY7C64215-28PVXCT, CY7C64215-56LTXIT Tape and Reel. ■Updated 28-Pin SSOP and 56-Pin QFN PUNCH and SAWN package diagrams. ■Updated copyright and Sales, Solutions, and Legal Information URLs. *F 2892683 03/15/2010 NJF Updated Cypress website links. Added T andT parameters in Absolute Maximum Ratings. BAKETEMP BAKETIME Updated AC Chip-Level Specifications Removed inactive parts from Ordering Information Updated note in Packaging Information. *G 3070717 10/25/2010 XUT Removed reference to CYFISPI in Features. Updated datasheet as per Cypress style guide and new datasheet template. *H 3090908 11/19/10 CSAI Updated AC Chip-Level Specifications table. Added DC I2C Specification. *I 3143408 01/17/11 NJF Added DC I2C Specifications table. Added Tjit_IMO specification, removed existing jitter specifications. Updated Analog reference tables. Updated Units of Measure, Acronyms, Glossary, and References sections. Updated solder reflow specifications. No specific changes were made to AC Digital Block Specifications table and I2C Timing Diagram. They were updated for clearer understanding. Document Number: 38-08036 Rev. *N Page 43 of 45

CY7C64215 Document History Page (continued) Description Title: CY7C64215, enCoRe™ III Full-Speed USB Controller Document Number: 38-08036 Submission Orig. of Rev. ECN No. Description of Change Date Change *J 3995635 05/09/2013 CSAI Updated Packaging Information: spec 001-12921 – Changed revision from *A to *B. spec 001-53450 – Changed revision from *B to *C. spec 51-85079 – Changed revision from *D to *E. Added Errata. *K 4080167 07/29/2013 CSAI Added Errata footnotes (Note 3, 5). Updated Electrical Specifications: Updated DC Electrical Characteristics: Updated DC Chip-Level Specifications: Added Note 3 and referred the same note in “Sleep Mode” in description of I SB parameter in Table7. Updated DC POR and LVD Specifications: Added Note 5 and referred the same note in V , V , V PPOR0 PPOR1 PPOR2 parameters in Table15. Updated Reference Documents: Removed references of spec 001-17397 and spec 001-14503 as these specs are obsolete. Updated in new template. *L 4247931 01/16/2014 CSAI Updated Packaging Information: spec 001-53450 – Changed revision from *C to *D. Completing Sunset Review. *M 4481449 08/28/2014 MVTA Updated Packaging Information: spec 001-12921 – Changed revision from *B to *C. Updated Ordering Information (Updated part numbers). Updated in new template. *N 5730242 05/10/2017 MVTA Updated Packaging Information: spec 51-85079 - Changed revsion from *E to *F. Updated Cypress Logo and Copyright. Document Number: 38-08036 Rev. *N Page 44 of 45

CY7C64215 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC®Solutions ARM® Cortex® Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Forums | WICED IoT Forums | Projects | Video | Blogs | Interface cypress.com/interface Training | Components Internet of Things cypress.com/iot Technical Support Memory cypress.com/memory cypress.com/support Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless © Cypress Semiconductor Corporation, 2003-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-08036 Rev. *N Revised May 19, 2017 Page 45 of 45

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: C ypress Semiconductor: CY7C64215-28PVXC CY7C64215-28PVXCT CY7C64215-56LTXCT CY7C64215-56LTXI CY7C64215-56LTXIT CY7C64215-56LTXC