CY7C4265 16K × 18 Deep Sync FIFOs 16K × 18 Deep Sync FIFOs Features Functional Description The CY7C4265 are high speed, low power, first-in first-out ■High speed, low power, first-in first-out (FIFO) memories (FIFO) memories with clocked read and write interfaces. All are ❐16K × 18 (CY7C4265) 18 bits wide and are pin/functionally compatible to the ■0.5 micron CMOS for optimum speed and power CY7C42X5 Synchronous FIFO family. The CY7C4265 can be cascaded to increase FIFO depth. Programmable features ■High speed 100 MHz operation (10 ns read/write cycle times) include Almost Full/Almost Empty flags. These FIFOs provide ■Low power - ICC = 45 mA solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications ■Fully asynchronous and simultaneous read and write operation buffering. ■Empty, full, half full, and programmable almost empty and These FIFOs have 18-bit input and output ports that are almost full status flags controlled by separate clock and enable signals. The input port ■TTL compatible is controlled by a free running Clock (WCLK) and a Write Enable ■Retransmit function pin (WEN). When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is ■Output enable (OE) pins continually written into the FIFO on each cycle. The output port is ■Independent read and write enable pins controlled in a similar manner by a free-running Read Clock (RCLK) and a Read Enable pin (REN). In addition, the CY7C4265 has an Output ■Center power and ground pins for reduced noise Enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for ■Supports free-running 50 percent duty cycle clock inputs asynchronous read/write applications. Clock frequencies up to 100 ■Width and depth expansion capability MHz are achievable. ■64-pin TQFP and 64-pin STQFP Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is ■Pb-free packages available possible using the Cascade Input (WXI, RXI), Cascade Output (WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to V SS and the FL pin of all the remaining devices should be tied to V . CC For a complete list of related documentation, click here. Logic Block Diagram D0–17 INPUT REGISTER WCLK WEN FLAG PROGRAM WRITE REGISTER CONTROL FF EF ARRARMAY LFOLGAGIC PPAAEF SMODE 16 Kx18 WRITE READ POINTER POINTER RS RESET LOGIC FLW/RXTI EXPANSION OUTTHPRUETER–ESGTIASTTEER CORNETARDOL WXO/HF LOGIC RXI RXO Q0–17 OE RCLK REN CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 38-06004 Rev. *K Revised February 15, 2018

CY7C4265 Contents Pin Configurations ...........................................................3 AC Test Loads and Waveforms .....................................11 Pin Description .................................................................3 Switching Characteristics ..............................................12 Selection Guide ................................................................3 Switching Waveforms ....................................................13 Density and Package ........................................................4 Ordering Information ......................................................21 Pin Definitions ..................................................................4 16K × 18 Deep Sync FIFO ........................................21 Architecture ......................................................................5 Ordering Code Definitions .........................................21 Resetting the FIFO ......................................................5 Package Diagrams ..........................................................22 FIFO Operation ...........................................................5 Acronyms ........................................................................24 Programming ...............................................................5 Document Conventions .................................................24 Flag Operation .............................................................5 Units of Measure .......................................................24 Retransmit .........................................................................6 Document History Page .................................................25 Width Expansion Configuration ......................................7 Sales, Solutions, and Legal Information ......................26 Depth Expansion Configuration Worldwide Sales and Design Support .......................26 (with Programmable Flags) .............................................7 Products ....................................................................26 Typical AC and DC Characteristics ................................9 PSoC® Solutions ......................................................26 Maximum Ratings ...........................................................10 Cypress Developer Community .................................26 Operating Range .............................................................10 Technical Support .....................................................26 Electrical Characteristics ...............................................10 Capacitance ....................................................................11 Document Number: 38-06004 Rev. *K Page 2 of 26

CY7C4265 Pin Configurations Figure 1. 64-pin TQFP/STQFP pinout (Top View) E D O M D16D17GNDRCLK RENLDOERSVCCGNDEFQ17Q16GNDQ15V/SCC 4321098765432109 D15 1 666665555555555448 Q14 D14 2 47 Q13 D13 3 46 GND D12 4 45 Q12 D11 5 44 Q11 D10 6 43 VCC D9 7 42 Q10 D8 8 CY7C4265 41 Q9 D7 9 40 GND D6 10 39 Q8 D5 11 38 Q7 D4 12 37 Q6 D3 13 36 Q5 D2 14 35 GND D1 15 34 Q4 D0 16 33 VCC 7890123456789012 1112222222222333 PAE FL/RTWCLKWENWXIVCCPAFRXIFFXO/HFRXO Q0Q1GNDQ2Q3 W Pin Description (WCLK). When entering or exiting the Empty states, the flag is updated exclusively by the RCLK. The flag denoting Full states The CY7C4265 provides five status pins. These pins are is updated exclusively by WCLK. The synchronous flag decoded to determine one of five states: Empty, Almost Empty, architecture guarantees that the flags remain valid from one Half Full, Almost Full, and Full. The Half Full flag shares the WXO clock cycle to the next. The Almost Empty/Almost Full flags pin. This flag is valid in the standalone and width-expansion become synchronous if the V /SMODE is tied to V . All CC SS configurations. In the depth expansion, this pin provides the configurations are fabricated using an advanced 0.5 CMOS expansion out (WXO) information that is used to signal the next technology. Input ESD protection is greater than 2001 V, and FIFO when it is activated. latch up is prevented by the use of guard rings. The Empty and Full flags are synchronous, that is, they change state relative to either the Read Clock (RCLK) or the Write Clock Selection Guide Description 7C4265-10 7C4265-15 Maximum Frequency (MHz) 100 66.7 Maximum Access Time (ns) 8 10 Minimum Cycle Time (ns) 10 15 Minimum Data or Enable Set-Up (ns) 3 4 Minimum Data or Enable Hold (ns) 0.5 1 Maximum Flag Delay (ns) 8 10 Active Power Supply Current (I ) (mA) Commercial 45 45 CC1 Industrial 50 50 Document Number: 38-06004 Rev. *K Page 3 of 26

CY7C4265 Density and Package Description CY7C4265 Density 16K × 18 Package 64-pin TQFP, STQFP Pin Definitions Signal Name Description I/O Function D Data Inputs I Data inputs for an 18-bit bus. 0–17 Q Data Outputs O Data outputs for an 18-bit bus. 0–17 WEN Write Enable I Enables the WCLK input. REN Read Enable I Enables the RCLK input. WCLK Write Clock I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. RCLK Read Clock I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset register. WXO/HF Write Expansion O Dual-Mode Pin: Out/Half Full Flag Single device or width expansion – Half Full status flag. Cascaded – Write Expansion Out signal, connected to WXI of next device. EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. FF Full Flag O When FF is LOW, the FIFO is full. FF is synchronized to WCLK. PAE Programmable O When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value Almost Empty programmed into the FIFO. PAE is asynchronous when V /SMODE is tied to V ; it CC CC is synchronized to RCLK when V /SMODE is tied to V . CC SS PAF Programmable O When PAF is LOW, the FIFO is almost full based on the almost full offset value Almost Full programmed into the FIFO. PAF is asynchronous when V /SMODE is tied to V ; it CC CC is synchronized to WCLK when V /SMODE is tied to V . CC SS LD Load I When LD is LOW, D (Q ) are written (read) into (from) the 0–17 0–17 programmable-flag-offset register. FL/RT First Load/ I Dual-Mode Pin: Retransmit Cascaded – The first device in the daisy chain has FL tied to V ; all other devices SS has FL tied to V . In standard mode or width expansion, FL is tied to V on all CC SS devices. Not Cascaded – Tied to V . Retransmit function is also available in stand-alone mode SS by strobing RT. WXI Write Expansion Input I Cascaded – Connected to WXO of previous device. Not Cascaded – Tied to V . SS RXI Read Expansion Input I Cascaded – Connected to RXO of previous device. Not Cascaded – Tied to V . SS RXO Read Expansion O Cascaded – Connected to RXI of next device. Output RS Reset I Resets device to empty condition. A reset is required before an initial read or write operation after power-up. OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. V /SMODE Synchronous I Dual-Mode Pin: CC Almost Empty/ Asynchronous Almost Empty/Almost Full flags – tied to V . CC Almost Full Flags Synchronous Almost Empty/Almost Full flags – tied to V . SS (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) Document Number: 38-06004 Rev. *K Page 4 of 26

CY7C4265 Architecture set LOW, and WEN is LOW, the next offset register in sequence is written. The CY7C4265 consists of an array of 16 K words of 18 bits each The contents of the offset registers can be read on the output (implemented by a dual-port array of SRAM cells), a read pointer, lines when the LD pin is set LOW and REN is set LOW; then, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), data can be read on the LOW-to-HIGH transition of the Read and flags (EF, PAE, HF, PAF, FF). The CY7C4265 also includes Clock (RCLK). the control signals WXI, RXI, WXO, RXO for depth expansion. Table 1. Write Offset Register Resetting the FIFO LD WEN WCLK[1] Selection Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by 0 0 Writing to offset registers: EF being LOW. All data outputs go LOW after the falling edge of Empty Offset RS only if OE is asserted. For the FIFO to reset to its default Full Offset state, a falling edge must occur on RS and the user must not read or write while RS is LOW. 0 1 No Operation FIFO Operation 1 0 Write Into FIFO When the WEN signal is active (LOW), data present on the D 0–17 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN signal is active LOW, data in the 1 1 No Operation FIFO memory are presented on the Q outputs. New data is 0–17 presented on each rising edge of RCLK while REN is active LOW and OE is LOW. REN must setup t before RCLK for it to be ENS a valid read function. WEN must occur tENS before WCLK for it Flag Operation to be a valid write function. The CY7C4265 devices provide five flag pins to indicate the An output enable (OE) pin is provided to three-state the Q 0–17 condition of the FIFO contents. Empty and Full are synchronous. outputs when OE is deasserted. When OE is enabled (LOW), PAE and PAF are synchronous if V /SMODE is tied to V . data in the output register is available to the Q outputs after CC SS 0–17 tOE. If devices are cascaded, the OE function only outputs data Full Flag on the FIFO that is read enabled. The Full Flag (FF) goes LOW when device is Full. Write The FIFO contains overflow circuitry to disallow additional writes operations are inhibited whenever FF is LOW regardless of the when the FIFO is full, and under flow circuitry to disallow state of WEN. FF is synchronized to WCLK: it is exclusively additional reads when the FIFO is empty. An empty FIFO updated by each rising edge of WCLK. maintains the data of the last valid read on its Q outputs even 0–17 after additional reads occur. Empty Flag The Empty Flag (EF) goes LOW when the device is empty. Read Programming operations are inhibited whenever EF is LOW, regardless of the The CY7C4265 devices contain two 14-bit offset registers. Data state of REN. EF is synchronized to RCLK, i.e., it is exclusively present on D0–13 during a program write determines the distance updated by each rising edge of RCLK. from Empty (Full) that the Almost Empty (Almost Full) flags become active. If the user elects not to program the FIFO’s flags, Programmable Almost Empty/Almost Full Flag the default offset values are used (see Table1). When the Load The CY7C4265 features programmable Almost Empty and LD pin is set LOW and WEN is set LOW, data on the inputs D0–13 Almost Full Flags. Each flag can be programmed (described in is written into the Empty offset register on the first LOW-to-HIGH the Programming section) a specific distance from the transition of the Write Clock (WCLK). When the LD pin and WEN corresponding boundary flags (Empty or Full). When the FIFO are held LOW then data is written into the Full offset register on contains the number of words or fewer for which the flags have the second LOW-to-HIGH transition of the Write Clock (WCLK). been programmed, the PAF or PAE are asserted, signifying that The third transition of the Write Clock (WCLK) again writes to the the FIFO is either Almost Full or Almost Empty. See Table 2 on Empty offset register (see Table1). Writing all offset registers page 6 for a description of programmable flags. does not have to occur at one time. One or two offset registers When the SMODE pin is tied LOW, the PAF flag signal transition can be written and then, by bringing the LD pin HIGH, the FIFO is caused by the rising edge of the write clock and the PAE flag is returned to normal read/write operation. When the LD pin is transition is caused by the rising edge of the read clock. Note 1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK. Document Number: 38-06004 Rev. *K Page 5 of 26

CY7C4265 Retransmit pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and t RTR The retransmit feature is beneficial when transferring packets of after the retransmit pulse. With every valid read cycle after data. It enables the receipt of data to be acknowledged by the retransmit, previously accessed data is read and the read pointer receiver and retransmitted if necessary. is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers The Retransmit (RT) input is active in the stand-alone and width and are updated during a retransmit cycle. Data written to the expansion modes. The retransmit feature is intended for use FIFO after activation of RT are transmitted also. when a number of writes equal to or less than the depth of the FIFO have occurred and at least one word has been read since The full depth of the FIFO can be repeatedly retransmitted. the last RS cycle. A HIGH pulse on RT resets the internal read Table 2. Flag Truth Table Number of Words in FIFO FF PAF HF PAE EF CY7C4265 – 16 K × 18 0 H H H L L 1 to n[2] H H H L H (n + 1) to 8192 H H H H H 8193 to (16384 – (m + 1)) H H L H H (16384 – m)[3] to 16383 H L L H H 16384 L L L H H Notes 2. n = Empty Offset (Default Values: CY7C4265 n = 127). 3. m = Full Offset (Default Values: CY7C4265 n = 127). Document Number: 38-06004 Rev. *K Page 6 of 26

CY7C4265 Width Expansion Configuration The CY7C4265 can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing the Empty (Full) flags of every FIFO; the PAE and PAF flags can be detected from any one device. This technique avoids reading data from, or writing data to the FIFO that is “staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure2 demonstrates a 36-word width by using two CY7C4265s. Figure 2. Block Diagram of 8K × 18/16K × 18 Synchronous FIFO Memory Used in a Width Expansion Configuration RESET(RS) RESET(RS) DATA IN(D) 36 18 18 READ CLOCK (RCLK) WRITE CLOCK(WCLK) READ ENABLE (REN) WRITEENABLE(WEN) OUTPUT ENABLE (OE) LOAD(LD) PROGRAMMABLE (PAF) PROGRAMMABLE(PAE) 7C4265 7C4265 HALF FULL FLAG (HF) EMPTY FLAG(EF) FF EF FF EF FULL FLAG (FF) 18 DATA OUT(Q) 36 18 FIRST LOAD(FL) WRITE EXPANSIONIN(WXI) READ EXPANSIONIN(RXI) Depth Expansion Configuration (with Programmable Flags) The CY7C4265 can easily be adapted to applications requiring more than 16384 words of buffering. Figure 3 on page 8 shows Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these steps: 1.The first device must be designated by grounding the First Load (FL) control input. 2.All other devices must have FL in the HIGH state. 3.The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device. 4.The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device. 5.All Load (LD) pins are tied together. 6.The Half-Full Flag (HF) is not available in the Depth Expansion Configuration. 7.EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite PAE and PAF flags are not precise. Document Number: 38-06004 Rev. *K Page 7 of 26

CY7C4265 Figure 3. Block Diagram of 16K × 18 Synchronous FIFO Memory with Programmable Flags used in Depth Expansion Configuration WXO RXO 7C4265 V CC FL FF EF PAF PAE WXI RXI WXO RXO DATA IN(D) 7C4265 DATA OUT(Q) V CC FL FF EF PAF PAE WXI RXI WRITECLOCK(WCLK) WXO RXO READCLOCK(RCLK) WRITEENABLE(WEN) READENABLE(REN) RESET(RS) 7C4265 OUTPUTENABLE(OE) LOAD(LD) FF EF FF EF PAF PAE PAF PAE WXI RXI FIRST LOAD(FL) Document Number: 38-06004 Rev. *K Page 8 of 26

CY7C4265 Typical AC and DC Characteristics Figure 4. Typical AC and DC Characteristics NORMALIZED tA vs. SUPPLY NORMALIZED tA vs. AMBIENT VOLTAGE TEMPERATURE 1.20 1.60 D tA 1.10 D tA 1.40 ZE ZE 1.20 LI 1.00 LI A A M M 1.00 R R O 0.90 O N TA= 25 °C N 0.80 VCC = 5.0 V 0.80 0.60 4.00 4.50 5.00 5.50 6.00 55.00 5.00 65.00 125.00 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. FREQUENCY 1.40 1.20 1.75 NORMALIZED ICC011...802000 VTf =AIN 2= =8 2 3M5. 0H° CVz NORMALIZED ICC011...901000 VVf =ICN C2 = 8= 3 M5.0.H0 V zV NORMALIZED ICC0111....70255050 VTC C= =2 55 .°0C V A 0.60 0.80 0.50 VIN = 3.0 V 4.00 4.50 5.00 5.50 6.00 55.00 5.00 65.00 125.00 20.00 30.00 40.00 50.00 60.00 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) FREQUENCY (MHz) Document Number: 38-06004 Rev. *K Page 9 of 26

CY7C4265 Maximum Ratings Output Current into Outputs (LOW) ............................20 mA Static Discharge Voltage Exceeding maximum ratings[4] may shorten the useful life of the (per MIL-STD-883, Method 3015) ...........................>2001 V device. User guidelines are not tested. Latch-up Current .....................................................>200 mA Storage Temperature ..............................–65 °C to +150 °C Operating Range Ambient Temperature with Power Applied .................................–55 °C to +125 °C Range Ambient Temperature [5] V CC Supply Voltage to Ground Potential .............–0.5 V to +7.0 V Commercial 0 °C to +70 °C 5 V  10% DC Voltage Applied to Outputs Industrial [6] –40 °C to +85 °C 5 V  10% in High Z State .............................................–0.5 V to +7.0 V DC Input Voltage 0.5 V to V +0.5 V CC Electrical Characteristics Over the Operating Range 7C4265-10 7C4265-15 Parameter [6] Description Test Conditions Unit Min Max Min Max V Output HIGH Voltage V = Min., 2.4 – 2.4 – V OH CC I = –2.0 mA OH V Output LOW Voltage V = Min., – 0.4 – 0.4 V OL CC I = 8.0 mA OL V [7] Input HIGH Voltage 2.0 V 2.0 V V IH CC CC V [7] Input LOW Voltage –0.5 0.8 –0.5 0.8 V IL I Input Leakage Current V = Max. –10 +10 –10 +10 A IX CC I Output OFF, High Z Current OE > V , –10 +10 –10 +10 A OZL IH I V < V < V OZH SS O CC I [8] Active Power Supply Current Commercial – 45 – 45 mA CC1 Industrial – 50 – 50 mA I [9] Average Standby Current Commercial – 10 – 10 mA CC2 Industrial – 15 – 15 mA Notes 4. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 5. TA is the “Instant On” case temperature. 6. See the last page of this specification for Group A subgroup testing information. 7. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous device or VSS. 8. Input signals switch from 0 V to 3 V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs are unloaded. ICC1(typical) = (25 mA + ((freq – 20 MHz) × (1.0 mA/MHz))). 9. All inputs = VCC – 0.2 V, except RCLK and WCLK (which are switching at frequency = 20 MHz), and FL/RT which is at VSS. All outputs are unloaded. Document Number: 38-06004 Rev. *K Page 10 of 26

CY7C4265 Capacitance Parameter [10, 11] Description Test Conditions Max Unit C Input capacitance T = 25 °C, f = 1 MHz, V = 5.0 V 5 pF IN A CC C Output capacitance 7 pF OUT AC Test Loads and Waveforms Figure 5. AC Test Loads and Waveforms [12, 13] R1 1.1 K ALL INPUT PULSES 5 V 3.0 V OUTPUT 90% 90% 10% GND 10% CL R2  3ns  3ns 680 INCLUDING JIGAND SCOPE Equivalentto: THÉV ENINEQUIVALENT 410 OUTPUT 1.91 V Notes 10.Tested initially and after any design changes that may affect these parameters. 11.Tested initially and after any process changes that may affect these parameters. 12.CL = 30 pF for all AC parameters except for tOHZ. 13.CL = 5 pF for tOHZ. Document Number: 38-06004 Rev. *K Page 11 of 26

CY7C4265 Switching Characteristics Over the Operating Range 7C4265-10 7C4265-15 Parameter Description Unit Min Max Min Max t Clock Cycle Frequency – 100 – 66.7 MHz S t Data Access Time 2 8 2 10 ns A t Clock Cycle Time 10 – 15 – ns CLK t Clock HIGH Time 4.5 – 6 – ns CLKH t Clock LOW Time 4.5 – 6 – ns CLKL t Data Setup Time 3 – 4 – ns DS t Data Hold Time 0.5 – 1 – ns DH t Enable Setup Time 3 – 4 – ns ENS t Enable Hold Time 0.5 – 1 – ns ENH t Reset Pulse Width[14] 10 – 15 – ns RS t Reset Recovery Time 8 – 10 – ns RSR t Reset to Flag and Output Time – 10 – 15 ns RSF t Retransmit Pulse Width 30 – 35 – ns PRT t Retransmit Recovery Time 60 – 65 – ns RTR t Output Enable to Output in Low Z[14] 0 – 0 – ns OLZ t Output Enable to Output Valid 3 7 3 8 ns OE t Output Enable to Output in High Z[15] 3 7 3 8 ns OHZ t Write Clock to Full Flag – 8 – 10 ns WFF t Read Clock to Empty Flag – 8 – 10 ns REF t Clock to Programmable Almost-Full Flag[15] (Asynchronous mode, – 12 – 16 ns PAFasynch V /SMODE tied to V ) CC CC t Clock to Programmable Almost-Full Flag (Synchronous mode, V /SMODE – 8 – 10 ns PAFsynch CC tied to V ) SS t Clock to Programmable Almost-Empty Flag[16] (Asynchronous mode, – 12 – 16 ns PAEasynch V /SMODE tied to V ) CC CC t Clock to Programmable Almost-Full Flag (Synchronous mode, V /SMODE – 8 – 10 ns PAEsynch CC tied to V ) SS t Clock to Half-Full Flag – 12 – 16 ns HF t Clock to Expansion Out – 6 – 10 ns XO t Expansion in Pulse Width 4.5 – 6.5 – ns XI t Expansion in Set-Up Time 4 – 5 – ns XIS t Skew Time between Read Clock and Write Clock for Full Flag 5 – 6 – ns SKEW1 t Skew Time between Read Clock and Write Clock for Empty Flag 5 – 6 – ns SKEW2 t Skew Time between Read Clock and Write Clock for Programmable Almost 10 – 15 – ns SKEW3 Empty and Programmable Almost Full Flags (Synchronous Mode only) Notes 14.Pulse widths less than minimum values are not enabled. 15.Values guaranteed by design, not currently tested. 16.tPAFasynch, tPAEasynch, after program register write is not be valid until 5 ns + tPAF(E). Document Number: 38-06004 Rev. *K Page 12 of 26

CY7C4265 Switching Waveforms Figure 6. Write Cycle Timing tCLK tCLKH tCLKL WCLK tDS tDH D0–D17 tENS tENH WEN NO OPERATION tWFF tWFF FF tSKEW1[17] RCLK REN Figure 7. Read Cycle Timing tCLK tCLKH tCLKL RCLK tENS tENH REN NO OPERATION tREF tREF EF tA Q0–Q17 VALID DATA tOLZ tOE tOHZ OE [18] tSKEW2 WCLK WEN Notes 17.tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge. 18.tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge. Document Number: 38-06004 Rev. *K Page 13 of 26

CY7C4265 Switching Waveforms (continued) Figure 8. Reset Timing [19] tRS RS tRSR REN,WEN, LD tRSF EF,PAE tRSF FF,PAF, HF tRSF [20] OE = 1 Q –Q 0 17 OE = 0 Figure 9. First Data Word Latency after Reset with Simultaneous Read and Write WCLK tDS D0–D17 D0(FIRSTVALIDWRITE) D1 D2 D3 D4 tENS [21] WEN tFRL tSKEW2 RCLK tREF EF REN [22] tA tA Q0–Q17 D0 D1 tOLZ tOE OE Notes 19.The clocks (RCLK, WCLK) can be free-running during reset. 20.After reset, the outputs are LOW if OE = 0 and three-state if OE = 1. 21.When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW). 22.The first word is available the cycle after EF goes HIGH, always. Document Number: 38-06004 Rev. *K Page 14 of 26

CY7C4265 Switching Waveforms (continued) Figure 10. Empty Flag Timing WCLK tDS tDS D0–D17 D0 D1 tENS tENH tENS tENH WEN tFRL[23] tFRL[23] RCLK tSKEW2 tREF tREF tSKEW2 tREF EF REN OE tA Q0–Q17 D0 Note 23.When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW). Document Number: 38-06004 Rev. *K Page 15 of 26

CY7C4265 Switching Waveforms (continued) Figure 11. Full Flag Timing NO WRITE NO WRITE WCLK [24] tSKEW1 tDS tSKEW1[24] DATA WRITE D0–D17 DATA WRITE tWFF tWFF tWFF FF WEN RCLK tENH tENH tENS tENS REN LOW OE tA tA Q0–Q17 DATA IN OUTPUT REGISTER DATA READ NEXT DATA READ Figure 12. Half-Full Flag Timing tCLKH tCLKL WCLK tENS tENH WEN tHF HALF FULL + 1 HF HALF FULLORLESS OR MORE HALF FULLORLESS tHF RCLK tENS REN Note 24.tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge. Document Number: 38-06004 Rev. *K Page 16 of 26

CY7C4265 Switching Waveforms (continued) Figure 13. Programmable Almost Empty Flag Timing tCLKH tCLKL WCLK tENS tENH WEN tPAE PAE[25] N + 1 WORDS n WORDS IN FIFO IN FIFO tPAE RCLK tENS REN Figure 14. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)) tCLKH tCLKL WCLK tENS tENH WEN WEN2 tENS tENH Note 26 PAE N+ 1 WORDS INFIFO Note tSKEW3[27] tPAE synch 28 tPAE synch RCLK tENS tENS tENH REN Note 25.PAE is offset = n. Number of data words into FIFO already = n. 26.PAE offset n. 27.tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK. 28.If a read is preformed on this rising edge of the read clock, there are Empty + (n1) words in the FIFO when PAE goes LOW. Document Number: 38-06004 Rev. *K Page 17 of 26

CY7C4265 Switching Waveforms (continued) Figure 15. Programmable Almost Full Flag Timing tCLKH tCLKL Note 29 WCLK tENS tENH WEN tPAF FULL– M WORDS PAF[30] INFIFO[31] FULL– (M+1) WORDS [32] IN FIFO tPAF RCLK tENS REN Figure 16. Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW)) tCLKH tCLKL Note 33 WCLK tENS tENH WEN Note 34 WEN2 tENS tENH tPAF FULL– M WORDS PAF FULL– M + 1 WORDS IN FIFO [31] IN FIFO tSKEW3[35] tPAF synch RCLK tENS tENS tENH REN Notes 29.PAF offset = m. Number of data words written into FIFO already = 16384 (m + 1) for the CY7C4265. 30.PAF is offset = m. 31.16384 – m words in CY7C4265. 32.16384 – (m + 1) CY7C4265. 33.If a write is performed on this rising edge of the write clock, there are Full  (m 1) words of the FIFO when PAF goes LOW. 34.PAF offset = m. 35.tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge. Document Number: 38-06004 Rev. *K Page 18 of 26

CY7C4265 Switching Waveforms (continued) Figure 17. Write Programmable Registers tCLK tCLKH tCLKL WCLK tENS tENH LD tENS WEN tDS tDH PAE OFFSET D0–D17 PAE OFFSET PAF OFFSET D0– D11 Figure 18. Read Programmable Registers tCLK tCLKH tCLKL RCLK tENS tENH LD tENS WEN tA Q0–Q17 UNKNOWN PAE OFFSET PAF OFFSET PAE OFFSET Figure 19. Write Expansion Out Timing tCLKH WCLK Note 36 tXO Note 36 WXO tXO tENS WEN Note 36.Write to Last Physical Location. Document Number: 38-06004 Rev. *K Page 19 of 26

CY7C4265 Switching Waveforms (continued) Figure 20. Read Expansion Out Timing tCLKH WCLK Note 37 tXO RXO tXO tENS REN Figure 21. Write Expansion In Timing tXI WXI tXIS WCLK Figure 22. Read Expansion In Timing tXI RXI tXIS RCLK Figure 23. Retransmit Timing [38, 39, 40] FL/RT tPRT tRTR REN/WEN EF/FF and all async flags HF/PAE/PAF Notes 37.Read from Last Physical Location. 38.Clocks are free-running in this case. 39.The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags are valid at tRTR. 40.For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags. Document Number: 38-06004 Rev. *K Page 20 of 26

CY7C4265 Ordering Information 16K × 18 Deep Sync FIFO Speed Package Operating Package Type (ns) Ordering Code Diagram Range 10 CY7C4265-10ASXC 51-85051 64-pin Small TQFP (Pb-free) Commercial CY7C4265-10AXI 51-85046 64-pin TQFP (Pb-free) Industrial 15 CY7C4265-15AXC 51-85046 64-pin TQFP (Pb-free) Commercial Ordering Code Definitions CY 7 C 4 26 5 - XX XX X X Temperature Range: C = C or I C = Commercial; I = Industrial X = Pb-free (RoHS Compliant) Package Type: XX = AS or A AS = 64-pin Small TQFP; A = 64-pin TQFP Speed Grade: XX = 10 or 15 10 = 10 ns; 15 = 15 ns Width: 5 = × 18 Depth: 26 = 16K Family Code: 4 = FIFO Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-06004 Rev. *K Page 21 of 26

CY7C4265 Package Diagrams Figure 24. 64-pin TQFP (10 × 10 × 1.4 mm) A64SB Package Outline, 51-85051 51-85051 *D Document Number: 38-06004 Rev. *K Page 22 of 26

CY7C4265 Package Diagrams (continued) Figure 25. 64-pin TQFP (14 × 14 × 1.4 mm) A64SA Package Outline, 51-85046 (cid:537) 1 (cid:537) (cid:537) 2 DIMENSIONS NOTE: SYMBOL MIN.NOM.MAX. 1. JEDEC STD REF MS-026 A 1.60 2. BODY LENGTH DIMENSION DOES NOT A1 0.05 0.15 INCLUDE MOLD PROTRUSION/END FLASH A2 1.35 1.40 1.45 MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE D 15.7516.0016.25 BODY LENGTH DIMENSIONS ARE MAX PLASTIC D1 13.9514.0014.05 BODY SIZE INCLUDING MOLD MISMATCH E 15.7516.0016.25 3. DIMENSIONS IN MILLIMETERS E1 13.9514.0014.05 R1 0.08 0.20 R2 0.08 0.20 (cid:537) 0° 7° (cid:537)1 0° (cid:537)2 11° 12° 13° c 0.20 b 0.30 0.35 0.40 L 0.45 0.60 0.75 L1 1.00 REF L2 0.25 BSC L3 0.20 e 0.80 TYP 51-85046 *H Document Number: 38-06004 Rev. *K Page 23 of 26

CY7C4265 Acronyms Document Conventions Acronym Description Units of Measure BGA Ball Grid Array Symbol Unit of Measure FS Frequency Select °C degree Celsius I/O Input/Output KHz kilohertz LVPECL Low Voltage Positive Emitter Coupled Logic K kilohm LVTTL Low Voltage Transistor-Transistor Logic MHz megahertz PLL Phase-Locked Loop µA microampere TQFP Thin Quad Flat Pack mA milliampere TTL Transistor-Transistor Logic ms millisecond VCO Voltage Controlled Oscillator mV millivolt ns nanosecond  ohm % percent pF picofarad ps picosecond V volt W watt Document Number: 38-06004 Rev. *K Page 24 of 26

CY7C4265 Document History Page Document Title: CY7C4265, 16K × 18 Deep Sync FIFOs Document Number: 38-06004 Orig. of Submission Revision ECN Description of Change Change Date ** 106465 SZV 07/11/2001 Changed Spec Number from 38-00468 to 38-06004. *A 122257 RBI 12/26/2002 Updated Maximum Ratings: Added Note 4 and referred the same note in “maximum ratings”. *B 252889 YDT 08/12/2004 Removed 64-pin PLCC package related information in all instances across the document. Updated Ordering Information: Updated part numbers. *C 385985 ESH 08/04/2005 Added Pb-Free logo to top of first page. Updated Ordering Information: Updated part numbers. *D 2623658 VKN / 12/17/2008 Removed Pb-Free logo to top of first page. PYRS Added CY7C4265A part related information in all instances across the document. Updated Ordering Information: Updated part numbers. Updated to new template. *E 2714768 VKN / 06/04/2009 Updated Logic Block Diagram. AESA Updated Pin Configurations: Updated Figure1. *F 2896039 RAME 03/19/2010 Updated Document Title to read as “CY7C4265, 16 K × 18 Deep Sync FIFOs”. Updated Ordering Information: Updated part numbers. Updated Package Diagrams: spec 51-85051 – Changed revision from *A to *B. spec 51-85046 – Changed revision from *B to *D. *G 3094385 ADMU 11/24/2010 Updated Ordering Information: No change in part numbers. Added Ordering Code Definitions. Completing Sunset Review. *H 3452178 ADMU 12/01/2011 Removed CY7C4255 part related information in all instances across the document. Removed -25 and -35 speed bins related information in all instances across the document. Updated Package Diagrams: spec 51-85051 – Changed revision from *B to *C. spec 51-85046 – Changed revision from *D to *E. Completing Sunset Review. *I 4197278 ADMU 11/20/2013 Updated Ordering Information: Updated part numbers. Updated to new template. Completing Sunset Review. *J 4575241 ADMU 11/19/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Package Diagrams: spec 51-85046 – Changed revision from *E to *F. Completing Sunset Review. *K 6072279 VINI 02/15/2018 Updated Package Diagrams: spec 51-85051 – Changed revision from *C to *D. spec 51-85046 – Changed revision from *F to *H. Updated to new template. Document Number: 38-06004 Rev. *K Page 25 of 26

CY7C4265 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions Arm® Cortex® Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Community | Projects | Video | Blogs | Training | Components Interface cypress.com/interface Technical Support Internet of Things cypress.com/iot cypress.com/support Memory cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless © Cypress Semiconductor Corporation, 2001-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-06004 Rev. *K Revised February 15, 2018 Page 26 of 26