CY7C2663KV18/CY7C2665KV18 ® 144-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations ■Separate independent read and write data ports With Read Cycle Latency of 2.5 cycles: ❐Supports concurrent transactions CY7C2663KV18: 8M × 18 ■550-MHz clock for high bandwidth CY7C2665KV18: 4M × 36 ■Four-word burst for reducing address bus frequency Functional Description ■Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz The CY7C2663KV18, and CY7C2665KV18 are 1.8V ■Available in 2.5-clock cycle latency synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture ■Two input clocks (K and K) for precise DDR timing consists of two separate ports: the read port and the write port to ❐Static random access memory (SRAM) uses rising edges access the memory array. The read port has dedicated data only outputs to support read operations and the write port has ■Echo clocks (CQ and CQ) simplify data capture in high-speed dedicated data inputs to support write operations. QDR II+ systems architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that ■Data valid pin (QVLD) to indicate valid data on the output exists with common I/O devices. Each port is accessed through ■On-die termination (ODT) feature a common address bus. Addresses for read and write addresses ❐Supported for D , BWS , and K/K inputs are latched on alternate rising edges of the input (K) clock. [x:0] [x:0] Accesses to the QDR II+ read and write ports are completely ■Single multiplexed address input bus latches address inputs independent of one another. To maximize data throughput, both for read and write ports read and write ports are equipped with DDR interfaces. Each ■Separate port selects for depth expansion address location is associated with four 18-bit words (CY7C2663KV18), or 36-bit words (CY7C2665KV18) that burst ■Synchronous internally self-timed writes sequentially into or out of the device. Because data is transferred ■Quad data rate (QDR®) II+ operates with 2.5-cycle read latency into and out of the device on every rising edge of both input when DOFF is asserted high clocks (K and K), memory bandwidth is maximized while simplifying system design by eliminating bus “turn arounds”. ■Operates similar to QDR I device with 1 cycle read latency when DOFF is asserted low These devices have an ODT feature supported for D[x:0], BWS , and K/K inputs, which helps eliminate external ■Available in × 18, and × 36 configurations [x:0] termination resistors, reduce cost, reduce board area, and ■Full data coherency, providing most current data simplify board routing. ■Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD [1] Depth expansion is accomplished with port selects, which ❐Supports both 1.5 V and 1.8 V I/O supply enables each port to operate independently. ■High-speed transceiver logic (HSTL) inputs and variable drive All synchronous inputs pass through input registers controlled by HSTL output buffers the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are ■Available in 165-ball fine-pitch ball grid array (FBGA) package conducted with on-chip synchronous self-timed write circuitry. (15 × 17 × 1.4 mm) For a complete list of related documentation, click here. ■Offered in both Pb-free and non Pb-free packages ■JTAG 1149.1 compatible test access port ■Phase locked loop (PLL) for accurate data placement Selection Guide Description 550 MHz 450 MHz Unit Maximum operating frequency 550 450 MHz Maximum operating current × 18 1090 940 mA × 36 1520 1290 Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD. CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-44141 Rev. *Q Revised November 24, 2017

CY7C2663KV18/CY7C2665KV18 Logic Block Diagram – CY7C2663KV18 18 D [17:0] Write Write Write Write 21 Reg Reg Reg Reg Address A(20:0) 21 Address Register A(20:0) Register code 2M 2M 2M 2M code De × × × × De K Add. 18 A 18 A 18 A 18 A Add. RPS K CGLeKn. Write rray rray rray rray Read CLoongtircol DOFF Read Data Reg. CQ 72 VREF 36 18 CQ Reg. Reg. Control WPS 18 Logic BWS[1:0] 36 Reg. 18 18 Q[17:0] 18 QVLD Logic Block Diagram – CY7C2665KV18 36 D [35:0] Write Write Write Write 20 Reg Reg Reg Reg Address A(19:0) 20 Address Register A(19:0) Register code 1M 1M 1M 1M code De × × × × De d. 36 36 36 36 d. K Ad A A A A Ad RPS K CGLeKn. Write rray rray rray rray Read CLoongtircol DOFF Read Data Reg. CQ 144 VREF 72 Reg. Reg. 36 CQ Control WPS 36 Logic BWS[3:0] 72 Reg. 36 36 Q[35:0] 36 QVLD Document Number: 001-44141 Rev. *Q Page 2 of 31

CY7C2663KV18/CY7C2665KV18 Contents Pin Configurations ...........................................................4 Scan Register Sizes .......................................................18 Pin Definitions ..................................................................5 Instruction Codes ...........................................................18 Functional Overview ........................................................6 Boundary Scan Order ....................................................19 Read Operations .........................................................6 Power-Up Sequence in QDR II+ SRAM .........................20 Write Operations .........................................................6 Power-Up Sequence .................................................20 Byte Write Operations .................................................7 PLL Constraints .........................................................20 Concurrent Transactions .............................................7 Maximum Ratings ...........................................................21 Depth Expansion .........................................................7 Operating Range .............................................................21 Programmable Impedance ..........................................7 Neutron Soft Error Immunity .........................................21 Echo Clocks ................................................................7 Electrical Characteristics ...............................................21 Valid Data Indicator (QVLD) ........................................7 DC Electrical Characteristics .....................................21 On-Die Termination (ODT) ..........................................7 AC Electrical Characteristics .....................................23 PLL ..............................................................................7 Capacitance ....................................................................23 Application Example ........................................................8 Thermal Resistance ........................................................23 Truth Table ........................................................................9 AC Test Loads and Waveforms .....................................23 Write Cycle Descriptions ...............................................10 Switching Characteristics ..............................................24 Write Cycle Descriptions ...............................................11 Switching Waveforms ....................................................25 IEEE 1149.1 Serial Boundary Scan (JTAG) ..................12 Read/Write/Deselect Sequence ................................25 Disabling the JTAG Feature ......................................12 Ordering Information ......................................................26 Test Access Port .......................................................12 Ordering Code Definitions .........................................26 Performing a TAP Reset ...........................................12 Package Diagram ............................................................27 TAP Registers ...........................................................12 Acronyms ........................................................................28 TAP Instruction Set ...................................................12 Document Conventions .................................................28 TAP Controller State Diagram .......................................14 Units of Measure .......................................................28 TAP Controller Block Diagram ......................................15 Document History Page .................................................29 TAP Electrical Characteristics ......................................15 Sales, Solutions, and Legal Information ......................31 TAP AC Switching Characteristics ...............................16 Worldwide Sales and Design Support .......................31 TAP Timing and Test Conditions ..................................17 Identification Register Definitions ................................18 Document Number: 001-44141 Rev. *Q Page 3 of 31

CY7C2663KV18/CY7C2665KV18 Pin Configurations The pin configurations for CY7C2663KV18, and CY7C2665KV18 follow. [2] Figure 1. 165-ball FBGA (15 × 17 × 1.4 mm) pinout CY7C2663KV18 (8M × 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ A A WPS BWS K NC/288M RPS A A CQ 1 B NC Q9 D9 A NC K BWS A NC NC Q8 0 C NC NC D10 V A NC A V NC Q7 D8 SS SS D NC D11 Q10 V V V V V NC NC D7 SS SS SS SS SS E NC NC Q11 V V V V V NC D6 Q6 DDQ SS SS SS DDQ F NC Q12 D12 V V V V V NC NC Q5 DDQ DD SS DD DDQ G NC D13 Q13 V V V V V NC NC D5 DDQ DD SS DD DDQ H DOFF V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J NC NC D14 V V V V V NC Q4 D4 DDQ DD SS DD DDQ K NC NC Q14 V V V V V NC D3 Q3 DDQ DD SS DD DDQ L NC Q15 D15 V V V V V NC NC Q2 DDQ SS SS SS DDQ M NC NC D16 V V V V V NC Q1 D2 SS SS SS SS SS N NC D17 Q16 V A A A V NC NC D1 SS SS P NC NC Q17 A A QVLD A A NC D0 Q0 R TDO TCK A A A ODT A A A TMS TDI CY7C2665KV18 (4M × 36) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/288M A WPS BWS K BWS RPS A A CQ 2 1 B Q27 Q18 D18 A BWS K BWS A D17 Q17 Q8 3 0 C D27 Q28 D19 V A NC A V D16 Q7 D8 SS SS D D28 D20 Q19 V V V V V Q16 D15 D7 SS SS SS SS SS E Q29 D29 Q20 V V V V V Q15 D6 Q6 DDQ SS SS SS DDQ F Q30 Q21 D21 V V V V V D14 Q14 Q5 DDQ DD SS DD DDQ G D30 D22 Q22 V V V V V Q13 D13 D5 DDQ DD SS DD DDQ H DOFF V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J D31 Q31 D23 V V V V V D12 Q4 D4 DDQ DD SS DD DDQ K Q32 D32 Q23 V V V V V Q12 D3 Q3 DDQ DD SS DD DDQ L Q33 Q24 D24 V V V V V D11 Q11 Q2 DDQ SS SS SS DDQ M D33 Q34 D25 V V V V V D10 Q1 D2 SS SS SS SS SS N D34 D26 Q25 V A A A V Q10 D9 D1 SS SS P Q35 D35 Q26 A A QVLD A A Q9 D0 Q0 R TDO TCK A A A ODT A A A TMS TDI Note 2. NC/288M is not connected to the die and can be tied to any voltage level. Document Number: 001-44141 Rev. *Q Page 4 of 31

CY7C2663KV18/CY7C2665KV18 Pin Definitions Pin Name I/O Pin Description D[x:0] Input- Data input signals. Sampled on the rising edge of K and K clocks when valid write operations are active. synchronous CY7C2663KV18  D [17:0] CY7C2665KV18  D [35:0] WPS Input- Write port select  Active low. Sampled on the rising edge of the K clock. When asserted active, a synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D . [x:0] BWS0, Input- Byte write select (BWS) 0, 1, 2, and 3  Active low. Sampled on the rising edge of the K and K clocks BWS1, synchronous when write operations are active. Used to select which byte is written into the device during the current BWS2, portion of the write operations. Bytes not written remain unaltered. BWS3 CY7C2663KV18  BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C2665KV18  BWS controls D , BWS controls D , 0 [8:0] 1 [17:9] BWS controls D and BWS controls D 2 [26:18] 3 [35:27]. All the BWs pins are sampled on the same edge as the data. Deselecting a BWS ignores the corresponding byte of data and it is not written into the device. A Input- Address inputs. Sampled on the rising edge of the K clock during active read and write operations. synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 8M × 18 (4 arrays each of 2M × 18) for CY7C2663KV18 and 4M × 36 (4 arrays each of 1M × 36) for CY7C2665KV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C2663KV18 and 20 address inputs for CY7C2665KV18. These inputs are ignored when the appropriate port is deselected. Q Outputs- Data output signals. These pins drive out the requested data when the read operation is active. Valid [x:0] synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the read port, Q are automatically tri-stated. [x:0] CY7C2663KV18  Q [17:0] CY7C2665KV18  Q [35:0] RPS Input- Read port select  Active low. Sampled on the rising edge of positive input clock (K). When active, a synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the K clock. Each read access consists of a burst of four sequential transfers. QVLD Valid output Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ. indicator ODT [3] ODT input pin ODT input. This pin is used for ODT of the input signals. ODT range selection is made during power-up initialization. A low on this pin selects a low range that follows RQ/3.33 for 175 < RQ < 350 (where RQ is the resistor tied to ZQ pin)A HIGH on this pin selects a high range that follows RQ/1.66 for 175<RQ < 250 (where RQ is the resistor tied to ZQ pin). When left floating, a high range termination value is selected by default. K Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q . All accesses are initiated on the rising edge of K. [x:0] K Input clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q . [x:0] CQ Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 24. CQ Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR II+.The timings for the echo clocks are shown in the Switching Characteristics on page 24. ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q output impedance are set to 0.2 × RQ, where RQ is a resistor [x:0] connected between ZQ and ground. Alternatively, this pin can be connected directly to V , which DDQ enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. Note 3. On-Die Termination (ODT) feature is supported for D[x:0], BWS[x:0], and K/K inputs. Document Number: 001-44141 Rev. *Q Page 5 of 31

CY7C2663KV18/CY7C2665KV18 Pin Definitions Pin Name I/O Pin Description DOFF Input PLL turn-off  Active low. Connecting this pin to ground turns off the PLL inside the device. The timings in the PLL turned off operation differs from those listed in this datasheet. For normal operation, this pin can be connected to a pull-up through a 10 k or less pull-up resistor. The device behaves in QDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167MHz with QDR I timing. TDO Output Test data out (TDO) pin for JTAG. TCK Input Test clock (TCK) pin for JTAG. TDI Input Test data in (TDI) pin for JTAG. TMS Input Test mode select (TMS) pin for JTAG. NC N/A Not connected to the die. Can be tied to any voltage level. NC/288M N/A Not connected to the die. Can be tied to any voltage level. V Input- Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC REF reference measurement points. V Power supply Power supply inputs to the core of the device. DD V Ground Ground for the device. SS V Power supply Power supply inputs for the outputs of the device. DDQ Functional Overview RPSactive at the rising edge of the positive input clock (K). The address presented to the address inputs is stored in the read The CY7C2663KV18, CY7C2665KV18 are synchronous address register. Following the next two K clock rise, the pipelined burst SRAMs equipped with a read port and a write corresponding lowest order 18-bit word of data is driven onto the port. The read port is dedicated to read operations and the write Q[17:0] using K as the output timing reference. On the port is dedicated to write operations. Data flows into the SRAM subsequent rising edge of K, the next 18-bit data word is driven through the write port and flows out through the read port. These onto the Q[17:0]. This process continues until all four 18-bit data devices multiplex the address inputs to minimize the number of words have been driven out onto Q[17:0]. The requested data is address pins required. By having separate read and write ports, valid 0.45 ns from the rising edge of the input clock (K or K). To the QDR II+ eliminates the need to “turnaround” the data bus and maintain the internal logic, each read access must be allowed to avoids any possible data contention, thereby simplifying system complete. Each read access consists of four 18-bit data words design. Each access consists of four 18-bit data transfers in the and takes two clock cycles to complete. Therefore, read case of CY7C2663KV18, and four 36-bit data transfers in the accesses to the device can not be initiated on two consecutive case of CY7C2665KV18, in two clock cycles. K clock rises. The internal logic of the device ignores the second read request. Read accesses can be initiated on every other K These devices operate with a read latency of two and half cycles clock rise. Doing so pipelines the data flow such that data is when DOFF pin is tied high. When DOFF pin is set low or transferred out of the device on every rising edge of the input connected to V then device behaves in QDR I mode with a SS clocks (K and K). read latency of one clock cycle. When the read port is deselected, the CY7C2663KV18 first Accesses for both ports are initiated on the positive input clock completes the pending read transactions. Synchronous internal (K). All synchronous input and output timing are referenced from circuitry automatically tri-states the outputs following the next the rising edge of the input clocks (K and K). rising edge of the negative input clock (K). This enables for a All synchronous data inputs (D[x:0]) pass through input registers seamless transition between devices without the insertion of wait controlled by the input clocks (K and K). All synchronous data states in a depth expanded memory. outputs (Q ) outputs pass through output registers controlled [x:0] by the rising edge of the input clocks (K and K) as well. Write Operations All synchronous control (RPS, WPS, BWS ) inputs pass Write operations are initiated by asserting WPS active at the [x:0] through input registers controlled by the rising edge of the input rising edge of the positive input clock (K). On the following K clocks (K and K). clock rise the data presented to D is latched and stored into [17:0] the lower 18-bit write data register, provided BWS are both CY7C2663KV18 is described in the following sections. The [1:0] asserted active. On the subsequent rising edge of the negative same basic descriptions apply to CY7C2665KV18. input clock (K) the information presented to D is also stored [17:0] Read Operations into the write data register, provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit The CY7C2663KV18 is organized internally as four arrays of words (a total of 72 bits) of data are stored in the SRAM. The 2M×18. Accesses are completed in a burst of four sequential 72bits of data are then written into the memory array at the 18-bit data words. Read operations are initiated by asserting specified location. Therefore, write accesses to the device can Document Number: 001-44141 Rev. *Q Page 6 of 31

CY7C2663KV18/CY7C2665KV18 not be initiated on two consecutive K clock rises. The internal driver impedance. The value of RQ must be 5 × the value of the logic of the device ignores the second write request. Write intended line impedance driven by the SRAM, the allowable accesses can be initiated on every other rising edge of the range of RQ to guarantee impedance matching with a tolerance positive input clock (K). Doing so pipelines the data flow such of ±15% is between 175  and 350 , with VDDQ=1.5 V. The that 18 bits of data can be transferred into the device on every output impedance is adjusted every 1024 cycles upon power-up rising edge of the input clocks (K and K). to account for drifts in supply voltage and temperature. When deselected, the write port ignores all inputs after the Echo Clocks pending write operations have been completed. Echo clocks are provided on the QDR II+ to simplify data capture Byte Write Operations on high-speed systems. Two echo clocks are generated by the QDR II+. CQ is referenced with respect to K and CQ is Byte write operations are supported by the CY7C2663KV18. A referenced with respect to K. These are free-running clocks and write operation is initiated as described in the section Write are synchronized to the input clock of the QDR II+. The timing Operations on page 6. The bytes that are written are determined for the echo clocks is shown in the Switching Characteristics on by BWS and BWS , which are sampled with each set of 18-bit 0 1 page 24. data words. Asserting the appropriate BWS input during the data portion of a write latches the data being presented and writes it Valid Data Indicator (QVLD) into the device. Deasserting the BWS input during the data portion of a write enables the data stored in the device for that QVLD is provided on the QDR II+ to simplify data capture on byte to remain unaltered. This feature can be used to simplify high-speed systems. The QVLD is generated by the QDR II+ read, modify, or write operations to a byte write operation. device along with data output. This signal is also edge-aligned with the echo clock and follows the timing of any data pin. This Concurrent Transactions signal is asserted half a cycle before valid data arrives. The read and write ports on the CY7C2663KV18 operate On-Die Termination (ODT) completely independently of one another. As each port latches the address inputs on different clock edges, the user can read or These devices have an ODT feature for data inputs (D[x:0]), byte write to any location, regardless of the transaction on the other write selects (BWS[x:0]), and input clocks (K and K). The port. If the ports access the same location when a read follows a termination resistors are integrated within the chip. The ODT write in successive clock cycles, the SRAM delivers the most range selection is enabled through ball R6 (ODT pin). The ODT recent information associated with the specified address termination tracks value of RQ where RQ is the resistor tied to location. This includes forwarding data from a write cycle that the ZQ pin. ODT range selection is made during power-up was initiated on the previous K clock rise. initialization. A low on this pin selects a low range that follows RQ/3.33 for 175 < RQ < 350 (where RQ is the resistor tied Read access and write access must be scheduled such that one to ZQ pin)A HIGH on this pin selects a high range that follows transaction is initiated on any clock cycle. If both ports are RQ/1.66 for 175 < RQ < 250 (where RQ is the resistor tied selected on the same K clock rise, the arbitration depends on the to ZQ pin). When left floating, a high range termination value is previous state of the SRAM. If both ports are deselected, the selected by default. For a detailed description of ODT read port takes priority. If a read was initiated on the previous implementation, refer to the application note, AN42468, On-Die cycle, the write port takes priority (as read operations can not be Termination for QDRII+/DDRII+ SRAMs. initiated on consecutive cycles). If a write was initiated on the previous cycle, the read port takes priority (as write operations PLL can not be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state results in alter- These chips use a PLL that is designed to function between nating read or write operations being initiated, with the first 120MHz and the specified maximum clock frequency. During access being a read. power-up, when the DOFF is tied high, the PLL is locked after 20s of stable clock. The PLL can also be reset by slowing or Depth Expansion stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the The CY7C2663KV18 has a port select input for each port. This desired frequency. The PLL automatically locks 20 s after a enables for easy depth expansion. Both port selects are sampled stable clock is presented. The PLL may be disabled by applying on the rising edge of the positive input clock only (K). Each port ground to the DOFF pin. When the PLL is turned off, the device select input can deselect the specified port. Deselecting a port behaves in QDR I mode (with one cycle latency and a longer does not affect the other port. All pending transactions (read and access time). write) are completed before the device is deselected. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V to allow the SRAM to adjust its output SS Document Number: 001-44141 Rev. *Q Page 7 of 31

CY7C2663KV18/CY7C2665KV18 Application Example Figure2 shows two QDR II+ used in an application. Figure 2. Application Example (Width Expansion) ZQ ZQ SRAM#1 SRAM#2 CQ/CQ CQ/CQ RQ RQ D[x:0] D[x:0] Q[x:0] Q[x:0] A RPS WPS BWS K K A RPS WPS BWS K K DATA IN[2x:0] DATA OUT [2x:0] ADDRESS RPS WPS BWS CLKIN1/CLKIN1 CLKIN2/CLKIN2 SOURCE K SOURCE K FPGA / ASIC Document Number: 001-44141 Rev. *Q Page 8 of 31

CY7C2663KV18/CY7C2665KV18 Truth Table The truth table for CY7C2663KV18, and CY7C2665KV18 follows. [4, 5, 6, 7, 8, 9] Operation K RPS WPS DQ DQ DQ DQ Write cycle: L–H H [10] L [11] D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2) Load address on the rising edge of K; input write data on two consecutive K and K rising edges. Read cycle: L–H L [11] X Q(A) at K(t + 2) Q(A + 1) at K(t + 3) Q(A + 2) at K(t + 3) Q(A + 3) at K(t + 4) (2.5 cycle Latency) Load address on the rising edge of K; wait two and half cycles; read data on two consecutive K and K rising edges. NOP: No operation L–H H H D = X D = X D = X D = X Q = High Z Q = High Z Q = High Z Q = High Z Standby: Clock stopped Stopped X X Previous state Previous state Previous state Previous state Notes 4. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 5. Device powers up deselected with the outputs in a tri-state condition. 6. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst. 7. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle. 8. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well. 9. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 10.If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation. 11.This signal was high on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the second read or write request. Document Number: 001-44141 Rev. *Q Page 9 of 31

CY7C2663KV18/CY7C2665KV18 Write Cycle Descriptions The write cycle description table for CY7C2663KV18 follows. [12, 13] BWS0/ BWS1/ K K Comments L L L–H – During the data portion of a write sequence CY7C2663KV18 both bytes (D ) are written into the device. [17:0] L L – L–H During the data portion of a write sequence: CY7C2663KV18 both bytes (D ) are written into the device. [17:0] L H L–H – During the data portion of a write sequence: CY7C2663KV18 only the lower byte (D ) is written into the device, D remains unaltered. [8:0] [17:9] L H – L–H During the data portion of a write sequence CY7C2663KV18 only the lower byte (D ) is written into the device, D remains unaltered. [8:0] [17:9] H L L–H – During the data portion of a write sequence: CY7C2663KV18 only the upper byte (D ) is written into the device, D remains unaltered. [17:9] [8:0] H L – L–H During the data portion of a write sequence: CY7C2663KV18 only the upper byte (D ) is written into the device, D remains unaltered. [17:9] [8:0] H H L–H – No data is written into the devices during this portion of a write operation. H H – L–H No data is written into the devices during this portion of a write operation. Notes 12.X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 13.Is based on a write cycle that was initiated in accordance with the Truth Table on page 9. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-44141 Rev. *Q Page 10 of 31

CY7C2663KV18/CY7C2665KV18 Write Cycle Descriptions The write cycle description table for CY7C2665KV18 follows. [14, 15] BWS BWS BWS BWS K K Comments 0 1 2 3 L L L L L–H – During the data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. L L L L – L–H During the data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. L H H H L–H – During the data portion of a write sequence, only the lower byte (D ) is written [8:0] into the device. D remains unaltered. [35:9] L H H H – L–H During the data portion of a write sequence, only the lower byte (D ) is written [8:0] into the device. D remains unaltered. [35:9] H L H H L–H – During the data portion of a write sequence, only the byte (D ) is written into the [17:9] device. D and D remains unaltered. [8:0] [35:18] H L H H – L–H During the data portion of a write sequence, only the byte (D ) is written into the [17:9] device. D and D remains unaltered. [8:0] [35:18] H H L H L–H – During the data portion of a write sequence, only the byte (D ) is written into [26:18] the device. D and D remains unaltered. [17:0] [35:27] H H L H – L–H During the data portion of a write sequence, only the byte (D ) is written into [26:18] the device. D and D remains unaltered. [17:0] [35:27] H H H L L–H – During the data portion of a write sequence, only the byte (D ) is written into [35:27] the device. D remains unaltered. [26:0] H H H L – L–H During the data portion of a write sequence, only the byte (D ) is written into [35:27] the device. D remains unaltered. [26:0] H H H H L–H – No data is written into the device during this portion of a write operation. H H H H – L–H No data is written into the device during this portion of a write operation. Notes 14.X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 15.Is based on a write cycle that was initiated in accordance with the Truth Table on page 9. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-44141 Rev. *Q Page 11 of 31

CY7C2663KV18/CY7C2665KV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Instruction Register Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan test access register. This register is loaded when it is placed between the TDI port (TAP) in the FBGA package. This part is fully compliant with and TDO pins, as shown in TAP Controller Block Diagram on IEEE Standard #1149.1-2001. The TAP operates using JEDEC page 15. Upon power-up, the instruction register is loaded with standard 1.8 V I/O logic levels. the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described Disabling the JTAG Feature in the previous section. It is possible to operate the SRAM without using the JTAG When the TAP controller is in the Capture-IR state, the two least feature. To disable the TAP controller, TCK must be tied low significant bits are loaded with a binary “01” pattern to allow for (V ) to prevent clocking of the device. TDI and TMS are SS fault isolation of the board level serial test path. internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull-up resistor. TDO Bypass Register must be left unconnected. Upon power-up, the device comes up To save time when serially shifting data through registers, it is in a reset state, which does not interfere with the operation of the sometimes advantageous to skip certain chips. The bypass device. register is a single-bit register that can be placed between TDI Test Access Port and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set low (V ) when the SS Test Clock BYPASS instruction is executed. The test clock is used only with the TAP controller. All inputs are Boundary Scan Register captured on the rising edge of TCK. All outputs are driven from The boundary scan register is connected to all of the input and the falling edge of TCK. output pins on the SRAM. Several No Connect (NC) pins are also Test Mode Select (TMS) included in the scan register to reserve pins for higher density devices. The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left The boundary scan register is loaded with the contents of the unconnected if the TAP is not used. The pin is pulled up RAM input and output ring when the TAP controller is in the internally, resulting in a logic HIGH level. Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The Test Data-In (TDI) EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The The Boundary Scan Order on page 19 shows the order in which register between TDI and TDO is chosen by the instruction that the bits are connected. Each bit corresponds to one of the bumps is loaded into the TAP instruction register. For information on on the SRAM package. The MSB of the register is connected to loading the instruction register, see the TAP Controller State TDI, and the LSB is connected to TDO. Diagram on page 14. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is Identification (ID) Register connected to the most significant bit (MSB) on any register. The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is Test Data-Out (TDO) loaded in the instruction register. The IDCODE is hardwired into The TDO output pin is used to serially clock data out from the the SRAM and can be shifted out when the TAP controller is in registers. The output is active, depending upon the current state the Shift-DR state. The ID register has a vendor code and other of the TAP state machine (see Instruction Codes on page 18). information described in Identification Register Definitions on The output changes on the falling edge of TCK. TDO is page 18. connected to the least significant bit (LSB) of any register. TAP Instruction Set Performing a TAP Reset Eight different instructions are possible with the three-bit A Reset is performed by forcing TMS high (VDD) for five rising instruction register. All combinations are listed in Instruction edges of TCK. This Reset does not affect the operation of the Codes on page 18. Three of these instructions are listed as SRAM and can be performed while the SRAM is operating. At RESERVED and must not be used. The other five instructions power-up, the TAP is reset internally to ensure that TDO comes are described in this section in detail. up in a High Z state. Instructions are loaded into the TAP controller during the Shift-IR TAP Registers state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the Registers are connected between the TDI and TDO pins to scan instruction register through the TDI and TDO pins. To execute the data in and out of the SRAM test circuitry. Only one register the instruction after it is shifted in, the TAP controller must be can be selected at a time through the instruction registers. Data moved into the Update-IR state. is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-44141 Rev. *Q Page 12 of 31

CY7C2663KV18/CY7C2665KV18 IDCODE PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection The IDCODE instruction loads a vendor-specific, 32-bit code into of another boundary scan test operation. the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the The shifting of data for the SAMPLE and PRELOAD phases can device when the TAP controller enters the Shift-DR state. The occur concurrently when required, that is, while the data IDCODE instruction is loaded into the instruction register at captured is shifted out, the preloaded data can be shifted in. power-up or whenever the TAP controller is supplied a Test-Logic-Reset state. BYPASS When the BYPASS instruction is loaded in the instruction register SAMPLE Z and the TAP is placed in a Shift-DR state, the bypass register is The SAMPLE Z instruction connects the boundary scan register placed between the TDI and TDO pins. The advantage of the between the TDI and TDO pins when the TAP controller is in a BYPASS instruction is that it shortens the boundary scan path Shift-DR state. The SAMPLE Z command puts the output bus when multiple devices are connected together on a board. into a High Z state until the next command is supplied during the Update IR state. EXTEST The EXTEST instruction drives the preloaded data out through SAMPLE/PRELOAD the system output pins. This instruction also connects the SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When boundary scan register for serial access between the TDI and the SAMPLE/PRELOAD instructions are loaded into the TDO in the Shift-DR controller state. instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured EXTEST OUTPUT BUS TRI-STATE in the boundary scan register. IEEE Standard 1149.1 mandates that the TAP controller be able The user must be aware that the TAP controller clock can only to put the output bus into a tri-state mode. operate at a frequency up to 20 MHz, while the SRAM clock The boundary scan register has a special bit located at bit #108. operates more than an order of magnitude faster. Because there When this scan cell, called the “extest output bus tri-state,” is is a large difference in the clock frequencies, it is possible that latched into the preload register during the Update-DR state in during the Capture-DR state, an input or output undergoes a the TAP controller, it directly controls the state of the output transition. The TAP may then try to capture a signal while in (Q-bus) pins, when the EXTEST is entered as the current transition (metastable state). This does not harm the device, but instruction. When high, it enables the output buffers to drive the there is no guarantee as to the value that is captured. output bus. When low, this bit places the output bus into a HighZ Repeatable results may not be possible. condition. To guarantee that the boundary scan register captures the This bit can be set by entering the SAMPLE/PRELOAD or correct value of a signal, the SRAM signal must be stabilized EXTEST command, and then shifting the desired bit into that cell, long enough to meet the TAP controller’s capture setup plus hold during the Shift-DR state. During Update-DR, the value loaded times (tCS and tCH). The SRAM clock input might not be captured into that shift-register cell latches into the preload register. When correctly if there is no way in a design to stop (or slow) the clock the EXTEST instruction is entered, this bit directly controls the during a SAMPLE/PRELOAD instruction. If this is an issue, it is output Q-bus pins. Note that this bit is preset high to enable the still possible to capture all other signals and simply ignore the output when the device is powered up, and also when the TAP value of the CK and CK captured in the boundary scan register. controller is in the Test-Logic-Reset state. After the data is captured, it is possible to shift out the data by Reserved putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. These instructions are not implemented but are reserved for future use. Do not use these instructions. Document Number: 001-44141 Rev. *Q Page 13 of 31

CY7C2663KV18/CY7C2665KV18 TAP Controller State Diagram The state diagram for the TAP controller follows. [16] TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 1 SELECT 1 SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 PAUSE-DR 0 PAUSE-IR 0 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 Note 16.The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-44141 Rev. *Q Page 14 of 31

CY7C2663KV18/CY7C2665KV18 TAP Controller Block Diagram 0 Bypass Register 2 1 0 TDI Selection Instruction Register Selection TDO Circuitry Circuitry 31 30 29 . . 2 1 0 Identification Register 108 . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range Parameter [17, 18, 19] Description Test Conditions Min Max Unit V Output high voltage I =2.0 mA 1.4 – V OH1 OH V Output high voltage I =100 A 1.6 – V OH2 OH V Output low voltage I = 2.0 mA – 0.4 V OL1 OL V Output low voltage I = 100 A – 0.2 V OL2 OL V Input high voltage – 0.65 × V V + 0.3 V IH DD DD V Input low voltage – –0.3 0.35 × V V IL DD I Input and output load current GND  V  V –5 5 A X I DD Notes 17.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 21. 18.Overshoot: VIH(AC) < VDD + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2). 19.All voltage referenced to ground. Document Number: 001-44141 Rev. *Q Page 15 of 31

CY7C2663KV18/CY7C2665KV18 TAP AC Switching Characteristics Over the Operating Range Parameter [20, 21] Description Min Max Unit t TCK clock cycle time 50 – ns TCYC t TCK clock frequency – 20 MHz TF t TCK clock high 20 – ns TH t TCK clock low 20 – ns TL Setup Times t TMS setup to TCK clock rise 5 – ns TMSS t TDI setup to TCK clock rise 5 – ns TDIS t Capture setup to TCK rise 5 – ns CS Hold Times t TMS hold after TCK clock rise 5 – ns TMSH t TDI hold after clock rise 5 – ns TDIH t Capture hold after clock rise 5 – ns CH Output Times t TCK clock low to TDO valid – 10 ns TDOV t TCK clock low to TDO invalid 0 – ns TDOX Notes 20.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 21.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document Number: 001-44141 Rev. *Q Page 16 of 31

CY7C2663KV18/CY7C2665KV18 TAP Timing and Test Conditions Figure3 shows the TAP timing and test conditions. [22] Figure 3. TAP Timing and Test Conditions 0.9 V ALL INPUT PULSES 1.8 V 50  0.9 V TDO 0 V Z0= 50  CL= 20 pF (a) GND tTH tTL Test Clock TCK t TCYC t TMSH t TMSS Test Mode Select TMS t TDIS t TDIH Test Data In TDI Test Data Out TDO tTDOV tTDOX Note 22.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document Number: 001-44141 Rev. *Q Page 17 of 31

CY7C2663KV18/CY7C2665KV18 Identification Register Definitions Value Instruction Field Description CY7C2663KV18 CY7C2665KV18 Revision number (31:29) 000 000 Version number. Cypress device ID (28:12) 11010010001010011 11010010001100011 Defines the type of SRAM. Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. ID register presence (0) 1 1 Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary scan 109 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-44141 Rev. *Q Page 18 of 31

CY7C2663KV18/CY7C2665KV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H Document Number: 001-44141 Rev. *Q Page 19 of 31

CY7C2663KV18/CY7C2665KV18 Power-Up Sequence in QDR II+ SRAM PLL Constraints ■PLL uses K clock as its synchronizing input. The input must QDR II+ SRAMs must be powered up and initialized in a have low phase jitter, which is specified as t . predefined manner to prevent undefined operations. KC Var ■The PLL functions at frequencies down to 120 MHz. Power-Up Sequence ■If the input clock is unstable and the PLL is enabled, then the ■Apply power and drive DOFF either high or low (All other inputs PLL may lock onto an incorrect frequency, causing unstable can be high or low). SRAM behavior. To avoid this, provide 20 s of stable clock to ❐Apply VDD before VDDQ. relock to the desired clock frequency. ❐Apply V before V or at the same time as V . DDQ REF REF ❐Drive DOFF high. ■Provide stable DOFF (high), power and clock (K, K) for 20 s to lock the PLL Figure 4. Power-Up Waveforms ~~ K K ~~ Unstable Clock > 20μs Stable clock Start Normal Operation Clock Start (Clock Starts after V D D / V D D Q Stable) VDD/VDDQ VDD/ VDDQStable (< +/- 0.1V DC per 50ns ) Fix HIGH (or tie to V ) DDQ DOFF Document Number: 001-44141 Rev. *Q Page 20 of 31

CY7C2663KV18/CY7C2665KV18 Maximum Ratings Operating Range Exceeding maximum ratings may impair the useful life of the Range Ambient V [24] V [24] device. These user guidelines are not tested. Temperature (T ) DD DDQ A Storage temperature ................................–65 °C to +150 °C Commercial 0 °C to +70 °C 1.8 ± 0.1 V 1.4 V to Ambient temperature Industrial –40 °C to +85 °C VDD with power applied ...................................–55 °C to +125 °C Supply voltage on V relative to GND .......–0.5 V to +2.9 V DD Supply voltage on VDDQ relative to GND ......–0.5 V to +VDD Neutron Soft Error Immunity DC applied to outputs in high Z ........–0.5 V to V + 0.3 V DDQ DC input voltage [23] ...........................–0.5 V to VDD + 0.3 V Parameter Description ConTdeistito ns Typ Max* Unit Current into outputs (low) ...........................................20 mA LSBU Logical 25 °C 197 216 FIT/ Static discharge voltage single-bit Mb (MIL-STD-883, M. 3015) .........................................> 2001 V upsets Latch up current .....................................................> 200 mA LMBU Logical 25 °C 0 0.01 FIT/ multi-bit Mb upsets SEL Single-event 85 °C 0 0.1 FIT/ latch up Dev * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates”. Electrical Characteristics Over the Operating Range DC Electrical Characteristics Over the Operating Range Parameter [25] Description Test Conditions Min Typ Max Unit V Power supply voltage 1.7 1.8 1.9 V DD V I/O supply voltage 1.4 1.5 V V DDQ DD V Output high voltage Note 26 V /2 – 0.12 V /2 + 0.12 V OH DDQ DDQ V Output low voltage Note 27 V /2 – 0.12 – V /2 + 0.12 V OL DDQ DDQ V Output high voltage I =0.1 mA, Nominal Impedance V – 0.2 – V V OH(LOW) OH DDQ DDQ V Output low voltage I = 0.1 mA, Nominal Impedance V – 0.2 V OL(LOW) OL SS V Input high voltage V + 0.1 – V + 0.15 V IH REF DDQ V Input low voltage –0.15 – V – 0.1 V IL REF I Input leakage current GND  V  V 2 – 2 A X I DDQ I Output leakage current GND  V  V Output Disabled 2 – 2 A OZ I DDQ, V Input reference voltage [28] Typical Value = 0.75 V 0.68 0.75 0.95 V REF Notes 23.Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2). 24.Power-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 25.All voltage referenced to ground. 26.Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175   RQ  350 . 27.Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175   RQ  350 . 28.VREF(min) = 0.68 V or 0.46 VDDQ, whichever is larger, VREF(max) = 0.95 V or 0.54 VDDQ, whichever is smaller. Document Number: 001-44141 Rev. *Q Page 21 of 31

CY7C2663KV18/CY7C2665KV18 Electrical Characteristics (continued) Over the Operating Range DC Electrical Characteristics (continued) Over the Operating Range Parameter [25] Description Test Conditions Min Typ Max Unit I [29] V operating supply V = Max, I = 0 mA, 550 MHz (× 18) – – 1090 mA DD DD DD OUT f = f = 1/t MAX CYC (× 36) – – 1520 450 MHz (× 18) – – 940 mA (× 36) – – 1290 I Automatic power-down Max V , 550 MHz (× 18) – – 500 mA SB1 DD current Both Ports Deselected, (× 36) – – 500 V  V or V  V , IN IH IN IL f = f = 1/t , 450 MHz (× 18) – – 460 mA MAX CYC Inputs Static (× 36) – – 460 Note 29.The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-44141 Rev. *Q Page 22 of 31

CY7C2663KV18/CY7C2665KV18 AC Electrical Characteristics Over the Operating Range Parameter [30] Description Test Conditions Min Typ Max Unit V Input high voltage V + 0.2 – V + 0.24 V IH REF DDQ V Input low voltage –0.24 – V – 0.2 V IL REF Capacitance Parameter [31] Description Test Conditions Max Unit C Input capacitance T = 25 C, f = 1 MHz, V = 1.8 V, V = 1.5 V 4 pF IN A DD DDQ C Output capacitance 4 pF O Thermal Resistance Parameter [31] Description Test Conditions 165-ball FBGA Unit Package  (0 m/s) Thermal resistance Socketed on a 170 × 220 × 2.35 mm, eight-layer printed 12.23 °C/W JA (junction to ambient) circuit board  (1 m/s) 11.17 °C/W JA  (3 m/s) 10.42 °C/W JA  Thermal resistance 9.34 °C/W JB (junction to board)  Thermal resistance 2.10 °C/W JC (junction to case) AC Test Loads and Waveforms Figure 5. AC Test Loads and Waveforms V = 0.75 V REF V 0.75 V REF OUTPUT VREF 0.75 V R = 50  [32] ALL INPUT PULSES Device Z0= 50  RL= 50  OUTPUT 1.25 V Under Device 0.75 V Test Under 5pF 0.25 V VREF = 0.75 V Test ZQ Slew Rate = 2 V/ns ZQ RQ = RQ = 250  250  INCLUDING JIG AND SCOPE (b) (a) Notes 30.Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2). 31.Tested initially and after any design or process change that may affect these parameters. 32.Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure5. Document Number: 001-44141 Rev. *Q Page 23 of 31

CY7C2663KV18/CY7C2665KV18 Switching Characteristics Over the Operating Range Parameters [33, 34] 550 MHz 450 MHz Cypress Consortium Description Unit Min Max Min Max Parameter Parameter t V (typical) to the first access [35] 1 – 1 – ms POWER DD t t K clock cycle time 1.81 8.4 2.2 8.4 ns CYC KHKH tKH tKHKL Input clock (K/K) high 0.4 – 0.4 – tCYC tKL tKLKH Input clock (K/K) low 0.4 – 0.4 – tCYC tKHKH tKHKH K clock rise to K clock rise (rising edge to rising edge) 0.77 – 0.94 – ns Setup Times t t Address setup to K clock rise 0.23 – 0.275 – ns SA AVKH tSC tIVKH Control setup to K clock rise (RPS, WPS) 0.23 – 0.275 – ns t t DDR control setup to clock (K/K) Rise (BWS , BWS ,BWS , BWS ) 0.18 – 0.22 – ns SCDDR IVKH 0 1 2 3 tSD tDVKH D[X:0] setup to clock (K/K) rise 0.18 – 0.22 – ns Hold Times tHA tKHAX Address hold after K clock rise 0.23 – 0.275 – ns t t Control hold after K clock rise (RPS, WPS) 0.23 – 0.275 – ns HC KHIX t t DDR control hold after clock (K/K) rise (BWS , BWS , BWS , BWS ) 0.18 – 0.22 – ns HCDDR KHIX 0 1 2 3 tHD tKHDX D[X:0] hold after clock (K/K) rise 0.18 – 0.22 – ns Output Times tCO tCHQV K/K clock rise to data valid – 0.45 – 0.45 ns tDOH tCHQX Data output hold after output K/K clock rise (active to active) –0.45 – –0.45 – ns tCCQO tCHCQV K/K clock rise to echo clock valid – 0.45 – 0.45 ns tCQOH tCHCQX Echo clock hold after K/K clock rise –0.45 – –0.45 – ns t t Echo clock high to data valid – 0.15 – 0.15 ns CQD CQHQV t t Echo clock high to data invalid –0.15 – –0.15 – ns CQDOH CQHQX t t Output clock (CQ/CQ) high [36] 0.655 – 0.85 – ns CQH CQHCQL tCQHCQH tCQHCQH CQ clock rise to CQ clock rise (rising edge to rising edge) [36] 0.655 – 0.85 – ns tCHZ tCHQZ Clock (K/K) rise to high Z (active to high Z) [37, 38] – 0.45 – 0.45 ns tCLZ tCHQX1 Clock (K/K) rise to low Z [37, 38] –0.45 – –0.45 – ns t t Echo clock high to QVLD valid [39] –0.15 0.15 –0.15 0.15 ns QVLD CQHQVLD PLL Timing t t Clock phase jitter – 0.15 – 0.15 ns KC Var KC Var t t PLL lock time (K) 20 – 20 – s KC lock KC lock t t K static to PLL reset [40] 30 – 30 – ns KC Reset KC Reset Notes 33.Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5 on page 23. 34.When a part with a maximum frequency above 400 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 35.This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be initiated. 36.These parameters are extrapolated from the input timing parameters (tCYC/2 – 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by design and are not tested in production. 37.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 23. Transition is measured ±100 mV from steady-state voltage. 38.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. 39.tQVLD spec is applicable for both rising and falling edges of QVLD signal. 40.Hold to >VIH or <VIL. Document Number: 001-44141 Rev. *Q Page 24 of 31

CY7C2663KV18/CY7C2665KV18 Switching Waveforms Read/Write/Deselect Sequence Figure 6. Waveform for 2.5-Cycle Read Latency [41, 42, 43] NOP READ WRITE READ WRITE NOP 1 2 3 4 5 6 7 8 K tKH tKL tCYC tKHKH K RPS tSC tHC tSC tHC WPS A A0 A1 A2 A3 t t tSA tHA HD HD tSD tSD D D10 D11 D12 D13 D30 D31 D32 D33 t QVLD t QVLD QVLD t DOH tCLZ tCO tCQD tCQDOH tCHZ Q Q00 Q01 Q02 Q03 Q20 Q21 Q22 Q23 (Read Latency = 2.5 Cycles) t t CCQO CQOH CQ t CCQO tCQH tCQHCQH tCQOH CQ DON’T CARE UNDEFINED Notes 41.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1. 42.Outputs are disabled (High Z) one clock cycle after a NOP. 43.In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-44141 Rev. *Q Page 25 of 31

CY7C2663KV18/CY7C2665KV18 Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed Package Operating Ordering Code Package Type (MHz) Diagram Range 450 CY7C2663KV18-450BZI 51-85195 165-ball FBGA (15 × 17 × 1.4 mm) Industrial CY7C2665KV18-450BZI CY7C2663KV18-450BZXC 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free Commercial CY7C2665KV18-450BZXI Industrial 550 CY7C2663KV18-550BZI 51-85195 165-ball FBGA (15 × 17 × 1.4 mm) Industrial CY7C2665KV18-550BZI CY7C2663KV18-550BZXC 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free Commercial CY7C2665KV18-550BZXC CY7C2663KV18-550BZXI Industrial CY7C2665KV18-550BZXI Ordering Code Definitions CY 7 C 26XX K V18 - XXX BZ X X Temperature Grade: X = C or I C = Commercial; I = Industrial Pb-free Package Type: BZ = 165-ball FBGA Frequency Range: XXX = 450 MHz or 550 MHz V18 = 1.8 V Die Revision Part Identifier: 26XX = 2663 or 2665 Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-44141 Rev. *Q Page 26 of 31

CY7C2663KV18/CY7C2665KV18 Package Diagram Figure 7. 165-ball FBGA (15 × 17 × 1.40 mm (0.50 Ball Diameter)) Package Outline, 51-85195 51-85195 *D Document Number: 001-44141 Rev. *Q Page 27 of 31

CY7C2663KV18/CY7C2665KV18 Acronyms Document Conventions Units of Measure Acronym Description BWS Byte Write Select Symbol Unit of Measure DDR Double Data Rate °C degree Celsius DLL Delay Lock Loop FIT/Dev failure in time per device FBGA Fine-Pitch Ball Grid Array FIT/Mb failure in time per mega bit MHz megahertz HSTL High-Speed Transceiver Logic µA microampere I/O Input/Output µs microsecond JTAG Joint Test Action Group mA milliampere LSB Least Significant Bit mm millimeter LSBU Logical Single-Bit Upsets ms millisecond LMBU Logical Multi-Bit Upsets ns nanosecond MSB Most Significant Bit  ohm ODT On-Die Termination % percent PLL Phase Locked Loop pF picofarad QDR Quad Data Rate V volt SEL Single Event Latch-up W watt SRAM Static Random Access Memory TAP Test Access Port TCK Test Clock TDI Test Data-In TDO Test Data-Out TMS Test Mode Select Document Number: 001-44141 Rev. *Q Page 28 of 31

CY7C2663KV18/CY7C2665KV18 Document History Page Document Title: CY7C2663KV18/CY7C2665KV18, 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Document Number: 001-44141 Orig. of Submission Rev. ECN Description of Change Change Date ** 1980429 VKN / AESA See ECN New data sheet. *A 2557050 VKN / AESA 09/24/2008 Updated Identification Register Definitions (Changed Revision Number (31:29) from 001 to 000). Updated Power-Up Sequence in QDR II+ SRAM (Updated description and Figure4). Updated Electrical Characteristics (Updated DC Electrical Characteristics (Updated maximum values of I and I parameters)). DD SB1 Updated Thermal Resistance (Replaced values of  and  parameters JA JC from TBD to respective Thermal Values for all Packages). Updated to new template. *B 2806011 VKN / PYRS 11/12/09 Added Neutron Soft Error Immunity. Updated Capacitance (Changed value of Input Capacitance (C ) from 2 pF IN to 4 pF, changed value of Output Capacitance (C ) from 3 pF to 4 pF). O Updated Switching Characteristics (Changed maximum values of t , t , CO CCQO t parameters to 450 ps for 550 MHz, 500 MHz and 450 MHz frequencies, CHZ changed minimum values of t , t , t parameters to –450 ps for DOH CQOH CLZ 550MHz, 500 MHz and 450 MHz frequencies). Updated Ordering Information(By including parts that are available, and added disclaimer at the top of Ordering Information table). Updated Package Diagram. *C 2886418 NJY 03/02/2010 Updated Switching Characteristics (Changed minimum value of t and HCDDR t from 0.28 ns to 0.22 ns for 450 MHz). HD Updated Ordering Information (Removed inactive parts). Updated links in Sales, Solutions, and Legal Information. *D 2975354 NJY 07/09/2010 Updated Ordering Information (Added part CY7C2663KV18-550BZI in the Ordering Information table). *E 3024181 NJY 09/07/2010 Changed status from Preliminary to Final. Updated Ordering Information (Updated part numbers). Added Units of Measure. *F 3242369 NJY 04/27/2011 Updated Ordering Information (Updated part numbers). Updated to new template. *G 3275033 NJY 06/06/2011 No technical updates. *H 3429006 PRIT 11/03/2011 Updated Ordering Information (Updated part numbers). Updated Package Diagram. *I 3599727 AVIA / PRIT 04/25/2012 Updated Features (Removed CY7C2661KV18, CY7C2676KV18 related information). Updated Configurations (Removed CY7C2661KV18, CY7C2676KV18 related information). Updated Functional Description (Removed CY7C2661KV18, CY7C2676KV18 related information). Updated Selection Guide (Removed 500 MHz, 400 MHz frequencies related information, removed CY7C2661KV18, CY7C2676KV18 related information). Removed Logic Block Diagram – CY7C2661KV18. Removed Logic Block Diagram – CY7C2676KV18. Updated Pin Configurations (Removed CY7C2661KV18, CY7C2676KV18 related information). Updated Pin Definitions (Removed CY7C2661KV18, CY7C2676KV18 related information). Document Number: 001-44141 Rev. *Q Page 29 of 31

CY7C2663KV18/CY7C2665KV18 Document History Page (continued) Document Title: CY7C2663KV18/CY7C2665KV18, 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Document Number: 001-44141 Orig. of Submission Rev. ECN Description of Change Change Date *I (cont.) 3599727 AVIA / PRIT 04/25/2012 Updated Functional Overview (Removed CY7C2661KV18, CY7C2676KV18 related information). Updated Truth Table (Removed CY7C2661KV18, CY7C2676KV18 related information). Updated Write Cycle Descriptions (Removed CY7C2661KV18 related information). Removed Write Cycle Descriptions (Corresponding to CY7C2676KV18). Updated Identification Register Definitions (Removed CY7C2661KV18, CY7C2676KV18 related information). Updated Electrical Characteristics (Removed 500 MHz, 400 MHz frequencies related information, removed CY7C2661KV18, CY7C2676KV18 related information). Updated Switching Characteristics (Removed 500 MHz, 400 MHz frequencies related information). *J 3744448 PRIT 09/14/2012 Updated Ordering Information (Updated part numbers). *K 3794817 PRIT 10/26/2012 No technical updates. Completing Sunset Review. *L 4372887 PRIT 05/07/2014 Updated Application Example: Updated Figure2. Updated Thermal Resistance: Updated values of  and  parameters. JA JC Included  parameter and its details. JB Updated to new template. *M 4404184 PRIT 06/10/2014 Updated Ordering Information (Updated part numbers). *N 4575228 PRIT 11/20/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *O 5059167 PRIT 12/21/2015 Updated Package Diagram: spec 51-85195 – Changed revision from *C to *D. Updated to new template. Completing Sunset Review. *P 5333901 PRIT 07/01/2016 Updated TAP Electrical Characteristics: Updated Note 18. Updated to new template. *Q 5975692 AESATMP9 11/24/2017 Updated logo and Copyright. Document Number: 001-44141 Rev. *Q Page 30 of 31

CY7C2663KV18/CY7C2665KV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions ARM® Cortex® Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Forums | WICED IOT Forums | Projects | Video | Blogs | Interface cypress.com/interface Training | Components Internet of Things cypress.com/iot Technical Support Memory cypress.com/memory cypress.com/support Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless © Cypress Semiconductor Corporation, 2008-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-44141 Rev. *Q Revised November 24, 2017 Page 31 of 31