CY7C1562XV18/CY7C1564XV18 ® 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations ■Separate independent read and write data ports With Read Cycle Latency of 2.5 cycles: ❐Supports concurrent transactions CY7C1562XV18 – 4M × 18 ■450 MHz clock for high bandwidth CY7C1564XV18 – 2M × 36 ■Two-word burst for reducing address bus frequency Functional Description ■Double Data Rate (DDR) interfaces on both read and write ports The CY7C1562XV18, and CY7C1564XV18 are 1.8V (data transferred at 900 MHz) at 450 MHz Synchronous Pipelined SRAMs, equipped with QDR® II+ ■Available in 2.5 clock cycle latency architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to ■Two input clocks (K and K) for precise DDR timing access the memory array. The read port has dedicated data ❐SRAM uses rising edges only outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ ■Echo clocks (CQ and CQ) simplify data capture in high speed architecture has separate data inputs and data outputs to systems completely eliminate the need to “turnaround” the data bus that ■Data valid pin (QVLD) to indicate valid data on the output exists with common I/Os devices. Access to each port is through a common address bus. Addresses for read and write addresses ■Single multiplexed address input bus latches address inputs are latched on alternate rising edges of the input (K) clock. for both read and write ports Accesses to the QDR II+ Xtreme read and write ports are completely independent of one another. To maximize data ■Separate port selects for depth expansion throughput, both read and write ports are equipped with DDR ■Synchronous internally self-timed writes interfaces. Each address location is associated with two 18-bit words (CY7C1562XV18), or 36-bit words (CY7C1564XV18) that ■QDR™-II+ Xtreme operates with 2.5 cycle read latency when burst sequentially into or out of the device. Because data can be DOFF is asserted HIGH transferred into and out of the device on every rising edge of both ■Operates similar to QDR-I device with 1 cycle read latency input clocks (K and K), memory bandwidth is maximized while when DOFF is asserted LOW simplifying system design by eliminating bus “turnarounds”. ■Available in × 18, and × 36 configurations Depth expansion is accomplished with port selects, which enables each port to operate independently. ■Full data coherency, providing most current data All synchronous inputs pass through input registers controlled by ■Core V = 1.8 V± 0.1 V; I/Os V = 1.4 V to 1.6 V the K or K input clocks. All data outputs pass through output DD DDQ ❐Supports 1.5 V I/O supply registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. ■HSTL inputs and variable drive HSTL output buffers For a complete list of related documentation, click here. ■Available in 165-ball FBGA package (13 × 15 × 1.4 mm) ■Offered in both Pb-free and non Pb-free packages ■JTAG 1149.1 compatible test access port ■Phase-Locked Loop (PLL) for accurate data placement Selection Guide Description 450 MHz 366 MHz Unit Maximum Operating Frequency 450 366 MHz Maximum Operating Current × 18 1205 970 mA × 36 1445 1165 CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-68998 Rev. *G Revised January 3, 2018

CY7C1562XV18/CY7C1564XV18 Logic Block Diagram – CY7C1562XV18 18 D [17:0] Write Write 21 Reg Reg Address A(20:0) 21 Address Register A(20:0) Register de 2 2 de co M M co d. De x 18 x 18 d. De K CLK e Ad Arra Arra d Ad Control RPS K Gen. Writ y y Rea Logic DOFF Read Data Reg. CQ 36 VREF 18 18 CQ Reg. Reg. Control WPS Logic BWS[1:0] 18 Reg. 18 18 Q[17:0] QVLD Logic Block Diagram – CY7C1564XV18 36 D [35:0] Write Write 20 Reg Reg Address A(19:0) 20 Address Register A(19:0) Register de 1 1 de co M M co d. De x 36 x 36 d. De K CLK e Ad Arra Arra d Ad Control RPS K Gen. Writ y y Rea Logic DOFF Read Data Reg. CQ 72 VREF 36 36 CQ Reg. Reg. Control WPS Logic BWS[3:0] 36 Reg. 36 36 Q[35:0] QVLD Document Number: 001-68998 Rev. *G Page 2 of 29

CY7C1562XV18/CY7C1564XV18 Contents Pin Configurations ...........................................................4 Boundary Scan Order ....................................................18 Pin Definitions ..................................................................5 Power Up Sequence in QDR II+ Xtreme SRAM ............19 Functional Overview ........................................................6 Power Up Sequence .................................................19 Read Operations .........................................................6 PLL Constraints .........................................................19 Write Operations .........................................................6 Maximum Ratings ...........................................................20 Byte Write Operations .................................................6 Neutron Soft Error Immunity .........................................20 Concurrent Transactions .............................................6 Operating Range .............................................................20 Depth Expansion .........................................................7 Electrical Characteristics ...............................................20 Programmable Impedance ..........................................7 DC Electrical Characteristics .....................................20 Echo Clocks ................................................................7 AC Electrical Characteristics .....................................22 Valid Data Indicator (QVLD) ........................................7 Capacitance ....................................................................22 PLL ..............................................................................7 Thermal Resistance ........................................................22 Application Example ........................................................8 AC Test Loads and Waveforms .....................................22 Truth Table ........................................................................9 Switching Characteristics ..............................................23 Write Cycle Descriptions .................................................9 Switching Waveforms ....................................................24 Write Cycle Descriptions ...............................................10 Read/Write/Deselect Sequence ................................24 IEEE 1149.1 Serial Boundary Scan (JTAG) ..................11 Ordering Information ......................................................25 Disabling the JTAG Feature ......................................11 Ordering Code Definitions .........................................25 Test Access Port .......................................................11 Package Diagram ............................................................26 Performing a TAP Reset ...........................................11 Acronyms ........................................................................27 TAP Registers ...........................................................11 Document Conventions .................................................27 TAP Instruction Set ...................................................11 Units of Measure .......................................................27 TAP Controller State Diagram .......................................13 Document History Page .................................................28 TAP Controller Block Diagram ......................................14 Sales, Solutions, and Legal Information ......................29 TAP Electrical Characteristics ......................................14 Worldwide Sales and Design Support .......................29 TAP AC Switching Characteristics ...............................15 Products ....................................................................29 TAP Timing and Test Conditions ..................................16 PSoC® Solutions ......................................................29 Identification Register Definitions ................................17 Cypress Developer Community .................................29 Scan Register Sizes .......................................................17 Technical Support .....................................................29 Instruction Codes ...........................................................17 Document Number: 001-68998 Rev. *G Page 3 of 29

CY7C1562XV18/CY7C1564XV18 Pin Configurations The pin configurations for CY7C1562XV18, and CY7C1564XV18 follow. [1] Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout CY7C1562XV18 (4M × 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/144M A WPS BWS K NC/288M RPS A A CQ 1 B NC Q9 D9 A NC K BWS A NC NC Q8 0 C NC NC D10 V A A A V NC Q7 D8 SS SS D NC D11 Q10 V V V V V NC NC D7 SS SS SS SS SS E NC NC Q11 V V V V V NC D6 Q6 DDQ SS SS SS DDQ F NC Q12 D12 V V V V V NC NC Q5 DDQ DD SS DD DDQ G NC D13 Q13 V V V V V NC NC D5 DDQ DD SS DD DDQ H DOFF V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J NC NC D14 V V V V V NC Q4 D4 DDQ DD SS DD DDQ K NC NC Q14 V V V V V NC D3 Q3 DDQ DD SS DD DDQ L NC Q15 D15 V V V V V NC NC Q2 DDQ SS SS SS DDQ M NC NC D16 V V V V V NC Q1 D2 SS SS SS SS SS N NC D17 Q16 V A A A V NC NC D1 SS SS P NC NC Q17 A A QVLD A A NC D0 Q0 R TDO TCK A A A NC A A A TMS TDI CY7C1564XV18 (2M × 36) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/288M A WPS BWS K BWS RPS A NC/144M CQ 2 1 B Q27 Q18 D18 A BWS K BWS A D17 Q17 Q8 3 0 C D27 Q28 D19 V A A A V D16 Q7 D8 SS SS D D28 D20 Q19 V V V V V Q16 D15 D7 SS SS SS SS SS E Q29 D29 Q20 V V V V V Q15 D6 Q6 DDQ SS SS SS DDQ F Q30 Q21 D21 V V V V V D14 Q14 Q5 DDQ DD SS DD DDQ G D30 D22 Q22 V V V V V Q13 D13 D5 DDQ DD SS DD DDQ H DOFF V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J D31 Q31 D23 V V V V V D12 Q4 D4 DDQ DD SS DD DDQ K Q32 D32 Q23 V V V V V Q12 D3 Q3 DDQ DD SS DD DDQ L Q33 Q24 D24 V V V V V D11 Q11 Q2 DDQ SS SS SS DDQ M D33 Q34 D25 V V V V V D10 Q1 D2 SS SS SS SS SS N D34 D26 Q25 V A A A V Q10 D9 D1 SS SS P Q35 D35 Q26 A A QVLD A A Q9 D0 Q0 R TDO TCK A A A NC A A A TMS TDI Note 1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. Document Number: 001-68998 Rev. *G Page 4 of 29

CY7C1562XV18/CY7C1564XV18 Pin Definitions Pin Name I/Os Pin Description D Input- Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. [x:0] Synchronous CY7C1562XV18  D [17:0] CY7C1564XV18  D [35:0] WPS Input- Write Port Select  Active LOW. Sampled on the rising edge of the K clock. When asserted active, a Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D . [x:0] BWS , Input- Byte Write Select 0, 1, 2 and 3  Active LOW. Sampled on the rising edge of the K and K clocks during 0 BWS1, Synchronous write operations. Used to select which byte is written into the device during the current portion of the write BWS , operations. Bytes not written remain unaltered. 2 BWS3 CY7C1562XV18  BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1564XV18 BWS controls D , BWS controls D , BWS controls D and BWS controls 0 [8:0] 1 [17:9] 2 [26:18] 3 D [35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device. A Input- Address Inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks during Synchronous active read and write operations. These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 4M × 18 (2 arrays each of 2M × 18) for CY7C1562XV18, and 2M×36 (2 arrays each of 1M × 36) for CY7C1564XV18. Therefore, only 21 address inputs for CY7C1562XV18, and 20 address inputs for CY7C1564XV18. These inputs are ignored when the appropriate port is deselected. The address pins (A) can be assigned any bit order. Q Output- Data Output Signals. These pins drive out the requested data during a read operation. Valid data is driven [x:0] Synchronous out on the rising edge of the K and K clocks during read operations. When the read port is deselected, Q are automatically tristated. [x:0] CY7C1562XV18  Q [17:0] CY7C1564XV18  Q [35:0] RPS Input- Read Port Select  Active LOW. Sampled on the rising edge of positive input clock (K). When active, a Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tristated following the next rising edge of the K clock. Each read access consists of a burst of two sequential transfers. QVLD Valid output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ. indicator K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q . All accesses are initiated on the rising edge of K. [x:0] K Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q . [x:0] CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR II+ Xtreme. The timing for the echo clocks is shown in Switching Characteristics on page 23. CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR II+ Xtreme. The timing for the echo clocks is shown in Switching Characteristics on page 23. ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q output impedance are set to 0.2 × RQ, where RQ is a resistor connected [x:0] between ZQ and ground. Alternatively, connect this pin directly to V , which enables the minimum DDQ impedance mode. This pin cannot be connected directly to GND or left unconnected. DOFF Input PLL Turn Off  Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing in the operation with the PLL turned off differs from those listed in this data sheet. For normal operation, connect this pin to a pull up through a 10 K or less pull up resistor. The device behaves in QDR-I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR-I timing. TDO Output TDO Pin for JTAG TCK Input TCK Pin for JTAG Document Number: 001-68998 Rev. *G Page 5 of 29

CY7C1562XV18/CY7C1564XV18 Pin Definitions (continued) Pin Name I/Os Pin Description TDI Input TDI Pin for JTAG TMS Input TMS Pin for JTAG NC N/A Not Connected to the Die. Can be tied to any voltage level. NC/144M Input Not Connected to the Die. Can be tied to any voltage level. NC/288M Input Not Connected to the Die. Can be tied to any voltage level. V Input- Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC REF Reference measurement points. V Power Supply Power Supply Inputs to the Core of the Device. DD V Ground Ground for the Device. SS V Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Functional Overview of K, the next 18-bit data word is driven onto the Q . The [17:0] requested data is valid 0.45 ns from the rising edge of the input The CY7C1562XV18, and CY7C1564XV18 are synchronous clock (K and K). pipelined Burst SRAMs equipped with a read port and a write When the read port is deselected, the CY7C1562XV18 first port. The read port is dedicated to read operations and the write completes the pending read transactions. Synchronous internal port is dedicated to write operations. Data flows into the SRAM circuitry automatically tristates the outputs following the next through the write port and flows out through the read port. These rising edge of the negative input clock (K). This enables for a devices multiplex the address inputs to minimize the number of seamless transition between devices without the insertion of wait address pins required. By having separate read and write ports, states in a depth expanded memory. the QDR II+ Xtreme completely eliminates the need to “turn around” the data bus and avoids any possible data contention, Write Operations thereby simplifying system design. Each access consists of two Write operations are initiated by asserting WPS active at the 18-bit data transfers in the case of CY7C1562XV18, and two rising edge of the positive input clock (K). On the same K clock 36-bit data transfers in the case of CY7C1564XV18 in one clock rise the data presented to D is latched and stored into the cycle. [17:0] lower 18-bit write data register, provided BWS are both [1:0] These devices operate with a read latency of two and half cycles asserted active. On the subsequent rising edge of the negative when DOFF pin is tied HIGH. When DOFF pin is set LOW or input clock (K), the address is latched and the information connected to VSS then the device behaves in QDR-I mode with presented to D[17:0] is also stored into the write data register, a read latency of one clock cycle. provided BWS are both asserted active. The 36 bits of data [1:0] Accesses for both ports are initiated on the rising edge of the are then written into the memory array at the specified location. positive input clock (K). All synchronous input and output timing When deselected, the write port ignores all inputs after the are referenced from the rising edge of the input clocks (K and K). pending write operations have been completed. All synchronous data inputs (D ) pass through input registers [x:0] Byte Write Operations controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the Byte write operations are supported by the CY7C1562XV18. A rising edge of the input clocks (K and K) as well. write operation is initiated as described in the Write Operations All synchronous control (RPS, WPS, BWS[x:0]) inputs pass section. The bytes that are written are determined by BWS0 and through input registers controlled by the rising edge of the input BWS1, which are sampled with each set of 18-bit data words. clocks (K and K). Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it CY7C1562XV18 is described in the following sections. The into the device. Deasserting the Byte Write Select input during same basic descriptions apply to CY7C1564XV18. the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to Read Operations simplify read, modify, or write operations to a byte write The CY7C1562XV18 is organized internally as two arrays of operation. 2M×18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting Concurrent Transactions RPS active at the rising edge of the positive input clock (K). The The read and write ports on the CY7C1562XV18 operate address is latched on the rising edge of the K clock. The address completely independently of one another. As each port latches presented to the address inputs is stored in the read address the address inputs on different clock edges, the user can read or register. Following the next two K clock rise, the corresponding write to any location, regardless of the transaction on the other lowest order 18-bit word of data is driven onto the Q[17:0] using port. The user can start reads and writes in the same clock cycle. K as the output timing reference. On the subsequent rising edge Document Number: 001-68998 Rev. *G Page 6 of 29

CY7C1562XV18/CY7C1564XV18 If the ports access the same location at the same time, the SRAM and are synchronized to the input clock of the QDR II+ Xtreme. delivers the most recent information associated with the The timing for the echo clocks is shown in Switching specified address location. This includes forwarding data from a Characteristics on page 23. write cycle that was initiated on the previous K clock rise. Valid Data Indicator (QVLD) Depth Expansion QVLD is provided on the QDR II+ Xtreme to simplify data capture The CY7C1562XV18 has a port select input for each port. This on high speed systems. The QVLD is generated by the QDR II+ enables for easy depth expansion. Both port selects are sampled Xtreme device along with data output. This signal is also on the rising edge of the positive input clock only (K). Each port edge-aligned with the echo clock and follows the timing of any select input can deselect the specified port. Deselecting a port data pin. This signal is asserted half a cycle before valid data does not affect the other port. All pending transactions (read and arrives. write) are completed before the device is deselected. PLL Programmable Impedance These chips use a PLL that is designed to function between An external resistor, RQ, must be connected between the ZQ pin 120MHz and the specified maximum clock frequency. During on the SRAM and V to enable the SRAM to adjust its output power up, when the DOFF is tied HIGH, the PLL is locked after SS driver impedance. The value of RQ must be 5 × the value of the 100 s of stable clock. The PLL can also be reset by slowing or intended line impedance driven by the SRAM. The allowable stopping the input clocks K and K for a minimum of 30 ns. range of RQ to guarantee impedance matching with a tolerance However, it is not necessary to reset the PLL to lock to the of ±15% is between 175  and 350 , with VDDQ=1.5V. The desired frequency. The PLL automatically locks 100 s after a output impedance is adjusted every 1024 cycles upon power up stable clock is presented. The PLL may be disabled by applying to account for drifts in supply voltage and temperature. ground to the DOFF pin. When the PLL is turned off, the device behaves in QDR-I mode with one cycle latency and a longer Echo Clocks access time). For information, refer to the application note, PLL Echo clocks are provided on the QDR II+ Xtreme to simplify data Considerations in QDRII/DDRII/QDRII+/DDRII+. capture on high speed systems. Two echo clocks are generated by the QDR II+ Xtreme. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free running clocks Document Number: 001-68998 Rev. *G Page 7 of 29

CY7C1562XV18/CY7C1564XV18 Application Example Figure2 shows two QDR II+ Xtreme SRAMs used in an application. Figure 2. Application Example (Width Expansion) ZQ ZQ SRAM#1 SRAM#2 CQ/CQ CQ/CQ RQ RQ D[x:0] D[x:0] Q[x:0] Q[x:0] A RPS WPS BWS K K A RPS WPS BWS K K DATA IN[2x:0] DATA OUT [2x:0] ADDRESS RPS WPS BWS CLKIN1/CLKIN1 CLKIN2/CLKIN2 SOURCE K SOURCE K FPGA / ASIC Document Number: 001-68998 Rev. *G Page 8 of 29

CY7C1562XV18/CY7C1564XV18 Truth Table The truth table for CY7C1562XV18, and CY7C1564XV18 follows. [2, 3, 4, 5, 6, 7, 8] Operation K RPS WPS DQ DQ Write Cycle: L–H X L D(A) at K(t)  D(A + 1) at K(t)  Load address on the rising edge of K; input write data on K and K rising edges. Read Cycle: (2.5 cycle Latency) L–H L X Q(A) at K(t + 2)  Q(A + 1) at K(t + 3)  Load address on the rising edge of K; wait two and half cycles; read data on K and K rising edges. NOP: No Operation L–H H H D = X D = X Q = High Z Q = High Z Standby: Clock Stopped Stopped X X Previous State Previous State Write Cycle Descriptions The write cycle description table for CY7C1562XV18 follows. [2, 8] BWS0 BWS1 K K Comments L L L–H – During the data portion of a write sequence CY7C1562XV18 both bytes (D ) are written into the device. [17:0] L L – L–H During the data portion of a write sequence: CY7C1562XV18 both bytes (D ) are written into the device. [17:0] L H L–H – During the data portion of a write sequence: CY7C1562XV18 only the lower byte (D ) is written into the device, D remains unaltered. [8:0] [17:9] L H – L–H During the data portion of a write sequence CY7C1562XV18 only the lower byte (D ) is written into the device, D remains unaltered. [8:0] [17:9] H L L–H – During the data portion of a write sequence CY7C1562XV18 only the upper byte (D ) is written into the device, D remains unaltered. [17:9] [8:0] H L – L–H During the data portion of a write sequence CY7C1562XV18 only the upper byte (D ) is written into the device, D remains unaltered. [17:9] [8:0] H H L–H – No data is written into the devices during this portion of a write operation. H H – L–H No data is written into the devices during this portion of a write operation. Notes 2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 3. Device powers up deselected with the outputs in a tristate condition. 4. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the internal address sequence in the burst. 5. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well. 7. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. Is based on a write cycle that was initiated in accordance with Truth Table. BWS0, BWS1, BWS2 and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-68998 Rev. *G Page 9 of 29

CY7C1562XV18/CY7C1564XV18 Write Cycle Descriptions The write cycle description table for CY7C1564XV18 follows. [9, 10] BWS BWS BWS BWS K K Comments 0 1 2 3 L L L L L–H – During the data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. L L L L – L–H During the data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. L H H H L–H – During the data portion of a write sequence, only the lower byte (D ) is written [8:0] into the device. D remains unaltered. [35:9] L H H H – L–H During the data portion of a write sequence, only the lower byte (D ) is written [8:0] into the device. D remains unaltered. [35:9] H L H H L–H – During the data portion of a write sequence, only the byte (D ) is written into [17:9] the device. D and D remains unaltered. [8:0] [35:18] H L H H – L–H During the data portion of a write sequence, only the byte (D ) is written into [17:9] the device. D and D remains unaltered. [8:0] [35:18] H H L H L–H – During the data portion of a write sequence, only the byte (D ) is written into [26:18] the device. D and D remains unaltered. [17:0] [35:27] H H L H – L–H During the data portion of a write sequence, only the byte (D ) is written into [26:18] the device. D and D remains unaltered. [17:0] [35:27] H H H L L–H – During the data portion of a write sequence, only the byte (D ) is written into [35:27] the device. D remains unaltered. [26:0] H H H L – L–H During the data portion of a write sequence, only the byte (D ) is written into [35:27] the device. D remains unaltered. [26:0] H H H H L–H – No data is written into the device during this portion of a write operation. H H H H – L–H No data is written into the device during this portion of a write operation. Notes 9. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 10.Is based on a write cycle that was initiated in accordance with Truth Table on page 9. BWS0, BWS1, BWS2 and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-68998 Rev. *G Page 10 of 29

CY7C1562XV18/CY7C1564XV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Instruction Register Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan Test Access register. This register is loaded when it is placed between the TDI Port (TAP) in the FBGA package. This part is fully compliant with and TDO pins, as shown in TAP Controller Block Diagram on IEEE Standard #1149.1-2001. The TAP operates using JEDEC page 14. Upon power up, the instruction register is loaded with standard 1.8 V I/Os logic levels. the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described Disabling the JTAG Feature in the previous section. It is possible to operate the SRAM without using the JTAG When the TAP controller is in the Capture-IR state, the two least feature. To disable the TAP controller, TCK must be tied LOW significant bits are loaded with a binary “01” pattern to allow for (V ) to prevent clocking of the device. TDI and TMS are SS fault isolation of the board level serial test path. internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO Bypass Register must be left unconnected. Upon power up, the device comes up To save time when serially shifting data through registers, it is in a reset state, which does not interfere with the operation of the sometimes advantageous to skip certain chips. The bypass device. register is a single-bit register that can be placed between TDI Test Access Port and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (V ) when SS Test Clock the BYPASS instruction is executed. The test clock is used only with the TAP controller. All inputs are Boundary Scan Register captured on the rising edge of TCK. All outputs are driven from The boundary scan register is connected to all of the input and the falling edge of TCK. output pins on the SRAM. Several No Connect (NC) pins are also Test Mode Select (TMS) included in the scan register to reserve pins for higher density devices. The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left The boundary scan register is loaded with the contents of the unconnected if the TAP is not used. The pin is pulled up RAM input and output ring when the TAP controller is in the internally, resulting in a logic HIGH level. Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The Test Data-In (TDI) EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The The section Boundary Scan Order on page 18 shows the order register between TDI and TDO is chosen by the instruction that in which the bits are connected. Each bit corresponds to one of is loaded into the TAP instruction register. For information on the bumps on the SRAM package. The MSB of the register is loading the instruction register, see TAP Controller State connected to TDI, and the LSB is connected to TDO. Diagram on page 13. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is Identification (ID) Register connected to the most significant bit (MSB) on any register. The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is Test Data-Out (TDO) loaded in the instruction register. The IDCODE is hardwired into The TDO output pin is used to serially clock data out from the the SRAM and can be shifted out when the TAP controller is in registers. The output is active, depending upon the current state the Shift-DR state. The ID register has a vendor code and other of the TAP state machine (see Instruction Codes on page 17). information described in Identification Register Definitions on The output changes on the falling edge of TCK. TDO is page 17. connected to the least significant bit (LSB) of any register. TAP Instruction Set Performing a TAP Reset Eight different instructions are possible with the three-bit A Reset is performed by forcing TMS HIGH (VDD) for five rising instruction register. All combinations are listed in Instruction edges of TCK. This Reset does not affect the operation of the Codes on page 17. Three of these instructions are listed as SRAM and can be performed while the SRAM is operating. At RESERVED and must not be used. The other five instructions power up, the TAP is reset internally to ensure that TDO comes are described in this section in detail. up in a high Z state. Instructions are loaded into the TAP controller during the Shift-IR TAP Registers state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the Registers are connected between the TDI and TDO pins to scan instruction register through the TDI and TDO pins. To execute the data in and out of the SRAM test circuitry. Only one register the instruction after it is shifted in, the TAP controller must be can be selected at a time through the instruction registers. Data moved into the Update-IR state. is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-68998 Rev. *G Page 11 of 29

CY7C1562XV18/CY7C1564XV18 IDCODE PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection The IDCODE instruction loads a vendor-specific, 32-bit code into of another boundary scan test operation. the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the The shifting of data for the SAMPLE and PRELOAD phases can device when the TAP controller enters the Shift-DR state. The occur concurrently when required, that is, while the data IDCODE instruction is loaded into the instruction register at captured is shifted out, the preloaded data can be shifted in. power up or whenever the TAP controller is supplied a Test-Logic-Reset state. BYPASS When the BYPASS instruction is loaded in the instruction register SAMPLE Z and the TAP is placed in a Shift-DR state, the bypass register is The SAMPLE Z instruction connects the boundary scan register placed between the TDI and TDO pins. The advantage of the between the TDI and TDO pins when the TAP controller is in a BYPASS instruction is that it shortens the boundary scan path Shift-DR state. The SAMPLE Z command puts the output bus when multiple devices are connected together on a board. into a High Z state until the next command is supplied during the Update IR state. EXTEST The EXTEST instruction drives the preloaded data out through SAMPLE/PRELOAD the system output pins. This instruction also connects the SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When boundary scan register for serial access between the TDI and the SAMPLE/PRELOAD instructions are loaded into the TDO in the Shift-DR controller state. instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured EXTEST OUTPUT BUS TRISTATE in the boundary scan register. IEEE Standard 1149.1 mandates that the TAP controller be able The user must be aware that the TAP controller clock can only to put the output bus into a tristate mode. operate at a frequency up to 20 MHz, while the SRAM clock The boundary scan register has a special bit located at bit #108. operates more than an order of magnitude faster. Because there When this scan cell, called the “extest output bus tristate,” is is a large difference in the clock frequencies, it is possible that latched into the preload register during the Update-DR state in during the Capture-DR state, an input or output undergoes a the TAP controller, it directly controls the state of the output transition. The TAP may then try to capture a signal while in (Q-bus) pins, when the EXTEST is entered as the current transition (metastable state). This does not harm the device, but instruction. When HIGH, it enables the output buffers to drive the there is no guarantee as to the value that is captured. output bus. When LOW, this bit places the output bus into a Repeatable results may not be possible. HighZ condition. To guarantee that the boundary scan register captures the This bit can be set by entering the SAMPLE/PRELOAD or correct value of a signal, the SRAM signal must be stabilized EXTEST command, and then shifting the desired bit into that cell, long enough to meet the TAP controller’s capture setup plus hold during the Shift-DR state. During Update-DR, the value loaded times (tCS and tCH). The SRAM clock input might not be captured into that shift-register cell latches into the preload register. When correctly if there is no way in a design to stop (or slow) the clock the EXTEST instruction is entered, this bit directly controls the during a SAMPLE/PRELOAD instruction. If this is an issue, it is output Q-bus pins. Note that this bit is pre-set LOW to enable the still possible to capture all other signals and simply ignore the output when the device is powered up, and also when the TAP value of the CK and CK captured in the boundary scan register. controller is in the Test-Logic-Reset state. After the data is captured, it is possible to shift out the data by Reserved putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. These instructions are not implemented but are reserved for future use. Do not use these instructions. Document Number: 001-68998 Rev. *G Page 12 of 29

CY7C1562XV18/CY7C1564XV18 TAP Controller State Diagram The state diagram for the TAP controller follows. [11] TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 1 SELECT 1 SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 PAUSE-DR 0 PAUSE-IR 0 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 Note 11.The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-68998 Rev. *G Page 13 of 29

CY7C1562XV18/CY7C1564XV18 TAP Controller Block Diagram 0 Bypass Register 2 1 0 TDI Selection Instruction Register Selection TDO Circuitry Circuitry 31 30 29 . . 2 1 0 Identification Register 108 . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range Parameter [12, 13, 14] Description Test Conditions Min Max Unit V Output HIGH Voltage I =2.0 mA 1.4 – V OH1 OH V Output HIGH Voltage I =100 A 1.6 – V OH2 OH V Output LOW Voltage I = 2.0 mA – 0.4 V OL1 OL V Output LOW Voltage I = 100 A – 0.2 V OL2 OL V Input HIGH Voltage 0.65 × V V + 0.3 V IH DD DD V Input LOW Voltage –0.3 0.35 × V V IL DD I Input and Output Load Current GND  V  V –5 5 A X I DD Notes 12.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 20. 13.Overshoot: VIH(AC) < VDD + 0.35 V (Pulse width less than tTCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tTCYC/2). 14.All Voltage referenced to Ground. Document Number: 001-68998 Rev. *G Page 14 of 29

CY7C1562XV18/CY7C1564XV18 TAP AC Switching Characteristics Over the Operating Range Parameter [15, 16] Description Min Max Unit t TCK Clock Cycle Time 50 – ns TCYC t TCK Clock Frequency – 20 MHz TF t TCK Clock HIGH 20 – ns TH t TCK Clock LOW 20 – ns TL Setup Times t TMS Setup to TCK Clock Rise 5 – ns TMSS t TDI Setup to TCK Clock Rise 5 – ns TDIS t Capture Setup to TCK Rise 5 – ns CS Hold Times t TMS Hold after TCK Clock Rise 5 – ns TMSH t TDI Hold after Clock Rise 5 – ns TDIH t Capture Hold after Clock Rise 5 – ns CH Output Times t TCK Clock LOW to TDO Valid – 10 ns TDOV t TCK Clock LOW to TDO Invalid 0 – ns TDOX Notes 15.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 16.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 V/ns. Document Number: 001-68998 Rev. *G Page 15 of 29

CY7C1562XV18/CY7C1564XV18 TAP Timing and Test Conditions Figure3 shows the TAP timing and test conditions. [17] Figure 3. TAP Timing and Test Conditions 0.9V ALL INPUT PULSES 1.8V 50 0.9V TDO 0V Z0= 50 CL= 20 pF Slew Rate = 1 V/ns (a) GND tTH tTL Test Clock TCK t TCYC t TMSH t TMSS Test Mode Select TMS t TDIS t TDIH Test Data In TDI Test Data Out TDO tTDOV tTDOX Note 17.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 V/ns. Document Number: 001-68998 Rev. *G Page 16 of 29

CY7C1562XV18/CY7C1564XV18 Identification Register Definitions Value Instruction Field Description CY7C1562XV18 CY7C1564XV18 Revision Number (31:29) 000 000 Version number. Cypress Device ID (28:12) 11010010000010100 11010010000100100 Defines the type of SRAM. Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. ID Register Presence (0) 1 1 Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 109 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the input and output contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-68998 Rev. *G Page 17 of 29

CY7C1562XV18/CY7C1564XV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H Document Number: 001-68998 Rev. *G Page 18 of 29

CY7C1562XV18/CY7C1564XV18 Power Up Sequence in QDR II+ Xtreme SRAM PLL Constraints ■PLL uses K clock as its synchronizing input. The input must QDR II+ Xtreme SRAMs must be powered up and initialized in a have low phase jitter, which is specified as t . predefined manner to prevent undefined operations. KC Var ■The PLL functions at frequencies down to 120 MHz. Power Up Sequence ■If the input clock is unstable and the PLL is enabled, then the ■Apply power and drive DOFF either HIGH or LOW (All other PLL may lock onto an incorrect frequency, causing unstable inputs can be HIGH or LOW). SRAM behavior. To avoid this, provide 100 s of stable clock ❐Apply VDD before VDDQ. to relock to the desired clock frequency. ❐Apply V before V or at the same time as V . DDQ REF REF ❐Drive DOFF HIGH. ■Provide stable DOFF (HIGH), power and clock (K, K) for 100 s to lock the PLL. Figure 4. Power Up Waveforms Document Number: 001-68998 Rev. *G Page 19 of 29

CY7C1562XV18/CY7C1564XV18 Maximum Ratings Neutron Soft Error Immunity Exceeding maximum ratings may impair the useful life of the Test Parameter Description Typ Max* Unit device. These user guidelines are not tested. Conditions Storage Temperature ...............................–65 °C to +150 °C LSBU Logical 25 °C 260 271 FIT/ Single-Bit Mb Supply Voltage on V Relative to GND .....–0.5 V to +2.9 V DD Upsets Supply Voltage on V Relative to GND ....–0.5 V to +V DDQ DD LMBU Logical 25 °C 0 0.01 FIT/ DC Applied to Outputs in High Z .......–0.5 V to VDDQ + 0.3 V Multi-Bit Mb DC Input Voltage [18] ...........................–0.5 V to V + 0.3 V Upsets DD Current into Outputs (LOW) ........................................20 mA SEL Single Event 85 °C 0 0.1 FIT/ Latchup Dev Static Discharge Voltage (MIL-STD-883, M. 3015) .........................................> 2001 V *s taNtois tLicMalB U 2o, r 9S5E%L ecovennfidtse noccec urlirmedit dcuarlicnugl atteiosnti.n gF; otrh ism coorelu mdne tareilpsr erseefenrt s tao Latch up Current ....................................................> 200 mA Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates”. Maximum Junction Temperature ...............................125 °C Operating Range Range Ambient V [19] V [19] Temperature (T ) DD DDQ A Commercial 0 °C to +70 °C 1.8 ± 0.1 V 1.4 V to 1.6 V Electrical Characteristics Over the Operating Range DC Electrical Characteristics Over the Operating Range Parameter [20] Description Test Conditions Min Typ Max Unit V Power Supply Voltage 1.7 1.8 1.9 V DD V I/Os Supply Voltage 1.4 1.5 1.6 V DDQ V Output HIGH Voltage Note 21 V /2 – 0.12 – V /2 + 0.12 V OH DDQ DDQ V Output LOW Voltage Note 22 V /2 – 0.12 – V /2 + 0.12 V OL DDQ DDQ V Output HIGH Voltage I =0.1 mA, Nominal Impedance V – 0.2 – V V OH(LOW) OH DDQ DDQ V Output LOW Voltage I = 0.1 mA, Nominal Impedance V – 0.2 V OL(LOW) OL SS V Input HIGH Voltage V + 0.1 – V + 0.15 V IH REF DDQ V Input LOW Voltage –0.15 – V – 0.1 V IL REF I Input Leakage Current GND  V  V 2 – 2 A X I DDQ I Output Leakage Current GND  V  V Output Disabled 2 – 2 A OZ I DDQ, V Input Reference Voltage Typical Value = 0.75 V 0.68 0.75 0.86 V REF Notes 18.Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2). 19.Power up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 20.All Voltage referenced to Ground. 21.Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 ohms < RQ < 350 ohms. 22.Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms < RQ < 350 ohms. Document Number: 001-68998 Rev. *G Page 20 of 29

CY7C1562XV18/CY7C1564XV18 Electrical Characteristics (continued) Over the Operating Range DC Electrical Characteristics (continued) Over the Operating Range Parameter [20] Description Test Conditions Min Typ Max Unit I [23] V Operating Supply V = Max, I = 0 mA, 450 MHz (× 18) – – 1205 mA DD DD DD OUT f = f = 1/t MAX CYC (× 36) – – 1445 366 MHz (× 18) – – 970 mA (× 36) – – 1165 I Automatic Power down Max V , 450 MHz (× 18) – – 1205 mA SB1 DD Current Both Ports Deselected, (× 36) – – 1445 V  V or V  V IN IH IN IL f = f = 1/t , 366 MHz (× 18) – – 970 mA MAX CYC Inputs Static (× 36) – – 1165 Note 23.The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-68998 Rev. *G Page 21 of 29

CY7C1562XV18/CY7C1564XV18 AC Electrical Characteristics Over the Operating Range Parameter [24] Description Test Conditions Min Typ Max Unit V Input HIGH Voltage V + 0.2 – V + 0.24 V IH REF DDQ V Input LOW Voltage –0.24 – V – 0.2 V IL REF Capacitance Parameter [25] Description Test Conditions Max Unit C Input capacitance T = 25 C, f = 1 MHz, V = 1.8 V, V = 1.5 V 4 pF IN A DD DDQ C Output capacitance 4 pF O Thermal Resistance Parameter [25] Description Test Conditions 165-ball FBGA Unit Package  (0 m/s) Thermal resistance Socketed on a 170 × 220 × 2.35 mm, eight-layer printed 14.43 °C/W JA (junction to ambient) circuit board  (1 m/s) 13.40 °C/W JA  (3 m/s) 12.66 °C/W JA  Thermal resistance 11.38 °C/W JB (junction to board)  Thermal resistance 3.30 °C/W JC (junction to case) AC Test Loads and Waveforms Figure 5. AC Test Loads and Waveforms V = 0.75 V REF V 0.75 V REF OUTPUT VREF 0.75 V R = 50  [26] ALL INPUT PULSES DEVICE Z0= 50  R = 50  OUTPUT 1.25 V L UNDER DEVICE 0.75 V TEST UNDER 5pF 0.25 V VREF = 0.75 V TEST ZQ SLEW RATE= 2 V/ns ZQ RQ = RQ = 250  250  INCLUDING JIG AND (b) (a) SCOPE Notes 24.Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2). 25.Tested initially and after any design or process change that may affect these parameters. 26.Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure5. Document Number: 001-68998 Rev. *G Page 22 of 29

CY7C1562XV18/CY7C1564XV18 Switching Characteristics Over the Operating Range Parameter [27, 28] 450 MHz 366 MHz Description Unit Cypress Consortium Min Max Min Max Parameter Parameter t V (typical) to the first access [29] 1 – 1 – ms POWER DD t t K clock cycle time 2.2 8.4 2.73 8.4 ns CYC KHKH t t Input clock (K/K) HIGH 0.4 – 0.4 – ns KH KHKL t t Input clock (K/K) LOW 0.4 – 0.4 – ns KL KLKH t t K clock rise to K clock rise (rising edge to rising edge) 0.94 – 1.16 – ns KHKH KHKH Setup Times t t Address setup to K clock rise 0.275 – 0.4 – ns SA AVKH tSC tIVKH Control setup to K clock rise (RPS, WPS) 0.275 – 0.4 – ns t t DDR control setup to clock (K/K) rise (BWS , BWS , BWS , BWS ) 0.275 – 0.4 – ns SCDDR IVKH 0 1 2 3 t t D setup to clock (K/K) rise 0.275 – 0.4 – ns SD DVKH [X:0] Hold Times t t Address hold after K clock rise 0.275 – 0.4 – ns HA KHAX tHC tKHIX Control hold after K clock rise (RPS, WPS) 0.275 – 0.4 – ns t t DDR control hold after clock (K/K) rise (BWS , BWS , BWS , BWS ) 0.275 – 0.4 – ns HCDDR KHIX 0 1 2 3 t t D hold after clock (K/K) rise 0.275 – 0.4 – ns HD KHDX [X:0] Output Times tCCQO tCHCQV K/K clock rise to echo clock valid – 0.45 – 0.45 ns tCQOH tCHCQX Echo clock hold after K/K clock rise –0.45 – –0.45 – ns t t Echo clock high to data valid – 0.13 – 0.15 ns CQD CQHQV t t Echo clock high to data invalid –0.13 – –0.15 – ns CQDOH CQHQX t t Output clock (CQ/CQ) HIGH [30] 1.02 – 1.285 – ns CQH CQHCQL tCQHCQH tCQHCQH CQ clock rise to CQ clock rise (rising edge to rising edge) [30] 1.02 – 1.285 – ns tCHZ tCHQZ Clock (K/K) rise to high Z (active to high Z) [31, 32] – 0.45 – 0.45 ns tCLZ tCHQX1 Clock (K/K) rise to low Z [31, 32] –0.45 – –0.45 – ns t t Echo clock high to QVLD valid [33] –0.15 0.15 –0.20 0.20 ns QVLD CQHQVLD PLL Timing t t Clock phase jitter – 0.15 – 0.15 ns KC Var KC Var t t PLL lock time (K) 100 – 100 – s KC lock KC lock t t K static to PLL reset [34] 30 – 30 – ns KC Reset KC Reset Notes 27.Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5 on page 22. 28.When a part with a maximum frequency above 366 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 29.This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD(minimum) initially before initiating a read or write operation. 30.These parameters are extrapolated from the input timing parameters (tCYC/2 – 80 ps, where 80 ps is the internal jitter). These parameters are only guaranteed by design and are not tested in production. 31.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of Figure 5 on page 22. Transition is measured  100 mV from steady state voltage. 32.At any voltage and temperature tCHZ is less than tCLZ . 33.tQVLD spec is applicable for both rising and falling edges of QVLD signal. 34.Hold to >VIH or <VIL. Document Number: 001-68998 Rev. *G Page 23 of 29

CY7C1562XV18/CY7C1564XV18 Switching Waveforms Read/Write/Deselect Sequence Figure 6. Waveform for 2.5 Cycle Read Latency [35, 36, 37] Notes 35.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1. 36.Outputs are disabled (High Z) one clock cycle after a NOP. 37.In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-68998 Rev. *G Page 24 of 29

CY7C1562XV18/CY7C1564XV18 Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed Package Operating Ordering Code Package Type (MHz) Diagram Range 450 CY7C1562XV18-450BZC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Commercial CY7C1562XV18-450BZXC 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free CY7C1564XV18-450BZC 165-ball FBGA (13 × 15 × 1.4 mm) CY7C1564XV18-450BZXC 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free 366 CY7C1562XV18-366BZXC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free Commercial Ordering Code Definitions CY 7 C 156X X V18 - XXX BZ X C Temperature range: C = Commercial Pb-free Package Type: BZ = 165-ball FBGA Speed grade: XXX = 450 MHz or 366 MHz V18 = 1.8 V Die Revision Part Identifier: 156X = 1562 or 1564 Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-68998 Rev. *G Page 25 of 29

CY7C1562XV18/CY7C1564XV18 Package Diagram Figure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180 51-85180 *G Document Number: 001-68998 Rev. *G Page 26 of 29

CY7C1562XV18/CY7C1564XV18 Acronyms Document Conventions Units of Measure Acronym Description DDR Double Data Rate Symbol Unit of Measure FBGA Fine-Pitch Ball Grid Array °C degree Celsius HSTL High-Speed Transceiver Logic MHz megahertz I/O Input/Output µA microampere µs microsecond JTAG Joint Test Action Group mA milliampere LSB Least Significant Bit mm millimeter LMBU Logical Multi-Bit Upsets ms millisecond LSBU Logical Single-Bit Upsets mV millivolt MSB Most Significant Bit ns nanosecond ODT On-Die Termination  ohm PLL Phase-Locked Loop % percent QDR Quad Data Rate pF picofarad SEL Single Event Latch-up ps picosecond SRAM Static Random Access Memory V volt TAP Test Access Port W watt TCK Test Clock TDI Test Data-In TDO Test Data-Out TMS Test Mode Select Document Number: 001-68998 Rev. *G Page 27 of 29

CY7C1562XV18/CY7C1564XV18 Document History Page Document Title: CY7C1562XV18/CY7C1564XV18, 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Document Number: 001-68998 Orig. of Submission Rev. ECN Description of Change Change Date ** 3302026 OSN 07/04/2011 New data sheet. *A 3532310 PRIT 02/22/2012 Changed status from Preliminary to Final. *B 3650993 PRIT 06/20/2012 No technical updates. *C 3767747 PRIT 10/05/2012 Updated Application Example (Updated Figure2). Updated TAP Electrical Characteristics (Updated Note 13). Updated TAP AC Switching Characteristics (Updated Note 16). Updated TAP Timing and Test Conditions (Updated Note 17 and updated Figure3). Updated Thermal Resistance (Changed value of  parameter from JA 23.94°C/W to 14.84°C/W for 165-ball FBGA Package, changed value of  JC parameter from 3.0°C/W to 5.1°C/W for 165-ball FBGA Package). Updated Package Diagram (spec 51-85180 (Changed revision from *E to *F)). *D 4388611 PRIT 05/23/2014 Updated Application Example: Updated Figure2. Updated Thermal Resistance: Updated values of  parameter. JA Included  parameter and its details. JB Updated to new template. Completing Sunset Review. *E 4575392 PRIT 11/20/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *F 5341268 PRIT 07/07/2016 Updated Ordering Information: Updated part numbers. Updated Package Diagram: spec 51-85180 – Changed revision from *F to *G. Updated to new template. Completing Sunset Review. *G 6012160 AESATP12 01/03/2018 Updated logo and copyright. Document Number: 001-68998 Rev. *G Page 28 of 29

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Document Number: 001-68998 Rev. *G Revised January 3, 2018 Page 29 of 29

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