Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com

THIS SPEC IS OBSOLETE Spec No: 38-05353 Spec Title: CY7C1460AV33/CY7C1462AV33, 36-MBIT (1M X 36/2M X 18) PIPELINED SRAM WITH NOBL(TM) ARCHITECTURE Replaced by: None

CY7C1460AV33 CY7C1462AV33 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description ■Pin compatible and functionally equivalent to ZBT The CY7C1460AV33/CY7C1462AV33 are 3.3V, 1M×36/2M×18 synchronous pipelined burst SRAMs with No Bus Latency™ ■Supports 250 MHz bus operations with zero wait states (NoBL logic, respectively. They are designed to support ❐Available speed grades are 250, 200 and 167 MHz unlimited true back-to-back read/write operations with no wait states. The CY7C1460AV33/CY7C1462AV33 are equipped with ■Internally self timed output buffer control to eliminate the need the advanced (NoBL) logic required to enable consecutive to use asynchronous OE read/write operations with data being transferred on every clock ■Fully registered (inputs and outputs) for pipelined operation cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. The ■Byte write capability CY7C1460AV33/CY7C1462AV33 are pin compatible and ■3.3 V power supply functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by ■3.3 V/2.5 V I/O power supply the rising edge of the clock. All data outputs pass through output ■Fast clock-to-output times registers controlled by the rising edge of the clock. The clock ❐2.6 ns (for 250 MHz device) input is qualified by the clock enable (CEN) signal, which when deasserted suspends operation and extends the previous clock ■Clock enable (CEN) pin to suspend operation cycle. ■Synchronous self timed writes Write operations are controlled by the byte write selects (BW –BW for CY7C1460AV33 and BW –BW for ■CY7C1460AV33 available in JEDEC-standard Pb-free 100-pin a d a b CY7C1462AV33) and a write enable (WE) input. All writes are TQFP and non Pb-free 165-ball FBGA package. conducted with on-chip synchronous self timed write circuitry. CY7C1462AV33 available in JEDEC-standard Pb-free 100-pin TQFP. Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 asynchronous output enable (OE) provide for easy bank ■IEEE 1149.1 JTAG-compatible boundary scan selection and output tristate control. To avoid bus contention, the ■Burst capability – linear or interleaved burst order output drivers are synchronously tristated during the data portion of a write sequence. ■“ZZ” sleep mode option and stop clock option For a complete list of related documentation, click here. Logic Block Diagram – CY7C1460AV33 A0, A1, A ADDRESS MODE REGISTER 0 AA01 DD10BLOURGSICT QQ10AA01'' CLK C ADV/LDC CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 ADVBBBB/WWWLWWDEbacd ANDWC ODRNAITTTEAR O RCELGO LIHSOETGRRIEYCNCY DWRIRVIETRES MAERMROARYY MNAEEPSSS EOUUGRRTPTETESSI DAANRTTEESI OUUUBRTPTEFFSE DDDDDQQQQQsPPPPcdab G INPUT INPUT REGISTER 1 E REGISTER 0 E OE CE1 READ LOGIC CE2 CE3 ZZ COSNLETERPOL CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 38-05353 Rev. *P Revised November 2, 2016

CY7C1460AV33 CY7C1462AV33 Logic Block Diagram – CY7C1462AV33 A0, A1, A ADDRESS REGISTER 0 A1 D1 Q1 A1' MODE A0 D0BLOURGSICT Q0A0' CLK C ADV/LDC CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 ADVBB/WWWLDEba ANDWC ODRNAITTTEAR O RCELGO LIHSOETGRRIEYCNCY DWRIRVIETRES MAERMROARYY MNAEEPSSS OUUGRRTPTETESSI DAANGRTTEESI OUUUBRTPTEFFS DDDQQQsPPab E E INPUT INPUT REGISTER 1 E REGISTER 0 E OE CE1 READ LOGIC CE2 CE3 ZZ CSolneterpol Document Number: 38-05353 Rev. *P Page 2 of 31

CY7C1460AV33 CY7C1462AV33 Contents Selection Guide ................................................................4 TAP DC Electrical Characteristics and Pin Configurations ...........................................................4 Operating Conditions .....................................................16 Pin Definitions ..................................................................6 Identification Register Definitions ................................17 Functional Overview ........................................................7 Scan Register Sizes .......................................................17 Single Read Accesses ................................................7 Instruction Codes ...........................................................17 Burst Read Accesses ..................................................7 Boundary Scan Order ....................................................18 Single Write Accesses .................................................7 Maximum Ratings ...........................................................19 Burst Write Accesses ..................................................8 Operating Range .............................................................19 Sleep Mode .................................................................8 Neutron Soft Error Immunity .........................................19 Interleaved Burst Address Table .................................8 Electrical Characteristics ...............................................19 Linear Burst Address Table .........................................8 Capacitance ....................................................................20 ZZ Mode Electrical Characteristics ..............................8 Thermal Resistance ........................................................20 Truth Table ........................................................................9 AC Test Loads and Waveforms .....................................21 Partial Write Cycle Description .....................................10 Switching Characteristics ..............................................22 Partial Write Cycle Description .....................................10 Switching Waveforms ....................................................23 IEEE 1149.1 Serial Boundary Scan (JTAG) ..................11 Ordering Information ......................................................25 Disabling the JTAG Feature ......................................11 Ordering Code Definitions .........................................25 Test Access Port (TAP) .............................................11 Package Diagrams ..........................................................26 PERFORMING A TAP RESET ..................................11 Acronyms ........................................................................28 TAP REGISTERS ......................................................11 Document Conventions .................................................28 TAP Instruction Set ...................................................11 Units of Measure .......................................................28 TAP Controller State Diagram .......................................13 Document History Page .................................................29 TAP Controller Block Diagram ......................................14 Sales, Solutions, and Legal Information ......................31 TAP Timing Diagram ......................................................14 Worldwide Sales and Design Support .......................31 TAP AC Switching Characteristics ...............................15 Products ....................................................................31 3.3 V TAP AC Test Conditions .......................................15 PSoC® Solutions ......................................................31 3.3 V TAP AC Output Load Equivalent .........................15 Cypress Developer Community .................................31 2.5 V TAP AC Test Conditions .......................................15 Technical Support .....................................................31 2.5 V TAP AC Output Load Equivalent .........................15 Document Number: 38-05353 Rev. *P Page 3 of 31

CY7C1460AV33 CY7C1462AV33 Selection Guide Description 250 MHz 200 MHz 167 MHz Unit Maximum access time 2.6 3.2 3.4 ns Maximum operating current 475 425 375 mA Maximum CMOS standby current 120 120 120 mA Pin Configurations Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout D D L L AACE1CE2BWdBWcBWbBWaCE3VDDVSSCLKWECENOEADV/AA AA AACE1CE2NCNCBWbBWaCE3VDDVSSCLKWECENOEADV/AA AA 0 0 09876543210987654321 09876543210987654321 19999999999888888888 19999999999888888888 DQPc 1 80 DQPb NC 1 80 A DQc 2 79 DQb NC 2 79 NC DQc 3 78 DQb NC 3 78 NC VDDQ 4 77 VDDQ VDDQ 4 77 VDDQ VSS 5 76 VSS VSS 5 76 VSS DQc 6 75 DQb NC 6 75 NC DQc 7 74 DQb NC 7 74 DQPa DQc 8 73 DQb DQb 8 73 DQa DQc 9 72 DQb DQb 9 72 DQa VVDSDSQ 1101 7710 VVSDSDQ VVDSDSQ 1101 7710 VVSDSDQ DQc 12 69 DQb DQb 12 69 DQa DQc 13 68 DQb DQb 13 68 DQa VNVNDCSCDS 11114567 CY7(1CM14 ×6 03A6)V33 66667654 VNVZSDCZSD NVNVCDCSDS 11114567 CY7(C2M14 ×6 21A8V)33 66667654 VNVZZSDCSD DQd 18 63 DQa DQb 18 63 DQa VVDDSDQSQd 122901 666210 DVVSQDSDaQ VDVDQSDSbQ 122901 666210 DVVSQDSDaQ DQd 22 59 DQa DQb 22 59 DQa DQd 23 58 DQa DQb 23 58 DQa DQd 24 57 DQa DQPb 24 57 NC DQd 25 56 DQa NC 25 56 NC VVDSDSQ 2267 5554 VVSDSDQ VVDSDSQ 2267 5554 VVSDSDQ DQd 28 53 DQa NC 28 53 NC DQd 29 52 DQa NC 29 52 NC DQPd 30 51 DQPa NC 30 51 NC 12345678901234567890 12345678901234567890 33333333344444444445 33333333344444444445 MODE AAAAA1A0NC/288M NC/144MVSSVDD NC/72MAAAAAAA A MODE AAAAA1A0 NC/288M NC/144MVSSVDD NC/72M AAAAAAA A Document Number: 38-05353 Rev. *P Page 4 of 31

CY7C1460AV33 CY7C1462AV33 Pin Configurations (continued) Figure 2. 165-ball FBGA (15 × 17 × 1.40 mm) pinout CY7C1460AV33 (1M × 36) 1 2 3 4 5 6 7 8 9 10 11 A NC/576M A CE1 BWc BWb CE3 CEN ADV/LD A A NC B NC/1G A CE BW BW CLK WE OE A A NC 2 d a C DQP NC V V V V V V V NC DQP c DDQ SS SS SS SS SS DDQ b D DQ DQ V V V V V V V DQ DQ c c DDQ DD SS SS SS DD DDQ b b E DQ DQ V V V V V V V DQ DQ c c DDQ DD SS SS SS DD DDQ b b F DQ DQ V V V V V V V DQ DQ c c DDQ DD SS SS SS DD DDQ b b G DQ DQ V V V V V V V DQ DQ c c DDQ DD SS SS SS DD DDQ b b H NC NC NC V V V V V NC NC ZZ DD SS SS SS DD J DQ DQ V V V V V V V DQ DQ d d DDQ DD SS SS SS DD DDQ a a K DQ DQ V V V V V V V DQ DQ d d DDQ DD SS SS SS DD DDQ a a L DQ DQ V V V V V V V DQ DQ d d DDQ DD SS SS SS DD DDQ a a M DQ DQ V V V V V V V DQ DQ d d DDQ DD SS SS SS DD DDQ a a N DQP NC V V NC NC NC V V NC DQP d DDQ SS SS DDQ a P NC/144M NC/72M A A TDI A1 TDO A A A NC/288M R MODE A A A TMS A0 TCK A A A A Document Number: 38-05353 Rev. *P Page 5 of 31

CY7C1460AV33 CY7C1462AV33 Pin Definitions Pin Name I/O Type Pin Description A , A , A Input- Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK. 0 1 synchronous BW , BW , Input- Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled a b BW , BW , synchronous on the rising edge of CLK. BW controls DQ and DQP , BW controls DQ and DQP , BW controls c d a a a b b b c BW , BW, DQ and DQP , BW controls DQ and DQP , BW controls DQ and DQP , BW controls DQ and e f c c d d d e e e f f BW , BW DQP, BW controls DQ and DQP , BW controls DQ and DQP . g h f g g g h h h WE Input- Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal synchronous must be asserted LOW to initiate a write sequence. ADV/LD Input- Advance/load input used to advance the on-chip address counter or load a new address. When synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW to load a new address. CLK Input- Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is clock only recognized if CEN is active LOW. CE Input- Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE 1 2 synchronous and CE to select/deselect the device. 3 CE Input- Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE 2 1 synchronous and CE to select/deselect the device. 3 CE Input- Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE 3 1 synchronous andCE to select/deselect the device. 2 OE Input- Output enable, active LOW. Combined with the synchronous logic block inside the device to control asynchronous the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. CEN Input- Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. DQ , DQ , I/O- Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the a b DQ , DQ , synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A c d X DQ , DQ, during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the e f DQ , DQ internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, g h DQ –DQ are placed in a tristate condition. The outputs are automatically tristated during the data a d portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQP , DQP , I/O- Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ . During write a b [31:0] DQP , DQP , synchronous sequences, DQP is controlled by BW , DQP is controlled by BW , DQP is controlled by BW , and c d a a b b c c DQP , DQP, DQP is controlled by BW , DQP is controlled by BW , DQP is controlled by BW, DQP is controlled e f d d e e f f g DQP , DQP by BW , DQP is controlled by BW . g h g h h MODE Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE defaults HIGH, to an interleaved burst order. TDO JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. output synchronous TDI JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. input synchronous Document Number: 38-05353 Rev. *P Page 6 of 31

CY7C1460AV33 CY7C1462AV33 Pin Definitions (continued) Pin Name I/O Type Pin Description TMS Test mode This pin controls the test access port state machine. Sampled on the rising edge of TCK. select synchronous TCK JTAG-clock Clock input to the JTAG circuitry. V Power supply Power supply inputs to the core of the device. DD V I/O power Power supply for the I/O circuitry. DDQ supply V Ground Ground for the device. Should be connected to ground of the system. SS NC N/A No connects. This pin is not connected to the die. NC/72M N/A Not connected to the die. Can be tied to any voltage level. NC/144M N/A Not connected to the die. Can be tied to any voltage level. NC/288M N/A Not connected to the die. Can be tied to any voltage level. NC/576M N/A Not connected to the die. Can be tied to any voltage level. NC/1G N/A Not connected to the die. Can be tied to any voltage level. ZZ Input- ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with asynchronous data integrity preserved. During normal operation, this pin can be connected to V or left floating. ZZ SS pin has an internal pull-down. Functional Overview progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the The CY7C1460AV33/CY7C1462AV33 are synchronous-pipelined requested data is allowed to propagate through the output burst NoBL SRAMs designed specifically to eliminate wait states register and onto the data bus within 2.6 ns (250 MHz device) during write/read transitions. All synchronous inputs pass provided OE is active LOW. After the first clock of the read through input registers controlled by the rising edge of the clock. access the output buffers are controlled by OE and the internal The clock signal is qualified with the clock enable input signal control logic. OE must be driven LOW for the device to drive out (CEN). If CEN is HIGH, the clock signal is not recognized and all the requested data. During the second clock, a subsequent internal states are maintained. All synchronous operations are operation (read/write/deselect) can be initiated. Deselecting the qualified with CEN. All data outputs pass through output registers device is also pipelined. Therefore, when the SRAM is controlled by the rising edge of the clock. Maximum access delay deselected at clock rise by one of the chip enable signals, its from the clock rise (t ) is 2.6 ns (250 MHz device). output tristates following the next clock rise. CO Accesses can be initiated by asserting all three chip enables Burst Read Accesses (CE , CE , CE ) active at the rising edge of the clock. If clock 1 2 3 enable (CEN) is active LOW and ADV/LD is asserted LOW, the The CY7C1460AV33/CY7C1462AV33 have an on-chip burst address presented to the device is latched. The access can counter that enables the user the ability to supply a single either be a read or write operation, depending on the status of address and conduct up to four reads without reasserting the the write enable (WE). BW can be used to conduct byte write address inputs. ADV/LD must be driven LOW in order to load a [x] operations. new address into the SRAM, as described in the section Single Read Accesses earlier. The sequence of the burst counter is Write operations are qualified by the write enable (WE). All writes determined by the MODE input signal. A LOW input on MODE are simplified with on-chip synchronous self timed write circuitry. selects a linear burst mode, a HIGH selects an interleaved burst Three synchronous chip enables (CE , CE , CE ) and an sequence. Both burst counters use A0 and A1 in the burst 1 2 3 asynchronous output enable (OE) simplify depth expansion. All sequence, and wraps around when incremented sufficiently. A operations (reads, writes, and deselects) are pipelined. ADV/LD HIGH input on ADV/LD increments the internal burst counter should be driven LOW after the device has been deselected to regardless of the state of chip enables inputs or WE. WE is load a new address for the next operation. latched at the beginning of a burst cycle. Therefore, the type of access (read or write) is maintained throughout the burst Single Read Accesses sequence. A read access is initiated when the following conditions are Single Write Accesses satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE , 1 2 and CE are all asserted active, (3) the write enable input signal Write access are initiated when the following conditions are 3 WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE , 1 2 address presented to the address inputs is latched into the and CE are all asserted active, and (3) the write signal WE is 3 address register and presented to the memory core and control asserted LOW. The address presented to the address inputs is logic. The control logic determines that a read access is in Document Number: 38-05353 Rev. *P Page 7 of 31

CY7C1460AV33 CY7C1462AV33 loaded into the address register. The write signals are latched on page 7 earlier. When ADV/LD is driven HIGH on the into the control logic block. subsequent clock rise, the chip enables (CE , CE , and CE ) 1 2 3 and WE inputs are ignored and the burst counter is incremented. On the subsequent clock rise the data lines are automatically The correct BW (BW for CY7C1460AV33 and BW for tristated regardless of the state of the OE input signal. This a,b,c,d a,b CY7C1462AV33) inputs must be driven in each cycle of the burst enables the external logic to present the data on DQand DQP write in order to write the correct bytes of data. (DQ /DQP for CY7C1460AV33 and DQ /DQP for a,b,c,d a,b,c,d a,b a,b CY7C1462AV33). In addition, the address for the subsequent Sleep Mode access (read/write/deselect) is latched into the address register (provided the appropriate control signals are asserted). The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock On the next clock rise the data presented to DQ and DQP cycles are required to enter into or exit from this “sleep” mode. (DQ /DQP for CY7C1460AV33 and DQ /DQP for a,b,c,d a,b,c,d a,b a,b While in this mode, data integrity is guaranteed. Accesses CY7C1462AV33) (or a subset for byte write operations, see pending when entering the “sleep” mode are not considered valid Write Cycle Description table for details) inputs is latched into the nor is the completion of the operation guaranteed. The device device and the write is complete. must be deselected prior to entering the “sleep” mode. CE , CE , 1 2 The data written during the write operation is controlled by BW and CE , must remain inactive for the duration of t after the 3 ZZREC (BWa,b,c,d for CY7C1460AV33 and BWa,b for CY7C1462AV33) ZZ input returns LOW. signals. The CY7C1460AV33/CY7C1462AV33 provides byte write capability that is described in the Write Cycle Description table. Asserting the write enable input (WE) with the selected Interleaved Burst Address Table byte write select (BW) input selectively writes to only the desired (MODE = Floating or V ) bytes. Bytes not selected during a byte write operation remains DD unaltered. A synchronous self timed write mechanism has been First Second Third Fourth provided to simplify the write operations. Byte write capability Address Address Address Address has been included in order to greatly simplify read/modify/write A1, A0 A1, A0 A1, A0 A1, A0 sequences, which can be reduced to simple byte write 00 01 10 11 operations. 01 00 11 10 Because the CY7C1460AV33/CY7C1462AV33 are common I/O devices, data should not be driven into the device while the 10 11 00 01 outputs are active. The output enable (OE) can be deasserted 11 10 01 00 HIGH before presenting data to the DQ and DQP (DQ /DQP for CY7C1460AV33 and DQ /DQP for a,b,c,d a,b,c,d a,b a,b CY7C1462AV33) inputs. Doing so tristates the output drivers. As a safety precaution, DQ and DQP (DQ /DQP for Linear Burst Address Table a,b,c,d a,b,c,d CY7C1460AV33 and DQ /DQP for CY7C1462AV33) are a,b a,b (MODE = GND) automatically tristated during the data portion of a write cycle, regardless of the state of OE. First Second Third Fourth Address Address Address Address Burst Write Accesses A1, A0 A1, A0 A1, A0 A1, A0 The CY7C1460AV33/CY7C1462AV33 has an on-chip burst 00 01 10 11 counter that allows the user the ability to supply a single address 01 10 11 00 and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the 10 11 00 01 initial address, as described in the section Single Write Accesses 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit I Sleep mode standby current ZZ  V  0.2 V – 100 mA DDZZ DD t Device operation to ZZ ZZV  0.2 V – 2t ns ZZS DD CYC t ZZ recovery time ZZ  0.2 V 2t – ns ZZREC CYC t ZZ active to sleep current This parameter is sampled – 2t ns ZZI CYC t ZZ inactive to exit sleep current This parameter is sampled 0 – ns RZZI Document Number: 38-05353 Rev. *P Page 8 of 31

CY7C1460AV33 CY7C1462AV33 Truth Table The Truth Table for CY7C1460AV33/CY7C1462AV33 follows. [1, 2, 3, 4, 5, 6, 7] Operation Address Used CE ZZ ADV/LD WE BW OE CEN CLK DQ x Deselect cycle None H L L X X X L L–H Tri-state Continue deselect cycle None X L H X X X L L–H Tri-state Read cycle (begin burst) External L L L H X L L L–H Data out (Q) Read cycle (continue burst) Next X L H X X L L L–H Data out (Q) NOP/dummy read (begin burst) External L L L H X H L L–H Tri-state Dummy read (continue burst) Next X L H X X H L L–H Tri-state Write cycle (begin burst) External L L L L L X L L–H Data in (D) Write cycle (continue burst) Next X L H X L X L L–H Data in (D) NOP/WRITE ABORT (begin burst) None L L L L H X L L–H Tri-state WRITE ABORT (continue burst) Next X L H X H X L L–H Tri-state IGNORE CLOCK EDGE (stall) Current X L X X X X H L–H – SLEEP MODE None X H X X X X X X Tri-state Notes 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BWX. See Write Cycle Description table for details. 3. When a write cycle is detected, all I/Os are tristated, even during byte writes. 4. The DQ and DQP pins are controlled by the current cycle and the OE signal. 5. CEN = H inserts wait states. 6. Device powers up deselected and the I/Os in a tristate condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Tristate when OE is inactive or when the device is deselected, and DQs=data when OE is active. Document Number: 38-05353 Rev. *P Page 9 of 31

CY7C1460AV33 CY7C1462AV33 Partial Write Cycle Description The Partial Write Cycle Description for CY7C1460AV33 follows. [8, 9, 10, 11] Function (CY7C1460AV33) WE BW BW BW BW d c b a Read H X X X X Write – no bytes written L H H H H Write byte a – (DQ andDQP ) L H H H L a a Write byte b – (DQ andDQP ) L H H L H b b Write bytes b, a L H H L L Write byte c – (DQ andDQP ) L H L H H c c Write bytes c, a L H L H L Write bytes c, b L H LL L H Write bytes c, b, a L H L L L Write byte d – (DQ andDQP ) L L H H H d d Write bytes d, a L L H H L Write bytes d, b L L H L H Write bytes d, b, a L L H L L Write bytes d, c L L L H H Write bytes d, c, a L L L H L Write bytes d, c, b L L L L H Write all bytes L L L L L Partial Write Cycle Description The Partial Write Cycle Description for CY7C1462AV33 follows. [9, 11] Function (CY7C1462AV33) WE BW BW b a Read H x x Write – no bytes written L H H Write byte a – (DQ andDQP ) L H L a a Write byte b – (DQ andDQP ) L L H b b Write both bytes L L L Notes 8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 9. Write is defined by WE and BWX. See Write Cycle Description table for details. 10.When a write cycle is detected, all I/Os are tristated, even during byte writes. 11.Table only lists a partial listing of the byte write combinations. Any combination of BW[a:d] is valid. Appropriate write is done based on which byte write is active. Document Number: 38-05353 Rev. *P Page 10 of 31

CY7C1460AV33 CY7C1462AV33 IEEE 1149.1 Serial Boundary Scan (JTAG) instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling The CY7C1460AV33 incorporates a serial boundary scan test edge of TCK. access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic Instruction Register level. Three bit instructions can be serially loaded into the instruction The CY7C1460AV33 contains a TAP controller, instruction register. This register is loaded when it is placed between the TDI register, boundary scan register, bypass register, and ID register. and TDO balls as shown in the TAP Controller Block Diagram on page 14. Upon power-up, the instruction register is loaded with Disabling the JTAG Feature the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described It is possible to operate the SRAM without using the JTAG in the previous section. feature. To disable the TAP controller, TCK must be tied LOW (V ) to prevent clocking of the device. TDI and TMS are When the TAP controller is in the Capture-IR state, the two least SS internally pulled up and may be unconnected. They may significant bits are loaded with a binary “01” pattern to enable alternately be connected to VDD through a pull-up resistor. TDO fault isolation of the board-level serial test data path. should be left unconnected. Upon power-up, the device comes Bypass Register up in a reset state which does not interfere with the operation of the device. To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass Test Access Port (TAP) register is a single bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the Test Clock (TCK) SRAM with minimal delay. The bypass register is set LOW (V ) SS The test clock is used only with the TAP controller. All inputs are when the BYPASS instruction is executed. captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Boundary Scan Register The boundary scan register is connected to all the input and Test Mode Select (TMS) bidirectional balls on the SRAM. The length of the boundary scan The TMS input is used to give commands to the TAP controller register for the SRAM in different packages is listed in the Scan and is sampled on the rising edge of TCK. It is allowable to leave Register Sizes table. this ball unconnected if the TAP is not used. The ball is pulled up The boundary scan register is loaded with the contents of the internally, resulting in a logic HIGH level. RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the Test Data-In (TDI) controller is moved to the Shift-DR state. The EXTEST, The TDI ball is used to serially input information into the registers SAMPLE/PRELOAD and SAMPLE Z instructions can be used to and can be connected to the input of any of the registers. The capture the contents of the I/O ring. register between TDI and TDO is chosen by the instruction that The Boundary Scan Order on page 18 and show the order in is loaded into the TAP instruction register. For information about which the bits are connected. Each bit corresponds to one of the loading the instruction register, see the TAP Controller State bumps on the SRAM package. The MSB of the register is Diagram on page 13. TDI is internally pulled up and can be connected to TDI, and the LSB is connected to TDO. unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. Identification (ID) Register Test Data-Out (TDO) The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is The TDO output ball is used to serially clock data-out from the loaded in the instruction register. The IDCODE is hardwired into registers. The output is active depending upon the current state the SRAM and can be shifted out when the TAP controller is in of the TAP state machine (see Instruction Codes on page 17). the Shift-DR state. The ID register has a vendor code and other The output changes on the falling edge of TCK. TDO is information described in the Identification Register Definitions on connected to the least significant bit (LSB) of any register. page 17. Performing a TAP Reset TAP Instruction Set A RESET is performed by forcing TMS HIGH (V ) for five rising DD edges of TCK. This RESET does not affect the operation of the Overview SRAM and may be performed while the SRAM is operating. Eight different instructions are possible with the three bit At power up, the TAP is reset internally to ensure that TDO instruction register. All combinations are listed in the Instruction comes up in a high Z state. Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions TAP Registers described in detail are as follows. Registers are connected between the TDI and TDO balls and Instructions are loaded into the TAP controller during the Shift-IR allow data to be scanned into and out of the SRAM test circuitry. state when the instruction register is placed between TDI and Only one register can be selected at a time through the TDO. During this state, instructions are shifted through the Document Number: 38-05353 Rev. *P Page 11 of 31

CY7C1460AV33 CY7C1462AV33 instruction register through the TDI and TDO balls. To execute PRELOAD allows an initial data pattern to be placed at the the instruction after it is shifted in, the TAP controller needs to be latched parallel outputs of the boundary scan register cells prior moved into the Update-IR state. to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can IDCODE occur concurrently when required – that is, while data captured The IDCODE instruction causes a vendor-specific, 32-bit code is shifted out, the preloaded data can be shifted in. to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows BYPASS the IDCODE to be shifted out of the device when the TAP When the BYPASS instruction is loaded in the instruction register controller enters the Shift-DR state. and the TAP is placed in a Shift-DR state, the bypass register is The IDCODE instruction is loaded into the instruction register placed between the TDI and TDO pins. The advantage of the upon power up or whenever the TAP controller is given a test BYPASS instruction is that it shortens the boundary scan path logic reset state. when multiple devices are connected together on a board. SAMPLE Z EXTEST The SAMPLE Z instruction causes the boundary scan register to The EXTEST instruction enables the preloaded data to be driven be connected between the TDI and TDO pins when the TAP out through the system output pins. This instruction also selects controller is in a Shift-DR state. The SAMPLE Z command puts the boundary scan register to be connected for serial access the output bus into a high Z state until the next command is given between the TDI and TDO in the shift-DR controller state. during the “Update IR” state. EXTEST OUTPUT BUS TRISTATE SAMPLE/PRELOAD IEEE Standard 1149.1 mandates that the TAP controller be able SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When to put the output bus into a tristate mode. the SAMPLE/PRELOAD instructions are loaded into the The boundary scan register has a special bit located at bit #89 instruction register and the TAP controller is in the Capture-DR (for 165-ball FBGA package) or bit #138 (for 209-ball FBGA state, a snapshot of data on the inputs and output pins is package). When this scan cell, called the “extest output bus captured in the boundary scan register. tristate,” is latched into the preload register during the The user must be aware that the TAP controller clock can only “Update-DR” state in the TAP controller, it directly controls the operate at a frequency up to 20 MHz, while the SRAM clock state of the output (Q-bus) pins, when the EXTEST is entered as operates more than an order of magnitude faster. Because there the current instruction. When HIGH, it enables the output buffers is a large difference in the clock frequencies, it is possible that to drive the output bus. When LOW, this bit places the output bus during the Capture-DR state, an input or output undergoes a into a high Z condition. transition. The TAP may then try to capture a signal while in This bit can be set by entering the SAMPLE/PRELOAD or transition (metastable state). This does not harm the device, but EXTEST command, and then shifting the desired bit into that cell, there is no guarantee as to the value that is captured. during the “Shift-DR” state. During “Update-DR,” the value Repeatable results may not be possible. loaded into that shift-register cell latches into the preload To guarantee that the boundary scan register captures the register. When the EXTEST instruction is entered, this bit directly correct value of a signal, the SRAM signal must be stabilized controls the output Q-bus pins. Note that this bit is preset HIGH long enough to meet the TAP controller’s capture setup plus hold to enable the output when the device is powered-up, and also times (t and t ). The SRAM clock input might not be captured when the TAP controller is in the “Test-Logic-Reset” state. CS CH correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is Reserved still possible to capture all other signals and simply ignore the These instructions are not implemented but are reserved for value of the CK and CK# captured in the boundary scan register. future use. Do not use these instructions. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 38-05353 Rev. *P Page 12 of 31

CY7C1460AV33 CY7C1462AV33 TAP Controller State Diagram TEST-LOGIC 1 RESET 0 RUN-TEST/ 1 SELECT 1 SELECT 1 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 PAUSE-DR 0 PAUSE-IR 0 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 0 1 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Document Number: 38-05353 Rev. *P Page 13 of 31

CY7C1460AV33 CY7C1462AV33 TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Selection Instruction Register TDI Circuitry Circuitry TDO 313029 . . . 2 1 0 Identification Register x . . . . . 2 1 0 Boundary Scan Register TCK TAP CONTROLLER TMS TAP Timing Diagram 1 2 3 4 5 6 Test Clock (TCK) tTH tTL tCYC tTMSS tTMSH Test Mode Select (TMS) tTDIS tTDIH Test Data-In (TDI) tTDOV tTDOX Test Data-Out (TDO) DON’T CARE UNDEFINED Document Number: 38-05353 Rev. *P Page 14 of 31

CY7C1460AV33 CY7C1462AV33 TAP AC Switching Characteristics Over the Operating Range Parameter [12, 13] Description Min Max Unit Clock t TCK clock cycle time 50 – ns TCYC t TCK clock frequency – 20 MHz TF t TCK clock HIGH time 20 – ns TH t TCK clock LOW time 20 – ns TL Output Times t TCK clock LOW to TDO valid – 10 ns TDOV t TCK clock LOW to TDO invalid 0 – ns TDOX Setup Times t TMS setup to TCK clock rise 5 – ns TMSS t TDI setup to TCK clock rise 5 – ns TDIS t Capture setup to TCK rise 5 – ns CS Hold Times t TMS hold after TCK clock rise 5 – ns TMSH t TDI hold after clock rise 5 – ns TDIH t Capture hold after clock rise 5 – ns CH 3.3 V TAP AC Test Conditions 2.5 V TAP AC Test Conditions Input pulse levels ...............................................V to 3.3 V Input pulse levels ...............................................V to 2.5 V SS SS Input rise and fall times ...................................................1 ns Input rise and fall time ....................................................1 ns Input timing reference levels .........................................1.5 V Input timing reference levels .......................................1.25 V Output reference levels ................................................1.5 V Output reference levels ..............................................1.25 V Test load termination supply voltage ............................1.5 V Test load termination supply voltage ..........................1.25 V 3.3 V TAP AC Output Load Equivalent 2.5 V TAP AC Output Load Equivalent 1.5V 1.25V 50Ω 50Ω TDO TDO Z O = 50Ω 20pF Z O = 50Ω 20pF Notes 12.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 13.Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document Number: 38-05353 Rev. *P Page 15 of 31

CY7C1460AV33 CY7C1462AV33 TAP DC Electrical Characteristics and Operating Conditions (0 °C < T < +70 °C; V = 3.135 V to 3.6 V unless otherwise noted) A DD Parameter [14] Description Test Conditions Min Max Unit V Output HIGH voltage I = –4.0 mA, V = 3.3 V 2.4 – V OH1 OH DDQ I = –1.0 mA, V = 2.5 V 2.0 – V OH DDQ V Output HIGH voltage I = –100 µA V = 3.3 V 2.9 – V OH2 OH DDQ V = 2.5 V 2.1 – V DDQ V Output LOW voltage I = 8.0 mA V = 3.3 V – 0.4 V OL1 OL DDQ I = 1.0 mA V = 2.5 V – 0.4 V OL DDQ V Output LOW voltage I = 100 µA V = 3.3 V – 0.2 V OL2 OL DDQ V = 2.5 V – 0.2 V DDQ V Input HIGH voltage V = 3.3 V 2.0 V + 0.3 V IH DDQ DD V = 2.5 V 1.7 V + 0.3 V DDQ DD V Input LOW voltage V = 3.3 V –0.3 0.8 V IL DDQ V = 2.5 V –0.3 0.7 V DDQ I Input load current GND < V < V –5 5 µA X IN DDQ Note 14.All voltages referenced to VSS (GND). Document Number: 38-05353 Rev. *P Page 16 of 31

CY7C1460AV33 CY7C1462AV33 Identification Register Definitions CY7C1460AV33 Instruction Field Description (1M × 36) Revision number (31:29) 000 Describes the version number. Device depth (28:24) [15] 01011 Reserved for internal use Architecture/memory type(23:18) 001000 Defines memory type and architecture Bus width/density(17:12) 100111 Defines width and density Cypress JEDEC ID code (11:1) 00000110100 Allows unique identification of SRAM vendor. ID register presence indicator (0) 1 Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size (× 36) Instruction 3 Bypass 1 ID 32 Boundary scan order (165-ball FBGA package) 89 Instruction Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to high Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Note 15.Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device. Document Number: 38-05353 Rev. *P Page 17 of 31

CY7C1460AV33 CY7C1462AV33 Boundary Scan Order 165-ball FBGA [16] CY7C1460AV33 (1M × 36) Bit# Ball ID Bit# Ball ID Bit# Ball ID Bit# Ball ID 1 N6 26 E11 51 A3 76 N1 2 N7 27 D11 52 A2 77 N2 3 10N 28 G10 53 B2 78 P1 4 P11 29 F10 54 C2 79 R1 5 P8 30 E10 55 B1 80 R2 6 R8 31 D10 56 A1 81 P3 7 R9 32 C11 57 C1 82 R3 8 P9 33 A11 58 D1 83 P2 9 P10 34 B11 59 E1 84 R4 10 R10 35 A10 60 F1 85 P4 11 R11 36 B10 61 G1 86 N5 12 H11 37 A9 62 D2 87 P6 13 N11 38 B9 63 E2 88 R6 14 M11 39 C10 64 F2 89 Internal 15 L11 40 A8 65 G2 16 K11 41 B8 66 H1 17 J11 42 A7 67 H3 18 M10 43 B7 68 J1 19 L10 44 B6 69 K1 20 K10 45 A6 70 L1 21 J10 46 B5 71 M1 22 H9 47 A5 72 J2 23 H10 48 A4 73 K2 24 G11 49 B4 74 L2 25 F11 50 B3 75 M2 Note 16.Bit# 89 is preset HIGH. Document Number: 38-05353 Rev. *P Page 18 of 31

CY7C1460AV33 CY7C1462AV33 Maximum Ratings Operating Range Exceeding maximum ratings may shorten the useful life of the Ambient Range V V device. User guidelines are not tested. Temperature DD DDQ Storage temperature ................................–65 °C to +150 °C Commercial 0 °C to +70 °C 3.3 V – 5% / 2.5 V – 5% to Ambient temperature with Industrial –40 °C to +85 °C + 10% VDD power applied ..........................................–55 °C to +125 °C Supply voltage on V relative to GND .......–0.5 V to +4.6 V DD Neutron Soft Error Immunity Supply voltage on V relative to GND ......–0.5 V to +V DDQ DD DC to outputs in tri-state ...................–0.5 V to VDDQ + 0.5 V Parameter Description Test Typ Max* Unit Conditions DC input voltage .................................–0.5 V to V + 0.5 V DD Current into outputs (LOW) ........................................20 mA LSBU Logical single 25 °C 361 394 FIT/ bit upsets Mb Static discharge voltage (per MIL-STD-883, method 3015) ......................... > 2001 V LMBU Logical multi 25 °C 0 0.01 FIT/ bit upsets Mb Latch-up current ................................................... > 200 mA SEL Single event 85 °C 0 0.1 FIT/ latch-up Dev * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates” Electrical Characteristics Over the Operating Range Parameter [17, 18] Description Test Conditions Min Max Unit V Power supply voltage 3.135 3.6 V DD V I/O supply voltage for 3.3 V I/O 3.135 V V DDQ DD for 2.5 V I/O 2.375 2.625 V V Output HIGH voltage for 3.3 V I/O, I =4.0 mA 2.4 – V OH OH for 2.5 V I/O, I = 1.0 mA 2.0 – V OH V Output LOW voltage for 3.3 V I/O, I =8.0 mA – 0.4 V OL OL for 2.5 V I/O, I =1.0 mA – 0.4 V OL V Input HIGH voltage [17] for 3.3 V I/O 2.0 V + 0.3 V V IH DD for 2.5 V I/O 1.7 V + 0.3 V V DD V Input LOW voltage [17] for 3.3 V I/O –0.3 0.8 V IL for 2.5 V I/O –0.3 0.7 V I Input leakage current except ZZ GND  V  V –5 5 A X I DDQ and MODE Input current of MODE Input = V –30 – A SS Input = V – 5 A DD Input current of ZZ Input = V –5 – A SS Input = V – 30 A DD I Output leakage current GND  V  V output disabled –5 5 A OZ I DDQ, Notes 17.Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2). 18.Tpower up: Assumes a linear ramp from 0 V to VDD(Min) within 200 ms. During this time VIH < VDD and VDDQ  VDD. Document Number: 38-05353 Rev. *P Page 19 of 31

CY7C1460AV33 CY7C1462AV33 Electrical Characteristics (continued) Over the Operating Range Parameter [17, 18] Description Test Conditions Min Max Unit I V operating supply V = Max, I = 0 mA, 4 ns cycle, – 475 mA DD DD DD OUT f = f = 1/t 250 MHz MAX CYC 5 ns cycle, – 425 mA 200 MHz 6 ns cycle, – 375 mA 167 MHz I Automatic CE power-down Max V , device deselected, All speed – 225 mA SB1 DD current – TTL inputs V  V or V  V , grades IN IH IN IL f = f = 1/t MAX CYC I Automatic CE power-down Max V , device deselected, All speed – 120 mA SB2 DD current – CMOS inputs V  0.3 V or V > V 0.3 V, grades IN IN DDQ f = 0 I Automatic CE power-down Max V , device deselected, All speed – 200 mA SB3 DD current – CMOS inputs V  0.3 V or V > V 0.3 V, grades IN IN DDQ f = f = 1/t MAX CYC I Automatic CE power-down Max V , device deselected, All speed – 135 mA SB4 DD current – TTL inputs V  V or V  V , grades IN IH IN IL f = 0 Capacitance Parameter [19] Description Test Conditions 100-pin TQFP 165-ball FBGA Unit Max Max C Input capacitance T = 25 C, f = 1 MHz, 6.5 7 pF IN A V = 2.5 V, V = 2.5 V C Clock input capacitance DD DDQ 3 7 pF CLK C Input/output capacitance 5.5 6 pF I/O Thermal Resistance Parameter [19] Description Test Conditions 100-pin TQFP 165-ball FBGA Unit Package Package  Thermal resistance Test conditions follow standard test 25.21 20.8 C/W JA (junction to ambient) methods and procedures for measuring thermal impedance, per EIA/JESD51.  Thermal resistance 2.28 3.2 C/W JC (junction to case) Note 19.Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-05353 Rev. *P Page 20 of 31

CY7C1460AV33 CY7C1462AV33 AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317  OUTPUT 3.3 V ALL INPUT PULSES OUTPUT VDDQ 90% Z0= 50  90% RL= 50  10% 10% 5pF GND INCLUDING R = 351   1 ns  1 ns V = 1.5 V T JIG AND (a) (b) (c) SCOPE 2.5 V I/O Test Load R = 1667  OUTPUT 2.5 V ALL INPUT PULSES V DDQ OUTPUT 90% Z0= 50  90% RL= 50  10% 10% 5pF GND INCLUDING R =1538   1 ns  1 ns V = 1.25 V T JIG AND (a) (b) (c) SCOPE Document Number: 38-05353 Rev. *P Page 21 of 31

CY7C1460AV33 CY7C1462AV33 Switching Characteristics Over the Operating Range -250 -200 -167 Parameter [20, 21] Description Unit Min Max Min Max Min Max t [22] V (typical) to the first access read or 1 – 1 – 1 – ms Power CC write Clock t Clock cycle time 4.0 – 5.0 – 6.0 – ns CYC F Maximum operating frequency – 250 – 200 – 167 MHz MAX t Clock HIGH 1.5 – 2.0 – 2.4 – ns CH t Clock LOW 1.5 – 2.0 – 2.4 – ns CL Output Times t Data output valid after CLK rise – 2.6 – 3.2 – 3.4 ns CO t OE LOW to output valid – 2.6 – 3.0 – 3.4 ns EOV t Data output hold after CLK rise 1.0 – 1.5 – 1.5 – ns DOH t Clock to high Z [23, 24, 25] – 2.6 – 3.0 – 3.4 ns CHZ t Clock to low Z [23, 24, 25] 1.0 – 1.3 – 1.5 – ns CLZ tEOHZ OE HIGH to output high Z [23, 24, 25] – 2.6 – 3.0 – 3.4 ns tEOLZ OE LOW to output low Z [23, 24, 25] 0 – 0 – 0 – ns Setup Times t Address setup before CLK rise 1.2 – 1.4 – 1.5 – ns AS t Data input setup before CLK rise 1.2 – 1.4 – 1.5 – ns DS t CEN setup before CLK rise 1.2 – 1.4 – 1.5 – ns CENS tWES WE, BWx setup before CLK rise 1.2 – 1.4 – 1.5 – ns t ADV/LD setup before CLK rise 1.2 – 1.4 – 1.5 – ns ALS t Chip select setup 1.2 – 1.4 – 1.5 – ns CES Hold Times t Address hold after CLK rise 0.3 – 0.4 – 0.5 – ns AH t Data input hold after CLK rise 0.3 – 0.4 – 0.5 – ns DH t CEN hold after CLK rise 0.3 – 0.4 – 0.5 – ns CENH t WE, BW hold after CLK rise 0.3 – 0.4 – 0.5 – ns WEH x t ADV/LD hold after CLK rise 0.3 – 0.4 – 0.5 – ns ALH t Chip select hold after CLK rise 0.3 – 0.4 – 0.5 – ns CEH Notes 20.Timing reference is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 21.Test conditions shown in (a) of Figure 3 on page 21 unless otherwise noted. 22.This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD(minimum) initially, before a Read or Write operation can be initiated. 23.tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of Figure 3 on page 21. Transition is measured ± 200 mV from steady-state voltage. 24.At any voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve highZ prior to low Z under the same system conditions. 25.This parameter is sampled and not 100% tested. Document Number: 38-05353 Rev. *P Page 22 of 31

CY7C1460AV33 CY7C1462AV33 Switching Waveforms Figure 4. Read/Write/Timing [26, 27, 28] 1 2 3 4 5 6 7 8 9 10 tCYC CLK tCENS tCENH tCH tCL CEN tCES tCEH CE ADV/LD WE BWx ADDRESS A1 A2 A3 A4 A5 A6 A7 tCO tAS tAH tDS tDH tCLZ tDOH tOEV tCHZ Data D(A1) D(A2) D(A2+1) Q(A3) Q(A4) Q(A4+1) D(A5) Q(A6) In-Out (DQ) tOEHZ tDOH OE tOELZ WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D(A1) D(A2) WRITE Q(A3) Q(A4) READ D(A5) Q(A6) D(A7) D(A2+1) Q(A4+1) DON’T CARE UNDEFINED Notes 26.For this waveform ZZ is tied low. 27.When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 28.Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional. Document Number: 38-05353 Rev. *P Page 23 of 31

CY7C1460AV33 CY7C1462AV33 Switching Waveforms (continued) Figure 5. NOP, STALL and DESELECT Cycles [29, 30, 31] 1 2 3 4 5 6 7 8 9 10 CLK CEN CE ADV/LD WE BWx ADDRESS A1 A2 A3 A4 A5 tCHZ Data D(A1) Q(A2) Q(A3) D(A4) Q(A5) In-Out (DQ) WRITE READ STALL READ WRITE STALL NOP READ DESELECT CONTINUE D(A1) Q(A2) Q(A3) D(A4) Q(A5) DESELECT DON’T CARE UNDEFINED Figure 6. ZZ Mode Timing [32, 33] CLK tZZ tZZREC ZZ tZZI I SUPPLY IDDZZ tRZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes 29.For this waveform ZZ is tied low. 30.When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 31.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. 32.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 33.I/Os are in high Z when exiting ZZ sleep mode. Document Number: 38-05353 Rev. *P Page 24 of 31

CY7C1460AV33 CY7C1462AV33 Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices Speed Package Operating Part and Package Type (MHz) Ordering Code Diagram Range 167 CY7C1460AV33-167AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial CY7C1462AV33-167AXC CY7C1460AV33-167BZC 51-85195 165-ball FBGA (15 × 17 × 1.4 mm) CY7C1460AV33-167AXI 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Industrial 200 CY7C1460AV33-200AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial CY7C1462AV33-200AXI Industrial 250 CY7C1460AV33-250AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial CY7C1460AV33-250AXI Industrial Ordering Code Definitions CY 7 C 14XX A V33 - 167 XX X X Temperature range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: XX = A or BZ A = 100-pin TQFP BZ = 165-ball FBGA Speed Grade: 167 MHz or 200 MHz or 250 MHz V33 = 3.3 V Process Technology  90 nm 14XX = 1460 or 1462 1460 = PL, 1Mb × 36 (36Mb) 1462 = PL, 2Mb × 18 (36Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05353 Rev. *P Page 25 of 31

CY7C1460AV33 CY7C1462AV33 Package Diagrams Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050 51-85050 *E Document Number: 38-05353 Rev. *P Page 26 of 31

CY7C1460AV33 CY7C1462AV33 Package Diagrams (continued) Figure 8. 165-ball FBGA (15 × 17 × 1.40 mm) (0.50 Ball Diameter) Package Outline, 51-85195 51-85195 *D Document Number: 38-05353 Rev. *P Page 27 of 31

CY7C1460AV33 CY7C1462AV33 Acronyms Document Conventions Units of Measure Acronym Description CE Chip Enable Symbol Unit of Measure CEN Clock Enable °C degree Celsius CMOS Complementary Metal Oxide Semiconductor MHz megahertz EIA Electronic Industries Alliance µA microampere mA milliampere FBGA Fine-Pitch Ball Grid Array ms millisecond I/O Input/Output mm millimeter JEDEC Joint Electron Devices Engineering Council mV millivolt JTAG Joint Test Action Group nm nanometer LMBU Logical Multi Bit Upsets ns nanosecond LSB Least Significant Bit  ohm LSBU Logical Single Bit Upsets % percent MSB Most Significant Bit pF picofarad NoBL No Bus Latency V volt OE Output Enable W watt SEL Single Event Latch-up SRAM Static Random Access Memory TAP Test Access Port TCK Test Clock TMS Test Mode Select TDI Test Data-In TDO Test Data-Out TQFP Thin Quad Flat Pack TTL Transistor-Transistor Logic WE Write Enable Document Number: 38-05353 Rev. *P Page 28 of 31

CY7C1460AV33 CY7C1462AV33 Document History Page Document Title: CY7C1460AV33/CY7C1462AV33, 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05353 Orig. of Submission Revision ECN Description of Change Change Date ** 254911 SYT See ECN New data sheet. Part number changed from previous revision. New and old part number differ by the letter “A”. *A 303533 SYT See ECN Updated Pin Configurations (Changed H9 pin from V to V on 209-ball SSQ SS FBGA). Updated Electrical Characteristics (Changed the test condition from V = Min DD to V = Max for V parameter, changed maximum value of I parameter DD OL DD from 450, 400 and 350 mA to 475, 425 and 375 mA for 250, 200 and 167 MHz respectively, changed maximum value of I parameter from 190, 180 and SB1 170 mA to 225 mA for 250, 200 and 167 MHz respectively, changed maximum value of I parameter from 80 mA to 100 mA for all frequencies, changed SB2 maximum value of I parameter from 180, 170 and 160 mA to 200 mA for SB3 250, 200 and 167 MHz respectively, changed maximum value of I SB4 parameter from 100 mA to 110 mA for all frequencies). Updated Capacitance (Changed the values of C , C and C parameters IN CLK I/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for 100-pin TQFP package). Updated Thermal Resistance (Replaced the values of  and  JA JC parameters from TBD to respective Thermal Values for all packages). Updated Switching Characteristics (Changed maximum value of t CO parameter from 3.0 ns to 3.2 ns and minimum vale of t parameter from DOH 1.3ns to 1.5 ns for 200 MHz speed bin). Updated Ordering Information (Added Pb-free information for 100-pin TQFP and 165-ball FBGA and 209-ball BGA packages). *B 331778 SYT See ECN Updated Pin Configurations (Modified Address Expansion balls in the pinouts for 165-ball FBGA and 209-ball BGA Package as per JEDEC standards) and updated Pin Definitions accordingly. Updated Operating Range (Added Industrial Temperature Grade). Updated Electrical Characteristics (Modified test conditions for V and V OL OH parameters, changed maximum value of I parameter from 100 mA to SB2 120mA and maximum value of I parameter from 110 mA to 135 mA). SB4 Updated Capacitance (Changed C , C and C to 7, 7and 6 pF from 5, 5 IN CLK I/O and 7 pF for 165-ball FBGA Package). Updated Ordering Information (by Shading and Unshading MPNs as per availability). *C 417509 RXU See ECN Changed status from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Updated Electrical Characteristics (Modified the description of I parameter X “Input Load Current except ZZ and MODE” to “Input Leakage Current except ZZ and MODE”, changed minimum value of I parameter from –5 A to –30A X and maximum value of I parameter from 30 A to 5 A respectively for “Input X Current of MODE”, and also changed minimum value of I parameter from X –30A to –5 A and maximum value of I parameter from 5 A to 30 A X respectively for “Input Current of ZZ”, Modified test condition from V < V IH DD toV V ). IH DD Updated Ordering Information (Replaced Package Name column with Package Diagram in the Ordering Information table). Updated Package Diagrams (for spec 51-85050). *D 473229 NXR See ECN Updated TAP AC Switching Characteristics (Changed minimum value of t , TH t parameters from 25 ns to 20 ns and maximum value of t parameter TL TDOV from 5 ns to 10 ns). Document Number: 38-05353 Rev. *P Page 29 of 31

CY7C1460AV33 CY7C1462AV33 Document History Page (continued) Document Title: CY7C1460AV33/CY7C1462AV33, 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05353 Orig. of Submission Revision ECN Description of Change Change Date *D (cont.) 473229 NXR See ECN Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage on V Relative to GND). DDQ Updated Ordering Information (Updated part numbers). *E 2756998 VKN 08/28/09 Included Neutron Soft Error Immunity. Updated Ordering Information (by including parts that are available) and modified the disclaimer for the Ordering Information. Updated Package Diagrams (for spec 51-85165). *F 2900822 NJY 03/29/2010 Updated Ordering Information (Added part number CY7C1460AV33-167AXI). Updated Package Diagrams (100-pin TQFP and 209-ball FBGA). Updated links in Sales, Solutions, and Legal Information. *G 3043005 NJY 09/30/2010 Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits. Updated to new template. *H 3051765 NJY 10/07/2010 Removed all information of CY7C1464 and 209-ball FBGA across the document as those part numbers are pruned. Corrected typos in Units of Measure. *I 3207715 NJY 03/28/2011 Updated Ordering Information (Updated part numbers). Updated Package Diagrams. *J 3365114 PRIT 09/14/2011 Updated Package Diagrams. *K 3538377 PRIT 03/02/2012 Updated Features (Removed all information related to CY7C1462AV33 165-ball FBGA packages). Updated Pin Configurations (Removed all information related to CY7C1462AV33 165-ball FBGA packages). Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed all information related to CY7C1462AV33 165-ball FBGA packages). Updated Identification Register Definitions (Removed all information related to CY7C1462AV33 165-ball FBGA packages). Updated Scan Register Sizes (Removed all information related to CY7C1462AV33 165-ball FBGA packages). Updated Boundary Scan Order (Removed all information related to CY7C1462AV33 165-ball FBGA packages). Updated Ordering Information (Added part number CY7C1462AV33-200AXI). Updated Package Diagrams. *L 3767562 PRIT 10/05/2012 No technical updates. Completing Sunset Review. *M 4541859 PRIT 10/17/2014 Updated Package Diagrams: spec 51-85050 – Changed revision from *D to *E. Updated to new template. Completing Sunset Review. *N 4569232 PRIT 11/14/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *O 4976716 PRIT 10/20/2015 Added watermark “Not recommended for New Designs” across the document. Updated Package Diagrams: spec 51-85195 – Changed revision from *C to *D. Updated to new template. Completing Sunset Review. *P 5506925 PRIT 11/02/2016 Obsolete document. Completing Sunset Review. Document Number: 38-05353 Rev. *P Page 30 of 31

CY7C1460AV33 CY7C1462AV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Interface cypress.com/go/interface Cypress Developer Community Lighting & Power Control cypress.com/go/powerpsoc Community | Forums | Blogs | Video | Training Memory cypress.com/go/memory Technical Support PSoC cypress.com/go/psoc cypress.com/go/support Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05353 Rev. *P Revised November 2, 2016 Page 31 of 31 QDR® is the registered trademark and NoBL™ and No Bus Latency™ are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.