CY7C1380DV33 CY7C1382DV33 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description ■Supports bus operation up to 200 MHz The CY7C1380DV33/CY7C1382DV33 SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced ■Available speed grades is 200 MHz synchronous peripheral circuitry and a two-bit counter for ■Registered inputs and outputs for pipelined operation internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input ■3.3 V core power supply (CLK). The synchronous inputs include all addresses, all data ■2.5 V or 3.3 V I/O power supply inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE and CE [1]), burst control inputs (ADSC, 2 3 ■Fast clock-to-output times ADSP, and ADV), write enables (BW , and BWE), and global X ❐3 ns (for 200 MHz device) write (GW). Asynchronous inputs include the output enable (OE) ■Provides high performance 3-1-1-1 access rate and the ZZ pin. ■User selectable burst counter supporting IntelPentium® Addresses and chip enables are registered at rising edge of clock when address strobe processor (ADSP) or address strobe interleaved or linear burst sequences controller (ADSC) are active. Subsequent burst addresses can ■Separate processor and controller address strobes be internally generated as they are controlled by the advance pin ■Synchronous self-timed write (ADV). Address, data inputs, and write controls are registered on-chip ■Asynchronous output enable to initiate a self-timed write cycle.This part supports byte write ■Single cycle chip deselect operations (see Pin Definitions on page 6 and Truth Table on page 10 for further details). Write cycles can be one to two or four ■CY7C1380DV33 is available in JEDEC-standard Pb-free bytes wide as controlled by the byte write control inputs. GW 100-pin TQFP and 165-ball FBGA package and when active LOW causes all bytes to be written. CY7C1382DV33 is available in 165-ball FBGA package The CY7C1380DV33/CY7C1382DV33 operates from a +3.3 V ■IEEE 1149.1 JTAG-Compatible Boundary Scan core power supply while all outputs operate with a +2.5 or +3.3V ■ZZ sleep mode option power supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible. For a complete list of related documentation, click here. Selection Guide Description 200 MHz 167 MHz Unit Maximum Access Time 3.0 3.4 ns Maximum Operating Current 300 275 mA Maximum CMOS Standby Current 70 70 mA Note 1. CE3, CE2 are for 100-pin TQFP and 165-ball FBGA packages only. CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-74445 Rev. *D December 29, 2015

CY7C1380DV33 CY7C1382DV33 Logic Block Diagram – CY7C1380DV33 A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV Q1 CLK BURST COUNTER CLR AND Q0 LOGIC ADSC ADSP DQD ,DQPD DQD ,DQPD BWD BYTE BYTE WRITE REGISTER WRITE DRIVER DQC ,DQPC DQC ,DQPC BBWWCB WWRRDIITTQEEB B BRRY Y,EETDTGGEEQIISSPTTEBERR WWDRRIIQTTBBEEBYY DD,TTDRREEQIIVVPEEBRR MAERMROARYY SAEMNPSSE ROEGUITSPTUERTS BOUUFTFPEEURTS DDDDQQQQPPPsABC DQPD DQA ,DQPA DQBAY ,DTEQPA BWA BYTE WRITE DRIVER BWE WRITE REGISTER INPUT GCCWEE12 REENGAISBTLEER PEIPNEALIBNLEED REGISTERS CE3 OE ZZ SLEEP CONTROL Logic Block Diagram – CY7C1382DV33 ADDRESS A0, A1, A REGISTER 2 ADV BURST Q1 CLK COUNTER AND LOGIC ADSC DQB,DQPB DQB,DQPB BWB WRITE REGISTER WRITE DRIVER MAERMROARYY SENSE OUTPUT BOUUFTFPEURTS DDQQsPA DQA,DQPA DQPB BWA WRIDTQE RAE,DGQISPTEAR WRITE DRIVER BWE INPUT GW ENABLE CE1 REGISTER PIPELINED CE2 ENABLE CE3 OE ZZ SLEEP CONTROL Document Number: 001-74445 Rev. *D Page 2 of 33

CY7C1380DV33 CY7C1382DV33 Contents Pin Configurations ...........................................................4 TAP DC Electrical Characteristics and Pin Definitions ..................................................................6 Operating Conditions .....................................................17 Functional Overview ........................................................8 Identification Register Definitions ................................18 Single Read Accesses ................................................8 Scan Register Sizes .......................................................18 Single Write Accesses Initiated by ADSP ...................8 Identification Codes .......................................................18 Single Write Accesses Initiated by ADSC ...................8 Boundary Scan Order ....................................................19 Burst Sequences .........................................................8 Maximum Ratings ...........................................................20 Sleep Mode .................................................................9 Operating Range .............................................................20 Interleaved Burst Address Table .................................9 Electrical Characteristics ...............................................20 Linear Burst Address Table .........................................9 Capacitance ....................................................................21 ZZ Mode Electrical Characteristics ..............................9 Thermal Resistance ........................................................21 Truth Table ......................................................................10 AC Test Loads and Waveforms .....................................22 Truth Table for Read/Write ............................................11 Switching Characteristics ..............................................23 Truth Table for Read/Write ............................................11 Switching Waveforms ....................................................24 IEEE 1149.1 Serial Boundary Scan (JTAG) ..................12 Ordering Information ......................................................28 Disabling the JTAG Feature ......................................12 Ordering Code Definitions .........................................28 Test Access Port (TAP) .............................................12 Package Diagrams ..........................................................29 PERFORMING A TAP RESET ..................................12 Acronyms ........................................................................31 TAP REGISTERS ......................................................12 Document Conventions .................................................31 TAP Instruction Set ...................................................12 Units of Measure .......................................................31 TAP Controller State Diagram .......................................14 Document History Page .................................................32 TAP Controller Block Diagram ......................................15 Sales, Solutions, and Legal Information ......................33 TAP Timing ......................................................................15 Worldwide Sales and Design Support .......................33 TAP AC Switching Characteristics ...............................16 Products ....................................................................33 3.3 V TAP AC Test Conditions .......................................17 PSoC® Solutions ......................................................33 3.3 V TAP AC Output Load Equivalent .........................17 Cypress Developer Community .................................33 2.5 V TAP AC Test Conditions .......................................17 Technical Support .....................................................33 2.5 V TAP AC Output Load Equivalent .........................17 Document Number: 001-74445 Rev. *D Page 3 of 33

CY7C1380DV33 CY7C1382DV33 Pin Configurations Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3-Chip Enable) CY7C1380DV33 (512 K × 36) Document Number: 001-74445 Rev. *D Page 4 of 33

CY7C1380DV33 CY7C1382DV33 Pin Configurations (continued) Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3-Chip Enable) CY7C1380DV33 (512 K × 36) 1 2 3 4 5 6 7 8 9 10 11 A NC/288M A CE1 BWC BWB CE3 BWE ADSC ADV A NC B NC/144M A CE2 BWD BWA CLK GW OE ADSP A NC/576M C DQP NC V V V V V V V NC/1G DQP C DDQ SS SS SS SS SS DDQ B D DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B E DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B F DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B G DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B H NC NC NC V V V V V NC NC ZZ DD SS SS SS DD J DQ DQ V V V V V V V DQ DQ D D DDQ DD SS SS SS DD DDQ A A K DQ DQ V V V V V V V DQ DQ D D DDQ DD SS SS SS DD DDQ A A L DQ DQ V V V V V V V DQ DQ D D DDQ DD SS SS SS DD DDQ A A M DQ DQ V V V V V V V DQ DQ D D DDQ DD SS SS SS DD DDQ A A N DQP NC V V NC A NC V V NC DQP D DDQ SS SS DDQ A P NC NC/72M A A TDI A1 TDO A A A A R MODE NC/36M A A TMS A0 TCK A A A A CY7C1382DV33 (1 M × 18) 1 2 3 4 5 6 7 8 9 10 11 A NC/288M A CE1 BWB NC CE3 BWE ADSC ADV A A B NC/144M A CE2 NC BW CLK GW OE ADSP A NC/576M A C NC NC V V V V V V V NC/1G DQP DDQ SS SS SS SS SS DDQ A D NC DQ V V V V V V V NC DQ B DDQ DD SS SS SS DD DDQ A E NC DQ V V V V V V V NC DQ B DDQ DD SS SS SS DD DDQ A F NC DQ V V V V V V V NC DQ B DDQ DD SS SS SS DD DDQ A G NC DQ V V V V V V V NC DQ B DDQ DD SS SS SS DD DDQ A H NC NC NC V V V V V NC NC ZZ DD SS SS SS DD J DQ NC V V V V V V V DQ NC B DDQ DD SS SS SS DD DDQ A K DQ NC V V V V V V V DQ NC B DDQ DD SS SS SS DD DDQ A L DQ NC V V V V V V V DQ NC B DDQ DD SS SS SS DD DDQ A M DQ NC V V V V V V V DQ NC B DDQ DD SS SS SS DD DDQ A N DQP NC V V NC A NC V V NC NC B DDQ SS SS DDQ P NC NC/72M A A TDI A1 TDO A A A A R MODE NC/36M A A TMS A0 TCK A A A A Document Number: 001-74445 Rev. *D Page 5 of 33

CY7C1380DV33 CY7C1382DV33 Pin Definitions Name I/O Description A , A , A Input- Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK 0 1 Synchronous if ADSP or ADSC is active LOW, and CE ,CE , andCE [3]are sampled active. A1:A0 are fed to the 1 2 3 two-bit counter. BW , BW , Input- Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled A B BW , BW Synchronous on the rising edge of CLK. C D GW Input- Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write Synchronous is conducted (all bytes are written, regardless of the values on BW and BWE). X BWE Input- Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted Synchronous LOW to conduct a byte write. CLK Input- Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst Clock counter when ADV is asserted LOW, during a burst operation. CE1 Input- Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 Synchronous and CE to select or deselect the device. ADSP is ignored if CE is HIGH. CE is sampled only when a 3 1 1 new external address is loaded. CE [2] Input- Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE 2 1 Synchronous and CE to select or deselect the device. CE is sampled only when a new external address is loaded. 3 2 CE [2] Input- Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE 3 1 Synchronous and CE to select or deselect the device. CE is sampled only when a new external address is loaded. 2 3 OE Input- Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, Asynchronou the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data s pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV Input- Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it Synchronous automatically increments the address in a burst cycle. ADSP Input- Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE is deasserted HIGH. 1 ADSC Input- Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ Input- ZZ sleep input. This active HIGH input places the device in a non-time critical sleep condition with data Asynchronou integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal s pull down. DQs, I/O- Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the DQP Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the X addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP X are placed in a tri-state condition. V Power Supply Power supply inputs to the core of the device DD V Ground Ground for the core of the device. SS V I/O Ground Ground for the I/O circuitry. SSQ Note 2. CE3, CE2 are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in 1-chip enable. Document Number: 001-74445 Rev. *D Page 6 of 33

CY7C1380DV33 CY7C1382DV33 Pin Definitions (continued) Name I/O Description V I/O Power Power supply for the I/O circuitry. DDQ Supply MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to V or left floating DD selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull up. TDO JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is output not being utilized, this pin must be disconnected. This pin is not available on 100-pin TQFP packages. Synchronous TDI JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being input utilized, this pin can be disconnected or connected to V . This pin is not available on 100-pin TQFP DD Synchronous packages. TMS JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being input utilized, this pin can be disconnected or connected to V . This pin is not available on 100-pin TQFP DD Synchronous packages. TCK JTAG- Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected Clock to V . This pin is not available on 100-pin TQFP packages. SS NC – No Connects. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. Document Number: 001-74445 Rev. *D Page 7 of 33

CY7C1380DV33 CY7C1382DV33 Functional Overview The write signals (GW, BWE, and BW ) and ADV inputs are X ignored during this first cycle. All synchronous inputs pass through input registers controlled by ADSP triggered write accesses require two clock cycles to the rising edge of the clock. All data outputs pass through output complete. If GW is asserted LOW on the second clock rise, the registers controlled by the rising edge of the clock. Maximum data presented to the DQs inputs is written into the access delay from the clock rise (t ) is 3 ns (200 MHz device). CO corresponding address location in the memory array. If GW is CY7C1380DV33/CY7C1382DV33 supports secondary cache in HIGH, then the write operation is controlled by BWE and BW X systems using a linear or interleaved burst sequence. The signals. interleaved burst order supports Pentium and i486 processors. CY7C1380DV33/CY7C1382DV33 provides byte write capability The linear burst sequence suits processors that use a linear that is described in the write cycle descriptions table. Asserting burst sequence. The burst order is user selectable, and is the byte write enable input (BWE) with the selected byte write determined by sampling the MODE input. Accesses can be (BW ) input, selectively writes to only the desired bytes. Bytes initiated with either the processor address strobe (ADSP) or the X not selected during a byte write operation remain unaltered. A controller address strobe (ADSC). Address advancement synchronous self-timed write mechanism has been provided to through the burst sequence is controlled by the ADV input. A simplify the write operations. two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the CY7C1380DV33/CY7C1382DV33 is a common I/O device, the address for the rest of the burst access. output enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so tri-states the output drivers. As Byte write operations are qualified with the byte write enable a safety precaution, DQs are automatically tri-stated whenever a (BWE) and byte write select (BW ) inputs. A global write enable X write cycle is detected, regardless of the state of OE. (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous Single Write Accesses Initiated by ADSC self-timed write circuitry. ADSC write accesses are initiated when the following conditions Three synchronous chip selects (CE , CE , CE ) and an 1 2 3 are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted asynchronous output enable (OE) provide for easy bank HIGH, (3) CE , CE , and CE are all asserted active, and (4) the 1 2 3 selection and output tri-state control. ADSP is ignored if CE is 1 appropriate combination of the write inputs (GW, BWE, and HIGH. BW ) are asserted active to conduct a write to the desired X byte(s). ADSC-triggered Write accesses require a single clock Single Read Accesses cycle to complete. The address presented to A is loaded into the This access is initiated when the following conditions are address register and the address advancement logic while being satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, delivered to the memory array. The ADV input is ignored during (2)CE1, CE2, CE3 are all asserted active, and (3) the write this cycle. If a global write is conducted, the data presented to signals (GW, BWE) are all deserted HIGH. ADSP is ignored if the DQs is written into the corresponding address location in the CE is HIGH. The address presented to the address inputs (A) memory core. If a byte write is conducted, only the selected bytes 1 is stored into the address advancement logic and the address are written. Bytes not selected during a byte write operation register while being presented to the memory array. The remain unaltered. A synchronous self-timed write mechanism corresponding data is enabled to propagate to the input of the has been provided to simplify the write operations. output registers. At the rising edge of the next clock, the data is CY7C1380DV33/CY7C1382DV33 is a common I/O device, the enabled to propagate through the output register and onto the output enable (OE) must be deserted HIGH before presenting data bus within 3 ns (200 MHz device) if OE is active LOW. The data to the DQs inputs. Doing so tri-states the output drivers. As only exception occurs when the SRAM is emerging from a a safety precaution, DQs are automatically tri-stated whenever a deselected state to a selected state; its outputs are always write cycle is detected, regardless of the state of OE. tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Burst Sequences Consecutive single read cycles are supported. Once the SRAM CY7C1380DV33/CY7C1382DV33 provides a two-bit is deselected at clock rise by the chip select and either ADSP or wraparound counter, fed by A1:A0, that implements an ADSC signals, its output tri-states immediately. interleaved or a linear burst sequence. The interleaved burst Single Write Accesses Initiated by ADSP sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support This access is initiated when both the following conditions are processors that follow a linear burst sequence. The burst satisfied at clock rise: (1) ADSP is asserted LOW and (2)CE , 1 sequence is user selectable through the MODE input. CE , and CE are all asserted active. The address presented to 2 3 A is loaded into the address register and the address Asserting ADV LOW at clock rise automatically increments the advancement logic while being delivered to the memory array. burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Document Number: 001-74445 Rev. *D Page 8 of 33

CY7C1380DV33 CY7C1382DV33 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places Linear Burst Address Table the SRAM in a power conservation sleep mode. Two clock cycles (MODE = GND) are required to enter into or exit from this sleep mode. While in First Second Third Fourth this mode, data integrity is guaranteed. Accesses pending when Address Address Address Address entering the sleep mode are not considered valid nor is the A1:A0 A1:A0 A1:A0 A1:A0 completion of the operation guaranteed. The device must be 00 01 10 11 deselected prior to entering the sleep mode. CE , CE , CE , 1 2 3 ADSP, and ADSC must remain inactive for the duration of t 01 10 11 00 ZZREC after the ZZ input returns LOW. 10 11 00 01 11 00 01 10 Interleaved Burst Address Table (MODE = Floating or VDD) First Second Third Fourth Address Address Address Address A1:A0 A1:A0 A1:A0 A1:A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit I Sleep mode standby current ZZ > V – 0.2 V – 80 mA DDZZ DD t Device operation to ZZ ZZ > V – 0.2 V – 2t ns ZZS DD CYC t ZZ recovery time ZZ < 0.2 V 2t – ns ZZREC CYC t ZZ Active to sleep current This parameter is sampled – 2t ns ZZI CYC t ZZ Inactive to exit sleep current This parameter is sampled 0 – ns RZZI Document Number: 001-74445 Rev. *D Page 9 of 33

CY7C1380DV33 CY7C1382DV33 Truth Table The Truth Table for this data sheet follows. [3, 4, 5, 6, 7] Operation Address Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 Deselect Cycle, Power Down None H X X L X L X X X L–H Tri-state Deselect Cycle, Power Down None L L X L L X X X X L–H Tri-state Deselect Cycle, Power Down None L X H L L X X X X L–H Tri-state Deselect Cycle, Power Down None L L X L H L X X X L–H Tri-state Deselect Cycle, Power Down None L X H L H L X X X L–H Tri-state Sleep Mode, Power Down None X X X H X X X X X X Tri-state READ Cycle, Begin Burst External L H L L L X X X L L–H Q READ Cycle, Begin Burst External L H L L L X X X H L–H Tri-state WRITE Cycle, Begin Burst External L H L L H L X L X L–H D READ Cycle, Begin Burst External L H L L H L X H L L–H Q READ Cycle, Begin Burst External L H L L H L X H H L–H Tri-state READ Cycle, Continue Burst Next X X X L H H L H L L–H Q READ Cycle, Continue Burst Next X X X L H H L H H L–H Tri-state READ Cycle, Continue Burst Next H X X L X H L H L L–H Q READ Cycle, Continue Burst Next H X X L X H L H H L–H Tri-state WRITE Cycle, Continue Burst Next X X X L H H L L X L–H D WRITE Cycle, Continue Burst Next H X X L X H L L X L–H D READ Cycle, Suspend Burst Current X X X L H H H H L L–H Q READ Cycle, Suspend Burst Current X X X L H H H H H L–H Tri-state READ Cycle, Suspend Burst Current H X X L X H H H L L–H Q READ Cycle, Suspend Burst Current H X X L X H H H H L–H Tri-state WRITE Cycle, Suspend Burst Current X X X L H H H L X L–H D WRITE Cycle, Suspend Burst Current H X X L X H H L X L–H D Notes 3. X = Don't Care, H = Logic HIGH, L = Logic LOW. 4. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 001-74445 Rev. *D Page 10 of 33

CY7C1380DV33 CY7C1382DV33 Truth Table for Read/Write The Truth Table for Read/Write for CY7C1380DV33 follows. [8, 9] Function (CY7C1380DV33) GW BWE BW BW BW BW D C B A Read H H X X X X Read H L H H H H Write Byte A – (DQ and DQP ) H L H H H L A A Write Byte B – (DQ and DQP ) H L H H L H B B Write Bytes B, A H L H H L L Write Byte C – (DQ and DQP ) H L H L H H C C Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQ and DQP ) H L L H H H D D Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L Write Bytes D, C, B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Truth Table for Read/Write The Truth Table for Read/Write for CY7C1382DV33 follows. [8, 9] Function (CY7C1382DV33) GW BWE BW BW B A Read H H X X Read H L H H Write Byte A – (DQ and DQP ) H L H L A A Write Byte B – (DQ and DQP ) H L L H B B Write Bytes B, A H L L L Write All Bytes H L L L Write All Bytes L X X X Notes 8. X = Don't Care, H = Logic HIGH, L = Logic LOW. 9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active. Document Number: 001-74445 Rev. *D Page 11 of 33

CY7C1380DV33 CY7C1382DV33 IEEE 1149.1 Serial Boundary Scan (JTAG) Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the The CY7C1380DV33/CY7C1382DV33 incorporates a serial rising edge of TCK. Data is output on the TDO ball on the falling boundary scan test access port (TAP).This part is fully compliant edge of TCK. with 1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic levels. Instruction Register CY7C1380DV33/CY7C1382DV33 contains a TAP controller, Three-bit instructions can be serially loaded into the instruction instruction register, boundary scan register, bypass register, and register. This register is loaded when it is placed between the TDI ID register. and TDO balls as shown in the TAP Controller Block Diagram on page 15. Upon power up, the instruction register is loaded with Disabling the JTAG Feature the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described It is possible to operate the SRAM without using the JTAG in the previous section. feature. To disable the TAP controller, TCK must be tied LOW (V ) to prevent clocking of the device. TDI and TMS are When the TAP controller is in the Capture-IR state, the two least SS internally pulled up and may be unconnected. They may significant bits are loaded with a binary ‘01’ pattern to enable fault alternately be connected to VDD through a pull up resistor. TDO isolation of the board-level serial test data path. must be left unconnected. Upon power up, the device comes up Bypass Register in a reset state which does not interfere with the operation of the device. To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass Test Access Port (TAP) register is a single-bit register that can be placed between the TDI and TDO balls. This enables data to be shifted through the Test Clock (TCK) SRAM with minimal delay. The bypass register is set LOW (V ) SS The test clock is used only with the TAP controller. All inputs are when the BYPASS instruction is executed. captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Boundary Scan Register The boundary scan register is connected to all the input and Test Mode Select (TMS) bidirectional balls on the SRAM. The TMS input is used to give commands to the TAP controller The boundary scan register is loaded with the contents of the and is sampled on the rising edge of TCK. This pin may be left RAM input and output ring when the TAP controller is in the unconnected if the TAP is not used. The ball is pulled up Capture-DR state and is then placed between the TDI and TDO internally, resulting in a logic HIGH level. balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can Test Data-In (TDI) be used to capture the contents of the input and output ring. The TDI ball is used to serially input information into the registers The boundary scan order tables show the order in which the bits and can be connected to the input of any of the registers. The are connected. Each bit corresponds to one of the bumps on the register between TDI and TDO is chosen by the instruction that SRAM package. The MSB of the register is connected to TDI, is loaded into the TAP instruction register. For information about and the LSB is connected to TDO. loading the instruction register, see the TAP Controller State Diagram on page 14. TDI is internally pulled up and can be Identification (ID) Register unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. The ID register is loaded with a vendor-specific 32-bit code during the Capture-DR state when the IDCODE command is Test Data-Out (TDO) loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in The TDO output ball is used to serially clock data-out from the the Shift-DR state. The ID register has a vendor code and other registers. The output is active depending upon the current state information described in the Identification Register Definitions on of the TAP state machine (see Identification Codes on page 18). page 18. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. TAP Instruction Set Performing a TAP Reset Overview A Reset is performed by forcing TMS HIGH (VDD) for five rising Eight different instructions are possible with the three bit edges of TCK. This Reset does not affect the operation of the instruction register. All combinations are listed in Identification SRAM and may be performed while the SRAM is operating. Codes on page 18. Three of these instructions are listed as At power up, the TAP is reset internally to ensure that TDO RESERVED and must not be used. The other five instructions comes up in a high Z state. are described in detail in this section. Instructions are loaded into the TAP controller during the Shift-IR TAP Registers state when the instruction register is placed between TDI and Registers are connected between the TDI and TDO balls and TDO. During this state, instructions are shifted through the enable data to be scanned in and out of the SRAM test circuitry. instruction register through the TDI and TDO balls. To execute Document Number: 001-74445 Rev. *D Page 12 of 33

CY7C1380DV33 CY7C1382DV33 the instruction once it is shifted in, the TAP controller must be still possible to capture all other signals and simply ignore the moved into the Update-IR state. value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by EXTEST putting the TAP into the Shift-DR state. This places the boundary The EXTEST instruction enables the preloaded data to be driven scan register between the TDI and TDO pins. out through the system output pins. This instruction also selects PRELOAD enables an initial data pattern to be placed at the the boundary scan register to be connected for serial access latched parallel outputs of the boundary scan register cells prior between the TDI and TDO in the Shift-DR controller state. to the selection of another boundary scan test operation. IDCODE The shifting of data for the SAMPLE and PRELOAD phases can The IDCODE instruction causes a vendor-specific 32-bit code to occur concurrently when required; that is, while data captured is be loaded into the instruction register. It also places the shifted out, the preloaded data is shifted in. instruction register between the TDI and TDO balls and enables BYPASS the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is The IDCODE instruction is loaded into the instruction register placed between the TDI and TDO balls. The advantage of the upon power up or whenever the TAP controller is given a test BYPASS instruction is that it shortens the boundary scan path logic reset state. when multiple devices are connected together on a board. SAMPLE Z EXTEST Output Bus Tri-State The SAMPLE Z instruction causes the boundary scan register to IEEE Standard 1149.1 mandates that the TAP controller be able be connected between the TDI and TDO balls when the TAP to put the output bus into a tri-state mode. controller is in a Shift-DR state. The SAMPLE Z command places all SRAM outputs into a high Z state. The boundary scan register has a special bit located at Bit #89 (for 165-ball FBGA package). When this scan cell, called the SAMPLE/PRELOAD “extest output bus tri-state,” is latched into the preload register SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When during the Update-DR state in the TAP controller, it directly the SAMPLE/PRELOAD instructions are loaded into the controls the state of the output (Q-bus) pins, when the EXTEST instruction register and the TAP controller is in the Capture-DR is entered as the current instruction. When HIGH, it enables the state, a snapshot of data on the input and output pins is captured output buffers to drive the output bus. When LOW, this bit places in the boundary scan register. the output bus into a high Z condition. The TAP controller clock can only operate at a frequency up to This bit can be set by entering the SAMPLE/PRELOAD or 20 MHz, while the SRAM clock operates more than an order of EXTEST command, and then shifting the desired bit into that cell, magnitude faster. As there is a large difference in the clock during the Shift-DR state. During Update-DR, the value loaded frequencies, it is possible that during the Capture-DR state, an into that shift-register cell latches into the preload register. When input or output undergoes a transition. The TAP may then try to the EXTEST instruction is entered, this bit directly controls the capture a signal while in transition (metastable state). This does output Q-bus pins. Note that this bit is preset HIGH to enable the not harm the device, but there is no guarantee as to the value output when the device is powered up, and also when the TAP that is captured. Repeatable results may not be possible. controller is in the Test-Logic-Reset state. To guarantee that the boundary scan register captures the Reserved correct value of a signal, the SRAM signal must be stabilized These instructions are not implemented but are reserved for long enough to meet the TAP controller’s capture setup plus hold future use. Do not use these instructions. times (t and t ). The SRAM clock input might not be captured CS CH correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is Document Number: 001-74445 Rev. *D Page 13 of 33

CY7C1380DV33 CY7C1382DV33 TAP Controller State Diagram TEST-LOGIC 1 RESET 0 RUN-TEST/ 1 SELECT 1 SELECT 1 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 PAUSE-DR 0 PAUSE-IR 0 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 0 1 0 The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK. Document Number: 001-74445 Rev. *D Page 14 of 33

CY7C1380DV33 CY7C1382DV33 TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Instruction Register TDI Circuitry Selection TDO 313029 . . . 2 1 0 Circuitry Identification Register x . . . . . 2 1 0 Boundary Scan Register TCK TMS TAP CONTROLLER TAP Timing Figure 3. TAP Timing Test Clock (TCK) tTH tTL tCYC tTMSS tTMSH Test Mode Select (TMS) tTDIS tTDIH Test Data-In (TDI) tTDOV tTDOX Test Data-Out (TDO) DON’T CARE UNDEFINED Document Number: 001-74445 Rev. *D Page 15 of 33

CY7C1380DV33 CY7C1382DV33 TAP AC Switching Characteristics Over the Operating Range Parameter [10, 11] Description Min Max Unit Clock t TCK Clock Cycle Time 50 – ns TCYC t TCK Clock Frequency – 20 MHz TF t TCK Clock HIGH time 20 – ns TH t TCK Clock LOW time 20 – ns TL Output Times t TCK Clock LOW to TDO Valid – 10 ns TDOV t TCK Clock LOW to TDO Invalid 0 – ns TDOX Setup Times t TMS Setup to TCK Clock Rise 5 – ns TMSS t TDI Setup to TCK Clock Rise 5 – ns TDIS t Capture Setup to TCK Rise 5 – ns CS Hold Times t TMS Hold after TCK Clock Rise 5 – ns TMSH t TDI Hold after Clock Rise 5 – ns TDIH t Capture Hold after Clock Rise 5 – ns CH Notes 10.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 11.Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document Number: 001-74445 Rev. *D Page 16 of 33

CY7C1380DV33 CY7C1382DV33 3.3 V TAP AC Test Conditions 2.5 V TAP AC Test Conditions Input pulse levels ...............................................V to 3.3 V Input pulse levels ...............................................V to 2.5 V SS SS Input rise and fall times ...................................................1 ns Input rise and fall time ....................................................1 ns Input timing reference levels .........................................1.5 V Input timing reference levels .......................................1.25 V Output reference levels ................................................1.5 V Output reference levels ..............................................1.25 V Test load termination supply voltage ............................1.5 V Test load termination supply voltage ..........................1.25 V 3.3 V TAP AC Output Load Equivalent 2.5 V TAP AC Output Load Equivalent 1.5V 1.25V 50Ω 50Ω TDO TDO Z O = 50Ω 20pF Z O = 50Ω 20pF TAP DC Electrical Characteristics and Operating Conditions (0 °C < T < +70 °C; V = 3.3 V ± 0.165 V unless otherwise noted) A DD Parameter [12] Description Test Conditions Min Max Unit V Output HIGH Voltage I = –4.0 mA, V = 3.3 V 2.4 – V OH1 OH DDQ I = –1.0 mA, V = 2.5 V 2.0 – V OH DDQ V Output HIGH Voltage I = –100 µA V = 3.3 V 2.9 – V OH2 OH DDQ V = 2.5 V 2.1 – V DDQ V Output LOW Voltage I = 8.0 mA V = 3.3 V – 0.4 V OL1 OL DDQ V = 2.5 V – 0.4 V DDQ V Output LOW Voltage I = 100 µA V = 3.3 V – 0.2 V OL2 OL DDQ V = 2.5 V – 0.2 V DDQ V Input HIGH Voltage V = 3.3 V 2.0 V + 0.3 V IH DDQ DD V = 2.5 V 1.7 V + 0.3 V DDQ DD V Input LOW Voltage V = 3.3 V –0.3 0.8 V IL DDQ V = 2.5 V –0.3 0.7 V DDQ I Input Load Current GND < V < V –5 5 µA X IN DDQ Note 12.All voltages referenced to VSS (GND). Document Number: 001-74445 Rev. *D Page 17 of 33

CY7C1380DV33 CY7C1382DV33 Identification Register Definitions CY7C1380DV33 CY7C1382DV33 Instruction Field Description (512 K × 36) (1 M × 18) Revision Number (31:29) 000 000 Describes the version number. Device Depth (28:24) [13] 01011 01011 Reserved for internal use. Device Width (23:18) 165-ball FBGA 000000 000000 Defines the memory type and architecture. Cypress Device ID (17:12) 100101 010101 Defines the width and density. Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. ID Register Presence Indicator (0) 1 1 Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size (× 36) Bit Size (× 18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (165-ball FBGA package) 89 89 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to high Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high Z state. RESERVED 011 Do Not Use. This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use. This instruction is reserved for future use. RESERVED 110 Do Not Use. This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Note 13.Bit #24 is 1 in the register definitions for both 2.5 V and 3.3 V versions of this device. Document Number: 001-74445 Rev. *D Page 18 of 33

CY7C1380DV33 CY7C1382DV33 Boundary Scan Order 165-ball BGA [14, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9 52 A2 82 R3 23 H10 53 B2 83 P2 24 G11 54 C2 84 R4 25 F11 55 B1 85 P4 26 E11 56 A1 86 N5 27 D11 57 C1 87 P6 28 G10 58 D1 88 R6 29 F10 59 E1 89 Internal 30 E10 60 F1 Note 14.Balls which are NC (No Connect) are pre-set LOW. 15.Bit# 89 is pre-set HIGH. Document Number: 001-74445 Rev. *D Page 19 of 33

CY7C1380DV33 CY7C1382DV33 Maximum Ratings DC Input Voltage ................................–0.5 V to V + 0.5 V DD Current into Outputs (LOW) ........................................20 mA Exceeding the maximum ratings may impair the useful life of the Static Discharge Voltage device. For user guidelines, not tested. (per MIL-STD-883, Method 3015) ..........................> 2001 V Storage Temperature ...............................–65 °C to +150 °C Latch-up Current ....................................................> 200 mA Ambient Temperature with Power Applied .........................................–55 °C to +125 °C Operating Range Supply Voltage on VDD Relative to GND ...................................–0.3 V to +4.6 V Range Ambient V V Temperature DD DDQ Supply Voltage on VDDQ Relative to GND ..................................–0.3 V to +VDD Industrial –40 °C to +85 °C 3.3 V– 5% / 2.5 V – 5% to DC Voltage Applied to Outputs + 10% VDD in tri-state ..........................................–0.5 V to V + 0.5 V DDQ Electrical Characteristics Over the Operating Range Parameter [16, 17] Description Test Conditions Min Max Unit V Power Supply Voltage 3.135 3.6 V DD V I/O Supply Voltage for 3.3 V I/O 3.135 V V DDQ DD for 2.5 V I/O 2.375 2.625 V V Output HIGH Voltage for 3.3 V I/O, I = –4.0 mA 2.4 – V OH OH for 2.5 V I/O, I = –1.0 mA 2.0 – V OH V Output LOW Voltage for 3.3 V I/O, I = 8.0 mA – 0.4 V OL OL for 2.5 V I/O, I = 1.0 mA – 0.4 V OL V Input HIGH Voltage [17] for 3.3 V I/O 2.0 V + 0.3 V IH DD for 2.5 V I/O 1.7 V + 0.3 V DD V Input LOW Voltage [17] for 3.3 V I/O –0.3 0.8 V IL for 2.5 V I/O –0.3 0.7 V I Input Leakage Current except ZZ GND  V  V –5 5 A X I DDQ and MODE Input Current of MODE Input = V –30 – A SS Input = V – 5 A DD Input Current of ZZ Input = V –5 – A SS Input = V – 30 A DD I Output Leakage Current GND  V  V Output Disabled –5 5 A OZ I DDQ, I V Operating Supply Current V = Max, I = 0 mA, 5.0-ns cycle, – 300 mA DD DD DD OUT f = f = 1/t 200 MHz MAX CYC 6.0-ns cycle, – 275 mA 167 MHz I Automatic CE power-down V = Max, Device Deselected, 5.0-ns cycle, – 150 mA SB1 DD Current – TTL Inputs V  V or V  V , 200 MHz IN IH IN IL f = f = 1/t MAX CYC 6.0-ns cycle, – 140 mA 167 MHz Notes 16.Overshoot: VIH(AC) < VDD +1.5 V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2). 17.TPower up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 001-74445 Rev. *D Page 20 of 33

CY7C1380DV33 CY7C1382DV33 Electrical Characteristics (continued) Over the Operating Range Parameter [16, 17] Description Test Conditions Min Max Unit I Automatic CE power-down V = Max, Device Deselected, All speeds – 70 mA SB2 DD Current – CMOS Inputs V  0.3 V or IN V > V – 0.3 V, IN DDQ f = 0 I Automatic CE power-down V = Max, Device Deselected, 5.0-ns cycle, – 130 mA SB3 DD Current – CMOS Inputs V  0.3 V or 200 MHz IN V > V – 0.3 V, IN DDQ 6.0-ns cycle, – 125 mA f = f = 1/t MAX CYC 167 MHz I Automatic CE power-down V = Max, Device Deselected, All speeds – 80 mA SB4 DD Current – TTL Inputs V  V or V  V , f = 0 IN IH IN IL Capacitance Parameter [18] Description Test Conditions 100-pin TQFP 165-ball FBGA Unit Package Package C Input Capacitance T = 25 °C, f = 1 MHz, 5 9 pF IN A V = 3.3 V, V = 2.5 V C Clock Input Capacitance DD DDQ 5 9 pF CLK C Input/Output Capacitance 5 9 pF IO Thermal Resistance Parameter [18] Description Test Conditions 100-pin TQFP 165-ball FBGA Unit Package Package  Thermal resistance Test conditions follow standard test 28.66 20.7 °C/W JA (junction to ambient) methods and procedures for measuring  Thermal resistance thermal impedance, in accordance with 4.08 4.0 °C/W JC EIA/JESD51. (junction to case) Note 18.Tested initially and after any design or process change that may affect these parameters. Document Number: 001-74445 Rev. *D Page 21 of 33

CY7C1380DV33 CY7C1382DV33 AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317  OUTPUT 3.3 V ALL INPUT PULSES V OUTPUT DDQ 90% Z0= 50  90% RL= 50  10% 10% 5pF GND R = 351   1 ns  1 ns V = 1.5 V T INCLUDING (a) JIG AND (c) (b) SCOPE 2.5 V I/O Test Load R = 1667  OUTPUT 2.5 V ALL INPUT PULSES V DDQ OUTPUT 90% Z0= 50  90% RL= 50  10% 10% 5pF GND R = 1538   1 ns  1 ns V = 1.25 V T INCLUDING JIG AND (a) SCOPE (c) (b) Document Number: 001-74445 Rev. *D Page 22 of 33

CY7C1380DV33 CY7C1382DV33 Switching Characteristics Over the Operating Range 200 MHz 167 MHz Parameter [19, 20] Description Unit Min Max Min Max t V (typical) to the first access [21] 1 – 1 – ms POWER DD Clock t Clock Cycle Time 5 – 6 – ns CYC t Clock HIGH 2.0 – 2.2 – ns CH t Clock LOW 2.0 – 2.2 – ns CL Output Times t Data Output Valid After CLK Rise – 3.0 – 3.4 ns CO t Data Output Hold After CLK Rise 1.3 – 1.3 – ns DOH t Clock to Low Z [22, 23, 24] 1.3 – 1.3 – ns CLZ t Clock to High Z [22, 23, 24] – 3.0 – 3.4 ns CHZ t OE LOW to Output Valid – 3.0 – 3.4 ns OEV t OE LOW to Output Low Z [22, 23, 24] 0 – 0 – ns OELZ t OE HIGH to Output High Z [22, 23, 24] – 3.0 – 3.4 ns OEHZ Setup Times t Address Setup Before CLK Rise 1.4 – 1.5 – ns AS t ADSC, ADSP Setup Before CLK Rise 1.4 – 1.5 – ns ADS t ADV Setup Before CLK Rise 1.4 – 1.5 – ns ADVS t GW, BWE, BW Setup Before CLK Rise 1.4 – 1.5 – ns WES X t Data Input Setup Before CLK Rise 1.4 – 1.5 – ns DS t Chip Enable SetUp Before CLK Rise 1.4 – 1.5 – ns CES Hold Times t Address Hold After CLK Rise 0.4 – 0.5 – ns AH t ADSP, ADSC Hold After CLK Rise 0.4 – 0.5 – ns ADH t ADV Hold After CLK Rise 0.4 – 0.5 – ns ADVH t GW, BWE, BW Hold After CLK Rise 0.4 – 0.5 – ns WEH X t Data Input Hold After CLK Rise 0.4 – 0.5 – ns DH t Chip Enable Hold After CLK Rise 0.4 – 0.5 – ns CEH Notes 19.Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 20.Test conditions shown in (a) of Figure 4 on page 22 unless otherwise noted. 21.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 22.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 22. Transition is measured ±200mV from steady-state voltage. 23.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system conditions. 24.This parameter is sampled and not 100% tested. Document Number: 001-74445 Rev. *D Page 23 of 33

CY7C1380DV33 CY7C1382DV33 Switching Waveforms Figure 5. Read Cycle Timing [25] tCYC CLK tCH tCL t t ADS ADH ADSP tADS tADH ADSC tAS tAH ADDRESS A1 A2 A3 Burst continued with tWES tWEH new base address GW, BWE, BWx tCES tCEH Dcyecsleelect CE tADVS tADVH ADV ADV suspends burst. OE tOEV tCO tCLZ tOEHZ tOELZ tDOH tCHZ Data Out (Q) High-Z Q(A1) Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) tCO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note 25.On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 001-74445 Rev. *D Page 24 of 33

CY7C1380DV33 CY7C1382DV33 Switching Waveforms (continued) Figure 6. Write Cycle Timing [26, 27] tCYC CLK tCH tCL tADS tADH ADSP ADSC extends burst tADS tADH tADS tADH ADSC tAS tAH ADDRESS A1 A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BWX tWES tWEH GW tCES tCEH CE t t ADVS ADVH ADV ADV suspends burst OE tDS tDH Data In (D) High-Z D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) t OEHZ Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON’T CARE UNDEFINED Notes 26.On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 27.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document Number: 001-74445 Rev. *D Page 25 of 33

CY7C1380DV33 CY7C1382DV33 Switching Waveforms (continued) Figure 7. Read/Write Cycle Timing [28, 29, 30] tCYC CLK tCH tCL tADS tADH ADSP ADSC tAS tAH ADDRESS A1 A2 A3 A4 A5 A6 tWES tWEH BWE, BWX tCES tCEH CE ADV OE tCO tDS tDH tOELZ Data In (D) High-Z D(A3) D(A5) D(A6) tCLZ tOEHZ Data Out (Q) High-Z Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back READs Single WRITE BURST READ Back-to-Back WRITEs DON’T CARE UNDEFINED Notes 28.On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 29.The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 30.GW is HIGH. Document Number: 001-74445 Rev. *D Page 26 of 33

CY7C1380DV33 CY7C1382DV33 Switching Waveforms (continued) Figure 8. ZZ Mode Timing [31, 32] CLK tZZ tZZREC ZZ tZZI I SUPPLY IDDZZ tRZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes 31.Device must be deselected when entering ZZ mode. See Truth Table on page 10 for all possible signal conditions to deselect the device. 32.DQs are in high Z when exiting ZZ sleep mode. Document Number: 001-74445 Rev. *D Page 27 of 33

CY7C1380DV33 CY7C1382DV33 Ordering Information The below table lists the key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Speed Package Operating Part and Package Type (MHz) Ordering Code Diagram Range 200 CY7C1380DV33-200AXI 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Industrial CY7C1382DV33-200BZI 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Ordering Code Definitions CY 7 C 138X D V33 - XXX XX X I Temperature Range: I = Industrial Pb-free Package Type: XX = A or BZ A = 100-pin TQFP; BZ = 165-ball FBGA Frequency Range: XXX = 200 MHz V33 = 3.3 V Die Revision: D  90 nm Part Identifier: 138X = 1380 or 1382 1380 = SCD, 512 K × 36 (18 Mb) 1382 = SCD, 1 Mb × 18 (18 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-74445 Rev. *D Page 28 of 33

CY7C1380DV33 CY7C1382DV33 Package Diagrams Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) Package Outline, 51-85050 51-85050 *E Document Number: 001-74445 Rev. *D Page 29 of 33

CY7C1380DV33 CY7C1382DV33 Package Diagrams (continued) Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180 51-85180 *G Document Number: 001-74445 Rev. *D Page 30 of 33

CY7C1380DV33 CY7C1382DV33 Acronyms Document Conventions Units of Measure Acronym Description CMOS Complementary Metal Oxide Semiconductor Symbol Unit of Measure EIA Electronic Industries Alliance °C degree Celsius FBGA Fine-Pitch Ball Grid Array MHz megahertz I/O Input/Output µA microampere JEDEC Joint Electron Devices Engineering Council mA milliampere JTAG Joint Test Action Group mm millimeter LSB Least Significant Bit ms millisecond MSB Most Significant Bit ns nanosecond OE Output Enable  ohm SRAM Static Random Access Memory % percent TCK Test Clock pF picofarad TDI Test Data-In V volt TDO Test Data-Out W watt TMS Test Mode Select TQFP Thin Quad Flat Pack TTL Transistor-Transistor Logic Document Number: 001-74445 Rev. *D Page 31 of 33

CY7C1380DV33 CY7C1382DV33 Document History Page Document Title: CY7C1380DV33/CY7C1382DV33, 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Document Number: 001-74445 Submission Orig. of Rev. ECN No. Description of Change Date Change ** 3420399 12/21/2011 NJY New data sheet *A 3514252 02/02/2012 NJY Changed status from Preliminary to Final. Updated Functional Description (Updated Note 1). Updated Selection Guide (Included 167 MHz information). Updated Pin Configurations (Included 100-pin TQFP information). Updated Pin Definitions (Updated Note 2 and included 100-pin TQFP information). Updated Operating Range (Removed Commercial Temperature information). Updated Electrical Characteristics (Included 167 MHz information). Updated Capacitance (Included 100-pin TQFP information). Updated Thermal Resistance (Included 100-pin TQFP information). Updated Switching Characteristics (Included 167 MHz information). Updated Ordering Information. Updated Package Diagrams. *B 4194894 11/18/2013 PRIT Updated Package Diagrams: spec 51-85180 – Changed revision from *E to *F. Updated to new template. Completing Sunset Review. *C 4575228 11/20/2014 PRIT Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Ordering Information: Updated part numbers. Updated Package Diagrams: spec 51-85050 – Changed revision from *D to *E. *D 5067400 12/29/2015 PRIT Updated Package Diagrams: spec 51-85180 – Changed revision from *F to *G. Updated to new template. Completing Sunset Review. Document Number: 001-74445 Rev. *D Page 32 of 33

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