CY74FCT2543T 8-BIT LATCHED TRANSCEIVER WITH 3-STATE OUTPUTS SCCS042C – SEPTEMBER 1994 – REVISED NOVEMBER 2001 (cid:0) Function and Pinout Compatible With FCT Q OR SO PACKAGE and F Logic (TOP VIEW) (cid:0) 25-(cid:0) Output Series Resistors to Reduce LEBA 1 24 VCC Transmission-Line Reflection Noise OEBA 2 23 CEBA (cid:0) Reduced VOH (Typically = 3.3 V) Versions A0 3 22 B0 of Equivalent FCT Functions A1 4 21 B1 (cid:0) Edge-Rate Control Circuitry for A2 5 20 B2 Significantly Improved Noise A3 6 19 B3 Characteristics A4 7 18 B4 (cid:0) Ioff Supports Partial-Power-Down Mode A5 8 17 B5 Operation A6 9 16 B6 (cid:0) Matched Rise and Fall Times A7 10 15 B7 (cid:0) CEAB 11 14 LEAB Fully Compatible With TTL Input and GND 12 13 OEAB Output Logic Levels (cid:0) 12-mA Output Sink Current 15-mA Output Source Current (cid:0) Separation Controls for Data Flow in Each Direction (cid:0) Back-to-Back Latches for Storage (cid:0) ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) (cid:0) 3-State Outputs description The CY74FCT2543T octal latched transceiver contains two sets of eight D-type latches. Separate latch enable (LEAB, LEBA) and output enable (OEAB, OEBA) inputs permit each latch set to have independent control of inputting and outputting in either direction of data flow. For example, for data flow from A to B, the A-to-B enable (CEAB) input must be low to enter data from A or to take data from B, as indicated in the function table. With CEAB low, a low signal on the A-to-B latch enable (LEAB) input makes the A-to-B latches transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the 3-state B output buffers are active and reflect data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB, LEAB, and OEAB inputs. On-chip termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2543T can replace the CY74FCT543T to reduce noise in an existing design. This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs, off off preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2001, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

CY74FCT2543T 8-BIT LATCHED TRANSCEIVER WITH 3-STATE OUTPUTS SCCS042C – SEPTEMBER 1994 – REVISED NOVEMBER 2001 PIN DESCRIPTION NAME DESCRIPTION OEAB A-to-B output-enable input (active low) OEBA B-to-A output-enable input (active low) CEAB A-to-B enable input (active low) CEBA B-to-A enable input (active low) LEAB A-to-B latch-enable input (active low) LEBA B-to-A latch-enable input (active low) A A-to-B data inputs or B-to-A 3-state outputs B B-to-A data inputs or A-to-B 3-state outputs ORDERING INFORMATION SPEED ORDERABLE TOP-SIDE TA PACKAGE† (ns) PART NUMBER MARKING QSOP – Q Tape and reel 5.3 CY74FCT2543CTQCT FCT2543C Tube 5.3 CY74FCT2543CTSOC SSOOIICC – SSOO FFCCTT22554433CC Tape and reel 5.3 CY74FCT2543CTSOCT –40°C to 85°C QSOP – Q Tape and reel 6.5 CY74FCT2543ATQCT FCT2543A Tube 6.5 CY74FCT2543ATSOC SSOOIICC – SSOO FFCCTT22554433AA Tape and reel 6.5 CY74FCT2543ATSOCT QSOP – Q Tape and reel 8.5 CY74FCT2543TQCT FCT2543 †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS LATCH OUTPUT CEAB LEAB OEAB A-TO-B‡ B H X X Storing Z X H X Storing X X X H X Z L L L Transparent Current A inputs L H L Storing Previous A inputs ‡Before LEAB low-to-high transition H = High logic level, L = Low logic level, X = Don’t care, Z = High-impedance state A-to-B data flow shown; B-to-A is the same, except using CEBA, LEBA, and OEBA. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CY74FCT2543T 8-BIT LATCHED TRANSCEIVER WITH 3-STATE OUTPUTS SCCS042C – SEPTEMBER 1994 – REVISED NOVEMBER 2001 functional block diagram DetailA D Q B0 LE A0 QD LE A1 B1 A2 B2 A3 B3 A4 DetailA x7 B4 A5 B5 A6 B6 A7 B7 OEBA OEAB CEBA CEAB LEBA LEAB absolute maximum rating over operating free-air temperature range (unless otherwise noted)† Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA Package thermal impedance, θ (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W JA SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W (cid:0) (cid:0) Ambient temperature range with power applied, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 C to 135 C A (cid:0) (cid:0) Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 C to 150 C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 2) MIN NOM MAX UNIT VCC Supply voltage 4.75 5 5.25 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V IOH High-level output current –15 mA IOL Low-level output current 12 mA TA Operating free-air temperature –40 85 °C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

CY74FCT2543T 8-BIT LATCHED TRANSCEIVER WITH 3-STATE OUTPUTS SCCS042C – SEPTEMBER 1994 – REVISED NOVEMBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK VCC = 4.75 V, IIN = –18 mA –0.7 –1.2 V VOH VCC = 4.75 V, IOH = –15 mA 2.4 3.3 V VOL VCC = 4.75 V, IOL = 12 mA 0.3 0.55 V Rout VCC = 4.75 V, IOL = 12 mA 20 25 40 (cid:0) Vhys All inputs 0.2 V VIN = VCC 5 IIIIHH VVCCCC = 55.2255 VV µµAA VIN = 2.7 V ±1 IIL VCC = 5.25 V, VIN = 0.5 V ±1 µA IOZH VCC = 5.25 V, VOUT = 2.7 V 15 µA IOZL VCC = 5.25 V, VOUT = 0.5 V –15 µA IOS‡ VCC = 5.25 V, VOUT = 0 V –60 –120 –225 mA Ioff VCC = 0 V, VOUT = 4.5 V ±1 µA ICC VCC = 5.25 V, VIN ≤ 0.2V, VIN ≥VCC – 0.2 V 0.1 0.2 mA ∆ICC VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.5 2 mA VCC = 5.25 V, One input switching at 50% duty cycle, Outputs open, mA/ ICCD¶ CEAB and OEAB = LOW, CEBA = HIGH, 0.06 1.2 MHz VIN ≤ 0.2 V or VIN ≥VCC – 0.2 V One bit switching VIN ≤ 0.2 V or VCC = 5.25 V, f0 = 10 MHz, at f11 = 5 MHz VIN ≥VCC – 0.2 V 0.7 1.4 IICC### OCCEEutAApBBu taas nnoddp eOOnEE, AABB == LLOOWW, at 50% duty cycle VIN = 3.4 V or GND 1.2 3.4 mmAA Cf00E =B LAE =A BH I G=H 1,0 MHz Eati gf11h t= b 5its M sHwzit ching VVIINN ≤≥ V0.C2C V –o r0 .2 V 2.8 5.6|| at 50% duty cycle VIN = 3.4 V or GND 5.1 14.6|| Ci 5 10 pF Co 9 12 pF †Typical values are at VCC = 5 V, TA = 25°C. ‡Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. §Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND ¶This parameter is derived for use in total power-supply calculations. #IC = ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1) Where: IC = Total supply current ICC = Power-supply current with CMOS input levels ∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V) DH = Duty cycle for TTL inputs high NT = Number of TTL inputs at DH ICCD = Dynamic current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero f1 = Input signal frequency N1 = Number of inputs changing at f1 All currents are in milliamperes and all frequencies are in megahertz. ||Values for these conditions are examples of the ICC formula. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CY74FCT2543T 8-BIT LATCHED TRANSCEIVER WITH 3-STATE OUTPUTS SCCS042C – SEPTEMBER 1994 – REVISED NOVEMBER 2001 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) CY74FCT2543T CY74FCT2543AT CY74FCT2543CT PPAARRAAMMEETTEERR UUNNIITT MIN MAX MIN MAX MIN MAX tw Pulse duration, LEBA or LEAB low 5 5 5 ns tsu Setup time, high or low A or B before LEBA↓ or LEAB↓ 2 2 2 ns th Hold time, high or low A or B after LEBA↓ or LEAB↓ 2 2 2 ns switching characteristics over operating free-air temperature range (see Figure 1) FROM TO CY74FCT2543T CY74FCT2543AT CY74FCT2543CT PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX tPLH AA oorr BB BB oorr AA 22.55 88.55 22.55 66.55 22.55 55.55 nnss tPHL tPLH LLEEBBAA oorr LLEEAABB AA oorr BB 22.55 1122.55 22.55 88 22.55 77 nnss tPHL tPZH 2 12 2 9 2 8 OOEEBBAA oorr OOEEAABB AA oorr BB nnss tPZL 2 12 2 9 2 8 tPZH 2 12 2 9 2 8 CCEEBBAA or CCEEAABB AA oorr BB nnss tPZL 2 12 2 9 2 8 tPHZ 2 9 2 7.5 2 6.5 OOEEBBAA oorr OOEEAABB AA oorr BB nnss tPLZ 2 9 2 7.5 2 6.5 tPHZ 2 9 2 7.5 2 6.5 CCEEBBAA oorr CCEEAABB AA oorr BB nnss tPLZ 2 9 2 7.5 2 6.5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

CY74FCT2543T 8-BIT LATCHED TRANSCEIVER WITH 3-STATE OUTPUTS SCCS042C – SEPTEMBER 1994 – REVISED NOVEMBER 2001 PARAMETER MEASUREMENT INFORMATION 7 V 500 Ω S1 Open From Output Test From Output Under Test Point Under Test GND TEST S1 (sCeeL N= o5t0e pAF) 500 Ω (sCeeL N= o5t0e pAF) 500 Ω ttPPLLHZ//ttPPZHLL O7p Ven tPHZ/tPZH Open LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3-STATE OUTPUTS 3 V Timing Input 1.5 V tw 0 V th 3 V tsu 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V Control 1.5 V 1.5 V 0 V 0 V tPLH tPHL tPZL tPLZ In-Phase VOH Output ≈3.5 V Output 1.5 V 1.5 V Waveform 1 1.5 V VOL + 0.3 V VOL (see Note B) VOL tPHL tPLH tPZH tPHZ VOH Output VOH Out-of-Phase 1.5 V 1.5 V Waveform 2 1.5 V VOH – 0.3 V Output VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CY74FCT2543ATQCT ACTIVE SSOP DBQ 24 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT2543A & no Sb/Br) CY74FCT2543ATSOC ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 FCT2543A & no Sb/Br) CY74FCT2543CTQCT ACTIVE SSOP DBQ 24 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT2543C & no Sb/Br) CY74FCT2543CTSOC ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 FCT2543C & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CY74FCT2543ATQCT SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CY74FCT2543CTQCT SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CY74FCT2543ATQCT SSOP DBQ 24 2500 367.0 367.0 38.0 CY74FCT2543CTQCT SSOP DBQ 24 2500 367.0 367.0 38.0 PackMaterials-Page2

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