CY54FCT240T, CY74FCT240T 8-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCCS017A – MAY 1994 – REVISED OCTOBER 2001 (cid:0) Function, Pinout, and Drive Compatible CY54FCT240T...D PACKAGE With FCT and F Logic CY74FCT240T...Q OR SO PACKAGE (cid:0) (TOP VIEW) Reduced V (Typically = 3.3 V) Versions OH of Equivalent FCT Functions OEA 1 20 VCC (cid:0) Edge-Rate Control Circuitry for DA0 2 19 OEB Significantly Improved Noise OB0 3 18 OA0 Characteristics DA1 4 17 DB0 (cid:0) I Supports Partial-Power-Down Mode OB1 5 16 OA1 off Operation DA2 6 15 DB1 (cid:0) OB 7 14 OA ESD Protection Exceeds JESD 22 2 2 DA 8 13 DB – 2000-V Human-Body Model (A114-A) 3 2 OB 9 12 OA – 200-V Machine Model (A115-A) 3 3 GND 10 11 DB – 1000-V Charged-Device Model (C101) 3 (cid:0) Matched Rise and Fall Times (cid:0) CY54FCT240T...L PACKAGE Fully Compatible With TTL Input and (TOP VIEW) Output Logic Levels (cid:0) 0 0 A C B CY54FCT240T B A E CE O D OV O – 48-mA Output Sink Current 12-mA Output Source Current 3 2 1 20 19 (cid:0) DA1 4 18 OA0 CY74FCT240T OB1 5 17 DB0 – 64-mA Output Sink Current DA2 6 16 OA1 32-mA Output Source Current (cid:0) OB2 7 15 DB1 3-State Outputs DA3 8 14 OA2 9 10 11 12 13 description 3D 3 3 2 B N BA B O G DO D The ’FCT240T devices are octal buffers and line drivers designed to be employed as memory address drivers, clock drivers, and bus-oriented transmitters/receivers. These devices provide speed and drive capabilities equivalent to their fastest bipolar logic counterparts, while reducing power consumption. The input and output voltage levels allow direct interface with TTL, NMOS, and CMOS devices without external components. These devices are fully specified for partial-power-down applications using I . The I circuitry disables the off off outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2001, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

CY54FCT240T, CY74FCT240T 8-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCCS017A – MAY 1994 – REVISED OCTOBER 2001 ORDERING INFORMATION SPEED ORDERABLE TOP-SIDE TA PACKAGE† (ns) PART NUMBER MARKING Tube 4.3 CY74FCT240CTSOC SSOOIICC – SSOO FFCCTT224400CC Tape and reel 4.3 CY74FCT240CTSOCT QSOP – Q Tape and reel 4.3 CY74FCT240CTQCT FCT240C Tube 4.8 CY74FCT240ATSOC SSOOIICC – SSOO FFCCTT224400AA –40°C to 85°C Tape and reel 4.8 CY74FCT240ATSOCT QSOP – Q Tape and reel 4.8 CY74FCT240ATQCT FCT240A Tube 8 CY74FCT240TSOC SSOOIICC – SSOO FFCCTT224400 Tape and reel 8 CY74FCT240TSOCT QSOP – Q Tape and reel 8 CY74FCT240TQCT FCT240 CDIP – D Tube 4.7 CY54FCT240CTDMB CDIP – D Tube 5.1 CY54FCT240ATDMB –5555°°CC ttoo 112255°°CC LCC – L Tube 5.1 CY54FCT240ATLMB CDIP – D Tube 9 CY54FCT240TDMB †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS OUTPUT OEA OEB D O L L L H L L H L H H X Z H = High logic level, L = Low logic level, X = Don’t care, Z = High-impedance state 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CY54FCT240T, CY74FCT240T 8-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCCS017A – MAY 1994 – REVISED OCTOBER 2001 logic diagram (positive logic) 1 OEA 2 18 DA0 OA0 DA1 4 16 OA1 6 14 DA2 OA2 8 12 DA3 OA3 19 OEB 17 3 DB0 OB0 15 5 DB1 OB1 13 7 DB2 OB2 11 9 DB3 OB3 absolute maximum rating over operating free-air temperature range (unless otherwise noted)† Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA Package thermal impedance, θ (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W JA SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W Ambient temperature range with power applied, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C A Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

CY54FCT240T, CY74FCT240T 8-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCCS017A – MAY 1994 – REVISED OCTOBER 2001 recommended operating conditions (see Note 2) CY54FCT240T CY74FCT240T UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current –12 –32 mA IOL Low-level output current 48 64 mA TA Operating free-air temperature –55 125 –40 85 °C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CY54FCT240T, CY74FCT240T 8-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCCS017A – MAY 1994 – REVISED OCTOBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) CY54FCT240T CY74FCT240T PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN TYP† MAX VCC = 4.5 V, IIN = –18 mA –0.7 –1.2 VVIIKK VV VCC = 4.75 V, IIN = –18 mA –0.7 –1.2 VCC = 4.5 V, IOH = –12 mA 2.4 3.3 VOH IOH = –32 mA 2 V VVCCCC = 44.7755 VV IOH = –15 mA 2.4 3.3 VCC = 4.5 V, IOL = 48 mA 0.3 0.55 VVOOLL VV VCC = 4.75 V, IOL = 64 mA 0.3 0.55 Vhys All inputs 0.2 0.2 V VCC = 5.5 V, VIN = VCC 5 IIII µµAA VCC = 5.25 V, VIN = VCC 5 VCC = 5.5 V, VIN = 2.7 V ±1 IIIIHH µµAA VCC = 5.25 V, VIN = 2.7 V ±1 VCC = 5.5 V, VIN = 0.5 V ±1 IIIILL µµAA VCC = 5.25 V, VIN = 0.5 V ±1 VCC = 5.5 V, VOUT = 2.7 V 10 IIOOZZHH µµAA VCC = 5.25 V, VOUT = 2.7 V 10 VCC = 5.5 V, VOUT = 0.5 V –10 IIOOZZLL µµAA VCC = 5.25 V, VOUT = 0.5 V –10 IIOOSS‡‡ VCC = 5.5 V, VOUT = 0 V –60 –120 –225 mmAA VCC = 5.25 V, VOUT = 0 V –60 –120 –225 Ioff VCC = 0 V, VOUT = 4.5 V ±1 ±1 µA VCC = 5.5 V, VIN ≤ 0.2 V, VIN ≥VCC – 0.2 V 0.1 0.2 IICCCC mmAA VCC = 5.25 V, VIN ≤ 0.2 V, VIN ≥VCC – 0.2 V 0.1 0.2 VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.5 2 ∆∆IICCCC VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.5 2 mmAA VCC = 5.5 V, One input switching at 50% duty cycle, Outputs open, OEA = OEB = GND, 0.06 0.12 VIN ≤ 0.2 V or VIN ≥VCC – 0.2 V mA/ IICCCCDD¶¶ VCC = 5.25 V, One input switching at 50% duty cycle, MHz Outputs open, OEA = OEB = GND, 0.06 0.12 VIN ≤ 0.2 V or VIN ≥VCC – 0.2 V †Typical values are at VCC = 5 V, TA = 25°C. ‡Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. §Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND ¶This parameter is derived for use in total power-supply calculations. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

CY54FCT240T, CY74FCT240T 8-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCCS017A – MAY 1994 – REVISED OCTOBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) CY54FCT240T CY74FCT240T PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN TYP† MAX One bit switching VIN ≤ 0.2 V or at f11 = 10 MHz VIN ≥VCC – 0.2 V 0.7 1.4 VCCCC = 5.5 V, at 50% duty cycle VIN = 3.4 V or GND 1 2.4 Outputs open, OEA = OEB = GND Eswigithcth binitgs VVIINN =≥ V0.C2C V – o 0r.2 V 1.3 2.6|| aatt ff11 == 22.55 MMHHzz at 50% duty cycle VIN = 3.4 V or GND 3.3 10.6|| IICC##### mmAA One bit switching VIN ≤ 0.2 V or at f11 = 10 MHz VIN ≥VCC – 0.2 V 0.7 1.4 VCCCC = 5.25 V, at 50% duty cycle VIN = 3.4 V or GND 1 2.4 Outputs open, OEA = OEB = GND Eswigithcth binitgs VVIINN =≥ V0.C2C V – o 0r.2 V 1.3 2.6|| aatt ff11 == 22.55 MMHHzz at 50% duty cycle VIN = 3.4 V or GND 3.3 10.6|| Ci 5 10 5 10 pF Co 9 12 9 12 pF †Typical values are at VCC = 5 V, TA = 25°C. #IC = ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1) Where: IC = Total supply current ICC = Power-supply current with CMOS input levels ∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V) DH = Duty cycle for TTL inputs high NT = Number of TTL inputs at DH ICCD = Dynamic current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero f1 = Input signal frequency N1 = Number of inputs changing at f1 All currents are in milliamperes and all frequencies are in megahertz. ||Values for these conditions are examples of the ICC formula. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CY54FCT240T, CY74FCT240T 8-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCCS017A – MAY 1994 – REVISED OCTOBER 2001 switching characteristics over operating free-air temperature range (see Figure 1) FROM TO CY54FCT240T CY54FCT240AT CY54FCT240CT PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX tPLH 1.5 9 1.5 5.1 1.5 4.7 DD OO nnss tPHL 1.5 9 1.5 5.1 1.5 4.7 tPZH 1.5 10.5 1.5 6.5 1.5 5.7 OOEE OO nnss tPZL 1.5 10.5 1.5 6.5 1.5 5.7 tPHZ 1.5 10 1.5 5.9 1.5 4.6 OOEE OO nnss tPLZ 1.5 10 1.5 5.9 1.5 4.6 switching characteristics over operating free-air temperature range (see Figure 1) FROM TO CY74FCT240T CY74FCT240AT CY74FCT240CT PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX tPLH 1.5 8 1.5 4.8 1.5 4.3 DD OO nnss tPHL 1.5 8 1.5 4.8 1.5 4.3 tPZH 1.5 10 1.5 6.2 1.5 5 OOEE OO nnss tPZL 1.5 10 1.5 6.2 1.5 5 tPHZ 1.5 9.5 1.5 5.6 1.5 4.5 OOEE OO nnss tPLZ 1.5 9.5 1.5 5.6 1.5 4.5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

CY54FCT240T, CY74FCT240T 8-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCCS017A – MAY 1994 – REVISED OCTOBER 2001 PARAMETER MEASUREMENT INFORMATION 7 V 500 Ω S1 Open From Output Test From Output Under Test Point Under Test GND TEST S1 (sCeeL N= o5t0e pAF) 500 Ω (sCeeL N= o5t0e pAF) 500 Ω ttPPLLHZ//ttPPZHLL O7p Ven tPHZ/tPZH Open LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3-STATE OUTPUTS 3 V Timing Input 1.5 V tw 0 V th 3 V tsu 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V Control 1.5 V 1.5 V 0 V 0 V tPLH tPHL tPZL tPLZ In-Phase VOH Output ≈3.5 V Output 1.5 V 1.5 V Waveform 1 1.5 V VOL + 0.3 V VOL (see Note B) VOL tPHL tPLH tPZH tPHZ VOH Output VOH Out-of-Phase 1.5 V 1.5 V Waveform 2 1.5 V VOH – 0.3 V Output VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9220301M2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9220301M2A CY54FCT 244TLMB 5962-9220301MRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9220301MR A CY54FCT244TDMB 5962-9220301MSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9220301MS A CY54FCT244TW 5962-9220302M2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9220302M2A CY54FCT 244ATLMB 5962-9220302MRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9220302MR A CY54FCT244ATDM B 5962-9220302MSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9220302MS A CY54FCT244ATW 5962-9220303M2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9220303M2A 5962-9220303MRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9220303MR A CY54FCT244CTDM B 5962-9221301MRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9221301MR A 5962-9221303M2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9221303M2A CY54FCT 240ATLMB 5962-9221303MRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9221303MR A CY54FCT240ATDM B Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9221305MRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9221305MR A CY54FCT240ATDMB ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9221303MR A CY54FCT240ATDM B CY54FCT240ATLMB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9221303M2A CY54FCT 240ATLMB CY54FCT244ATDMB ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9220302MR A CY54FCT244ATDM B CY54FCT244ATLMB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9220302M2A CY54FCT 244ATLMB CY54FCT244ATW ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9220302MS A CY54FCT244ATW CY54FCT244CTDMB ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9220303MR A CY54FCT244CTDM B CY54FCT244TDMB ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9220301MR A CY54FCT244TDMB CY54FCT244TLMB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9220301M2A CY54FCT 244TLMB CY54FCT244TW ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9220301MS A CY54FCT244TW CY74FCT240ATQCT ACTIVE SSOP DBQ 20 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT240A & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CY74FCT240ATQCTG4 ACTIVE SSOP DBQ 20 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT240A & no Sb/Br) CY74FCT240ATSOC ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 FCT240A & no Sb/Br) CY74FCT240ATSOCT ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 FCT240A & no Sb/Br) CY74FCT240TQCT ACTIVE SSOP DBQ 20 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT240 & no Sb/Br) CY74FCT240TSOC ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 FCT240 & no Sb/Br) CY74FCT240TSOCT ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 FCT240 & no Sb/Br) CY74FCT244ATPC ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 CY74FCT244ATPC (RoHS) CY74FCT244ATQCT ACTIVE SSOP DBQ 20 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT244A & no Sb/Br) CY74FCT244ATQCTE4 ACTIVE SSOP DBQ 20 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT244A & no Sb/Br) CY74FCT244ATSOC ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 FCT244A & no Sb/Br) CY74FCT244ATSOCT ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 FCT244A & no Sb/Br) CY74FCT244CTQCT ACTIVE SSOP DBQ 20 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT244C & no Sb/Br) CY74FCT244CTSOC ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 FCT244C & no Sb/Br) CY74FCT244DTSOC ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 FCT244D & no Sb/Br) CY74FCT244DTSOCT ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 FCT244D & no Sb/Br) CY74FCT244DTSOCTE4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 FCT244D & no Sb/Br) CY74FCT244TQCT ACTIVE SSOP DBQ 20 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT244 & no Sb/Br) CY74FCT244TSOC ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 FCT244 & no Sb/Br) Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CY74FCT244TSOCT ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 FCT244 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CY74FCT240ATQCT SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CY74FCT240ATSOCT SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 CY74FCT240TQCT SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CY74FCT240TSOCT SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 CY74FCT244ATQCT SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CY74FCT244ATSOCT SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 CY74FCT244CTQCT SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CY74FCT244DTSOCT SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 CY74FCT244TQCT SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CY74FCT244TSOCT SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CY74FCT240ATQCT SSOP DBQ 20 2500 367.0 367.0 38.0 CY74FCT240ATSOCT SOIC DW 20 2000 367.0 367.0 45.0 CY74FCT240TQCT SSOP DBQ 20 2500 367.0 367.0 38.0 CY74FCT240TSOCT SOIC DW 20 2000 367.0 367.0 45.0 CY74FCT244ATQCT SSOP DBQ 20 2500 367.0 367.0 38.0 CY74FCT244ATSOCT SOIC DW 20 2000 367.0 367.0 45.0 CY74FCT244CTQCT SSOP DBQ 20 2500 367.0 367.0 38.0 CY74FCT244DTSOCT SOIC DW 20 2000 367.0 367.0 45.0 CY74FCT244TQCT SSOP DBQ 20 2500 367.0 367.0 38.0 CY74FCT244TSOCT SOIC DW 20 2000 367.0 367.0 45.0 PackMaterials-Page2

None

None

None

None

None

None

PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated