CY62256N 256-Kbit (32 K × 8) Static RAM 256-Kbit (32 K × 8) Static RA Features Functional Description ■Temperature ranges The CY62256N is a high performance CMOS static RAM ❐Commercial: 0 °C to +70 °C organized as 32K words by 8 bits. Easy memory expansion is ❐Industrial: –40 °C to +85 °C provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tristate drivers. This device has an ❐Automotive-A: –40 °C to +85 °C automatic power-down feature, reducing the power consumption ❐Automotive-E: –40 °C to +125 °C by 99.9 percent when deselected. ■High speed: 55 ns An active LOW write enable signal (WE) controls the ■Voltage range: 4.5 V to 5.5 V operation writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins ■Low active power (I/O through I/O ) is written into the memory location addressed 0 7 ❐275 mW (max) by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and ■Low standby power (LL version) enabling the outputs, CE and OE active LOW, while WE remains ❐82.5 W (max) inactive or HIGH. Under these conditions, the contents of the ■Easy memory expansion with CE and OE Features location addressed by the information on address pins are present on the eight data input/output pins. ■TTL-compatible inputs and outputs The input/output pins remain in a high impedance state unless ■Automatic power-down when deselected the chip is selected, outputs are enabled, and write enable (WE) is HIGH. ■CMOS for optimum speed and power For a complete list of related documentation, click here. ■Available in Pb-free and non Pb-free 28-pin (600-mil) PDIP, 28-pin (300-mil) narrow SOIC, 28-pin TSOP I, and 28-pin reverse TSOP I packages Logic Block Diagram I/O0 INPUTBUFFER A10 R I/O1 A9 E A8 OD PS I/O2 A7 C M AA65 W DE 32AKR Rx A8Y SE A I/O3 AA43 RO SEN I/O4 A2 I/O5 WCEE COLUMN POWER I/O6 DOWN DECODER OE I/O7 A14 A13A12A11A1A0 CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-06511 Rev. *J Revised April 28, 2017

CY62256N Contents Product Portfolio ..............................................................3 Truth Table ......................................................................11 Pin Configurations ...........................................................3 Ordering Information ......................................................12 Pin Definitions ..................................................................3 Ordering Code Definitions .........................................12 Maximum Ratings .............................................................4 Package Diagrams ..........................................................13 Operating Range ...............................................................4 Acronyms ........................................................................15 Electrical Characteristics .................................................4 Document Conventions .................................................15 Capacitance ......................................................................5 Units of Measure .......................................................15 Thermal Resistance ..........................................................5 Document History Page .................................................16 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ......................17 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support .......................17 Data Retention Waveform ................................................6 Products ....................................................................17 Switching Characteristics ................................................7 PSoC® Solutions ......................................................17 Switching Waveforms ......................................................8 Cypress Developer Community .................................17 Typical DC and AC Characteristics ..............................10 Technical Support .....................................................17 Document Number: 001-06511 Rev. *J Page 2 of 17

CY62256N Product Portfolio Power Dissipation V Range (V) CC Product Speed (ns) Operating, I (mA) Standby, I (A) CC SB2 Min Typ[1] Max Typ[1] Max Typ[1] Max CY62256NLL Commercial 4.5 5.0 5.5 70 25 50 0.1 5 CY62256NLL Industrial 55/70 25 50 0.1 10 CY62256NLL Automotive-A 55/70 25 50 0.1 10 CY62256NLL Automotive-E 55 25 50 0.1 15 Pin Configurations Figure 1. 28-pin DIP and Narrow SOIC pinout Figure 2. 28-pin TSOP I and Reverse TSOP I pinout Pin Definitions Pin Number Type Description 1–10, 21, 23–26 Input A –A . Address Inputs 0 14 11–13, 15–19, Input/Output I/O –I/O . Data lines. Used as input or output lines depending on operation 0 7 27 Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted 20 Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip 22 Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins 14 Ground GND. Ground for the device 28 Power Supply V . Power supply for the device CC Note 1. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA=25 °C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested. Document Number: 001-06511 Rev. *J Page 3 of 17

CY62256N Maximum Ratings Output current into outputs (LOW) .............................20 mA Static discharge voltage Exceeding maximum ratings may impair the useful life of the (per MIL-STD-883, method 3015) ......................... > 2001 V device. These user guidelines are not tested. Latch-up current ................................................... > 200 mA Storage temperature ................................–65 C to +150 C Ambient temperature with Operating Range power applied ..........................................–55 C to +125 C Supply voltage to ground potential Range Ambient Temperature (TA) [3] VCC (pin 28 to pin 14) [2] .....................................–0.5 V to +7.0 V Commercial 0 C to +70 C 5 V  10% DC voltage applied to outputs Industrial –40 C to +85 C 5 V  10% in high Z State [2] ................................–0.5 V to V + 0.5 V CC Automotive-A –40 C to +85 C 5 V  10% DC input voltage [2] .............................–0.5 V to V + 0.5 V CC Automotive-E –40 C to +125 C 5 V  10% Electrical Characteristics Over the Operating Range -55 -70 Parameter Description Test Conditions Unit Min Typ [4] Max Min Typ [4] Max V Output HIGH V = Min, I = 1.0 mA 2.4 – – 2.4 – – V OH CC OH voltage V Output LOW V = Min, I = 2.1 mA – – 0.4 – – 0.4 V OL CC OL voltage V Input HIGH 2.2 – V + 0.5 2.2 – V + 0.5 V IH CC CC voltage V Input LOW –0.5 – 0.8 –0.5 – 0.8 V IL voltage I Input leakage GND  V  V –0.5 – +0.5 –0.5 – +0.5 A IX I CC current I Output leakage GND  V  V , output disabled –0.5 – +0.5 –0.5 – +0.5 A OZ O CC current I V operating V = Max, LL - Commercial – – – – 25 50 mA CC CC CC supply current I = 0 mA, OUT LL - Industrial – 25 50 – 25 50 mA f = f = 1/t MAX RC LL - Automotive-A – 25 50 – 25 50 mA LL - Automotive-E – 25 50 – – – mA I Automatic CE Max. V , CE  V , LL - Commercial – – – – 0.3 0.5 mA SB1 CC IH power-down V  V or V  V , IN IH IN IL LL - Industrial – 0.3 0.5 – 0.3 0.5 mA current – TTL f = f MAX inputs LL - Automotive-A – 0.3 0.5 – 0.3 0.5 mA LL - Automotive-E – 0.3 0.5 – – – mA I Automatic CE Max. V , LL - Commercial – – – – 0.1 5 A SB2 CC power-down CE  V  0.3 V, CC LL - Industrial – 0.1 10 – 0.1 10 A current – CMOS V  V  0.3 V, or IN CC inputs V  0.3 V, f = 0 LL - Automotive-A – 0.1 10 – 0.1 10 A IN LL - Automotive-E – 0.1 15 – – – A Notes 2. VIL (min) = 2.0 V for pulse durations of less than 20 ns. 3. TA is the “Instant-On” case temperature. 4. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA=25 °C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested. Document Number: 001-06511 Rev. *J Page 4 of 17

CY62256N Capacitance Parameter [5] Description Test Conditions Max Unit C Input capacitance T = 25 C, f = 1 MHz, V = 5.0 V 6 pF IN A CC C Output capacitance 8 pF OUT Thermal Resistance Parameter [5] Description Test Conditions DIP SOIC TSOP RTSOP Unit  Thermal resistance Still air, soldered on 75.61 76.56 93.89 93.89 C/W JA (junction to ambient) a 4.25 × 1.125 inch, 4-layer printed  Thermal resistance 43.12 36.07 24.64 24.64 C/W JC circuit board (junction to case) AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms R1 1800  R1 1800  5 V 5 V ALL INPUT PULSES OUTPUT OUTPUT 3.0 V 90% 90% 10% 10% 100pF R2 5pF R2 GND 990 990  5ns < 5ns INCLUDING INCLUDING JIG AND JIG AND SCOPE (a) SCOPE (b) Equivalentto: THÉV ENINEQUIVALENT 639 OUTPUT 1.77 V Note 5. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-06511 Rev. *J Page 5 of 17

CY62256N Data Retention Characteristics Parameter Description Conditions [6] Min Typ [7] Max Unit V V for data retention 2.0 – – V DR CC I Data LL – Commercial V = 2.0 V, CE  V  0.3 V, – 0.1 5 A CCDR CC CC retention LL – Industrial/ VIN  VCC  0.3 V, or VIN  0.3 V – 0.1 10 A current Automotive-A LL – Automotive-E – 0.1 10 A t [7] Chip deselect to data retention 0 – – ns CDR time t [7] Operation recovery time CY62256NLL-55 55 – – ns R CY62256NLL-70 70 – – Data Retention Waveform Figure 4. Data Retention Waveform DATA RETENTION MODE VCC 3.0 V VDR 2 V 3.0 V tCDR tR CE Notes 6. No input may exceed VCC + 0.5 V. 7. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA=25 °C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested. Document Number: 001-06511 Rev. *J Page 6 of 17

CY62256N Switching Characteristics Over the Operating Range CY62256N-55 CY62256N-70 Parameter [8] Description Unit Min Max Min Max Read Cycle t Read cycle time 55 – 70 – ns RC t Address to data valid – 55 – 70 ns AA t Data hold from address change 5 – 5 – ns OHA t CE LOW to data valid – 55 – 70 ns ACE t OE LOW to data valid – 25 – 35 ns DOE t OE LOW to low Z [9] 5 – 5 – ns LZOE t OE HIGH to high Z [9, 10] – 20 – 25 ns HZOE t CE LOW to low Z [9] 5 – 5 – ns LZCE t CE HIGH to high Z [9, 10] – 20 – 25 ns HZCE t CE LOW to power-up 0 – 0 – ns PU t CE HIGH to power-down – 55 – 70 ns PD Write Cycle [11, 12] t Write cycle time 55 – 70 – ns WC t CE LOW to write end 45 – 60 – ns SCE t Address setup to write end 45 – 60 – ns AW t Address hold from write end 0 – 0 – ns HA t Address setup to write start 0 – 0 – ns SA t WE pulse width 40 – 50 – ns PWE t Data setup to write end 25 – 30 – ns SD t Data hold from write end 0 – 0 – ns HD t WE LOW to high Z [9, 10] – 20 – 25 ns HZWE t WE HIGH to low Z [9] 5 – 5 – ns LZWE Notes 8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 9. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 10.tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 11.The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write. 12.The minimum write cycle time for Write Cycle No. 3 (WE Controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-06511 Rev. *J Page 7 of 17

CY62256N Switching Waveforms Figure 5. Read Cycle No. 1 [13, 14] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 6. Read Cycle No. 2 [14, 15] tRC CE tACE OE tLZOEtDOE ttHHZZOCEE HIGH HIGH IMPEDANCE IMPEDANCE DATA OUT DATA VALID tLZCE tPU tPD VCC ICC SUPPLY 50% 50% CURRENT ISB Notes 13.Device is continuously selected. OE, CE = VIL. 14.WE is HIGH for Read cycle. 15.Address valid prior to or coincident with CE transition LOW. Document Number: 001-06511 Rev. *J Page 8 of 17

CY62256N Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (WE Controlled) [16, 17, 18] tWC ADDRESS CE tAW tHA tSA tPWE WE OE tSD tHD DATA I/O NOTE19 DATAINVALID tHZOE Figure 8. Write Cycle No. 2 (CE Controlled) [16, 17, 18] tWC ADDRESS CE tSCE tSA tAW tHA WE tSD tHD DATA I/O DATAINVALID Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [18, 20] tWC ADDRESS CE tAW tHA tSA WE tSD tHD DATA I/O NOTE 19 DATAINVALID tHZWE tLZWE Notes 16.The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write. 17.Data I/O is high impedance if OE = VIH. 18.If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 19.During this period, the I/Os are in output state and input signals should not be applied. 20.The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE. Document Number: 001-06511 Rev. *J Page 9 of 17

CY62256N Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT STANDBY CURRENT vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. AMBIENT TEMPERATURE 1.4 1.4 3.0 I CC SB1.2 1.2 2.5 RMALIZED I, ICC100...068 ICCVTAIN = = 2 55.0CV RMALIZED I CC 010...608 VCC = 5.0V I ASB2211...050 ISB O 0.4 O 0.4 V = 5.0V 0.5 N N IN V = 5.0V 0.2 0.2 0.0 CC I V = 5.0V SB IN 0.0 0.0 –0.5 4.0 4.5 5.0 5.5 6.0 55 25 125 55 25 105 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME NORMALIZED ACCESS TIME OUTPUT SINK CURRENT vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE 1.4 1.6 A) 140 m T ( 120 1.3 1.4 N D tAA 1.2 D tAA RRE 100 ZE ZE 1.2 CU 80 NORMALI 11..10 TA = 25C NORMALI 1.0 VCC = 5.0V PUT SINK 6400 VTCA C= =2 55.0CV 0.8 T 0.9 U 20 O 0.8 0.6 0 4.0 4.5 5.0 5.5 6.0 55 25 125 0.0 1.0 2.0 3.0 4.0 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) OUTPUT VOLTAGE (V) OUTPUT SOURCE CURRENT A) vs. OUTPUT VOLTAGE m120 T ( N100 E R R U 80 C E VCC = 5.0V C 60 R TA = 25C U O 40 S T U P 20 T U O 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) Document Number: 001-06511 Rev. *J Page 10 of 17

CY62256N Typical DC and AC Characteristics (continued) TYPICAL POWER-ON CURRENT TYPICAL ACCESS TIME CHANGE vs. SUPPLY VOLTAGE vs. OUTPUT LOADING NORMALIZED I vs. CYCLE TIME CC 3.0 30.0 1.25 MALIZED IPO 221...505 ELTA t (ns)AA 221505...000 RMALIZED ICC1.00 VTVACIN C= = =2 5 55. 0.0 CV V OR 1.0 D 10.0 VCC = 4.5 V NO0.75 N T = 25 C A 0.5 5.0 0.0 0.0 0.50 0.0 1.0 2.0 3.0 4.0 5.0 0 200 400 600 800 1000 10 20 30 40 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Truth Table CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/power-down Standby (I ) SB L H L Data Out Read Active (I ) CC L L X Data In Write Active (I ) CC L H H High Z Output Disabled Active (I ) CC Document Number: 001-06511 Rev. *J Page 11 of 17

CY62256N Ordering Information Speed Package Operating Package Type (ns) Ordering Code Diagram Range 55 CY62256NLL55SNXI 51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free) Industrial CY62256NLL55ZXI 51-85071 28-pin TSOP I (Pb-free) CY62256NLL55ZXA 51-85071 28-pin TSOP I (Pb-free) Automotive-A CY62256NLL55SNXE 51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free) Automotive-E CY62256NLL55ZXE 51-85071 28-pin TSOP I (Pb-free) 70 CY62256NLL70PXC 51-85017 28-pin (600 Mil) Molded DIP (Pb-free) Commercial CY62256NLL70SNXC 51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free) CY62256NLL70ZRXI 51-85074 28-pin Reverse TSOP I (Pb-free) Industrial CY62256NLL70SNXA 51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free) Automotive-A Ordering Code Definitions CY 62 256 N LL - XX XXX X Temperature Grade: X = C or I or A or E C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C; A = Automotive-A = –40 °C to +85 °C; E = Automotive-E = –40 °C to +125 °C Package Type: XXX = SNX or ZX or PX or ZRX SNX = 28-pin SNC (Pb-free) ZX= 28-pin TSOP I (Pb-free) PX = 28-pin Molded DIP (Pb-free) ZRX = 28-pin Reverse TSOP I (Pb-free) Speed Grade: XX = 55 ns or 70 ns Low Power Nitride Seal Mask fix Density: 256 kbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document Number: 001-06511 Rev. *J Page 12 of 17

CY62256N Package Diagrams Figure 10. 28-pin PDIP (1.480 × 0.550 × 0.195 Inches) P28.6/PZ28.6 Package Outline, 51-85017 51-85017 *F Figure 11. 28-pin SNC (300 Mils) SN28.3 (Narrow Body) Package Outline, 51-85092 51-85092 *E Document Number: 001-06511 Rev. *J Page 13 of 17

CY62256N Package Diagrams (continued) Figure 12. 28-pin TSOP I (8 × 13.4 × 1.2 mm) Z28 (Standard) Package Outline, 51-85071 51-85071 *J Figure 13. 28-pin TSOP I (8 × 13.4 mm) Package Outline - Reverse, 51-85074 51-85074 *H Document Number: 001-06511 Rev. *J Page 14 of 17

CY62256N Acronyms Document Conventions Acronym Description Units of Measure CMOS Complementary Metal Oxide Semiconductor Symbol Unit of Measure I/O Input/Output °C degree Celsius SRAM Static Random Access Memory A microampere TSOP Thin Small Outline Package mA milliampere VFBGA Very Fine-Pitch Ball Grid Array MHz megahertz ns nanosecond  ohm pF picofarad V volt W watt Document Number: 001-06511 Rev. *J Page 15 of 17

CY62256N Document History Page Document Title: CY62256N, 256-Kbit (32 K × 8) Static RAM Document Number: 001-06511 Orig. of Submission Revision ECN Description of Change Change Date ** 426504 NXR See ECN New data sheet. *A 488954 NXR See ECN Added Automotive product Updated ordering Information table *B 2715270 VKN / AESA 06/05/2009 Updated POD of 28-Pin (600-Mil) Molded DIP package (Spec# 51-85017) *C 2891344 VKN 03/12/2010 Added Table of Contents Removed “L” product information Updated Ordering Information table Updated Package Diagrams (Figure 10, Figure 11, and Figure 12) Updated Sales, Solutions, and Legal Information *D 3119519 AJU 01/04/2011 Updated Ordering Information. Added Ordering Code Definitions. *E 3329873 RAME 07/27/11 Updated template and styles according to current Cypress standards. Added acronyms and units. Removed reference to AN1064 SRAM system guidelines. Updated operation recovery time parameter under Data Retention Characteristics on page 6. *F 3433878 TAVA 11/09/11 Updated Package Diagrams. *G 4122787 VINI 09/13/2013 Updated Package Diagrams: spec 51-85092 – Changed revision from *D to *E. Updated in new template. Completing Sunset Review. *H 4525875 VINI 10/06/2014 Updated Maximum Ratings: Referred Note 2 in “Supply voltage to ground potential (pin 28 to pin 14)”. Updated Package Diagrams: spec 51-85071 – Changed revision from *I to *J. spec 51-85074 – Changed revision from *G to *H. Completing Sunset Review. *I 4576406 VINI 01/16/2015 Added related documentation hyperlink in page 1. Added Note 12 in Switching Characteristics. Added note reference 12 in the Switching Characteristics table. Added Note 20 in Switching Waveforms. Added note reference 20 in Figure9. Updated Figure10 in Package Diagrams (spec 51-85017 *E to *F). *J 5718683 AESATMP7 04/28/2017 Updated Cypress Logo and Copyright. Document Number: 001-06511 Rev. *J Page 16 of 17

CY62256N Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP| PSoC 6 Interface cypress.com/go/interface Cypress Developer Community Lighting & Power Control cypress.com/go/powerpsoc Community | Forums | Blogs | Video | Training Memory cypress.com/go/memory Technical Support PSoC cypress.com/go/psoc cypress.com/go/support Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-06511 Rev. *J Revised April 28, 2017 Page 17 of 17

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: C ypress Semiconductor: CY62256NLL-55SNXE CY62256NLL-55SNXET CY62256NLL-55ZXA CY62256NLL-55ZXAT CY62256NLL-55ZXET CY62256NLL-55ZXIT CY62256NLL-70SNXAT CY62256NLL-70ZRXIT CY62256NLL-55SNXIT CY62256NLL-55ZXE CY62256NLL-55ZXI CY62256NLL-70PXC CY62256NLL-70SNXC CY62256NLL-70SNXCT CY62256NLL-55SNXI CY62256NLL-70SNXA CY62256NLL-70ZRXI