® CY62146EV30 MoBL 4-Mbit (256K × 16) Static RAM 4-Mbit (256K × 16) Static RAM Features advanced circuit design designed to provide an ultra low active current. Ultra low active current is ideal for providing More ■Very high speed: 45 ns Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down ■Temperature ranges feature that significantly reduces power consumption by 80 ❐Industrial: –40 °C to +85 °C percent when addresses are not toggling.The device can also be ❐Automotive-A: –40 °C to +85 °C put into standby mode reducing power consumption by more than 99 percent when deselected (CE HIGH). The input and ■Wide voltage range: 2.20 V to 3.60 V output pins (I/O through I/O ) are placed in a high impedance 0 15 ■Pin compatible with CY62146DV30 state when the device is deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low ■Ultra low standby power Enable are disabled (BHE, BLE HIGH), or a write operation is in ❐Typical standby current: 1 A progress (CE LOW and WE LOW). ❐Maximum standby current: 7 A To write to the device, take Chip Enable (CE) and Write Enable ■Ultra low active power (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data ❐ Typical active current: 2 mA at f = 1 MHz from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A through A ). If Byte High 0 17 ■Easy memory expansion with CE and OE features Enable (BHE) is LOW, then data from the I/O pins (I/O through 8 ■Automatic power down when deselected I/O15) is written into the location specified on the address pins (A through A ). 0 17 ■Complementary metal oxide semiconductor (CMOS) for To read from the device, take Chip Enable (CE) and Output optimum speed and power Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If ■Available in a Pb-free 48-ball very fine-pitch ball grid array Byte Low Enable (BLE) is LOW, then data from the memory (VFBGA) and 44-pin TSOP II Packages location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory Functional Description appears on I/O to I/O . See the Truth Table on page 11 for a 8 15 complete description of read and write modes. The CY62146EV30 is a high performance CMOS static RAM For a complete list of related documentation, click here. organized as 256K words by 16 bits. This device features an Logic Block Diagram DATA IN DRIVERS A 10 A 9 A R 8 E S A7 D P A6 CO 256K x 16 AM AA5 DE RAM Array SE I/O0–I/O7 4 W N AA3 RO SE I/O8–I/O15 2 A 1 A 0 COLUMN DECODER BHE WE A11 A12 A13 A14 A15 A16 A17 OCEE BLE CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 38-05567 Rev. *M Revised January 12, 2018

® CY62146EV30 MoBL Contents Pin Configurations ...........................................................3 Ordering Information ......................................................12 Product Portfolio ..............................................................3 Ordering Code Definitions .........................................12 Maximum Ratings .............................................................4 Package Diagrams ..........................................................13 Operating Range ...............................................................4 Acronyms ........................................................................15 Electrical Characteristics .................................................4 Document Conventions .................................................15 Capacitance ......................................................................5 Units of Measure .......................................................15 Thermal Resistance ..........................................................5 Document History Page .................................................16 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ......................19 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support .......................19 Data Retention Waveform ................................................6 Products ....................................................................19 Switching Characteristics ................................................7 PSoC® Solutions ......................................................19 Switching Waveforms ......................................................8 Cypress Developer Community .................................19 Truth Table ......................................................................11 Technical Support .....................................................19 Document Number: 38-05567 Rev. *M Page 2 of 19

® CY62146EV30 MoBL Pin Configurations Figure 1. 48-ball VFBGA pinout [1, 2] Figure 2. 44-pin TSOP II pinout [1] 1 2 3 4 5 6 A4 1 44 A5 A3 2 43 A6 BLE OE A0 A1 A2 NC A A2 3 42 A7 A1 4 41 OE A0 5 40 BHE I/O8 BHE A3 A4 CE I/O0 B CE 6 39 BLE I/O0 7 38 I/O15 I/O9 I/O10 A5 A6 I/O1 I/O2 C I/O1 8 37 I/O14 I/O2 9 36 I/O13 VSS I/O11 A17 A7 I/O3 VCC D VI/COC3 1110 3354 VI/OSS12 VCC I/O12 NC A16 I/O4 VSS E VI/SOS4 1123 3323 IV/OCC11 I/O5 14 31 I/O10 I/O14 I/O13 A14 A15 I/O5 I/O6 F II//OO76 1165 2390 II//OO89 WE 17 28 NC I/O15 NC A12 A13 WE I/O7 G A17 18 27 A8 A16 19 26 A9 NC A8 A9 A10 A11 NC H AA1154 2201 2254 AA1110 A13 22 23 A12 Product Portfolio Power Dissipation VCC Range (V) Speed Operating ICC (mA) Product Range Standby I (A) (ns) f = 1 MHz f = f SB2 max Min Typ [3] Max Typ [3] Max Typ [3] Max Typ [3] Max CY62146EV30LL Industrial / 2.2 3.0 3.6 45 2 2.5 15 20 1 7 Automotive-A Notes 1. NC pins are not connected on the die. 2. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8Mb, 16Mb and 32Mb respectively. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document Number: 38-05567 Rev. *M Page 3 of 19

® CY62146EV30 MoBL Maximum Ratings DC input voltage [4, 5] .......–0.3 V to 3.9 V (V + 0.3 V) CC max Output current into outputs (LOW) .............................20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... >2001 V Storage temperature ...............................–65 °C to + 150 °C Latch-up Current ....................................................>200 mA Ambient temperature with power applied ..................................–55 °C to + 125 °C Operating Range Supply voltage to ground potential ..........–0.3 V to + 3.9 V (V + 0.3 V) Device Range Ambient V [6] CCmax Temperature CC DC voltage applied to outputs in High-Z state [4, 5] ............–0.3 V to 3.9 V (V + 0.3 V) CY62146EV30 Industrial / –40 °C to +85 °C 2.2 V to 3.6 V CCmax Automotive-A Electrical Characteristics Over the Operating Range 45 ns (Ind’l/Auto-A) Parameter Description Test Conditions Unit Min Typ [7] Max V Output high voltage I = –0.1 mA 2.0 – – V OH OH I = –1.0 mA, V > 2.70 V 2.4 – – V OH CC V Output low voltage I = 0.1 mA – – 0.4 V OL OL I = 2.1 mA, V > 2.70 V – – 0.4 V OL CC V Input high voltage V = 2.2 V to 2.7 V 1.8 – V + 0.3 V IH CC CC V = 2.7 V to 3.6 V 2.2 – V + 0.3 V CC CC V Input LOW Voltage V = 2.2 V to 2.7 V –0.3 – 0.6 V IL CC V = 2.7 V to 3.6 V –0.3 – 0.8 V CC I Input leakage current GND < V < V –1 – +1 A IX I CC I Output leakage current GND < V < V , Output disabled –1 – +1 A OZ O CC I V operating supply current f = f = 1/t V = V , – 15 20 mA CC CC max RC CC CC(max) I = 0 mA f = 1 MHz OUT – 2 2.5 CMOS levels I Automatic CE power down CE > V – 0.2 V, – 1 7 A SB1 CC current – CMOS inputs V > V – 0.2 V or V < 0.2 V, IN CC IN f = f (Address and data only), max f = 0 (OE, BHE, BLE and WE), V = 3.60 V CC I [8] Automatic CE power down CE > V – 0.2 V, – 1 7 A SB2 CC current – CMOS inputs V > V – 0.2 V or V < 0.2 V, IN CC IN f = 0, V = 3.60 V CC Notes 4. VIL(min) = –2.0 V for pulse durations less than 20 ns. 5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to Vcc(min) and 200 s wait time after Vcc stabilization. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document Number: 38-05567 Rev. *M Page 4 of 19

® CY62146EV30 MoBL Capacitance Parameter [9] Description Test Conditions Max Unit C Input capacitance T = 25 C, f = 1 MHz, V = V 10 pF IN A CC CC(typ) C Output capacitance 10 pF OUT Thermal Resistance Parameter [9] Description Test Conditions VFBGA TSOP II Unit  Thermal resistance Still air, soldered on a 3 × 4.5 inch, 42.10 55.52 C/W JA (junction to ambient) four-layer printed circuit board  Thermal resistance 23.45 16.03 C/W JC (junction to case) AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms R1 V All Input Pulses CC Output VCC 90% 90% 10% 10% GND 30 pF R2 Rise Time = 1 V/ns Fall Time = 1 V/ns Including JIG and Scope Equivalent to: Thevenin Equivalent R TH Output V TH Parameters 2.50 V 3.0 V Unit R1 16667 1103  R2 15385 1554  R 8000 645  TH V 1.20 1.75 V TH Note 9. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-05567 Rev. *M Page 5 of 19

® CY62146EV30 MoBL Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ [10] Max Unit V V for data retention 1.5 – – V DR CC I [11] Data retention current V = 1.5 V, Industrial / – 0.8 7 A CCDR CC Automotive-A CE > V – 0.2 V, CC V > V – 0.2 V or IN CC V < 0.2 V IN t [12] Chip deselect to data retention – 0 – – ns CDR time t [13] Operation recovery time – 45 – – ns R Data Retention Waveform Figure 4. Data Retention Waveform DATA RETENTION MODE VCC VCC(min) VDR> 1.5 V VCC(min) tCDR tR CE Notes 10.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 11.Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ ISB2 / ICCDR spec. Other inputs can be left floating. 12.Tested initially and after any design or process changes that may affect these parameters. 13.Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. Document Number: 38-05567 Rev. *M Page 6 of 19

® CY62146EV30 MoBL Switching Characteristics Over the Operating Range 45 ns Parameter [14, 15] Description (Industrial / Automotive-A) Unit Min Max Read Cycle t Read cycle time 45 – ns RC t Address to data valid – 45 ns AA t Data hold from address change 10 – ns OHA tACE CE LOW to data valid – 45 ns tDOE OE LOW to data valid – 22 ns tLZOE OE LOW to Low-Z [16] 5 – ns tHZOE OE HIGH to High-Z [16, 17] – 18 ns tLZCE CE LOW to Low-Z [16] 10 – ns tHZCE CE HIGH to High-Z [16, 17] – 18 ns tPU CE LOW to power up 0 – ns tPD CE HIGH to power down – 45 ns tDBE BLE / BHE LOW to data valid – 22 ns tLZBE BLE / BHE LOW to Low-Z [16] 5 – ns tHZBE BLE / BHE HIGH to High-Z [16, 17] – 18 ns Write Cycle [18, 19] t Write cycle time 45 – ns WC tSCE CE LOW to write end 35 – ns t Address setup to write end 35 – ns AW t Address hold from write end 0 – ns HA t Address setup to write start 0 – ns SA tPWE WE pulse width 35 – ns tBW BLE / BHE LOW to write end 35 – ns t Data setup to write end 25 – ns SD t Data hold from write end 0 – ns HD tHZWE WE LOW to High-Z [16, 17] – 18 ns tLZWE WE HIGH to Low-Z [16] 10 – ns Notes 14.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 3 on page 5. 15.In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application Notes are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has been in production. 16.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 17.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 18.The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write 19.The minimum write pulse width for Write Cycle No. 3 (WE controlled, OE LOW) should be sum of tHZWE and tSD. Document Number: 38-05567 Rev. *M Page 7 of 19

® CY62146EV30 MoBL Switching Waveforms Figure 5. Read Cycle 1 (Address Transition Controlled) [20, 21] t RC ADDRESS t AA t OHA DATA I/O PREVIOUS DATA VALID DATA VALID OUT Figure 6. Read Cycle No. 2 (OE Controlled) [21, 22] ADDRESS tRC CE tPD tACE tHZCE OE t tHZOE DOE tLZOE BHE/BLE t HZBE t DBE tLZBE HIGH HIGHI MPEDANCE IMPEDANCE DATA I/O DATAOUT VALID t LZCE t PU I CC VCC 50% 50% SUPPLY ISB CURRENT Notes 20.The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 21.WE is HIGH for read cycle. 22.Address valid before or similar to CE and BHE, BLE transition LOW. Document Number: 38-05567 Rev. *M Page 8 of 19

® CY62146EV30 MoBL Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (WE Controlled) [23, 24, 25] tWC ADDRESS t SCE CE tAW tHA tSA tPWE WE BHE/BLE tBW OE tSD tHD DATA I/O NOTE 26 DATAIN tHZOE Figure 8. Write Cycle No. 2 (CEControlled) [23, 24, 25] tWC ADDRESS tSCE CE t SA tAW tHA t WE PWE BHE/BLE tBW OE tSD tHD DATAI/O NOTE 26 DATAIN tHZOE Notes 23.The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 24.Data I/O is high impedance if OE = VIH. 25.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 26.During this period, the I/Os are in output state and input signals must not be applied. Document Number: 38-05567 Rev. *M Page 9 of 19

® CY62146EV30 MoBL Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [27, 28] tWC ADDRESS tSCE CE BHE/BLE tBW tAW tHA tSA tPWE WE tHD tSD DATA I/O NOTE 29 DATA IN tHZWE tLZWE Figure 10. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [27] tWC ADDRESS CE tSCE tAW tHA t BW BHE/BLE tSA t WE PWE tHZWE tSD tHD DATA I/O NOTE 29 DATAIN tLZWE Notes 27.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 28.The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD. 29.During this period, the I/Os are in output state and input signals must not be applied. Document Number: 38-05567 Rev. *M Page 10 of 19

® CY62146EV30 MoBL Truth Table CE [30] WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High-Z Deselect/power-down Standby (I ) SB L X X H H High-Z Output disabled Active (I ) CC L H L L L Data out (I/O –I/O ) Read Active (I ) 0 15 CC L H L H L Data out (I/O –I/O ); Read Active (I ) 0 7 CC I/O –I/O in High-Z 8 15 L H L L H Data out (I/O –I/O ); Read Active (I ) 8 15 CC I/O –I/O in High-Z 0 7 L H H L L High-Z Output disabled Active (I ) CC L H H H L High-Z Output disabled Active (I ) CC L H H L H High-Z Output disabled Active (I ) CC L L X L L Data in (I/O –I/O ) Write Active (I ) 0 15 CC L L X H L Data in (I/O –I/O ); Write Active (I ) 0 7 CC I/O –I/O in High-Z 8 15 L L X L H Data in (I/O –I/O ); Write Active (I ) 8 15 CC I/O –I/O in High-Z 0 7 Note 30.Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted. Document Number: 38-05567 Rev. *M Page 11 of 19

® CY62146EV30 MoBL Ordering Information Speed Package Operating Package Type (ns) Ordering Code Diagram Range 45 CY62146EV30LL-45BVXI 51-85150 48-ball VFBGA (Pb-free) Industrial CY62146EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free) Please contact your local Cypress sales representative for availability of other parts Ordering Code Definitions CY 621 4 6 E V30 LL - 45 XX X X Temperature Grade: X = I I = Industrial Pb-free Package Type: XX = BV or ZS BV = VFBGA; ZS = TSOP II Speed Grade: 45 ns LL = Low Power Voltage Range: V30 = 3 V typical Process Technology: E = 90 nm Buswidth: 6 = × 16 Density: 4 = 4-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document Number: 38-05567 Rev. *M Page 12 of 19

® CY62146EV30 MoBL Package Diagrams Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Document Number: 38-05567 Rev. *M Page 13 of 19

® CY62146EV30 MoBL Package Diagrams (continued) Figure 12. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 38-05567 Rev. *M Page 14 of 19

® CY62146EV30 MoBL Acronyms Document Conventions Units of Measure Acronym Description BHE Byte High Enable Symbol Unit of Measure BLE Byte Low Enable °C degree Celsius CMOS Complementary Metal Oxide Semiconductor MHz megahertz CE Chip Enable A microampere I/O Input/Output mA milliampere ns nanosecond OE Output Enable  ohm SRAM Static Random Access Memory pF picofarad TSOP Thin Small Outline Package V volt VFBGA Very Fine-Pitch Ball Gird Array W watt WE Write Enable Document Number: 38-05567 Rev. *M Page 15 of 19

® CY62146EV30 MoBL Document History Page Document Title: CY62146EV30 MoBL®, 4-Mbit (256K × 16) Static RAM Document Number: 38-05567 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 223225 AJU 05/05/2004 New data sheet. *A 247373 SYT 07/28/2004 Changed status from Advance Information to Preliminary. Updated Operating Range: Updated Note 6 (Replaced “100 s wait time” with “200 s wait time”). Updated Data Retention Characteristics: Changed maximum value of I parameter from 2.0 A to 2.5 A. CCDR Changed minimum value of t parameter from 100 s to t ns. R RC Updated Switching Characteristics: Changed minimum value of t parameter from 6 ns to 10 ns corresponding OHA to both 35 ns and 45 ns speed bin. Changed maximum value of t parameter from 15 ns to 18 ns corresponding DOE to 35 ns speed bin. Changed maximum value of t , t , and t parameters from 12 ns HZOE HZBE HZWE to 15 ns corresponding 35 ns speed bin and from 15 ns to 18 ns corresponding to 45 ns speed bin. Changed maximum value of t parameter from 12 ns to 18 ns HZCE corresponding to 35 ns speed bin and from 15 ns to 22 ns corresponding to 45ns speed bin. Changed maximum value of t parameter from 15 ns to 18 ns corresponding DBE to 35 ns speed bin. Changed minimum value of t and t parameters from 25 to 30 ns SCE BW corresponding to 35 ns speed bin and from 40 ns to 35 ns corresponding to 45ns speed bin. Changed minimum value of t parameter from 15 ns to 18 ns corresponding SD to 35 ns speed bin and from 20 ns to 22 ns corresponding to 45 ns speed bin. Removed Note “If both Byte Enables (BHE and BLE) are toggled together then this value is 6 ns min. Otherwise this value is 3 ns min.” and its reference in t parameter. LZBE Updated Ordering Information: Updated part numbers. *B 414807 ZSD 12/16/2005 Changed status from Preliminary to Final. Removed “L” version of CY62146EV30 part in all instances across the document. Removed 35 ns speed bin related information in all instances across the document. Changed the address of Cypress Semiconductor Corporation in Page 1 from “3901 North First Street” to “198 Champion Court”. Updated Pin Configurations: Updated Figure1 (Replaced DNU with NC corresponding to ball E3). Removed Note “DNU pins have to be left floating or tied to Vss to ensure proper application.” and its reference. Document Number: 38-05567 Rev. *M Page 16 of 19

® CY62146EV30 MoBL Document History Page (continued) Document Title: CY62146EV30 MoBL®, 4-Mbit (256K × 16) Static RAM Document Number: 38-05567 Orig. of Submission Rev. ECN No. Description of Change Change Date *B (cont.) 414807 ZSD 12/16/2005 Updated Electrical Characteristics: Changed typical value of I parameter from 12 mA to 15 mA corresponding CC to 45 ns speed bin and Test Condition “f = f ”. max Changed typical value of I parameter from 1.5 mA to 2 mA corresponding CC to 45 ns speed bin and Test Condition “f = 1 MHz”. Changed maximum value of I parameter from 2 mA to 2.5 mA corresponding CC to 45 ns speed bin and Test Condition “f = 1 MHz”. Changed typical value of I parameter from 0.7 A to 1 A corresponding to SB1 45 ns speed bin. Changed maximum value of I parameter from 2.5 A to 7 A corresponding SB1 to 45 ns speed bin. Changed typical value of I parameter from 0.7 A to 1 A corresponding to SB2 45 ns speed bin. Changed maximum value of I parameter from 2.5 A to 7 A corresponding SB2 to 45 ns speed bin. Updated AC Test Loads and Waveforms: Updated Figure3 (Replaced 50 pF with 30 pF). Updated Data Retention Characteristics: Changed maximum value of I parameter from 2.5 A to 7 A. CCDR Added typical value of I parameter. CCDR Updated Switching Characteristics: Changed minimum value of t parameter from 3 ns to 5 ns corresponding LZOE to 45 ns speed bin. Changed minimum value of t parameter from 6 ns to 10 ns corresponding LZCE to 45 ns speed bin. Changed maximum value of t parameter from 22 ns to 18 ns HZCE corresponding to 45 ns speed bin. Changed minimum value of t parameter from 6 ns to 5 ns corresponding LZBE to 45 ns speed bin. Changed minimum value of t parameter from 30 ns to 35 ns corresponding PWE to 45 ns speed bin. Changed minimum value of t parameter from 22 ns to 25 ns corresponding SD to 45 ns speed bin. Changed minimum value of t parameter from 6 ns to 10 ns corresponding LZWE to 45 ns speed bin. Updated Ordering Information: Updated part numbers. Removed “Package Name” column. Added “Package Diagram” column. Updated Package Diagrams: spec 51-85150 – Changed revision from *B to *D. Updated to new template. *C 925501 VKN 04/09/2007 Updated Electrical Characteristics: Added Note 8 and referred the same note in I parameter. SB2 Updated Data Retention Characteristics: Added Note 11 and referred the same note in I parameter. CCDR Updated Switching Characteristics: Added Note 15 and referred the same note in “Parameter” column. *D 2678796 VKN / 03/25/2009 Added Automotive-A information in all instances across the document. PYRS Completing Sunset Review. Document Number: 38-05567 Rev. *M Page 17 of 19

® CY62146EV30 MoBL Document History Page (continued) Document Title: CY62146EV30 MoBL®, 4-Mbit (256K × 16) Static RAM Document Number: 38-05567 Orig. of Submission Rev. ECN No. Description of Change Change Date *E 2944332 VKN 06/04/2010 Updated Truth Table: Added Note 30 and referred the same note in “CE” column. Updated Package Diagrams: spec 51-85150 – Changed revision from *D to *E. spec 51-85087 – Changed revision from *A to *C. Updated to new template. *F 3109050 PRAS 12/13/2010 Changed all Table Footnotes to Notes in all instances across the document. Updated Ordering Information: No change in part numbers. Added Ordering Code Definitions. Updated Package Diagrams: spec 51-85150 – Changed revision from *E to *F. *G 3302915 RAME 07/14/2011 Updated Functional Description: Updated description (Removed references of AN1064 SRAM system guidelines). Updated Ordering Information: No change in part numbers. Updated Ordering Code Definitions. Added Units of Measure. Updated to new template. *H 3961126 TAVA 04/10/2013 Updated Package Diagrams: spec 51-85150 – Changed revision from *F to *H. spec 51-85087 – Changed revision from *C to *E. Completing Sunset Review. *I 4101995 VINI 08/22/2013 Updated Switching Characteristics: Updated Note 15. Updated to new template. *J 4348752 MEMJ 04/16/2014 Updated Switching Characteristics: Added Note 19 and referred the same note in “Write Cycle” (for t parameter PWE in WE controlled, OE LOW Write cycle). Updated Switching Waveforms: Added Note 28 and referred the same note in Figure9 (for t parameter in PWE WE controlled, OE LOW Write cycle). Completing Sunset Review. *K 4576526 MEMJ 11/21/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *L 5233278 VINI 04/21/2016 Updated Thermal Resistance: Replaced “two-layer” with “four-layer” in “Test Conditions” column. Updated all values in “VFBGA” and “TSOP II” columns. Updated to new template. Completing Sunset Review. *M 6029183 VINI 01/12/2018 Updated Ordering Information: Updated part numbers. Updated to new template. Document Number: 38-05567 Rev. *M Page 18 of 19

® CY62146EV30 MoBL Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions Arm® Cortex® Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Community | Projects | Video | Blogs | Training | Components Interface cypress.com/interface Technical Support Internet of Things cypress.com/iot cypress.com/support Memory cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless © Cypress Semiconductor Corporation, 2004-2018. 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You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-05567 Rev. *M Revised January 12, 2018 Page 19 of 19 MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor Corporation.

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