CY25811/12/14 Spread Spectrum Clock Generator Spread Spectrum Clock Generator Features Applications ■4 to 32 MHz input frequency range ■Printers and MFPs ■4 to 128 MHz output frequency range ■LCD panels ■Accepts clock, crystal, and resonator inputs ■Digital copiers ■1x, 2x, and 4x frequency multiplication: ■PDAs ❐CY25811: 1x; CY25812: 2x; CY25814: 4x ■CD-ROM, VCD, and DVD ■Center and Down Spread modulation ■Networking, LAN, and WAN ■Low power dissipation: ■Scanners ❐3.3V = 52 mW - typ at 6 MHz ❐3.3V = 60 mW - typ at 12 MHz ■Modems ❐3.3V = 72 mW - typ at 24 MHz ■Embedded digital systems ■Low cycle-to-cycle jitter: Benefits ❐8 MHz = 480 ps-max ❐16 MHz = 400 ps-max ■Peak EMI reduction by 8 to 16 dB ❐32 MHz = 450 ps-max ■Fast time to market ■Available in 8-pin SOIC and TSSOP packages ■Cost reduction ■Commercial and industrial temperature ranges Functional Description For a complete list of related documentation, click here. Logic Block Diagram 300K REFERENCE PD and XIN 1 LF DIVIDER CP 8pF XOUT8 8pF VCO MODULATION COUNTE VCO CONTROL R VDD 7 INPUT COUNTER DECODER and 5 VSS 2 LOGIC MUX SSCLK 6 3 4 FRSEL S1 S0 CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 38-07112 Rev. *N Revised May 24, 2017

CY25811/12/14 Contents Pin Configuration .............................................................3 Ordering Information ......................................................13 Pin Definitions ..................................................................3 Ordering Code Definitions .........................................13 Functional Overview ........................................................3 Package Drawing and Dimensions ...............................14 Input Frequency Range and Selection ........................3 Acronyms ........................................................................16 Spread Percentage Selection ......................................4 Document Conventions .................................................16 Input and Output Frequency Selection ........................5 Units of Measure .......................................................16 Absolute Maximum Conditions .......................................6 Document History Page .................................................17 DC Electrical Specifications ............................................6 Sales, Solutions, and Legal Information ......................19 DC Electrical Specifications ............................................7 Worldwide Sales and Design Support .......................19 Thermal Resistance ..........................................................7 Products ....................................................................19 AC Electrical Specifications ............................................8 PSoC®Solutions .......................................................19 AC Electrical Specifications ............................................9 Cypress Developer Community .................................19 Characteristic Curves ....................................................10 Technical Support .....................................................19 SSCG Profiles .................................................................11 Application Schematic ...................................................12 Document Number: 38-07112 Rev. *N Page 2 of 19

CY25811/12/14 Pin Configuration Figure 1. 8-pin SOIC/TSSOP pinout CY25811/12/14 XIN/CLKIN 1 8 XOUT VSS 2 CY25811 7 VDD CY25812 CY25814 S1 3 6 FRSEL S0 4 5 SSCLK Pin Definitions Pin No. Name Type Description 1 XIN/CLKIN Input Crystal, Ceramic Resonator or Clock Input Pin. 2 VSS Power Power Supply Ground. 3 S1 Input Digital Spread% Control Pin. 3-Level input (H-M-L). Default = M. 4 S0 Input Digital Spread% Control Pin. 3-Level input (H-M-L). Default = M. 5 SSCLK Output Spread Spectrum Output Clock. 6 FRSEL Input Input Frequency Range Selection Digital Control Input. 3-Level input (H-M-L). Default = M. 7 VDD Power Positive Power Supply. 8 XOUT Output Crystal or Ceramic Resonator Output Pin. Functional Overview Select the Center Spread or Down Spread frequency modulation based on four discrete values of Spread% for each Spread The CY25811/12/14 products are Spread Spectrum Clock mode with the option of a Non Spread mode for system test and Generator (SSCG) ICs used for the purpose of reducing verification purposes. electromagnetic interference (EMI) found in today’s high-speed The CY25811/12/14 products are available in an 8-pin SOIC digital electronic systems. (150 mils) package with a commercial operating temperature The devices use a Cypress proprietary phase-locked loop (PLL) range of 0 C to 70 C and industrial temperature range of –40C and Spread Spectrum Clock (SSC) technology to synthesize and to 85 °C. Refer to CY25568 for multiple clock output options such modulate the frequency of the input clock. By frequency as modulated and unmodulated clock outputs or power down modulating the clock, the measured EMI at the fundamental and function. harmonic frequencies is greatly reduced. Input Frequency Range and Selection This reduction in radiated energy significantly reduces the cost of complying with regulatory agency requirements and improves The CY25811/12/14 input frequency range is 4 to 32 MHz. This time to market without degrading system performance. range is divided into three segments and controlled by a 3-level FRSEL pin as given in Table1. The input frequency range is 4 to 32 MHz and accepts clock, crystal and ceramic resonator inputs. The output clock can be Table 1. Input Frequency Selection selected to produce 1x, 2x, or 4x multiplication of the input frequency with Spread Spectrum Frequency Modulation. FRSEL Input Frequency Range The use of 2x or 4x frequency multiplication eliminates the need 0 4.0 to 8.0 MHz for higher order crystals and enables you to generate up to 1 8.0 to 16.0 MHz 128MHz Spread Spectrum Clock (SSC) by using only first-order crystals. This reduces the cost while improving the system clock M 16.0 to 32.0 MHz accuracy, performance, and complexity. Document Number: 38-07112 Rev. *N Page 3 of 19

CY25811/12/14 Spread Percentage Selection The CY25811/12/14 SSCG products provide Center Spread, Down Spread, and No Spread functions. The amount of Spread percentage is selected using 3-level. S0 and S1 digital inputs and Spread percent values are given in Table2. Table 2. Spread Percent Selection XIN S1 = 0 S1 = 0 S1 = 0 S1 = M S1 = 1 S1 = 1 S1 = M S1 = 1 S1 = M FRSEL (MHz) S0 = 0 S0 = M S0 = 1 S0 = 0 S0 = 1 S0 = 0 S0 = 1 S0 = M S0 = M Center Center Center Center Down Down Down Down No (%) (%) (%) (%) (%) (%) (%) (%) Spread 4–5 0 ±1.4 ±1.2 ±0.6 ±0.5 –3.0 –2.2 –1.9 –0.7 0 5–6 0 ±1.3 ±1.1 ±0.5 ±0.4 –2.7 –1.9 –1.7 –0.6 0 6–7 0 ±1.2 ±0.9 ±0.5 ±0.4 –2.5 –1.8 –1.5 –0.6 0 7–8 0 ±1.1 ±0.9 ±0.4 ±0.3 –2.3 –1.7 –1.4 –0.5 0 8–10 1 ±1.4 ±1.2 ±0.6 ±0.5 –3.0 –2.2 –1.9 –0.7 0 10–12 1 ±1.3 ±1.1 ±0.5 ±0.4 –2.7 –1.9 –1.7 –0.6 0 12–14 1 ±1.2 ±0.9 ±0.5 ±0.4 –2.5 –1.8 –1.5 –0.6 0 14–16 1 ±1.1 ±0.9 ±0.4 ±0.3 –2.3 –1.7 –1.4 –0.5 0 16–20 M ±1.4 ±1.2 ±0.6 ±0.5 –3.0 –2.2 –1.9 –0.7 0 20–24 M ±1.3 ±1.1 ±0.5 ±0.4 –2.7 –1.9 –1.7 –0.6 0 24–28 M ±1.2 ±0.9 ±0.5 ±0.4 –2.5 –1.8 –1.5 –0.6 0 28–32 M ±1.1 ±0.9 ±0.4 ±0.3 –2.3 –1.7 –1.4 –0.5 0 3-Level Digital Inputs Modulation Rate S0, S1, and FRSEL digital inputs are designed to sense three SSCGs use frequency modulation (FM) to distribute energy over different logic levels designated as High “1”, Low “0”, and Middle a specific band of frequencies. The maximum frequency of the “M”. With this 3-Level digital input logic, the 3-Level Logic detects clock (f ) and minimum frequency of the clock (f ) determine max min nine different logic states. this band of frequencies. The time required to transition from f min to f and back to f is the period of the Modulation Rate. The S0, S1, and FRSEL pins include an on chip 20K (10K and 10K) max min Modulation Rate of SSCG clocks are generally referred to in resistor divider. No external application resistors are needed to terms of frequency, or: implement the 3-level logic levels as shown here: f = 1/T . Logic Level “0”: 3-Level logic pin connected to GND. mod mod The input clock frequency, f , and the internal divider determine Logic Level “M”: 3-Level logic pin left floating (no connection). in the Modulation Rate. Logic Level “1”: 3-Level logic pin connected to V . DD In CY25811/12/14 devices, the (Spread Spectrum) modulation Figure2 illustrates how to implement 3-Level Logic. rate, f , is given by the following formula: mod Figure 2. 3-Level Logic f = f /DR mod in Here f is the Modulation Rate, f is the Input Frequency, and LOGIC LOGIC LOGIC DR is mtohde Divider Ratio as giveni nin Table3. Note that Input LOW (0) MIDDLE (M) HIGH (H) Frequency Range is set by FRSEL. S0, S1 S0, S1 S0, S1 Table 3. Modulation Rate Divider Ratios and and and FRSEL FRSEL FRSEL Input Frequency Range Divider Ratio to VSS UNCONNECTED to VDD FRSEL (MHz) (DR) 0 4 to 8 128 VSS 1 8 to 16 256 M 16 to 32 512 Document Number: 38-07112 Rev. *N Page 4 of 19

CY25811/12/14 Input and Output Frequency Selection The relationship between input frequency and output frequency in device selection and FRSEL setting is given in Table4. As shown, the input frequency range is selected by FRSEL and is the same for CY25811, CY25812, and CY25814. The selection of CY25811 (1x), CY25812 (2x), or CY25814 (4x) determines the frequency multiplication at the output (SSCLK, Pin 5) with respect to input frequency (XIN, Pin-1). Table 4. Input and Output Frequency Selection Input Frequency Range Output Frequency Range FRSEL Product Multiplication (MHz) (MHz) 4 to 8 0 CY25811 1x 4 to 8 8 to 16 1 CY25811 1x 8 to 16 16 to 32 M CY25811 1x 16 to 32 4 to 8 0 CY25812 2x 8 to 16 8 to 16 1 CY25812 2x 16 to 32 16 to 32 M CY25812 2x 32 to 64 4 to 8 0 CY25814 4x 16 to 32 8 to 16 1 CY25814 4x 32 to 64 16 to 32 M CY25814 4x 64 to 128 Document Number: 38-07112 Rev. *N Page 5 of 19

CY25811/12/14 Absolute Maximum Conditions Both Commercial and Industrial Grades Parameter [1, 2] Description Condition Min Max Unit V Supply Voltage –0.5 4.6 V DD V Input Voltage Relative to V –0.5 V + 0.5 V IN SS DD T Temperature, Storage Non Functional –65 150 °C S T Temperature, Operating Ambient Functional, C-Grade 0 70 °C A1 T Temperature, Operating Ambient Functional, I-Grade –40 85 °C A2 T Temperature, Junction Functional – 150 °C J ESD ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V HBM UL-94 Flammability Rating at 1/8 in. V–0 MSL Moisture Sensitivity Level 3 DC Electrical Specifications Commercial Grade Parameter Description Condition Min Max Unit V 3.3 V Operating Voltage 3.3 V ± 10% 2.97 3.63 V DD V Input Low Voltage S0, S1 and FRSEL Inputs 0 0.15 × V V IL DD V Input Middle Voltage S0, S1 and FRSEL Inputs 0.40 × V 0.60 × V V IM DD DD V Input High Voltage S0, S1 and FRSEL Inputs 0.85 × V V V IH DD DD V Output Low Voltage I = 4 mA, SSCLK Output – 0.4 V OL1 OL V Output Low Voltage I = 10 mA, SSCLK Output – 1.2 V OL2 OL V Output High Voltage I = 4 mA, SSCLK Output 2.4 – V OH1 OH V Output High Voltage I = 6 mA, SSCLK Output 2.0 – V OH2 OH C Input Pin Capacitance XIN (Pin 1) and XOUT (Pin 8) 3.5 9.0 pF IN1 C Input Pin Capacitance All Digital Inputs 2.8 6.0 pF IN2 C Output Load Capacitor SSCLK Output – 15 pF L I Dynamic Supply Current F = 12 MHz, no load – 28 mA DD1 in I Dynamic Supply Current F = 24 MHz, no load – 33 mA DD2 in I Dynamic Supply Current F = 32 MHz, no load – 40 mA DD3 in Notes 1. Operation at any Absolute Maximum Rating is not implied. 2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up. Document Number: 38-07112 Rev. *N Page 6 of 19

CY25811/12/14 DC Electrical Specifications Industrial Grade Parameter Description Condition Min Max Unit V 3.3 V Operating Voltage 3.3 V ± 5% 3.135 3.465 V DD V Input Low Voltage S0, S1 and FRSEL Inputs 0 0.13 × V V IL DD V Input Middle Voltage S0, S1 and FRSEL Inputs 0.40 × V 0.60 × V V IM DD DD V Input High Voltage S0, S1 and FRSEL Inputs 0.85 × V V V IH DD DD V Output Low Voltage I = 4 mA, SSCLK Output – 0.4 V OL1 OL V Output Low Voltage I = 10 mA, SSCLK Output – 1.2 V OL2 OL V Output High Voltage I = 4 mA, SSCLK Output 2.4 – V OH1 OH V Output High Voltage I = 6 mA, SSCLK Output 2.0 – V OH2 OH C Input Pin Capacitance XIN (Pin 1) and XOUT (Pin 8) 3.5 9.0 pF IN1 C Input Pin Capacitance All Digital Inputs 2.8 6.0 pF IN2 C Output Load Capacitor SSCLK Output – 15 pF L I Dynamic Supply Current F = 12 MHz, no load – 28 mA DD1 in I Dynamic Supply Current F = 24 MHz, no load – 33 mA DD2 in I Dynamic Supply Current F = 32 MHz, no load – 41 mA DD3 in Thermal Resistance Parameter [3] Description Test Conditions 8-pin SOIC 8-pin TSSOP Unit θ Thermal resistance Test conditions follow standard test 139 159 °C/W JA (junction to ambient) methods and procedures for measuring thermal impedance, in accordance with θ Thermal resistance 54 32 °C/W JC EIA/JESD51. (junction to case) Note 3. These parameters are guaranteed by design and are not tested. Document Number: 38-07112 Rev. *N Page 7 of 19

CY25811/12/14 AC Electrical Specifications Commercial Grade Parameter Description Condition Min Max Unit F Input Frequency Range Clock, Crystal, or Ceramic Resonator Input 4 32 MHz IN T Clock Rise Time SSCLK, CY25811 and CY25812 2.0 5.0 ns R1 T Clock Fall Time SSCLK, CY25811 and CY25812 1.6 4.4 ns F1 T Clock Rise Time SSCLK, only CY25814 when FRSEL = M 1.0 2.2 ns R2 T Clock Fall Time SSCLK, only CY25814 when FRSEL = M 0.8 2.2 ns F2 T Input Clock Duty Cycle XIN 40 60 % DCIN T Output Clock Duty Cycle SSCLK 40 60 % DCOUT T Cycle to Cycle Jitter, Spread on F = 4 MHz, F = 4 MHz, CY25811 – 800 ps CCJ1 in out T Cycle to Cycle Jitter, Spread on F = 8 MHZ, F = 8 MHz, CY25811 – 480 ps CCJ2 in out T Cycle to Cycle Jitter, Spread on F = 8 MHz, F = 16 MHz, CY25812 – 400 ps CCJ3 in out T Cycle to Cycle Jitter, Spread on F = 16 MHz, F = 32 MHz, CY25812 – 450 ps CCJ4 in out T Cycle to Cycle Jitter, Spread on F = 16 MHz, F = 64 MHz, CY25814 – 550 ps CCJ5 in out T Cycle to Cycle Jitter, Spread on F = 32 MHz, F = 128 MHz, CY25814 – 380 ps CCJ6 in out T PLL Lock Time From V = 3.0 V to valid SSCLK – 3 ms SU DD Document Number: 38-07112 Rev. *N Page 8 of 19

CY25811/12/14 AC Electrical Specifications Industrial Grade Parameter Description Condition Min Max Unit F Input Frequency Range Clock, Crystal or Ceramic Resonator Input 4 32 MHz IN T Clock Rise Time SSCLK, CY25811, and CY25812 2.0 5.0 ns R1 T Clock Fall Time SSCLK, CY25811, and CY25812 1.6 4.4 ns F1 T Clock Rise Time SSCLK, only CY25814 when FRSEL = M 1.0 2.2 ns R2 T Clock Fall Time SSCLK, only CY25814 when FRSEL = M 0.8 2.2 ns F2 T Input Clock Duty Cycle XIN 40 60 % DCIN T Output Clock Duty Cycle SSCLK 40 60 % DCOUT T Cycle to Cycle Jitter, Spread on Fin = 6 MHz, CY25811/12/14 – 650 ps CCJ1 T Cycle to Cycle Jitter, Spread on Fin = 12 MHz, CY25811/12/14 – 630 ps CCJ2 T Cycle to Cycle Jitter, Spread on Fin = 24 MHz, CY25811/12/14 – 520 ps CCJ3 T PLL Lock Time From V = 3.0 V to valid SSCLK – 4 ms SU DD Document Number: 38-07112 Rev. *N Page 9 of 19

CY25811/12/14 Characteristic Curves The following curves demonstrate the characteristic behavior of CY25811/12/14 when tested over a number of environmental and application specific parameters. These are typical performance curves and are not meant to replace any parameter specified in DC and AC Specification tables. Figure 3. Characteristic Curves 600 2.75 6.0 MHz 32.0 MHz 500 2.5 400 ps) % J (300 W 2.25 C B C 200 2 100 0 1.75 4 8 12 16 20 24 28 32 -40 -25 -10 5 20 35 50 65 80 95 110 125 Input Frequency (MHz) Temp (C) Jitter vs. Input Frequency (No Load) Bandwidth % vs. Temperature 30 3 28 2.9 FRSEL = M 2.8 26 16 - 32 MHz 2.7 24 %)2.6 4.0 MHz DD (mA)2202 F8 R- S1E6 LM =H z1 BW (22..45 I 2.3 18 2.2 8.0 MHz 16 FRSEL = 0 2.1 14 4 - 8 MHz 2 1.9 12 1.8 10 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 4 4.5 5 5.5 6 6.5 7 7.5 8 Frequency (MHz), no load, normalized to FRSEL = 0, (4 - 8 MHz). VDD (volts) IDD vs. Frequency (FRSEL = 0, 1, M) Bandwidth % vs. VDD Document Number: 38-07112 Rev. *N Page 10 of 19

CY25811/12/14 SSCG Profiles CY25811/12/14 SSCG products use a non-linear “optimized” frequency profile as shown in Figure4. The use of Cypress proprietary “optimized” frequency profile maintains flat energy distribution over the fundamental and higher order harmonics. This results in additional EMI reduction in electronic systems. Figure 4. Spread Spectrum Profiles (Frequency versus Time) Xin = 6.0 MHz SSCLK1 = 6.0 MHz Xin = 24.0 MHz SSCLK1 = 24.0 MHz S1, S0 = 0 S1, S0 = 0 FRSEL = 0 P/N = CY25811 FRSEL = M P/N = CY25811 Xin = 12.0 MHz SSCLK1 = 48.0 MHz Xin = 24.0 MHz SSCLK1 = 96.0 MHz S1, S0 = 0 S1, S0 = 0 FRSEL = 1 P/N = CY25814 FRSEL = M P/N = CY25814 Document Number: 38-07112 Rev. *N Page 11 of 19

CY25811/12/14 Application Schematic VDD C3 0.1 uF 7 C2 1 VDD XIN 5 25 MHz (CY25811) 27 pF Y1 SSCLK 50 MHz (CY25812) C3 25 MHz 100 MHz (CY25814) 8 XOUT 27 pF CY25811 CY25812 CY25814 3 S1 6 N/C FRSEL 4 S0 VSS 2 Document Number: 38-07112 Rev. *N Page 12 of 19

CY25811/12/14 Ordering Information Part Number Package Type Product Flow Pb-free Devices CY25811SXC 8-pin SOIC Commercial, 0C to 70 C CY25811SXCT 8-pin SOIC – Tape and Reel Commercial, 0 C to 70 C CY25811SXI 8-pin SOIC Industrial, –40 °C to 85 °C CY25811SXIT 8-pin SOIC – Tape and Reel Industrial, –40 °C to 85 °C CY25812SXC 8-pin SOIC Commercial, 0 C to 70 C CY25812SXCT 8-pin SOIC – Tape and Reel Commercial, 0 C to 70 C CY25812ZXC 8-pin TSSOP Commercial, 0 C to 70 C CY25812ZXCT 8-pin TSSOP – Tape and Reel Commercial, 0 C to 70 C CY25814SXC 8-pin SOIC Commercial, 0 C to 70 C CY25814SXCT 8-pin SOIC – Tape and Reel Commercial, 0 C to 70 C CY25814SXI 8-pin SOIC Industrial, –40 °C to 85 °C CY25814SXIT 8-pin SOIC – Tape and Reel Industrial, –40 °C to 85 °C Ordering Code Definitions CY 2581 X X X X T T = Tape and Reel; blank = Tube Temperature Range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: X = S or Z S = 8-pin SOIC Z = 8-pin TSSOP Frequency Multiplier: X = 1 or 2 or 4 1 = 1X; 2 = 2X; 4 = 4X Part Identifier Company ID: CY = Cypress Document Number: 38-07112 Rev. *N Page 13 of 19

CY25811/12/14 Package Drawing and Dimensions Figure 5. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066 51-85066 *H Document Number: 38-07112 Rev. *N Page 14 of 19

CY25811/12/14 Package Drawing and Dimensions (continued) Figure 6. 8-pin TSSOP (4.40 mm Body) Z08.173/ZZ08.173 Package Outline, 51-85093 51-85093 *E Document Number: 38-07112 Rev. *N Page 15 of 19

CY25811/12/14 Acronyms Document Conventions Units of Measure Acronym Description CD-ROM compact disc, read only memory Symbol Unit of Measure DVD digital versatile/video disc °C degree Celsius EMI Electromagnetic Interference dB decibel ESD electrostatic discharge MHz megahertz FM frequency modulation F microfarad mA milliampere LAN local area network mm millimeter LCD liquid crystal display ms millisecond PLL phase locked loop mW milliwatt SOIC small outline integrated circuit ns nanosecond SSC spread spectrum clock % percent SSCG spread spectrum clock generator pF picofarad TSSOP thin shrink small outline package ps picosecond VCD video compact disc V volt VCO voltage controlled oscillator WAN wide area network Document Number: 38-07112 Rev. *N Page 16 of 19

CY25811/12/14 Document History Page Document Title: CY25811/12/14, Spread Spectrum Clock Generator Document Number: 38-07112 Orig. of Submission Revision ECN Description of Change Change Date ** 107516 NDP 06/14/02 Converted from IMI to Cypress *A 108002 NDP 06/29/02 Deleted Junction Temp. in Absolute Maximum Ratings *B 121578 RGL 01/29/03 Converted from Word to FrameMaker Added 8-pin TSSOP package in Commercial Temp. only Added an Industrial Temperature Range to all existing 8-pin SOIC packages *C 125550 RGL 05/14/03 Changed IDD values from 19.6/22/27.2 to 25/30/35 in Commercial Grade DC Specs table Changed IDD values from 24/26.5/33 to 26/32/37 in Industrial grade DC Specs table Changed T values from 675/260 to 800/450 in Commercial grade AC CCJ1/2 Specs table Changed T value from 350 to 650 in Industrial grade AC Specs table CCJ1 *D 131941 RGL 12/24/03 Removed automotive in the Applications section Changed the Output Clock Duty Cycle (T ) from min. 45 and max. 55 to DCOUT 40 and 60% respectively for both industrial and commercial grade Changed the min. Input Low Voltage (V ) from 0.15V to 0.13V IL DD DD Removed preliminary from the industrial AC/DC Electrical Specifications table *E 231057 RGL See ECN Added Pb Free Devices *F 1499165 KVM See ECN Updated Ordering Information table Corrected jitter values in features section on page 1 Changed:VDD from ±5% to ±10%, CIN1 min from 6 to 3.5 pF, CIN2 min from 3.5 to 2.8 pF, TF1 min from 2 to 1.6 ns, and TF2 min from 1.0 to 0.8 ns. Commercial grade: IDD1 max from 25 to 28 mA, IDD2 max from 30 to 33 mA, IDD3 max from 35 to 40 mA, TCCJ2 from 450 to 480 ps, TCCJ4 from 380 to 450 ps, and TCCJ5 from 380 to 550 ps Industrial grade: IDD1 max from 26 to 28 mA, IDD2 max from 32 to 33 mA, IDD3 max from 37 to 41 mA, TCCJ2 from 400 to 630 ps, and TCCJ3 from 400 to 520 ps *G 2592288 CXQ / 10/23/08 Removed Pb package devices from Ordering Table PYRS *H 2761988 CXQ 09/10/09 Removed reference to non-existent “Automotive” version. Fixed typo in DC spec table for VDD from min of 3.97 to 2.97. Fixed typo for PLL Lock time conditions. Removed CY25812SXI, CY25812SXIT, CY25814ZXC, and CY25814ZXCT from Ordering Information. *I 2887509 CXQ 03/04/2010 Updated MSL value in Absolute Maximum Conditions Added Contents Updated 8-pin SOIC and 8-pin TSSOP package drawings. Updated URLs in Sales, Solutions, and Legal Information *J 3339686 PURU 08/08/2011 Added Ordering Code Definitions. Updated Package Drawing and Dimensions. Added Acronyms and Units of Measure. Updated to new template. *K 4499792 TAVA 09/11/2014 Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *E to *F. spec 51-85093 – Changed revision from *C to *D. Updated to new template. Completing Sunset Review. Document Number: 38-07112 Rev. *N Page 17 of 19

CY25811/12/14 Document History Page (continued) Document Title: CY25811/12/14, Spread Spectrum Clock Generator Document Number: 38-07112 Orig. of Submission Revision ECN Description of Change Change Date *L 4587350 TAVA 12/05/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Package Drawing and Dimensions: spec 51-85093 – Changed revision from *D to *E. *M 5279207 PSR 05/26/2016 Added Thermal Resistance. Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *F to *H. Updated to new template. *N 5747567 PSR 05/24/2017 Added the pin type column in Pin Definitions. Corrected unit for the V parameter. IN Updated the Cypress logo, copyright information, Sales, Solutions, and Legal Information based on the new template. Document Number: 38-07112 Rev. *N Page 18 of 19

CY25811/12/14 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions ARM® Cortex® Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Forums | WICED IOT Forums | Projects | Video | Blogs | Interface cypress.com/interface Training | Components Internet of Things cypress.com/iot Technical Support Memory cypress.com/memory cypress.com/support Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless © Cypress Semiconductor Corporation, 2001-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, WICED, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-07112 Rev. *N Revised May 24, 2017 Page 19 of 19

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: C ypress Semiconductor: CY25811SXC CY25811SXCT CY25811SXI CY25811SXIT CY25812SXC CY25812SXCT CY25812ZXC CY25812ZXCT CY25814SXC CY25814SXCT CY25814SXI CY25814SXIT