CY25568 Spread Spectrum Clock Generator Spread Spectrum Clock Generator Features ■LCD panels and monitors ■Digital copiers ■4 to 32 MHz Input frequency range ■PDAs ■4 to 128 MHz Output frequency range ■Automotive ■accepts clock, crystal and resonator Inputs ■CD-ROM, VCD and DVD ■1x, 2x and 4x frequency multiplication ■Networking, LAN/WAN ■Non-modulated reference frequency output ■Scanners ■Center and down spread modulation ■Modems ■Low power dissipation ❐3.3 V = 52 mW-typ at 6 MHz ■Embedded digital systems ❐3.3 V = 60 mW-typ at 12 MHz Benefits ❐3.3 V = 72 mW-typ at 24 MHz ■Power-down mode ■Peak EMI reduction by 8 to 16dB ■Low cycle-to cycle jitter ■Fast time to market ❐8 MHz = 195 ps-typ ■Cost reduction ❐16 MHz = 175 ps-typ ❐32 MHz = 100 ps-typ Functional Description ■Available in 16-pin (150-mil.) SOIC package For a complete list of related documentation, click here. Applications ■Printers and MFPs Logic Block Diagram 300K 7 REFOUT REFERENCE XIN 1 PD and CP LF DIVIDER 8pF XOUT 16 8pF MODULATION VCO VCO CONTROL COUNTER VDD 13 6 SSCLK1 VDD 12 INPUT DIVIDER and 9 SSCLK2 DECODER LOGIC MUX VSS 3 8 SSCLK3 VSS 2 11 4 5 1 1 1 5 4 0 FRSEL S1 SO D1 DO PD# CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 38-07111 Rev. *H Revised December 1, 2017

CY25568 Contents Pin Configuration .............................................................3 SSCG Profiles ...........................................................10 Pin Definitions ..................................................................3 Application Schematic ...................................................11 Functional Overview ........................................................3 Ordering Information ......................................................11 Absolute Maximum Ratings ............................................4 Ordering Code Definitions .........................................11 DC Electrical Characteristics ..........................................4 Package Diagram ............................................................12 Thermal Resistance ..........................................................4 Acronyms ........................................................................13 Timing Electrical Characteristics ....................................5 Document Conventions .................................................13 Input Frequency Range and Selection ...........................5 Units of Measure .......................................................13 Output Clocks ..............................................................6 Document History Page .................................................14 REFOUT ......................................................................6 Sales, Solutions, and Legal Information ......................15 SSCLK1, 2 and 3 .........................................................6 Worldwide Sales and Design Support .......................15 Spread% Selection ...........................................................7 Products ....................................................................15 3-Level Digital Inputs ...................................................7 PSoC® Solutions .......................................................15 Power-down (PD#) ......................................................8 Cypress Developer Community .................................15 Modulation Rate ..........................................................8 Technical Support .....................................................15 Characteristic Curves ......................................................9 Document Number: 38-07111 Rev. *H Page 2 of 15

CY25568 Pin Configuration Figure 1. 16-pin SOIC pinout CY25568 XIN/CLKIN 1 16 XOUT VSS 2 15 D1 VSS 3 14 D0 S1 4 CY25568 13 VDD S0 5 12 VDD SSCLK1 6 11 FRSEL REFOUT 7 10 PD# SSCK3 8 9 SSCLK2 Pin Definitions Pin Function Description 1 Xin/CLK Clock, crystal or ceramic resonator input pin 2 V Power supply ground. SS 3 V Power supply ground. SS 4 S1 Digital Spread% control pin 3-Level input (H-M-L). Default = M. 5 S0 Digital Spread% control pin 3-Level input (H-M-L). Default = M. 6 SSCLK1 Output clock. Refer to Table 2 on page 6 for frequency programmability. 7 REFOUT Reference clock output. The same frequency as Xin/CLK input. 8 SSCLK3 Output clock. Refer to Table 2 on page 6 for frequency programmability. 9 SSCLK2 Output clock. Refer to Table 2 on page 6 for frequency programmability. 10 PD# Power-down control Internally pulled to V , Default = High. DD 11 FRSEL Input frequency range selection digital control input 3-Level input (H-M-L). Default = M. 12 V Positive power supply. DD 13 V Positive power supply. DD 14 D0 3-Level (H-M-L) Digital output clock scaling control. Refer to Table 2 on page 6. Default = M. 15 D1 3-Level (H-M-L) Digital output clock scaling control. Refer to Table 2 on page 6. Default = M. 16 XOUT Crystal or ceramic resonator output pin Functional Overview the input frequency with spread spectrum. A separate non-modulated reference clock is also provided. The Cypress CY25568 is a spread spectrum clock generator The use of 2x or 4x frequency multiplication eliminates the need (SSCG) IC used for the purpose of reducing electro magnetic for higher order crystals and allows the user to generate up to interference (EMI) found in today's high-speed digital electronic 128 MHz spread spectrum clock (SSC) by using only first order systems. crystals. This reduces the cost while improving the system clock The CY25568 uses a Cypress proprietary phase-locked loop accuracy, performance and complexity. (PLL) and spread spectrum clock (SSC) technology to The center spread or down spread frequency modulation can be synthesize and modulate the frequency of the digital clock. By selected by the user based on 4 discrete values of Spread% for frequency modulating the clock, the measured EMI at the each spread mode with the option of a non-spread mode for fundamental and harmonic frequencies is greatly reduced. system test and verification purposes. This reduction in radiated energy can significantly reduce the The CY25568 is available in a 16-pin SOIC (150-mil.) package cost of complying with regulatory agency requirements and with a commercial operating temperature range of 0 to 70 C. improve time to market without degrading system performance. Contact Cypress for availability of –25 to +85 C industrial The CY25568 input frequency range is 4 to 32 MHz and accepts temperature range operation. Refer to CY25811/12/14 products clock, crystal, and ceramic resonator inputs. The output clocks for 8-pin SOIC package versions of the CY25568. can be programmed to produce 1x, 2x, and 4x multiplication of Document Number: 38-07111 Rev. *H Page 3 of 15

CY25568 Absolute Maximum Ratings Input voltage relative to V : .............................V + 0.3 V DD DD Input voltage relative to VSS: .............................V – 0.3 V Exceeding maximum ratings [1] may shorten the useful life of the SS device. User guidelines are not tested. Operating temperature: .........................................0 to 70C Supply voltage (V ): .................................................+5.5 V storage Temperature: ..............................–65 C to +150C DD Note: Operation at any Absolute Maximum Rating is not implied. DC Electrical Characteristics Test Conditions: V = 3.3 V, T = 25 °C, unless otherwise noted DD Symbol Parameter Min Typ Max Unit Conditions VDD Power supply range 2.90 3.3 3.60 V VINH Input high voltage 0.85 × V V V V S0,S1,D0,D1 and FRSEL Inputs DD DD DD VINM Input middle voltage 0.40 × V 0.50 × V 0.60 × V V S0,S1,D0,D1 and FRSEL Inputs DD DD DD VINL Input low voltage 0.0 0.0 0.15 × V V S0,S1,D0,D1 and FRSEL Inputs DD VINH1 Input high voltage 2.0 – – V PD# input only VINL1 Input low voltage – – 0.8 V PD# input only VOH1 Output high voltage 2.4 – – V IOH = 4 mA, all output clocks VOH2 Output high voltage 2.0 – – V IOH = 6 mA, all output clocks VOL1 Output low voltage – – 0.4 V IOL = 4 mA, all output clocks VOL2 Output low voltage – – 1.2 V IOL = 10 mA, all output clocks Cin1 Input capacitance 6.0 7.5 9.0 pF Xin (Pin 1) and Xout (Pin 16) Cin2 Input capacitance 3.5 4.5 6.0 pF All digital inputs IDD1 Power supply current – 13.0 16.0 mA Fin = 4 MHz, no load (refer to Figure 4 on page 9) IDD2 Power supply current – 28.0 32.0 mA Fin = 32 MHz, no load (refer to Figure 4 on page 9) IDD3 Power supply current – 300 400 µA PD# = GND Thermal Resistance Parameter [2] Description Test Conditions 16-pin SOIC Unit θ Thermal resistance Test conditions follow standard test methods and 115 °C/W JA (junction to ambient) procedures for measuring thermal impedance, in accordance with EIA/JESD51. θ Thermal resistance 45 °C/W JC (junction to case) Notes 1. Single Power Supply: The voltage on any input or IO pin cannot exceed the power pin during power-up. 2. These parameters are guaranteed by design and are not tested. Document Number: 38-07111 Rev. *H Page 4 of 15

CY25568 Timing Electrical Characteristics Test Conditions: V = 3.3 V, T = 25 °C, CL = 15 pF. Rise/Fall time at 0.4 and 2.4 V, duty cycle at 1.5 V DD Symbol Parameter Min Typ Max Unit Conditions ICLKFR Input frequency range 4 32 MHz Clock, crystal or ceramic resonator input trise1 Clock rise time 2.4 3.2 4.0 ns SSCLK1, 2, and 3, all cases when 1x or 2x scaling selected, when 4x if FRSEL = 1 or 0 tfall1 Clock fall time 2.4 3.2 4.0 ns SSCLK1,2, and 3, all cases when 1x or 2x scaling selected, when 4x if FRSEL= 1 or 0 trise2 Clock rise time 1.2 1.6 2.0 ns SSCLK2, and 3, only when 4x scaling is selected and FRSEL = M tfall2 Clock fall time 1.2 1.6 2.0 ns SSCLK2, and 3, only when 4x scaling is selected and FRSEL = M trise3 Clock rise time 2.4 3.2 4.0 ns REFOUT only tfall3 Clock fall time 2.4 3.2 4.0 ns REFOUT only CDCin Input clock duty cycle 20 50 80 % XIN/CLK (Pin 1) CDCout Output clock duty cycle 45 50 55 % SSCLK1, 2 and 3 CCJ1 Cycle-to-cycle jitter - 195 260 ps Fin = 8 MHz (refer to Figure 4 on page 9) CCJ2 Cycle-to-cycle jitter - 170 225 ps Fin = 16 MHz (refer to Figure 4 on page 9) CCJ3 Cycle-to-cycle jitter - 100 150 ps Fin = 32 MHz (refer to Figure 4A) Input Frequency Range and Selection The CY25568 input frequency range is 4 to 32 MHz. This range is divided into 3 segments and controlled by 3-Level FRSEL pin as given in Table1. Table 1. Input Frequency Selection FRSEL INPUT FREQUENCY RANGE 0 4.0 to 8.0 MHz 1 8.0 to 16.0 MHz M 16.0 to 32.0 MHz Document Number: 38-07111 Rev. *H Page 5 of 15

CY25568 Output Clocks The CY25568 provides 4 separate output clocks, REFOUT, SSCLK1, SSCLK2 and SSCLK3, for use in a wide variety of applications.Each clock output is described in detail. REFOUT REFOUT is a 3.3 volt CMOS level non-modulated copy of the clock at XIN/CLKIN. SSCLK1, 2 and 3 SSCLK1, SSCLK2 and SSCLK3 are Spread Spectrum clock outputs used for the purpose of reducing EMI in digital systems. Each clock can drive separate nets with a capacitive load of up to 20 pF. The frequency function of these clock outputs are selected by using 3-Level D0 and D1 digital inputs and are given in Table2. Table 2. Output Clocks Function Selection D0 D1 REFOUT SSCLK1 SSCLK2 SSCLK3 0 0 REF REF 1x 1x 0 M REF 1x 2x 2x 0 1 REF REF 2x 2x M 0 REF REF 1x 2x M M REF REF REF REF M 1 REF REF 2x 4x 1 0 REF REF 4x 4x 1 M REF 1x 2x 4x 1 1 REF 1x 2x 4x REF is the same non-modulated frequency as the input clock. 1x, 2x, or 4x are modulated and multiplied (in the case of 2x and 4x) frequency of the input clock. Document Number: 38-07111 Rev. *H Page 6 of 15

CY25568 Spread% Selection The CY25568 provides Center-Spread, Down-Spread and No-Spread functions. These functions and the amount of Spread% are selected by using 3-Level S0 and S1 digital inputs and are given in Table3. Table 3. Spread% Selection XIN S1=0 S1=0 S1=0 S1=M S1=1 S1=1 S1=M S1=1 S1=M FRSEL (MHz) S0=0 S0=M S0=1 S0=0 S0=1 S0=0 S0=1 S0=M S0=M CENTER CENTER CENTER CENTER DOWN DOWN DOWN DOWN NO (%) (%) (%) (%) (%) (%) (%) (%) SPREAD 4-5 0 +/–1.4 +/–1.2 +/–0.6 +/–0.5 –3.0 –2.2 –1.9 –0.7 0 5-6 0 +/–1.3 +/–1.1 +/–0.5 +/–0.4 –2.7 –1.9 –.7 –0.6 0 6-7 0 +/–1.2 +/–0.9 +/–0.5 +/–0.4 –2.5 –1.8 –1.5 –0.6 0 7-8 0 +/–1.1 +/–0.9 +/–0.4 +/–0.3 –2.3 –1.7 –1.4 –0.5 0 8-10 1 +/–1.4 +/–1.2 +/–0.6 +/–0.5 –3.0 –2.2 –1.9 –0.7 0 10-12 1 +/–1.3 +/–1.1 +/–0.5 +/–0.4 –2.7 –1.9 –1.7 –0.6 0 12-14 1 +/–1.2 +/–0.9 +/–0.5 +/–0.4 –2.5 –1.8 –1.5 –0.6 0 14-16 1 +/–1.1 +/–0.9 +/–0.4 +/–0.3 –2.3 –1.7 –1.4 –0.5 0 16-20 M +/–1.4 +/–1.2 +/–0.6 +/–0.5 –3.0 –2.2 –1.9 –0.7 0 20-24 M +/–1.3 +/–1.1 +/–0.5 +/–0.4 –2.7 –1.9 –1.7 –0.6 0 24-28 M +/–1.2 +/–0.9 +/–0.5 +/–0.4 –2.5 –1.8 –1.5 –0.6 0 28-32 M +/–1.1 +/–0.9 +/–0.4 +/–0.3 –2.3 –1.7 –1.4 –0.5 0 3-Level Digital Inputs Figure 2. 3-Level Logic LOGIC LOGIC LOGIC LOW (0) MIDDLE (M) HIGH (H) VDD DO, D1, S0, S1 D0, D1, S0, S1 D0, D1, S0, S1 and and and FRSEL FRSEL FRSEL to GND UNCONNECTED to VDD GND S0, S1, D0, D1, and FRSEL digital inputs of the CY25568 are designed to sense 3 different logic levels designated as High - 1, Low- 0 and Middle - M. With this 3-Level digital input logic, the CY25568 is able to detect 9 different logic states in the case of (S0, S1) and (D0, D1) logic pairs and 3 different logic states in the case of FRSEL. S0, S1, D0, D1, and FRSEL pins include an on chip 20K (10K /10K) resistor divider. No external application resistors are needed to implement the 3-Level logic levels as shown in the following: Logic State 0 = 3-Level logic pin connected to GND. Logic State M = 3-Level logic pin left floating (no connection). Logic State 1 = 3-Level logic pin connected to VDD. Figure2 illustrates how to implement 3-Level Logic. Document Number: 38-07111 Rev. *H Page 7 of 15

CY25568 Power-down (PD#) CY25568 includes a Power-down (PD#, Pin 10) function. This input uses standard 2-Level CMOS logic and is internally pulled up to VDD (HIGH). Connect this pin to GND if power is to be turned off. Modulation Rate Spread Spectrum Clock Generators use frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies. The time required to transition from fmin to fmax and back to fmin is the period of the Modulation Rate, Tmod. The Modulation Rate of SSCG clocks are generally referred to in terms of frequency or fmod = 1/Tmod. The input clock frequency, fin, and the internal divider determine the modulation rate. In the case of CY25568, the (spread spectrum) modulation rate is given by the following formula: fmod = fin/DR Where; fmod is the modulation rate, fin is the Input Frequency and DR is the divider ratio as given in Table4. Notice that Input frequency range is set by FRSEL. Table 4. Modulation Rate FRSEL INPUT FREQUENCY RANGE (MHz) DIVIDER RATIO (DR) 0 4 to 8 128 1 8 to 16 256 M 16 to 32 512 Document Number: 38-07111 Rev. *H Page 8 of 15

CY25568 Characteristic Curves The following curves demonstrate the characteristic behavior of the CY25568 when tested over a number of environmental and application specific parameters. These are typical performance curves and are not meant to replace any parameter specified in tables DC Electrical Characteristics on page 4 and Timing Electrical Characteristics on page 5. Figure 3. Jitter vs. Input Frequency (No Load) Figure 5. IDD vs. Frequency (FRSEL = 0, 1, M) 600 30 28 500 FRSEL = M 26 16 - 32 MHz 24 400 CCJ (ps)300 IDD (mA) 122802 F8 R- S16E LM =H z1 200 16 FRSEL = 0 100 14 4 - 8 MHz 12 0 10 4 8 12 16 20 24 28 32 4 4.5 5 5.5 6 6.5 7 7.5 8 Input Frequency (MHz) Frequency (MHz) no load, normalized to FRSEL = 0, (4 - 8 MHz). Figure 4. Bandwidth% vs. Temperature Figure 6. Bandwidth% vs. VDD 2.75 3 6.0 MHz 2.9 32.0 MHz 2.8 2.5 2.7 2.6 4.0 MHz %)2.5 W %2.25 W (2.4 B B 2.3 2.2 8.0 MHz 2 2.1 2 1.9 1.75 1.8 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Temp (C) VDD (volts) Document Number: 38-07111 Rev. *H Page 9 of 15

CY25568 SSCG Profiles The CY25568 uses a non-linear frequency profile as shown in Figure7. The use of Cypress proprietary “optimized” frequency profile maintains flat energy distribution over the fundamental and higher order harmonics. This results in additional EMI reduction in electronic systems. Figure 7. Spread Spectrum Profiles (Frequency versus Time)   Xin = 6.0 MHz SSCLK1 = 6.0 MHz Xin = 24.0 MHz SSCLK1 = 24.0 MHz S1, S0 = 0 D1, D0 = 1 S1, S0 = 0 D1, D0 = 1 Xin = 12.0 MHz SSCLK1 = 48.0 MHz Xin = 24.0 MHz SSCLK1 = 96.0 MHz S1, S0 = 0 D1, D0 = 1 S1, S0 = 0 D1, D0 = 1 Document Number: 38-07111 Rev. *H Page 10 of 15

CY25568 Application Schematic Figure 8. Application Schematic Ordering Information Part No. Package Operating Temperature Range Pb-free CY25568SXC 16-pin SOIC Commercial, 0 °C to 70 °C CY25568SXCT 16-pin SOIC – Tape and Reel Commercial, 0 °C to 70 °C Ordering Code Definitions CY 25568 S X C T T = Tape and Reel; blank = Tube Temperature Range: C = Commercial Pb-free Package: S = 16-pin SOIC Base Part Number Company ID: CY = Cypress Document Number: 38-07111 Rev. *H Page 11 of 15

CY25568 Package Diagram Figure 9. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068 51-85068 *E Document Number: 38-07111 Rev. *H Page 12 of 15

CY25568 Acronyms Document Conventions Acronym Description Units of Measure DVD digital versatile/video disc Symbol Unit of Measure EMI Electromagnetic Interference % percent I/O input/output °C degree Celsius LAN local area network dB decibel LCD liquid crystal display MHz megahertz PLL phase-locked loop mA milliampere SOIC small-outline integrated circuit mm millimeter SSC spread spectrum clock ms millisecond SSCG spread spectrum clock generator mW milliwatt VCD video compact disc ns nanosecond WAN wide area network  ohm pF picofarad ps picosecond V volt W watt Document Number: 38-07111 Rev. *H Page 13 of 15

CY25568 Document History Page Document Title: CY25568, Spread Spectrum Clock Generator Document Number: 38-07111 Orig. of Submission Rev. ECN Description of Change Change Date ** 107515 NDP 06/14/2001 Convert from IMI to Cypress. *A 108182 NDP 07/03/2001 Updated Absolute Maximum Ratings: Removed “Junction Temperature (10-sec. soldering)”. *B 122682 RBI 12/21/2002 Updated Absolute Maximum Ratings: Added Note 1 and referred the same note in maximum ratings. *C 2658020 KVM / 02/16/2009 Updated Ordering Information: PYRS Updated part numbers. Updated Package Diagram: Deleted the table “16 Pin SOIC Outline Dimensions (150 mil)”. Updated to new template. *D 3319217 BASH 07/08/2011 Added Ordering Code Definitions under Ordering Information. Updated Package Diagram. Added Acronyms and Units of Measure. Updated to new template. *E 4468746 TAVA 08/07/2014 Updated Package Diagram: spec 51-85068 – Changed revision from *C to *E. Updated to new template. Completing Sunset Review. *F 4586478 TAVA 12/03/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *G 5281153 PSR 05/23/2016 Added Thermal Resistance. Updated to new template. Completing Sunset Review. *H 5981734 AESATP12 12/01/2017 Updated logo and copyright. Document Number: 38-07111 Rev. *H Page 14 of 15

CY25568 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions ARM® Cortex® Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Forums | WICED IOT Forums | Projects | Video | Blogs | Interface cypress.com/interface Training | Components Internet of Things cypress.com/iot Technical Support Memory cypress.com/memory cypress.com/support Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless © Cypress Semiconductor Corporation, 2001-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-07111 Rev. *H Revised December 1, 2017 Page 15 of 15

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