CY2305C CY2309C 3.3 V Zero Delay Clock Buffer 3.3 V Zero Delay Clock Buffer Features 100MHz–133 MHz frequencies and have higher drive than the -1 devices. All parts have on-chip phase locked loops (PLLs) ■10 MHz to 100–133 MHz operating range which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. ■Zero input and output propagation delay The CY2309C has two banks of four outputs each that are ■Multiple low skew outputs controlled by the select inputs as shown in the Select Input ■One input drives five outputs (CY2305C) Decoding on page 6. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the outputs ■One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C) by the select inputs for chip and system testing purposes. ■50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz) The CY2305C and CY2309C PLLs enter a power down mode ■Test mode to bypass phase locked loop (PLL) (CY2309C) only, when there are no rising edges on the REF input. In this state, see Select Input Decoding on page 6 the outputs are three-stated and the PLL is turned off. This ■Available in space saving 16-pin 150 Mil small outline results in less than 12.0 A of current draw for commercial integrated circuit (SOIC) or 4.4 mm thin shrunk small outline temperature devices and 25.0 A for industrial and automotive-A package (TSSOP) packages (CY2309C), and 8-pin, 150 Mil temperature parts. The CY2309C PLL shuts down in one SOIC package (CY2305C) additional case as shown in the Select Input Decoding on page 6. ■3.3 V operation In the special case when S2:S1 is 1:0, the PLL is bypassed and REF is output from DC to the maximum allowable frequency. The ■Commercial, industrial and automotive-A flows available part behaves as a non-zero delay buffer in this mode and the Functional Description outputs are not three-stated. The CY2305C or CY2309C is available in two or three different The CY2305C and CY2309C are die replacement parts for configurations as shown in the Ordering Information on page 15. CY2305 and CY2309. The CY2305C-1 or CY2309C-1 is the base part. The CY2305-1H The CY2309C is a low-cost 3.3 V zero delay buffer designed to or CY2309-1H is the high drive version of the -1. Its rise and fall distribute high speed clocks and is available in a 16-pin SOIC or times are much faster than the -1. TSSOP package. The CY2305C is an 8-pin version of the For a complete list of related documentation, click here. CY2309C. It accepts one reference input and drives out five low skew clocks. The -1H versions of each device operate up to Logic Block Diagram – CY2305C PLL CLKOUT REF CLK1 CLK2 CLK3 CLK4 CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 38-07672 Rev. *Q Revised April 27, 2017

CY2305C CY2309C Logic Block Diagram – CY2309C PLL MUX CLKOUT REF CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 S2 Select Input CLKB2 Decoding S1 CLKB3 CLKB4 Document Number: 38-07672 Rev. *Q Page 2 of 22

CY2305C CY2309C Contents Pinouts ..............................................................................4 Switching Waveforms ....................................................14 Pin Definitions ..................................................................5 Ordering Information ......................................................15 Pin Definitions ..................................................................5 Ordering Code Definitions .........................................16 Functional Overview ........................................................6 Package Diagrams ..........................................................17 Select Input Decoding .................................................6 Acronyms ........................................................................19 Zero Delay and Skew Control .....................................6 Document Conventions .................................................19 Absolute Maximum Conditions .......................................7 Units of Measure .......................................................19 Operating Conditions .......................................................7 Document History Page .................................................20 Operating Conditions .......................................................7 Sales, Solutions, and Legal Information ......................22 Electrical Characteristics .................................................8 Worldwide Sales and Design Support .......................22 Electrical Characteristics .................................................8 Products ....................................................................22 Test Circuits ......................................................................9 PSoC®Solutions .......................................................22 Thermal Resistance ..........................................................9 Cypress Developer Community .................................22 Switching Characteristics ..............................................10 Technical Support .....................................................22 Switching Characteristics ..............................................11 Switching Characteristics ..............................................12 Switching characteristics ..............................................13 Document Number: 38-07672 Rev. *Q Page 3 of 22

CY2305C CY2309C Pinouts Figure 1. 8-pin SOIC pinout (Top View) CY2305C REF 1 8 CLKOUT CLK2 2 7 CLK4 CY2305C CLK1 3 6 VDD GND 4 5 CLK3 Figure 2. 16-pin SOIC / TSSOP pinout (Top View) CY2309C REF 1 16 CLKOUT CLKA1 2 15 CLKA4 CY2309C CLKA2 3 14 CLKA3 VDD 4 13 VDD GND 5 12 GND CLKB1 6 11 CLKB4 CLKB2 7 10 CLKB3 S2 8 9 S1 Document Number: 38-07672 Rev. *Q Page 4 of 22

CY2305C CY2309C Pin Definitions 8-pin SOIC Pin Signal Description 1 REF [1] Input reference frequency 2 CLK2 [2] Buffered clock output 3 CLK1 [2] Buffered clock output 4 GND Ground 5 CLK3 [2] Buffered clock output 6 V 3.3 V supply DD 7 CLK4 [2] Buffered clock output 8 CLKOUT [2] Buffered clock output, internal feedback on this pin Pin Definitions 16-pin SOIC / TSSOP Pin Signal Description 1 REF [1] Input reference frequency 2 CLKA1 [2] Buffered clock output, Bank A 3 CLKA2 [2] Buffered clock output, Bank A 4 V 3.3 V supply DD 5 GND Ground 6 CLKB1 [2] Buffered clock output, Bank B 7 CLKB2 [2] Buffered clock output, Bank B 8 S2 [3] Select input, bit 2 9 S1 [3] Select input, bit 1 10 CLKB3 [2] Buffered clock output, Bank B 11 CLKB4 [2] Buffered clock output, Bank B 12 GND Ground 13 V 3.3 V supply DD 14 CLKA3 [2] Buffered clock output, Bank A 15 CLKA4 [2] Buffered clock output, Bank A 16 CLKOUT [2] Buffered output, internal feedback on this pin Notes 1. Weak pull down. 2. Weak pull down on all outputs. 3. Weak pull ups on these inputs. Document Number: 38-07672 Rev. *Q Page 5 of 22

CY2305C CY2309C Functional Overview Select Input Decoding For CY2309C S2 S1 CLOCK A1–A4 CLOCK B1–B4 CLKOUT [4] Output Source PLL Shutdown 0 0 Three state Three state Driven PLL N 0 1 Driven Three state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N Figure 3. REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB pins Zero Delay and Skew Control For zero output to output skew, all outputs must be loaded equally. All outputs must be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the Even if CLKOUT is not used, it must have a capacitive load, internal feedback to the PLL, its relative loading can adjust the equal to that on other outputs, for obtaining zero input-output input or output delay. delay. If input to output delay adjustments are required, use Figure 3 to calculate loading differences between the CLKOUT For applications requiring zero input or output delay, all outputs pin and other outputs. including CLKOUT are equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs for obtaining zero input or output delay. Note 4. This output is driven and has an internal feedback for the PLL. The load on this output is adjusted to change the skew between the reference and output. Document Number: 38-07672 Rev. *Q Page 6 of 22

CY2305C CY2309C Absolute Maximum Conditions Storage temperature ................................–65 °C to +150 °C Junction temperature .................................................150 °C Supply voltage to ground potential ..............–0.5 V to +4.6 V Static discharge voltage DC input voltage (Except REF) ..........–0.5 V to VDD + 0.5 V (per MIL-STD-883, Method 3015) .........................> 2,000 V DC input voltage REF .........................–0.5 V to V + 0.5 V DD Operating Conditions Operating Conditions Table for CY2305CSXC-XX and CY2309CSXC-XX Commercial Temperature devices. Parameter Description Min Max Unit V Supply voltage 3.0 3.6 V DD T Operating temperature (ambient temperature) 0 70 °C A C Load capacitance, below 100 MHz – 30 pF L C Load capacitance, from 100 MHz to 133 MHz – 10 pF L C Input capacitance – 7 pF IN t Power-up time for all V s to reach minimum specified voltage (power ramps are 0.05 50 ms PU DD monotonic) Operating Conditions Operating Conditions Table for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX Industrial / Automotive-A Temperature devices. Parameter Description Min Max Unit V Supply voltage 3.0 3.6 V DD T Operating temperature (ambient temperature) –40 85 °C A C Load capacitance, below 100 MHz – 30 pF L C Load capacitance, from 100 MHz to 133 MHz – 10 pF L C Input capacitance – 7 pF IN t Power-up time for all V s to reach minimum specified voltage (power ramps are 0.05 50 ms PU DD monotonic) Document Number: 38-07672 Rev. *Q Page 7 of 22

CY2305C CY2309C Electrical Characteristics Electrical Characteristics Table for CY2305CSXC-XX and CY2309CSXC-XX Commercial Temperature devices. Parameter Description Test Conditions Min Max Unit V Input LOW voltage [5] – 0.8 V IL V Input HIGH voltage [5] 2.0 – V IH I Input LOW current V = 0 V – 50 A IL IN I Input HIGH current V = V – 100 A IH IN DD V Output LOW voltage [6] I = 8 mA (–1) – 0.4 V OL OL I = 12mA (–1H) OL V Output HIGH voltage [6] I = –8 mA (–1) 2.4 – V OH OH I = –12 mA (–1H) OH I (PD mode) Power-down supply current REF = 0 MHz – 12 A DD I Supply current Unloaded outputs at 66.67 MHz, SEL inputs at – 32 mA DD V DD Electrical Characteristics Electrical Characteristics Table for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX Industrial / Automotive-A Temperature devices. Parameter Description Test Conditions Min Max Unit V Input LOW voltage [5] – 0.8 V IL V Input HIGH voltage [5] 2.0 – V IH I Input LOW current V = 0 V – 50 A IL IN I Input HIGH current V = V – 100 A IH IN DD V Output LOW voltage [6] I = 8 mA (–1) – 0.4 V OL OL I = 12mA (–1H) OL V Output HIGH voltage [6] I = –8 mA (–1) 2.4 – V OH OH I = –12 mA (–1H) OH I (PD mode) Power-down supply current REF = 0 MHz – 25 A DD I Supply current Unloaded outputs at 66.67 MHz, SEL inputs at – 35 mA DD V DD Notes 5. REF input has a threshold voltage of VDD/2. 6. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document Number: 38-07672 Rev. *Q Page 8 of 22

CY2305C CY2309C Test Circuits Figure 4. Test Circuits Test Circuit # 1 Test Circuit # 2 VDD VDD 1 k CLK out 0.1 F 0.1 F OUTPUTS OUTPUTS 10 pF CLOAD 1 k VDD VDD 0.1 F GND GND 0.1 F GND GND For parameter t (output slew rate) on -1H devices 8 Thermal Resistance Parameter [7] Description Test Conditions 8-pin SOIC 16-pin SOIC 16-pin TSSOP Unit θ Thermal resistance Test conditions follow 145 121 111 °C/W JA (junction to ambient) standard test methods and procedures for θ Thermal resistance 62 53 26 °C/W JC measuring thermal (junction to case) impedance, in accordance with EIA/JESD51. Note 7. These parameters are guaranteed by design and are not tested. Document Number: 38-07672 Rev. *Q Page 9 of 22

CY2305C CY2309C Switching Characteristics Switching Characteristics Table for CY2305CSXC-1 and CY2309CSXC-1 Commercial Temperature devices. All parameters are specified with loaded outputs. Parameter Description Test Conditions Min Typ Max Unit t Output frequency 30 pF load 10 – 100 MHz 1 10 pF load 10 – 133.33 MHz t Output duty cycle [8] = t  t Measured at 1.4 V, F > 50 MHz 40 50 60 % DC 2 1 out Measured at 1.4 V, F  50 MHz 45 50 55 % out t Rise time [8] Measured between 0.8 V and 2.0 V – – 2.25 ns 3 t Fall time [8] Measured between 0.8 V and 2.0 V – – 2.25 ns 4 t Output-to-output skew [8] All outputs equally loaded – – 200 ps 5 t Delay, REF rising edge to Measured at V /2 – 0 ±350 ps 6A DD CLKOUT rising edge [8] t Delay, REF rising edge to Measured at V /2. Measured in 1 5 8.7 ns 6B DD CLKOUT rising edge [8] PLL Bypass mode, CY2309C device only. t Device-to-device skew [8] Measured at V /2 on the CLKOUT – 0 700 ps 7 DD pins of devices t Cycle-to-cycle jitter, peak [8] Measured at 66.67 MHz, loaded – 50 175 ps J outputs t PLL lock time [8] Stable power supply, valid clock – – 1.0 ms LOCK presented on REF pin Note 8. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document Number: 38-07672 Rev. *Q Page 10 of 22

CY2305C CY2309C Switching Characteristics Switching Characteristics Table for CY2305CSXC-1H and CY2309CSXC-1H Commercial Temperature devices. All parameters are specified with loaded outputs. Parameter Description Description Min Typ Max Unit t Output frequency 30 pF load 10 – 100 MHz 1 10 pF load 10 – 133.33 MHz tDC Output duty cycle [9] = t2  t1 Measured at 1.4 V, Fout > 50 MHz 40 50 60 % Measured at 1.4 V, F  50 MHz 45 50 55 % out t Rise time [9] Measured between 0.8 V and 2.0 V – – 1.5 ns 3 t Fall time [9] Measured between 0.8 V and 2.0 V – – 1.5 ns 4 t Output-to-output skew [9] All outputs equally loaded – – 200 ps 5 t Delay, REF rising edge to Measured at V /2 – 0 ±350 ps 6A DD CLKOUT rising edge [9] t Delay, REF rising edge to Measured at V /2. Measured in 1 5 8.7 ns 6B DD CLKOUT rising edge [9] PLL Bypass mode, CY2309C device only. t Device-to-device skew [9] Measured at V /2 on the CLKOUT – 0 700 ps 7 DD pins of devices t Output slew rate [9] Measured between 0.8 V and 2.0 V 1 – – V/ns 8 using Test circuit #2 t Cycle-to-cycle jitter, peak [9] Measured at 66.67 MHz, loaded – – 175 ps J outputs t PLL lock time [9] Stable power supply, valid clock – – 1.0 ms LOCK presented on REF pin Note 9. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document Number: 38-07672 Rev. *Q Page 11 of 22

CY2305C CY2309C Switching Characteristics Switching Characteristics Table for CY2305CSXI-1, CY2305CSXA-1, and CY2309CSXI-1 Industrial Temperature devices. All parameters are specified with loaded outputs. Parameter Description Test Conditions Min Typ Max Unit t Output frequency 30 pF load 10 – 100 MHz 1 10 pF load 10 – 133.33 MHz t Output duty cycle [10] = t  t Measured at 1.4 V, F > 50 MHz 40 50 60 % DC 2 1 out Measured at 1.4 V, F < 50 MHz 45 50 55 % out t Rise time [10] Measured between 0.8 V and 2.0 V – – 2.25 ns 3 t Fall time [10] Measured between 0.8 V and 2.0 V – – 2.25 ns 4 t Output-to-output skew [10] All outputs equally loaded – – 200 ps 5 t Delay, REF rising edge to Measured at V /2 – 0 ±350 ps 6A DD CLKOUT rising edge [10] t Delay, REF rising edge to Measured at V /2. Measured in 1 5 8.7 ns 6B DD CLKOUT rising edge [10] PLL Bypass mode, CY2309C device only. t Device-to-device skew [10] Measured at V /2 on the CLKOUT – 0 700 ps 7 DD pins of devices t Cycle-to-cycle jitter, peak [10] Measured at 66.67 MHz, loaded – 50 175 ps J outputs t PLL lock time [10] Stable power supply, valid clock – – 1.0 ms LOCK presented on REF pin Note 10.Parameter is guaranteed by design and characterization. Not 100% tested in production. Document Number: 38-07672 Rev. *Q Page 12 of 22

CY2305C CY2309C Switching characteristics Switching Characteristics Table for CY2305CSXI-1H, CY2305CSXA-1H and CY2309CSXI-1H Industrial / Automotive-A Temperature devices. All parameters are specified with loaded outputs. Parameter Description Description Min Typ Max Unit t Output frequency 30 pF load 10 – 100 MHz 1 10 pF load 10 – 133.33 MHz tDC Output duty cycle [11] = t2  t1 Measured at 1.4 V, Fout > 50 MHz 40 50 60 % Measured at 1.4 V, F < 50 MHz 45 50 55 % out t Rise time [11] Measured between 0.8 V and 2.0 V – – 1.5 ns 3 t Fall time [11] Measured between 0.8 V and 2.0 V – – 1.5 ns 4 t Output-to-output skew [11] All outputs equally loaded – – 200 ps 5 t Delay, REF rising edge to Measured at V /2 – 0 ±350 ps 6A DD CLKOUT rising edge [11] t Delay, REF rising edge to Measured at V /2. Measured in 1 5 8.7 ns 6B DD CLKOUT rising edge [11] PLL Bypass mode, CY2309C device only. t Device-to-device skew [11] Measured at V /2 on the CLKOUT – 0 700 ps 7 DD pins of devices t Output slew rate [11] Measured between 0.8 V and 2.0 V 1 – – V/ns 8 using Test circuit #2 t Cycle-to-cycle jitter, peak [11] Measured at 66.67 MHz, loaded – – 175 ps J outputs t PLL lock time [11] Stable power supply, valid clock – – 1.0 ms LOCK presented on REF pin Note 11.Parameter is guaranteed by design and characterization. Not 100% tested in production. Document Number: 38-07672 Rev. *Q Page 13 of 22

CY2305C CY2309C Switching Waveforms Figure 5. Duty Cycle Timing t1 t2 1.4 V 1.4 V 1.4 V Figure 6. All Outputs Rise/Fall Time 2.0 V 2.0 V 3.3 V OUTPUT 0.8 V 0.8 V 0 V t3 t4 Figure 7. Output-Output Skew 1.4 V OUTPUT 1.4 V OUTPUT t5 Figure 8. Input-Output Propagation Delay V /2 INPUT DD V /2 OUTPUT DD t6 Figure 9. Device-Device Skew V /2 CLKOUT, Device 1 DD V /2 CLKOUT, Device 2 DD t 7 Document Number: 38-07672 Rev. *Q Page 14 of 22

CY2305C CY2309C Ordering Information Ordering Code Package Type Operating Range Pb-free - CY2305C CY2305CSXC-1 8-pin SOIC (150 Mil) Commercial CY2305CSXC-1T 8-pin SOIC (150 Mil) – Tape and Reel Commercial CY2305CSXC-1H 8-pin SOIC (150 Mil) Commercial CY2305CSXC-1HT 8-pin SOIC (150 Mil) – Tape and Reel Commercial CY2305CSXI-1 8-pin SOIC (150 Mil) Industrial CY2305CSXI-1T 8-pin SOIC (150 Mil) – Tape and Reel Industrial CY2305CSXI-1H 8-pin SOIC (150 Mil) Industrial CY2305CSXI-1HT 8-pin SOIC (150 Mil) – Tape and Reel Industrial CY2305CSXA-1H 8-pin SOIC (150 Mil) Automotive-A CY2305CSXA-1HT 8-pin SOIC (150 Mil) – Tape and Reel Automotive-A Pb-free - CY2309C CY2309CSXC-1 16-pin SOIC (150 Mil) Commercial CY2309CSXC-1T 16-pin SOIC (150 Mil) – Tape and Reel Commercial CY2309CSXC-1H 16-pin SOIC (150 Mil) Commercial CY2309CSXC-1HT 16-pin SOIC (150 Mil) – Tape and Reel Commercial CY2309CSXI-1 16-pin SOIC (150 Mil) Industrial CY2309CSXI-1T 16-pin SOIC (150 Mil) – Tape and Reel Industrial CY2309CSXI-1H 16-pin SOIC (150 Mil) Industrial CY2309CSXI-1HT 16-pin SOIC (150 Mil) – Tape and Reel Industrial CY2309CZXC-1 16-pin TSSOP (4.4 mm) Commercial CY2309CZXC-1T 16-pin TSSOP (4.4 mm) – Tape and Reel Commercial CY2309CZXC-1H 16-pin TSSOP (4.4 mm) Commercial CY2309CZXC-1HT 16-pin TSSOP (4.4 mm) – Tape and Reel Commercial CY2309CZXI-1 16-pin TSSOP (4.4 mm) Industrial CY2309CZXI-1T 16-pin TSSOP (4.4 mm) – Tape and Reel Industrial CY2309CZXI-1H 16-pin TSSOP (4.4 mm) Industrial CY2309CZXI-1HT 16-pin TSSOP (4.4 mm) – Tape and Reel Industrial Document Number: 38-07672 Rev. *Q Page 15 of 22

CY2305C CY2309C Ordering Code Definitions CY 230XC X X X – 1X X X = blank or T blank = Tube; T = Tape and Reel Output Drive: 1X = 1 or 1H 1 = Standard Drive; 1H = High Drive Temperature Grade: X = C or I or A C = Commercial; I = Industrial; A = Automotive Pb-free Package Type: X = S or Z S = 8-pin SOIC or 16-pin SOIC; Z = 16-pin TSSOP Base Device Part Number: 230XC = 2305C or 2309C 2305C = 5-output zero delay buffer, rev C 2309C = 9-output zero delay buffer, rev C Company ID: CY = Cypress Document Number: 38-07672 Rev. *Q Page 16 of 22

CY2305C CY2309C Package Diagrams Figure 10. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066 51-85066 *H Document Number: 38-07672 Rev. *Q Page 17 of 22

CY2305C CY2309C Package Diagrams (continued) Figure 11. 16-pin SOIC (150 Mil) S16.15/SZ16.15 Package Outline, 51-85068 51-85068 *E Figure 12. 16-pin TSSOP (4.40 mm Body) Z16.173/ZZ16.173 Package Outline, 51-85091 51-85091 *E Document Number: 38-07672 Rev. *Q Page 18 of 22

CY2305C CY2309C Acronyms Document Conventions Acronym Description Units of Measure CMOS Complementary Metal Oxide Semiconductor Symbol Unit of Measure PLL Phase Locked Loop °C degree Celsius SOIC Small Outline Integrated Circuit kHz kilohertz TSSOP Thin Shrunk Small Outline Package MHz megahertz µA microampere mA milliampere ms millisecond ns nanosecond pF picofarad ps picosecond V volt Document Number: 38-07672 Rev. *Q Page 19 of 22

CY2305C CY2309C Document History Page Document Title: CY2305C/CY2309C, 3.3 V Zero Delay Clock Buffer Document Number: 38-07672 Orig. of Rev. ECN No. Issue Date Description of Change Change ** 224421 See ECN RGL New data sheet *A 268571 See ECN RGL Added bullet for 5 V tolerant inputs in the features *B 276453 See ECN RGL Minor Change: Moved one sentence from the features to the Functional Description *C 303063 See ECN RGL Updated data sheet as per characterization data *D 318315 See ECN RGL Data sheet rewrite *E 344815 See ECN RGL Minor Error: Corrected the header of all the AC/DC tables with the right part numbers. *F 1279889 See ECN KVM Changed title from “CY2305C/CY2309C‚ Low Cost 3.3 V Zero Delay Buffer” to “CY2305C/CY2309C, 3.3 V Zero Delay Clock Buffer”. Specified the VIL minimum value to -0.3 V Specified the VIH maximum value to VDD + 0.3 V Changed DC Input Voltage (REF) maximum value in Absolute Maximum section Removed references to 5 V tolerant inputs (pages 1 and 2) Removed Pentium compatibility reference Added CY2305C block diagram Added ‚peak to the jitter specifications Changed typical jitter from 75 ps to 50 ps for standard drive devices For standard drive devices, tightened rise/fall times from 2.5 ns to 2.25 ns Tightened cycle-to-cycle jitter from 200 ps to 175 ps Tightened output-to-output skew from 250 ps to 200 ps *G 1561504 See ECN KVM / NSI / Changed status from Preliminary to Final. AESA Added CY2305C Automotive-A grade devices Extended duty cycle specs to cover entire frequency range *H 2558537 08/27/08 KVM / AESA Updated Ordering Information: Added CY2305CSXA-1 and CY2305CSXA-1T parts under Pb-free CY2305C. *I 2901743 03/30/2010 VIVG Added Ordering Code Definitions under Ordering Information. Updated Package Diagrams. *J 3080990 11/10/2010 BASH Updated Pinouts: Updated Figure1 (Modified pin diagram). Added Acronyms and Units of Measure. Updated to new template. *K 3160535 02/03/2011 BASH Updated Electrical Characteristics: Removed minimum value of V parameter and maximum value of V IL IH parameter. Updated Electrical Characteristics: Removed minimum value of V parameter and maximum value of V IL IH parameter. Updated Ordering Information: Removed Prune parts CY2305CSXA-1 and CY2305CSXA-1T. *L 3822852 11/27/2012 PURU Updated Functional Overview: Updated Select Input Decoding (Added Figure3 only, no edits). Updated Zero Delay and Skew Control (Minor edits). Updated Package Diagrams: spec 51-85091 – Changed revision from *C to *D. spec 51-85068 – Changed revision from *C to *E. spec 51-85066 – Changed revision from *D to *E. Document Number: 38-07672 Rev. *Q Page 20 of 22

CY2305C CY2309C Document History Page (continued) Document Title: CY2305C/CY2309C, 3.3 V Zero Delay Clock Buffer Document Number: 38-07672 Orig. of Rev. ECN No. Issue Date Description of Change Change *M 4201564 11/25/2013 CINM Updated Package Diagrams: spec 51-85066 – Changed revision from *E to *F. Updated to new template. Completing Sunset Review. *N 4578443 11/25/2014 TAVA Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Package Diagrams. *O 5242528 04/15/2016 SDHK / PSR Updated Electrical Characteristics: Updated details in “Test Conditions” column corresponding to V and V OL OH parameters. Updated Electrical Characteristics: Updated details in “Test Conditions” column corresponding to V and V OL OH parameters. Added Thermal Resistance. Updated Package Diagrams: spec 51-85066 – Changed revision from *F to *H. Updated to new template. *P 5553658 12/14/2016 TAVA Updated to new template. Completing Sunset Review. *Q 5708829 04/27/2017 AESATMP7 Updated Cypress Logo and Copyright. Document Number: 38-07672 Rev. *Q Page 21 of 22

CY2305C CY2309C Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC®Solutions ARM® Cortex® Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP| PSoC 6 Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Forums | WICED IoT Forums | Projects | Video | Blogs | Interface cypress.com/interface Training | Components Internet of Things cypress.com/iot Technical Support Lighting & Power Control cypress.com/powerpsoc cypress.com/support Memory cypress.com/memory PSoC cypress.com/psoc Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless/RF cypress.com/wireless © Cypress Semiconductor Corporation, 2004-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-07672 Rev. *Q Revised April 27, 2017 Page 22 of 22