Product Sample & Technical Tools & Support & Folder Buy Documents Software Community CSD87588N SLPS384D–MARCH2013–REVISEDAPRIL2015 CSD87588N Synchronous Buck NexFET™ Power Block II 1 Features 3 Description • Half-BridgePowerBlock The CSD87588N NexFET™ power block II is a 1 highly-optimized design for synchronous buck • 90%SystemEfficiencyat20A applications offering high current and high efficiency • Upto25AOperation capability in a small 5 mm × 2.5 mm outline. • HighDensity –5mmx2.5mmLGAFootprint Optimized for 5 V gate drive applications, this product offers an efficient and flexible solution capable of • DoubleSideCoolingCapability providing a high density power supply when paired • Ultra-LowProfile –0.48mmMax with any 5 V gate driver from an external • Optimizedfor5VGateDrive controller/driver. • LowSwitchingLosses TEXTADDEDFORSPACING • LowInductancePackage OrderingInformation(1) • RoHSCompliant Device Media Qty Package Ship • HalogenFree CSD87588N 13-InchReel 2500 Tapeand 5x2.5LGA • PbFree CSD87588NT 7-InchReel 250 Reel (1) For all available packages, see the orderable addendum at 2 Applications theendofthedatasheet. • SynchronousBuckConverters TEXTADDEDFORSPACING – High-Current,LowDutyCycleApplications • MultiphaseSynchronousBuckConverters • POLDC-DCConverters TypicalCircuit TypicalPowerBlockEfficiencyandPowerLoss VIN 100 7 BOOT VDD VDD VIN 90 6 TG GND DRVH 80 VGS = 5V 5 EPNWABMLE EPNWAMBLE DRVLLL BG VPGSWND VOUT Efficiency (%) 567000 VVLfTSOAIOWN UU= T==T 2 ==155 2001ºV0C..23k9VHµzH 234 Power Loss (W) Driver IC CSD87588N 40 1 30 0 0 5 10 15 20 25 Output Current (A) G001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

CSD87588N SLPS384D–MARCH2013–REVISEDAPRIL2015 www.ti.com Table of Contents 1 Features.................................................................. 1 7 Layout................................................................... 13 2 Applications........................................................... 1 7.1 LayoutGuidelines...................................................13 3 Description............................................................. 1 7.2 LayoutExample......................................................13 4 RevisionHistory..................................................... 2 8 DeviceandDocumentationSupport.................. 14 5 Specifications......................................................... 3 8.1 Trademarks.............................................................14 5.1 AbsoluteMaximumRatings......................................3 8.2 ElectrostaticDischargeCaution..............................14 5.2 RecommendedOperatingConditions.......................3 8.3 Glossary..................................................................14 5.3 ThermalInformation..................................................3 9 Mechanical,Packaging,andOrderable Information........................................................... 15 5.4 PowerBlockPerformance........................................4 9.1 CSD87588NPackageDimensions.........................15 5.5 ElectricalCharacteristics...........................................4 9.2 LandPatternRecommendation..............................16 5.6 TypicalPowerBlockDeviceCharacteristics.............5 9.3 StencilRecommendation(100µm).........................16 5.7 TypicalPowerBlockMOSFETCharacteristics.........7 9.4 StencilRecommendation(125µm).........................17 6 ApplicationandImplementation........................ 10 9.5 PinDrawing.............................................................17 6.1 ApplicationInformation............................................10 9.6 CSD87588NEmbossedCarrierTapeDimensions.18 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(June2014)toRevisionD Page • ChangedcapacitanceunitstoreadpFinFigure15 ............................................................................................................. 8 • ChangedcapacitanceunitstoreadpFinFigure16 ............................................................................................................. 8 ChangesfromRevisionB(January2014)toRevisionC Page • Changed"Pb-FreeTerminalPlating"featuretostate"PbFree" ........................................................................................... 1 ChangesfromRevisionA(May2013)toRevisionB Page • Addedsmallreelinfo.............................................................................................................................................................. 1 • UpdatedFigure5.................................................................................................................................................................... 5 • UpdatedFigure6.................................................................................................................................................................... 5 • UpdatedFigure7.................................................................................................................................................................... 5 • UpdatedFigure8.................................................................................................................................................................... 5 • ChangedfigurereferencetoFigure29inelectricalperformance........................................................................................ 13 ChangesfromOriginal(March2013)toRevisionA Page • ChangedR To:R intheThermalInformationtable................................................................................................... 3 θJC-PCB θJC 2 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated

CSD87588N www.ti.com SLPS384D–MARCH2013–REVISEDAPRIL2015 5 Specifications 5.1 Absolute Maximum Ratings T =25°C(unlessotherwisenoted) (1) A MIN MAX UNIT V toP –0.8 30 IN GND V toP 30 SW GND Voltage V toP (10ns) 32 V SW GND T toV –20 20 G SW B toP –20 20 G GND I PulsedCurrentRating(2) 50 A DM P PowerDissipation(3) 6 W D SyncFET,I =45,L=0.1mH 101 D E AvalancheEnergy mJ AS ControlFET,I =26,L=0.1mH 34 D T OperatingJunction –55 150 °C J T StorageTemperatureRange –55 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedisnotimplied.Exposureto absolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) PulseDuration≤50µs,dutycycle≤0.01 (3) DevicemountedonFR4materialwith1inch2(6.45cm2)Cu 5.2 Recommended Operating Conditions T =25°C(unlessotherwisenoted) A MIN MAX UNIT V GateDriveVoltage 4.5 16 V GS V InputSupplyVoltage 24 V IN ƒ SwitchingFrequency C =0.1μF(min) 200 1500 kHz SW BST NoAirflow 25 A OperatingCurrent WithAirflow(200LFM) 30 A WithAirflow+HeatSink 35 A T OperatingTemperature 125 °C J 5.3 Thermal Information T =25°C(unlessotherwisestated) A THERMALMETRIC MIN TYP MAX UNIT Junction-to-ambientthermalresistance(MinCu) (1) 170 R θJA Junction-to-ambientthermalresistance(MaxCu) (2) (1) 70 °C/W Junction-to-casethermalresistance(Topofpackage) (1) 3.7 R θJC Junction-to-casethermalresistance(P Pin) (1) 1.25 GND (1) R isdeterminedwiththedevicemountedona1inch2(6.45cm2),2oz.(0.071mmthick)Cupadona1.5inches×1.5inches θJC (3.81cm×3.81cm),0.06inch(1.52mm)thickFR4board.R isspecifiedbydesignwhileR isdeterminedbytheuser’sboard θJC θJA design. (2) DevicemountedonFR4materialwith1inch2(6.45cm2)Cu. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3

CSD87588N SLPS384D–MARCH2013–REVISEDAPRIL2015 www.ti.com 5.4 Power Block Performance T =25°C(unlessotherwisenoted) A PARAMETER CONDITIONS MIN TYP MAX UNIT V =12V,V =5V IN GS P PowerLoss(1) VOUT=1.3V,IOUT=15A 2.1 W LOSS ƒ =500kHz SW L =0.29µH,T =25ºC OUT J T toT =0V I V QuiescentCurrent G GR 10 µA QVIN IN B toP =0V G GND (1) Measurementmadewithsix10µF(TDKC3216X5R1C106KTorequivalent)ceramiccapacitorsplacedacrossV toP pinsand IN GND usingahighcurrent5VdriverIC. 5.5 Electrical Characteristics T =25°C(unlessotherwisestated) A Q1FET Q2FET PARAMETER TESTCONDITIONS UNIT MIN TYP MAX MIN TYP MAX STATICCHARACTERISTICS BV Drain-to-SourceVoltage V =0V,I =250μA 30 30 V DSS GS DS I Drain-to-SourceLeakageCurrent V =0V,V =24V 1 1 μA DSS GS DS I Gate-to-SourceLeakageCurrent V =0V,V =20 100 100 nA GSS DS GS V Gate-to-SourceThresholdVoltage V =V ,I =250μA 1.1 1.9 1.1 1.9 V GS(th) DS GS DS V =4.5V,I =15A 10.4 12.5 3.5 4.2 GS DS R Drain-to-SourceOnResistance mΩ DS(on) V =10V,I =15A 8 9.6 2.9 3.5 GS DS g Transconductance V =10V,I =15A 43 93 S ƒs DS DS DYNAMICCHARACTERISTICS C InputCapacitance (1) 566 736 2310 3000 pF ISS C OutputCapacitance (1) VGS=0V,VDS=15V, 341 444 682 887 pF OSS ƒ=1MHz C ReverseTransferCapacitance (1) 10.3 13.4 62 80.4 pF RSS R SeriesGateResistance (1) 1.2 2.4 1.1 2.2 Ω G Q GateChargeTotal(4.5V) (1) 3.2 4.1 13.7 17.9 nC g Qgd GateCharge-Gate-to-Drain VDS=15V, 0.7 4.3 nC Qgs GateCharge-Gate-to-Source IDS=15A 1.4 4.3 nC Q GateChargeatV 0.8 2.8 nC g(th) th Q OutputCharge V =12V,V =0V 7 18.6 nC OSS DD GS t TurnOnDelayTime 7.3 12.1 ns d(on) tr RiseTime VDS=15V,VGS=4.5V, 31.6 36.7 ns td(off) TurnOffDelayTime IDS=15A,RG=2Ω 10.2 20.1 ns t FallTime 5.0 6.3 ns ƒ DIODECHARACTERISTICS V DiodeForwardVoltage I =15A,V =0V 0.85 0.78 V SD DS GS Qrr ReverseRecoveryCharge Vdd=15V,IF=15A, 12.5 26.7 nC t ReverseRecoveryTime di/dt=300A/μs 16 23 ns rr (1) Specifiedbydesign 4 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated

CSD87588N www.ti.com SLPS384D–MARCH2013–REVISEDAPRIL2015 MaxR =70°C/W MaxR =170°C/W θJA θJA whenmountedon whenmountedon 1inch2(6.45cm2)of minimumpadareaof 2oz.(0.071mmthick) 2oz.(0.071mmthick) Cu. Cu. 5.6 Typical Power Block Device Characteristics T =125°C,unlessstatedotherwise.TheTypicalPowerBlockSystemCharacteristiccurvesFigure3andFigure4arebased J onmeasurementsmadeonaPCBdesignwithdimensionsof4.0inches(W)×3.5inches(L)×0.062inch(H)and6copper layersof1oz.copperthickness.SeeApplicationandImplementationfordetailedexplanation. 8 1.1 VIN = 12V VIN = 12V 7 VGS = 5V 1 VGS = 5V VOUT = 1.3V d VOUT = 1.3V 6 fSW = 500kHz ze fSW = 500kHz s (W) 5 LOUT = 0.29µH ormali 0.9 LOUT = 0.29µH wer Los 34 Loss, N 0.8 Po er 0.7 w 2 o P 0.6 1 0 0.5 1 3 5 7 9 11 13 15 17 19 21 23 25 −50 −25 0 25 50 75 100 125 150 Output Current (A) Junction Temperature (ºC) G001 G001 Figure1.PowerLossvsOutputCurrent Figure2.NormalizedPowerLossvsTemperature 30 30 25 25 nt (A) 20 nt (A) 20 e e urr 15 urr 15 C C ut ut p p ut 10 ut 10 VIN = 12V O 400LFM O VGS = 5V 5 200LFM 5 VOUT = 1.3V 100LFM fSW = 500kHz Nat Conv LOUT = 0.29µH 0 0 0 10 20 30 40 50 60 70 80 90 0 20 40 60 80 100 120 140 Ambient Temperature (ºC) Board Temperature (ºC) G001 G001 Figure3.SafeOperatingArea–PCBHorizontalMount Figure4.TypicalSafeOperatingArea Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5

CSD87588N SLPS384D–MARCH2013–REVISEDAPRIL2015 www.ti.com Typical Power Block Device Characteristics (continued) T =125°C,unlessstatedotherwise.TheTypicalPowerBlockSystemCharacteristiccurvesFigure3andFigure4arebased J onmeasurementsmadeonaPCBdesignwithdimensionsof4.0inches(W)×3.5inches(L)×0.062inch(H)and6copper layersof1oz.copperthickness.SeeApplicationandImplementationfordetailedexplanation. 1.35 3.0 1.4 3.5 VGS = 5V 1.3 2.6 1.35 VOUT = 1.3V 3.0 d 1.25 2.2 C) d 1.3 LOUT = 0.29µH 2.6 C) Loss, Normalize 11.11..152 011...937 mperature Adj (º Loss, Normalize11.1.12.525 fISOWUT = = 5 2050AkHz 112...372 mperature Adj (º er 1.05 VIN = 12V 0.4 Te er 1.1 0.9 Te Pow 1 VVGOSU T= = 5 1V.3V 0.0 SOA Pow1.05 0.4 SOA 0.95 LOUT = 0.29µH −0.4 1 0.0 IOUT = 25A 0.9 −0.9 0.95 −0.4 0 200 400 600 800 1000 1200 1400 1600 1800 0 2 4 6 8 10 12 14 16 18 20 22 24 Switching Frequency (kHz) Input Voltage (V) G001 G001 Figure5.NormalizedPowerLossvsSwitchingFrequency Figure6.NormalizedPowerLossvsInputVoltage 2 8.6 1.12 1.04 VIN = 12V 1.8 6.9 1.1 VGS = 5V 0.87 d C) d1.08 VOUT = 1.3V 0.69 C) Loss, Normalize 11..46 35..41 mperature Adj (º Loss, Normalize111...000246 fISOWUT = = 5 2050AkHz 000...135752 mperature Adj (º er 1.2 VIN = 12V 1.7 Te er 1 0 Te Pow 1 VfSGWS == 550V0kHz 0 SOA Pow0.98 −0.17 SOA LOUT = 0.29µH 0.96 −0.35 IOUT = 25A 0.8 −1.7 0.94 −0.52 0.3 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 0 100 200 300 400 500 600 700 800 900 10001100 Output Voltage (V) Output Inductance (nH) G001 G001 Figure7.NormalizedPowerLossvsOutputVoltage Figure8.NormalizedPowerLossvsOutputInductance 6 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated

CSD87588N www.ti.com SLPS384D–MARCH2013–REVISEDAPRIL2015 5.7 Typical Power Block MOSFET Characteristics T =25°C,unlessstatedotherwise. A 50 200 A) 45 A) 180 nt ( 40 nt ( 160 e e urr 35 urr 140 C C e 30 e 120 c c our 25 our 100 S S o- 20 o- 80 n-t n-t ai 15 ai 60 Dr Dr I - DS 150 VVVGGGSSS === 844...050VVV I - DS 2400 VVVGGGSSS === 844...050VVV 0 0 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 1.2 VDS - Drain-to-Source Voltage (V) G001 VDS - Drain-to-Source Voltage (V) G001 Figure9. ControlMOSFETSaturation Figure10.SyncMOSFETSaturation 100 1000 VDS = 5V VDS = 5V A) 10 A) 100 nt ( nt ( e e urr 1 urr 10 C C ce 0.1 ce 1 ur ur o o o-S 0.01 o-S 0.1 n-t n-t ai 0.001 ai 0.01 Dr Dr - DS0.0001 TTCC == 12255°C°C - DS 0.001 TTCC == 12255°C°C I TC = −55°C I TC = −55°C 0.00001 0.0001 0 0.5 1 1.5 2 2.5 3 0.5 1 1.5 2 2.5 3 VGS - Gate-to-Source Voltage (V) G001 VGS - Gate-to-Source Voltage (V) G001 Figure11.ControlMOSFETTransfer Figure12.SyncMOSFETTransfer 10 10 e (V) 89 IVDD =S 1=5 1A5V e (V) 89 IVDD =S 1=5 1A5V g g a a olt 7 olt 7 V V e 6 e 6 c c our 5 our 5 S S o- 4 o- 4 e-t e-t at 3 at 3 G G - S 2 - S 2 G G V 1 V 1 0 0 0 1 2 3 4 5 6 7 8 0 5 10 15 20 25 30 Qg - Gate Charge (nC) G001 Qg - Gate Charge (nC) G001 Figure13.ControlMOSFETGateCharge Figure14.SyncMOSFETGateCharge Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7

CSD87588N SLPS384D–MARCH2013–REVISEDAPRIL2015 www.ti.com Typical Power Block MOSFET Characteristics (continued) T =25°C,unlessstatedotherwise. A 10000 10000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd F) 1000 F) 1000 p p e ( e ( c c n n a a cit 100 cit 100 a a p p a a C C − − C 10 C 10 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 1 1 0 5 10 15 20 25 30 0 5 10 15 20 25 30 VDS - Drain-to-Source Voltage (V) G001 VDS - Drain-to-Source Voltage (V) G001 Figure15.ControlMOSFETCapacitance Figure16.SyncMOSFETCapacitance 2 1.8 1.9 ID = 250µA 1.7 ID = 250µA V) 1.8 V) 1.6 ge ( 1.7 ge ( 1.5 a a olt 1.6 olt 1.4 V V d 1.5 d 1.3 hol 1.4 hol 1.2 s s hre 1.3 hre 1.1 - T()Sth 11..12 - T()Sth 0.91 VG 1 VG 0.8 0.9 0.7 0.8 0.6 −75 −25 25 75 125 175 −75 −25 25 75 125 175 TC - Case Temperature (ºC) G001 TC - Case Temperature (ºC) G001 Figure17.ControlMOSFETV Figure18.SyncMOSFETV GS(th) GS(th) 30 10 ) 27 ID = 15A ) 9 ID = 15A Wm Wm e ( 24 e ( 8 c c an 21 an 7 st st si 18 si 6 e e R R e 15 e 5 at at St 12 St 4 n- n- O 9 O 3 R - ()DSon 36 TTCC == 2152°5CºC R - ()DSon 12 TTCC == 2152°5CºC 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 VGS - Gate-to- Source Voltage (V) G001 VGS - Gate-to- Source Voltage (V) G001 Figure19.ControlMOSFETR vsV Figure20.SyncMOSFETR vsV DS(on) GS DS(on) GS 8 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated

CSD87588N www.ti.com SLPS384D–MARCH2013–REVISEDAPRIL2015 Typical Power Block MOSFET Characteristics (continued) T =25°C,unlessstatedotherwise. A 1.8 1.8 1.7 ID = 15A 1.7 ID = 15A nce 1.6 VGS = 8V nce 1.6 VGS = 8V a a st 1.5 st 1.5 si si Re 1.4 Re 1.4 ate 1.3 ate 1.3 St 1.2 St 1.2 n- n- O 1.1 O 1.1 ed 1 ed 1 z z ali 0.9 ali 0.9 m m or 0.8 or 0.8 N N 0.7 0.7 0.6 0.6 −75 −25 25 75 125 175 −75 −25 25 75 125 175 TC - Case Temperature (ºC) G001 TC - Case Temperature (ºC) G001 Figure21.ControlMOSFETNormalizedR Figure22.SyncMOSFETNormalizedR DS(on) DS(on) 100 100 A) A) nt ( 10 nt ( 10 e e Curr 1 Curr 1 n n ai ai Dr 0.1 Dr 0.1 o- o- e-t e-t urc 0.01 urc 0.01 o o S S − SD 0.001 TC = 25°C − SD 0.001 TC = 25°C I TC = 125°C I TC = 125°C 0.0001 0.0001 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 VSD − Source-to-Drain Voltage (V) G001 VSD − Source-to-Drain Voltage (V) G001 Figure23.ControlMOSFETBodyDiode Figure24.SyncMOSFETBodyDiode 100 100 A) A) nt ( nt ( e e urr urr C C e e h h c c an 10 an 10 al al v v A A k k a a e e P P - )AV TC = 25°C - )AV TC = 25°C I( TC = 125°C I( TC = 125°C 1 1 0.01 0.1 1 0.01 0.1 1 t(AV) - Time in Avalanche (ms) G001 t(AV) - Time in Avalanche (ms) G001 Figure25.ControlMOSFETUnclampedInductiveSwitching Figure26.SyncMOSFETUnclampedInductiveSwitching Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9

CSD87588N SLPS384D–MARCH2013–REVISEDAPRIL2015 www.ti.com 6 Application and Implementation 6.1 Application Information The CSD87588N NexFET power block is an optimized design for synchronous buck applications using 5 V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a new rating method is needed which is tailored toward a more systems-centric environment. System-level performance curves such as Power Loss, Safe Operating Area, and normalized graphsallowengineerstopredicttheproductperformanceintheactualapplication. 6.1.1 PowerLossCurves MOSFET-centric parameters such as R and Q are needed to estimate the loss generated by the devices. DS(ON) gd To simplify the design process for engineers, TI has provided measured power loss performance curves. Figure 1 plots the power loss of the CSD87588N as a function of load current. This curve is measured by configuring and running the CSD87588N as it would be in the final application (see Figure 27). The measured power loss is the CSD87588N loss and consists of both input conversion loss and gate drive loss. Equation 1 is usedtogeneratethepowerlosscurve. (V ×I )+(V ×I )–(V ×I )=PowerLoss (1) IN IN DD DD SW_AVG OUT The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C underisothermaltestconditions. 6.1.2 SafeOperatingCurves(SOA) The SOA curves in the CSD87588N data sheet provide guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 4 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 inches (W) ×3.5inches(L)× 0.062inch(T)and6copperlayersof1oz.copperthickness. 6.1.3 NormalizedCurves The normalized curves in the CSD87588N data sheet provides guidance on the Power Loss and SOA adjustments based on their application-specific needs. These curves show how the power loss and SOA boundaries adjust for a given set of systems conditions. The primary y-axis is the normalized change in power loss and the secondary y-axis is the change in system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is subtractedfromtheSOAcurve. Input Current (I ) IN A V IN BOOT VDD A VDD V VIN Input Voltage (VIN) Gate Drive V TG DRVH Voltage (V ) ENABLE DD Output Current (I ) OUT V LL SW A V PWM OUT PWM BG DRVL GND P GND Averaged Switch CSD873588N Averaging Driver IC V Node Voltage Circuit (V ) SW_AVG Figure27. TypicalApplication 10 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated

CSD87588N www.ti.com SLPS384D–MARCH2013–REVISEDAPRIL2015 Application Information (continued) 6.1.4 CalculatingPowerLossandSOA The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following procedure outlines the steps the user should take to predict product performance for any set of system conditions. 6.1.4.1 DesignExample OperatingConditions: • OutputCurrent=15A • InputVoltage=7V • OutputVoltage=1V • SwitchingFrequency=800kHz • Inductor=0.2µH 6.1.4.2 CalculatingPowerLoss • PowerLossat15A=2.75W(Figure1) • NormalizedPowerLossforinputvoltage ≈ 1.03(Figure6) • NormalizedPowerLossforoutputvoltage ≈ 0.94(Figure7) • NormalizedPowerLossforswitchingfrequency ≈ 1.08(Figure5) • NormalizedPowerLossforoutputinductor≈ 1.03(Figure8) • FinalcalculatedPowerLoss=2.75W ×1.05 ×0.95 ×1.05 ×1.05 ≈ 3.02W 6.1.4.3 CalculatingSOAAdjustments • SOAadjustmentforinputvoltage ≈ 0.3ºC(Figure6) • SOAadjustmentforoutputvoltage ≈ –0.5ºC(Figure7) • SOAadjustmentforswitchingfrequency ≈ 0.7ºC(Figure5) • SOAadjustmentforoutputinductor ≈ 0.3ºC(Figure8) • FinalcalculatedSOAadjustment=0.3+(–0.5)+0.7+0.3 ≈ 0.8ºC In the previous design example, the estimated power loss of the CSD87588N would increase to 3.02 W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 0.8ºC. Figure 28 graphicallyshowshowtheSOAcurvewouldbeadjustedaccordingly. 1. StartbydrawingahorizontallinefromtheapplicationcurrenttotheSOAcurve. 2. DrawaverticallinefromtheSOAcurveinterceptdowntotheboard/ambienttemperature. 3. AdjusttheSOAboard/ambienttemperaturebysubtractingthetemperatureadjustmentvalue. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11

CSD87588N SLPS384D–MARCH2013–REVISEDAPRIL2015 www.ti.com Application Information (continued) In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 0.8ºC. In the event the adjustment value is a negative number, subtracting the negative number wouldyieldanincreaseinallowableboard/ambienttemperature. Figure28. PowerBlockSOA 12 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated

CSD87588N www.ti.com SLPS384D–MARCH2013–REVISEDAPRIL2015 7 Layout 7.1 Layout Guidelines There are two key system-level parameters that can be addressed with a proper PCB design: electrical and thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. The followingsectionsprovideabriefdescriptiononhowtoaddresseachparameter. 7.1.1 ElectricalPerformance The CSD87588N has the ability to switch voltages at rates greater than 10 kV/µs. Take special care with the PCBlayoutdesignandplacementoftheinputcapacitors,inductor,andoutputcapacitors. • The placement of the input capacitors relative to VIN and PGND pins of CSD87588N device should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 29). The example in Figure 29 uses 1 x 10 nF 0402 25 V and 4 x 10 μF 1206 25 V ceramic capacitors (TDK part number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the PowerStageC21,C5,C8,C19,andC18shouldfollowinorder. • The switching node of the output inductor should be placed relatively close to the Power Block II CSD87588N VSW pins. Minimizing the VSW node length between these two components will reduce the PCB conduction lossesandactuallyreducetheswitchingnoiselevel.SeeFigure29. (1) 7.1.2 ThermalPerformance The CSD87588N has the ability to utilize the PGND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount ofsolderattachthatwicksdowntheviabarrel: • Intentionallyspaceouttheviasfromeachothertoavoidaclusterofholesinagivenarea. • Use the smallest drill size allowed in your design. The example in Figure 29 uses vias with a 10 mil drill hole anda16milcapturepad. • Tenttheoppositesideoftheviawithsolder-mask. The number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturingcapabilities. 7.2 Layout Example Figure29. RecommendedPCBLayout(TopDownView) (1) KeongW.Kam,DavidPommerenke,“EMIAnalysisMethodsforSynchronousBuckConverterEMIRootCauseAnalysis”,Universityof Missouri–Rolla Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13

CSD87588N SLPS384D–MARCH2013–REVISEDAPRIL2015 www.ti.com 8 Device and Documentation Support 8.1 Trademarks NexFETisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 8.2 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 8.3 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated

CSD87588N www.ti.com SLPS384D–MARCH2013–REVISEDAPRIL2015 9 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 9.1 CSD87588N Package Dimensions PinConfiguration Position Designation Pin1 TG Pin2 V IN Pin3 P GND Pin4 BG Pin5 V SW Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15

CSD87588N SLPS384D–MARCH2013–REVISEDAPRIL2015 www.ti.com 9.2 Land Pattern Recommendation G G K K P P F F E E R R 0 8 8 0 0 0 3 0 5 1 2 5 2. 2. 1. 2. 1.250 REF PKG 0.858 2 3 5 0.000 0.238 0.238 0.538 0.538 1 4 0.858 1.250 REF PKG PACKAGE 002 8 0 00 0 0 OUTLINE 649 5 0 00 2 0 964 7 0 58 1 0 1.1.1. 0. 0. 0.0. 1. 2. 9.3 Stencil Recommendation (100 µm) TextForSpacing 16 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated

CSD87588N www.ti.com SLPS384D–MARCH2013–REVISEDAPRIL2015 9.4 Stencil Recommendation (125 µm) Text For Spacing For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCBLayoutTechniques. 9.5 Pin Drawing 87588N TI YMS LLLL E TextForSpacing Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17

CSD87588N SLPS384D–MARCH2013–REVISEDAPRIL2015 www.ti.com 9.6 CSD87588N Embossed Carrier Tape Dimensions (1) Pin1isorientedinthetop-leftquadrantofthetapeenclosure(closesttothecarriertapesprocketholes). spacer 18 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CSD87588N ACTIVE PTAB MPA 5 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 150 87588N & no Sb/Br) CSD87588NT ACTIVE PTAB MPA 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 150 87588N & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CSD87588N PTAB MPA 5 2500 330.0 12.4 2.8 5.3 0.55 8.0 12.0 Q1 CSD87588NT PTAB MPA 5 250 180.0 12.4 2.8 5.3 0.55 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CSD87588N PTAB MPA 5 2500 367.0 367.0 35.0 CSD87588NT PTAB MPA 5 250 182.0 182.0 20.0 PackMaterials-Page2

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