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  • 型号: CSD86330Q3D
  • 制造商: Texas Instruments
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CSD86330Q3D产品简介:

ICGOO电子元器件商城为您提供CSD86330Q3D由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 CSD86330Q3D价格参考。Texas InstrumentsCSD86330Q3D封装/规格:晶体管 - FET,MOSFET - 阵列, 2 个 N 通道(半桥) Mosfet 阵列 25V 20A 6W 表面贴装 8-LSON(3.3x3.3)。您可以下载CSD86330Q3D参考资料、Datasheet数据手册功能说明书,资料中有CSD86330Q3D 详细功能的应用电路图电压和使用方法及教程。

产品参数 图文手册 常见问题
参数 数值
产品目录

分立半导体产品

描述

MOSFET 2N-CH 25V 20A 8SONMOSFET Sync Buck NexFET Pwr Block MOSFET

产品分类

FET - 阵列分离式半导体

FET功能

逻辑电平门

FET类型

2 个 N 通道(半桥)

Id-ContinuousDrainCurrent

20 A

Id-连续漏极电流

20 A

品牌

Texas Instruments

产品手册

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产品图片

rohs

符合RoHS含铅 / 不受限制有害物质指令(RoHS)规范要求限制

产品系列

晶体管,MOSFET,Texas Instruments CSD86330Q3DNexFET™

数据手册

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产品型号

CSD86330Q3D

PCN封装

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PCN组件/产地

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PCN设计/规格

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Pd-PowerDissipation

6 W

Pd-功率耗散

6 W

RdsOn-Drain-SourceResistance

10 mOhms

RdsOn-漏源导通电阻

10 mOhms

Vds-Drain-SourceBreakdownVoltage

25 V

Vds-漏源极击穿电压

25 V

Vgs-栅源极击穿电压

10 V

不同Id时的Vgs(th)(最大值)

2.1V @ 250µA

不同Vds时的输入电容(Ciss)

920pF @ 12.5V

不同Vgs时的栅极电荷(Qg)

6.2nC @ 4.5V

不同 Id、Vgs时的 RdsOn(最大值)

9.6 毫欧 @ 14A,8V

产品培训模块

http://www.digikey.cn/PTM/IndividualPTM.page?site=cn&lang=zhs&ptm=25585

产品种类

MOSFET

供应商器件封装

8-SON(3.3x3.3)

其它名称

296-28216-1

制造商产品页

http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&orderablePartNumber=CSD86330Q3D

功率-最大值

6W

包装

剪切带 (CT)

商标

Texas Instruments

商标名

NexFET

安装类型

表面贴装

安装风格

SMD/SMT

封装

Reel

封装/外壳

8-LDFN

封装/箱体

LSON-8 Clip

工厂包装数量

2500

晶体管极性

N-Channel

最大工作温度

+ 150 C

最小工作温度

- 55 C

标准包装

1

漏源极电压(Vdss)

25V

特色产品

http://www.digikey.com/cn/zh/ph/texas-instruments/csd86330q3d-nexfet.htmlhttp://www.digikey.com/cn/zh/ph/texas-instruments/tps53219-csd86330-powerblock.html

电流-连续漏极(Id)(25°C时)

20A

系列

CSD86330Q3D

视频文件

http://www.digikey.cn/classic/video.aspx?PlayerID=1364138032001&width=640&height=455&videoID=1083957888001

配置

Dual

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PDF Datasheet 数据手册内容提取

Product Sample & Technical Tools & Support & Folder Buy Documents Software Community CSD86330Q3D SLPS264D–OCTOBER2010–REVISEDMAY2015 CSD86330Q3D Synchronous Buck NexFET™ Power Block 1 Features 3 Description • Half-BridgePowerBlock The CSD86330Q3D NexFET™ power block is an 1 optimized design for synchronous buck applications • 90%SystemEfficiencyat15A offering high current, high efficiency, and high • Upto20AOperation frequency capability in a small 3.3 mm × 3.3 mm • HighFrequencyOperation(UpTo1.5MHz) outline. Optimized for 5 V gate drive applications, this product offers a flexible solution capable of offering a • HighDensity –SON3.3mm× 3.3mmFootprint high density power supply when paired with any 5 V • Optimizedfor5VGateDrive gatedrivefromanexternalcontroller/driver. • LowSwitchingLosses TEXTADDEDFORSPACING • UltraLowInductancePackage TopView • RoHSCompliant • HalogenFree VIN 1 8 VSW • Pb-FreeTerminalPlating VIN 2 7 VSW PGND (Pin 9) 2 Applications TG 3 6 VSW • SynchronousBuckConverters TGR 4 5 BG – HighFrequencyApplications P0116-01 – HighCurrent,LowDutyCycleApplications TEXTADDEDFORSPACING OrderingInformation(1) • MultiphaseSynchronousBuckConverters Device Media Qty Package Ship • POLDC-DCConverters 13-Inch • IMVP,VRM,andVRDApplications CSD86330Q3D Reel 2500 SON3.3mm×3.3mm Tapeand 7-Inch PlasticPackage Reel CSD86330Q3DT 250 Reel (1) For all available packages, see the orderable addendum at theendofthedatasheet. Addedtextforspacing Addedtextforspacing Addedtextforspacing Addedtextforspacing R vsV GateCharge DS(on) GS DriverIC CSD86330Q3D 100 5 VDD VDD BST D1 VI Control 90 4 EPNWAMBLE EPGNWNADMBLE DDRRVVLHLL GGG112R SSDFF2yEE2n/TTSc1 VO Efficiency (%) 7800 VVVfLTSOGIOAWNU SU= =T T= = 2 = =1 555 2101°VVCµ0.3HkVHz 23 ower Loss (W) P S0474-04 60 1 Efficiency Power Loss 50 0 0 5 10 15 20 Output Current (A) G029 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

CSD86330Q3D SLPS264D–OCTOBER2010–REVISEDMAY2015 www.ti.com Table of Contents 1 Features.................................................................. 1 6.3 SafeOperatingCurves(SOA)................................12 2 Applications........................................................... 1 6.4 NormalizedCurves..................................................12 3 Description............................................................. 1 6.5 CalculatingPowerLossandSOA..........................14 4 RevisionHistory..................................................... 2 7 RecommendedPCBDesignOverview..............15 7.1 ElectricalPerformance............................................15 5 Specifications......................................................... 3 7.2 ThermalPerformance.............................................15 5.1 AbsoluteMaximumRatings......................................3 8 DeviceandDocumentationSupport.................. 17 5.2 RecommendedOperatingConditions.......................3 5.3 ThermalInformation..................................................3 8.1 Trademarks.............................................................17 5.4 PowerBlockPerformance........................................3 8.2 ElectrostaticDischargeCaution..............................17 5.5 ElectricalCharacteristics...........................................4 8.3 Glossary..................................................................17 5.6 TypicalPowerBlockDeviceCharacteristics.............5 9 Mechanical,Packaging,andOrderable Information........................................................... 18 5.7 TypicalPowerBlockMOSFETCharacteristics.........7 9.1 Q3DPackageDimensions......................................18 6 ApplicationandImplementation........................ 10 9.2 LandPatternRecommendation..............................19 6.1 ApplicationInformation............................................10 9.3 StencilRecommendation........................................19 6.2 PowerLossCurves ................................................12 9.4 Q3DTapeandReelInformation.............................20 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(October2011)toRevisionD Page • Corrected125°ClineinFigure20toagreewithdatainFigure22 ....................................................................................... 8 • Corrected125°ClineinFigure21toagreewithdatainFigure23 ....................................................................................... 8 ChangesfromRevisionB(September2011)toRevisionC Page • Changed"DIMA"MillimeterMaxvalueFrom:1.55To:1.5andInchesMaxvalueFrom:0.061To:0.059....................... 18 ChangesfromRevisionA(December2010)toRevisionB Page • ChangeR toZ ......................................................................................................................................................... 4 DS(on) DS(on) • AddedEquivalentSystemPerformancesection.................................................................................................................. 10 • AddedElectricalPerformancebullet.................................................................................................................................... 15 ChangesfromOriginal(October2010)toRevisionA Page • ChangedI ConditionsFrom:20ATo:15A,andtheTYPvalueFrom:2.9WTo:1.9W..................................................... 3 OUT 2 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:CSD86330Q3D

CSD86330Q3D www.ti.com SLPS264D–OCTOBER2010–REVISEDMAY2015 5 Specifications 5.1 Absolute Maximum Ratings T =25°C(unlessotherwisenoted)(1) A MIN MAX UNIT V toP –0.8 25 V IN GND Voltagerange T toT –8 10 V G GR B toP –8 10 V G GND PulsedCurrentRating,I 60 A DM PowerDissipation,P 6 W D SyncFET,I =65A,L=0.1mH 211 D AvalancheEnergyE mJ AS ControlFET,I =42A,L=0.1mH 88 D Operatingjunction,T –55 150 °C J Storagetemperature,T –55 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedisnotimplied.Exposuretoabsolute- maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 5.2 Recommended Operating Conditions T =25°(unlessotherwisenoted) A MIN MAX UNIT Gatedrivevoltage,V 4.5 8 V GS Inputsupplyvoltage,V 22 V IN Switchingfrequency,f C =0.1µF(min) 200 1500 kHz SW BST Operatingcurrent 20 A Operatingtemperature,T 125 °C J 5.3 Thermal Information T =25°C(unlessotherwisestated) A THERMALMETRIC MIN TYP MAX UNIT Junction-to-ambientthermalresistance(MinCu)(1) 135 R θJA Junction-to-ambientthermalresistance(MaxCu)(1)(2) 73 °C/W Junction-to-casethermalresistance(Topofpackage)(1) 29 R θJC Junction-to-casethermalresistance(P Pin)(1) 2.5 GND (1) R isdeterminedwiththedevicemountedona1inch2(6.45cm2),2oz.(0.071mmthick)Cupadona1.5inches×1.5inches θJC (3.81cm×3.81cm),0.06inch(1.52mm)thickFR4board.R isspecifiedbydesignwhileR isdeterminedbytheuser’sboard θJC θJA design. (2) DevicemountedonFR4materialwith1inch2(6.45cm2)Cu. 5.4 Power Block Performance T =25°(unlessotherwisenoted) A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V =12V,V =5V, IN GS PowerLoss,P (1) VOUT=1.3V,IOUT=15A, 1.9 W LOSS f =500kHz, SW L =1µH,T =25ºC OUT J T toT =0V V QuiescentCurrent,I G GR 10 µA IN QVIN B toP =0V G GND (1) Measurementmadewithsix10µF(TDKC3216X5R1C106KTorequivalent)ceramiccapacitorsplacedacrossV toP pinsand IN GND usingahighcurrent5VdriverIC. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:CSD86330Q3D

CSD86330Q3D SLPS264D–OCTOBER2010–REVISEDMAY2015 www.ti.com 5.5 Electrical Characteristics T =25°C(unlessotherwisestated) A Q1ControlFET Q2SyncFET UNIT PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX STATICCHARACTERISTICS BV Drain-to-SourceVoltage V =0V,I =250µA 25 25 V DSS GS DS Drain-to-SourceLeakage I V =0V,V =20V 1 1 µA DSS Current GS DS Gate-to-SourceLeakage I V =0V,V =+10/–8 100 100 nA GSS Current DS GS Gate-to-SourceThreshold V V =V ,I =250µA 0.9 1.4 2.1 0.9 1.1 1.6 V GS(th) Voltage DS GS DS V =12V,V =5V, IN GS V =1.3V,I =15A, Z EffectiveACOn-Impedance OUT OUT 8.8 3.3 mΩ DS(on) ƒ =500kHz, SW L =1µH OUT g Transconductance V =15V,I =14A 52 82 S ƒs DS DS DYNAMICCHARACTERISTICS C InputCapacitance(1) 710 920 1280 1660 pF ISS C OutputCapacitance(1) V =0V,V =12.5V, 350 455 680 880 pF OSS GS DS ƒ=1MHz ReverseTransfer CRSS Capacitance(1) 18 23 38 49 pF R SeriesGateResistance(1) 1.5 3.0 1.2 2.4 Ω G Q GateChargeTotal(4.5V)(1) 4.8 6.2 9.2 12 nC g Q GateCharge-Gate-to-Drain 0.9 1.6 nC gd V =12.5V, DS Qgs GSoautercCeharge-Gate-to- IDS=14A 1.6 2.1 nC Q GateChargeatVth 0.9 1.2 nC g(th) Q OutputCharge V =15.5V,V =0V 7.2 13.6 nC OSS DS GS t TurnOnDelayTime 4.9 5.3 ns d(on) tr RiseTime VDS=12.5V,VGS=4.5V, 7.5 6.3 ns td(off) TurnOffDelayTime IDS=14A,RG=2Ω 8.5 15.8 ns t FallTime 1.9 4.2 ns ƒ DIODECHARACTERISTICS V DiodeForwardVoltage I =14A,V =0V 0.85 1 0.8 1 V SD DS GS Qrr ReverseRecoveryCharge Vdd=15.5V,IF=14A, 3.9 7.3 nC t ReverseRecoveryTime di/dt=300A/µs 13.9 19 ns rr (1) Specifiedbydesign HD LD HD LD 8 8 6 6 3 3 3 3 0 0 Q MaxR =76°C/W Q MaxR =140°C/W 3 θJA 3 θJA D D whenmountedon whenmountedon 3 3 .3x 1inch2(6.45cm2)of .3x minimumpadareaof 3 3 .3 2oz.(0.071mmthick) .3 2oz.(0.071mmthick) MI Cu. MI Cu. N N R R e e v v 0 LG HS 0 LG HS HG LS HG LS M0205-01 M0206-01 4 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:CSD86330Q3D

CSD86330Q3D www.ti.com SLPS264D–OCTOBER2010–REVISEDMAY2015 5.6 Typical Power Block Device Characteristics V =12V,V =5V,ƒ =500kHz,V =1.2V,L =1.0µH,I =20A,T =125°C,unlessstatedotherwise. IN DD SW OUT OUT OUT J 4 1.2 3.5 1.1 3 d ze 1 W) 2.5 mali s ( or 0.9 s N Power Lo 1.25 er Loss, 0.8 w 0.7 1 Po 0.5 0.6 0 0.5 0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 150 Output Current (A) Junction Temperature (°C) G001 G002 Figure1.PowerLossvsOutputCurrent Figure2.PowerLossvsTemperature 25 25 20 20 A) A) nt ( 15 nt ( 15 e e urr urr C C ut 10 ut 10 p p ut ut O O 400LFM 400LFM 5 200LFM 5 200LFM 100LFM 100LFM Nat Conv Nat Conv 0 0 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90 Ambient Temperature (°C) Ambient Temperature (°C) G003 G004 Figure3.SafeOperatingArea–PCBVerticalMount(1) Figure4.SafeOperatingArea–PCBHorizontalMount(1) (1) The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with dimensionsof4.0”(W)×3.5”(L)×0.062”(H)and6copperlayersof1oz.copperthickness.SeeApplicationSection fordetailedexplanation. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:CSD86330Q3D

CSD86330Q3D SLPS264D–OCTOBER2010–REVISEDMAY2015 www.ti.com Typical Power Block Device Characteristics (continued) V =12V,V =5V,ƒ =500kHz,V =1.2V,L =1.0µH,I =20A,T =125°C,unlessstatedotherwise. IN DD SW OUT OUT OUT J 25 20 A) nt ( 15 e urr C ut 10 p ut O 5 0 0 20 40 60 80 100 120 140 Board Temperature (°C) G005 Figure5.TypicalSafeOperatingArea(1) 1.6 15.7 1.6 15.7 1.5 13.1 1.5 13.1 d 1.4 10.5 C) d 1.4 10.5 C) Loss, Normalize 111...1123 0257...629 °mperature Adj ( Loss, Normalize 111...1123 0257...628 °mperature Adj ( er Te er Te Pow 0.9 -2.6 OA Pow 0.9 -2.6 OA 0.8 -5.2 S 0.8 -5.2 S 0.7 -7.9 0.7 -7.8 0.6 -10.5 0.6 -10.5 200 400 600 800 1000 1200 1400 1600 3 6 9 12 15 18 21 24 Switching Frequency (kHz) Input Voltage (V) G006 G007 Figure6.NormalizedPowerLossvsSwitchingFrequency Figure7.NormalizedPowerLossvsInputVoltage 1.6 15.7 1.6 15.7 1.5 13.1 1.5 13.1 d 1.4 10.5 C) d 1.4 10.5 C) Loss, Normalize 111...1123 0257...629 °mperature Adj ( Loss, Normalize 111...1123 0257...629 mperature Adj (° er Te er Te Pow 0.9 -2.6 OA Pow 0.9 -2.6 OA 0.8 -5.2 S 0.8 -5.2 S 0.7 -7.9 0.7 -7.9 0.6 -10.5 0.6 -10.5 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 Output Voltage (V) Output Inductance (µH) G008 G009 Figure8.NormalizedPowerLossvsOutputVoltage Figure9.NormalizedPowerLossvsOutputInductance 6 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:CSD86330Q3D

CSD86330Q3D www.ti.com SLPS264D–OCTOBER2010–REVISEDMAY2015 5.7 Typical Power Block MOSFET Characteristics T =25°C,unlessstatedotherwise. A 60 60 VGS = 8V nt - A 50 nt - A 50 e e urr 40 urr 40 e C VGS = 8V e C ourc 30 ourc 30 VGS = 6V o-S VGS = 6V o-S ain-t 20 ain-t 20 - DrDS 10 VGS = 4.5V - DrDS 10 VGS = 4.5V I I 0 0 0 0.2 0.4 0.6 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 VDS - Drain-to-Source Voltage - V G010 VDS - Drain-to-Source Voltage - V G011 Figure10.ControlMOSFETSaturation Figure11.SyncMOSFETSaturation 100 100 VDS = 5V VDS = 5V A A nt - 10 nt - 10 e e urr urr C C urce 1 TC = 125°C urce 1 TC = 125°C o o S S o- 0.1 o- 0.1 ain-t TC = 25°C ain-t TC = 25°C Dr Dr I - DS 0.01 TC = -55°C I - DS 0.01 TC = -55°C 0.001 0.001 1 1.5 2 2.5 3 3.5 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 VGS - Gate-to-Source Voltage - V G012 VGS - Gate-to-Source Voltage - V G013 Figure12.ControlMOSFETTransfer Figure13.SyncMOSFETTransfer 8 8 ID = 14A ID = 14A e - V 7 VDS = 12.5V e - V 7 VDS = 12.5V g 6 g 6 a a olt olt V 5 V 5 e e c c our 4 our 4 S S o- o- e-t 3 e-t 3 at at G G - S 2 - S 2 G G V 1 V 1 0 0 0 2 4 6 8 0 3 6 9 12 15 Qg - Gate Charge - nC G014 Qg - Gate Charge - nC G015 Figure14.ControlMOSFETGateCharge Figure15.SyncMOSFETGateCharge Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:CSD86330Q3D

CSD86330Q3D SLPS264D–OCTOBER2010–REVISEDMAY2015 www.ti.com Typical Power Block MOSFET Characteristics (continued) T =25°C,unlessstatedotherwise. A 10 10 f = 1MHz VGS = 0V Ciss = Cgd + Cgs Ciss = Cgd + Cgs 1 F F e - n e - n 1 c c n n a a acit 0.1 Coss = Cds + Cgd acit Coss = Cds + Cgd p p a a C C C - C - 0.1 Crss = Cgd 0.01 Crss = Cgd f = 1MHz VGS = 0V 0.001 0.01 0 5 10 15 20 25 0 5 10 15 20 25 VDS - Drain-to-Source Voltage - V G016 VDS - Drain-to-Source Voltage - V G017 Figure16.ControlMOSFETCapacitance Figure17.SyncMOSFETCapacitance 1.8 1.8 1.6 ID = 250µA 1.6 ID = 250µA V V e - 1.4 e - 1.4 g g olta 1.2 olta 1.2 V V d 1 d 1 ol ol h h es 0.8 es 0.8 hr hr T T - S(th) 00..46 - S(th) 00..46 G G V V 0.2 0.2 0 0 -75 -25 25 75 125 175 -75 -25 25 75 125 175 TC - Case Temperature - °C G018 TC - Case Temperature - °C G019 Figure18.ControlMOSFETV Figure19.SyncMOSFETV GS(th) GS(th) 25 16 TC = 25°C, ID = 14A TC = 25°C, ID = 14A Wm TC = 125°C, ID = 14A Wm 14 TC = 125°C, ID = 14A ce - 20 ce - 12 n n a a sist 15 sist 10 e e R R e e 8 at at n-St 10 n-St 6 O O - ()DSon 5 - ()DSon 24 R R 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 VGS - Gate-to- Source Voltage - V G001 VGS - Gate-to- Source Voltage - V G001 Figure20.ControlMOSFETR vsV Figure21.SyncMOSFETR vsV DS(on) GS DS(on) GS 8 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:CSD86330Q3D

CSD86330Q3D www.ti.com SLPS264D–OCTOBER2010–REVISEDMAY2015 Typical Power Block MOSFET Characteristics (continued) T =25°C,unlessstatedotherwise. A 1.6 1.6 ID = 14A ID = 14A ce 1.4 VGS = 8V ce 1.4 VGS = 8V n n sta 1.2 sta 1.2 si si e e R 1 R 1 e e at at St 0.8 St 0.8 n- n- O O d 0.6 d 0.6 e e z z mali 0.4 mali 0.4 or or N 0.2 N 0.2 0 0 -75 -25 25 75 125 175 -75 -25 25 75 125 175 TC - Case Temperature - °C G022 TC - Case Temperature - °C G023 Figure22.ControlMOSFETNormalizedR Figure23.SyncMOSFETNormalizedR DS(on) DS(on) 100 100 nt - A 10 TC = 125°C nt - A 10 TC = 125°C e e urr 1 urr 1 C C n n ai ai Dr 0.1 Dr 0.1 o- o- urce-t 0.01 TC = 25°C urce-t 0.01 TC = 25°C o o S S - D 0.001 - D 0.001 S S I I 0.0001 0.0001 0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 1.2 VSD - Source-to-Drain Voltage - V G024 VSD - Source-to-Drain Voltage - V G025 Figure24.ControlMOSFETBodyDiode Figure25.SyncMOSFETBodyDiode 100 100 A A TC = 25°C nt - TC = 25°C nt - e e urr urr C C e e alanch 10 TC = 125°C alanch 10 TC = 125°C v v A A k k a a e e P P - V) - V) A A I( I(AV) = t(AV) ÷ (0.021 × L) I( I(AV) = t(AV) ÷ (0.021 × L) 1 1 0.01 0.1 1 10 0.01 0.1 1 10 t(AV) - Time in Avalanche - ms G026 t(AV) - Time in Avalanche - ms G027 Figure26.ControlMOSFETUnclampedInductiveSwitching Figure27.SyncMOSFETUnclampedInductiveSwitching Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:CSD86330Q3D

CSD86330Q3D SLPS264D–OCTOBER2010–REVISEDMAY2015 www.ti.com 6 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 6.1 Application Information 6.1.1 EquivalentSystemPerformance Many of today’s high performance computing systems require low power consumption in an effort to reduce system operating temperatures and improve overall system efficiency. This has created a major emphasis on improving the conversion efficiency of today’s Synchronous Buck Topology. In particular, there has been an emphasis in improving the performance of the critical Power Semiconductor in the Power Stage of this Application (see Figure 28). As such, optimization of the power semiconductors in these applications, needs to gobeyondsimplyreducingR . DS(ON) Figure28. The CSD86330Q3D is part of TI’s Power Block product family which is a highly optimized product for use in a synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest generation silicon which has been optimized for switching performance, as well as minimizing losses associated with Q , Q , and Q . Furthermore, TI’s patented packaging technology has minimized losses by nearly GD GS RR eliminating parasitic elements between the Control FET and Sync FET connections (see Figure 29). A key challenge solved by TI’s patented packaging technology is the system level impact of Common Source Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI andmodificationofswitchinglossequationsareoutlinedinTI’sApplicationNoteSLPA009. 10 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:CSD86330Q3D

CSD86330Q3D www.ti.com SLPS264D–OCTOBER2010–REVISEDMAY2015 Application Information (continued) Figure29. The combination of TI’s latest generation silicon and optimized packaging technology has created a benchmarking solution that outperforms industry standard MOSFET chipsets of similar R and MOSFET DS(ON) chipsets with lower R . Figure 30 and Figure 31 compare the efficiency and power loss performance of the DS(ON) CSD86330Q3D versus industry standard MOSFET chipsets commonly used in this type of application. This comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The performance of CSD86330Q3D clearly highlights the importance of considering the Effective AC On-Impedance (Z ) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET DS(ON) R specifications is not an indicator of the actual in-circuit performance when using TI’s Power Block DS(ON) technology. TEXTADDEDFORSPACING 96 4.5 PowerBlock HS/LS RDS(ON) = 8.8mW /4.6mW 94 4 Discrete HS/LS RDS(ON) = 8.8mW /4.6mW Discrete HS/LS RDS(ON) = 8.8mW /3.3mW 92 3.5 VGS = 5V Efficiency (%) 88894680 VVVLfSOGIOWNUSU T= =T= ==1 55 2011VV0µ.3kHVHz Power Loss (W) 12..5253 VVLfTSOAIOWN UU= T==T 2 ==155 2011ºV0Cµ.3kHVHz TA = 25ºC 82 PowerBlock HS/LS RDS(ON) = 8.8mW /4.6mW 1 80 Discrete HS/LS RDS(ON) = 8.8mW /4.6mW 0.5 Discrete HS/LS RDS(ON) = 8.8mW /3.3mW 78 0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20 22 Output Current (A) Output Current (A) Figure30. Figure31. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:CSD86330Q3D

CSD86330Q3D SLPS264D–OCTOBER2010–REVISEDMAY2015 www.ti.com Application Information (continued) Table 1 compares the traditional DC measured R of CSD86330Q3D versus its Z . This comparison DS(ON) DS(ON) takes into account the improved efficiency associated with TI’s patented packaging technology. As such, when comparing TI’s Power Block products to individually packaged discrete MOSFETs or dual MOSFETs in a standard package, the in-circuit switching performance of the solution must be considered. In this example, individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC measured R values that are equivalent to CSD86330Q3D’s Z value in order to have the same DS(ON) DS(ON) efficiencyperformanceatfullload.Midtolight-loadefficiencywillstillbelowerwithindividuallypackageddiscrete MOSFETsordualMOSFETsinastandardpackage. Table1.ComparisonofR vsZ DS(ON) DS(ON) HS LS Parameter Typ Max Typ Max EffectiveACOn-ImpedanceZ (V =5V) 8.8 - 3.3 - DS(ON) GS DCMeasuredR (V =4.5V) 8.8 11.5 4.6 6 DS(ON) GS The CSD86330Q3D NexFET power block is an optimized design for synchronous buck applications using 5 V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems centric environment. System level performance curves such as Power Loss, Safe Operating Area, and normalizedgraphsallowengineerstopredicttheproductperformanceintheactualapplication. 6.2 Power Loss Curves MOSFET centric parameters such as R and Q are needed to estimate the loss generated by the devices. DS(ON) gd In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss performancecurves.Figure1plotsthepowerlossoftheCSD86330Q3Dasafunctionofloadcurrent.Thiscurve is measured by configuring and running the CSD86330Q3D as it would be in the final application (see Figure 32).The measured power loss is the CSD86330Q3D loss and consists of both input conversion loss and gatedriveloss.Equation1isusedtogeneratethepowerlosscurve. (V ×I )+(V ×I )–(V ×I )=PowerLoss (1) IN IN DD DD SW_AVG OUT The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C underisothermaltestconditions. 6.3 Safe Operating Curves (SOA) The SOA curves in the CSD86330Q3D data sheet provides guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4” (W) × 3.5”(L)×0.062”(T)and6copperlayersof1oz.copperthickness. 6.4 Normalized Curves The normalized curves in the CSD86330Q3D data sheet provides guidance on the Power Loss and SOA adjustments based on their application specific needs. These curves show how the power loss and SOA boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in power loss and the secondary Y-axis is the change is system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is subtractedfromtheSOAcurve. 12 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:CSD86330Q3D

CSD86330Q3D www.ti.com SLPS264D–OCTOBER2010–REVISEDMAY2015 Normalized Curves (continued) Gate Drive Input Current (IIN) Current (IDD) DriverIC CSD86330Q3D V I V A DD V A VDD BST IN V Input Voltage (V ) VoGltaatgee D (rVivDeD) V ENABLE DRVH TG CFonEtTrol Output CurreInNt (IOUT) V T V O PWM LL GR SW A PWM B Sync GND DRVL G FET P GND Averaging Averaged Switched V Circuit Node Voltage (V ) SW_AVG S0475-04 Figure32. TypicalApplication Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:CSD86330Q3D

CSD86330Q3D SLPS264D–OCTOBER2010–REVISEDMAY2015 www.ti.com 6.5 Calculating Power Loss and SOA The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following procedure will outline the steps the user should take to predict product performance for any set of system conditions. 6.5.1 DesignExample OperatingConditions: • OutputCurrent=15A • InputVoltage=12V • OutputVoltage=1.2V • SwitchingFrequency=1000kHz • Inductor=0.4µH 6.5.2 CalculatingPowerLoss • PowerLossat15A=2.2W(Figure1) • NormalizedPowerLossforinputvoltage ≈ 1.0(Figure7) • NormalizedPowerLossforoutputvoltage ≈ 0.98(Figure8) • NormalizedPowerLossforswitchingfrequency ≈ 1.17(Figure6) • NormalizedPowerLossforoutputinductor≈ 1.06(Figure9) • FinalcalculatedPowerLoss=2.2W × 1.0 ×0.98 ×1.17 ×1.06 ≈ 2.67W 6.5.3 CalculatingSOAAdjustments • SOAadjustmentforinputvoltage ≈ 0ºC(Figure7) • SOAadjustmentforoutputvoltage ≈ –0.29ºC(Figure8) • SOAadjustmentforswitchingfrequency ≈ 4.1ºC(Figure6) • SOAadjustmentforoutputinductor ≈ 1.5ºC(Figure9) • FinalcalculatedSOAadjustment=0+(–0.29)+4.1+1.5 ≈ 5.3ºC In the design example above, the estimated power loss of the CSD86330Q3D would increase to 2.67 W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.3ºC. Figure 33 graphicallyshowshowtheSOAcurvewouldbeadjustedaccordingly. 1. StartbydrawingahorizontallinefromtheapplicationcurrenttotheSOAcurve. 2. DrawaverticallinefromtheSOAcurveinterceptdowntotheboard/ambienttemperature. 3. AdjusttheSOAboard/ambienttemperaturebysubtractingthetemperatureadjustmentvalue. In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 5.3ºC. In the event the adjustment value is a negative number, subtracting the negative number wouldyieldanincreaseinallowableboard/ambienttemperature. 25 20 nt (A) 15 1 e urr C Output 10 VVGINS== 1 52VV 2 5 VOUT= 1.3V fSW= 500kHz LOUT= 1mH 3 0 0 20 40 60 80 100 120 140 BoardTemperature (°C) G028 Figure33. PowerBlockSOA 14 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:CSD86330Q3D

CSD86330Q3D www.ti.com SLPS264D–OCTOBER2010–REVISEDMAY2015 7 Recommended PCB Design Overview There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief descriptiononhowtoaddresseachparameterisprovided. 7.1 Electrical Performance The Power Block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then takenwiththePCBlayoutdesignandplacementoftheinputcapacitors,DriverIC,andoutputinductor. • The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 34). The example in Figure 34 uses 6 × 10 µF ceramic capacitors (TDK part number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8shouldfollowinorder. • The Driver IC should be placed relatively close to the Power Block Gate pins. T and B should connect to G G the outputs of the Driver IC. The T pin serves as the return path of the high-side gate drive circuitry and GR should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitorfortheDriverICwillalsoconnecttothispin. • The switching node of the output inductor should be placed relatively close to the Power Block VSW pins. Minimizing the node length between these two components will reduce the PCB conduction losses and actuallyreducetheswitchingnoiselevel. • In the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a Boost Resistor or RC snubber can be an effective way to reduce the peak ring level. The recommended Boost Resistor value will range between 1 Ω to 4.7 Ω depending on the output characteristics of Driver IC used in conjunction with the Power Block. The RC snubber values can range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Refer to TI App Note SLUP100 for more details on how to properly tune the RC snubber values. The RC snubber should be placed as close as possible to the Vsw node and PGND see Figure34 (1) 7.2 Thermal Performance The Power Block has the ability to utilize the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount ofsolderattachthatwillwickdowntheviabarrel: • Intentionallyspaceouttheviasfromeachothertoavoidaclusterofholesinagivenarea. • Use the smallest drill size allowed in your design. The example in Figure 34 uses vias with a 10 mil drill hole anda16milcapturepad. • Tenttheoppositesideoftheviawithsolder-mask. In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturingcapabilities. (1) KeongW.Kam,DavidPommerenke,“EMIAnalysisMethodsforSynchronousBuckConverterEMIRootCauseAnalysis”,Universityof Missouri–Rolla Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:CSD86330Q3D

CSD86330Q3D SLPS264D–OCTOBER2010–REVISEDMAY2015 www.ti.com Thermal Performance (continued) Figure34. RecommendedPCBLayout(TopDown) 16 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:CSD86330Q3D

CSD86330Q3D www.ti.com SLPS264D–OCTOBER2010–REVISEDMAY2015 8 Device and Documentation Support 8.1 Trademarks NexFETisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 8.2 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 8.3 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:CSD86330Q3D

CSD86330Q3D SLPS264D–OCTOBER2010–REVISEDMAY2015 www.ti.com 9 Mechanical, Packaging, and Orderable Information 9.1 Q3D Package Dimensions A E2 L E1 c1 L d1 q 5 4 4 5 b 6 3 3 6 9 E D1 D2 7 2 2 7 d e 8 1 1 8 Top View Side View d3 d2 K Pinout Bottom View Position Designation Pin 1 VIN Pin 2 VIN Pin 3 TG c Pin 4 TGR Pin 5 BG Pin 6 VSW Pin 7 VSW q Exposed tie clips may vary Pin 8 VSW Pin 9 PGND M0192-01 MILLIMETERS INCHES DIM MIN MAX MIN MAX A 1.40 1.5 0.055 0.059 b 0.280 0.400 0.011 0.016 c 0.150 0.250 0.006 0.010 c1 0.150 0.250 0.006 0.010 d 0.940 1.040 0.037 0.041 d1 0.160 0.260 0.006 0.010 d2 0.150 0.250 0.006 0.010 d3 0.250 0.350 0.010 0.014 D1 3.200 3.400 0.126 0.134 D2 2.650 2.750 0.104 0.108 E 3.200 3.400 0.126 0.134 E1 3.200 3.400 0.126 0.134 E2 1.750 1.850 0.069 0.073 e 0.650TYP 0.026TYP L 0.400 0.500 0.016 0.020 θ 0.00 — — — K 0.300TYP 0.012TYP 18 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:CSD86330Q3D

CSD86330Q3D www.ti.com SLPS264D–OCTOBER2010–REVISEDMAY2015 9.2 Land Pattern Recommendation 1.900 (0.075) 0.200 0.210 (0.008) (0.008) 0.350 (0.014) 4 5 0.440 (0.017) 0.650 2.800 (0.026) 2.390 (0.110) (0.094) 1.090 (0.043) 0.210 8 1 (0.008) 0.300 (0.012) 0.650 (0.026) 0.650 (0.026) 3.600 (0.142) M0193-01 NOTE: Dimensionsareinmm(inches). 9.3 Stencil Recommendation 0.160 (0.005) 0.550 (0.022) 0.200 (0.008) 0.300 (0.012) 5 4 0.300 0.340 (0.012) (0.013) 2.290 (0.090) 0.333 0.990 (0.013) (0.039) 8 1 0.100 (0.004) 0.350 (0.014) 0.300 (0.012) 0.850 (0.033) 3.500 (0.138) M0207-01 NOTE: Dimensionsareinmm(inches). For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCBLayoutTechniques. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:CSD86330Q3D

CSD86330Q3D SLPS264D–OCTOBER2010–REVISEDMAY2015 www.ti.com 9.4 Q3D Tape and Reel Information 0 1 0. ± 5 4.00 ±0.10 (See Note 1) 2.00 ±0.05 7 1. 8.00 ±0.10 Ø 1.50 +0.10 –0.00 00 31 0.0. +– 0 0 2. 1 5 0 50 ±0. 3.60 5. 0 3 3.60 1. M0144-01 NOTES: 1.10-sprockethole-pitchcumulativetolerance±0.2 2.Cambernottoexceed1mmin100mm,noncumulativeover250mm 3.Material:blackstatic-dissipativepolystyrene 4.Alldimensionsareinmm,unlessotherwisespecified. 5.Thickness:0.30±0.05mm 6.MSL1260°C(IRandconvection)PbFreflowcompatible Spacer 20 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:CSD86330Q3D

PACKAGE MATERIALS INFORMATION www.ti.com 13-Apr-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CSD86330Q3D LSON- DQZ 8 2500 330.0 15.4 3.6 3.6 1.7 8.0 12.0 Q1 CLIP CSD86330Q3D LSON- DQZ 8 2500 330.0 12.4 3.55 3.55 1.7 8.0 12.0 Q1 CLIP PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 13-Apr-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CSD86330Q3D LSON-CLIP DQZ 8 2500 335.0 335.0 32.0 CSD86330Q3D LSON-CLIP DQZ 8 2500 367.0 367.0 35.0 PackMaterials-Page2

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