CSD17505Q5A www.ti.com SLPS301A–DECEMBER2010–REVISEDJULY2011 30V, N-Channel NexFET™ Power MOSFETs CheckforSamples:CSD17505Q5A FEATURES PRODUCTSUMMARY 1 • UltralowQ andQ TA=25°Cunlessotherwisestated TYPICALVALUE UNIT 2• LowThermgalResigsdtance VDS DraintoSourceVoltage 30 V • AvalancheRated Qg GateChargeTotal(4.5V) 10 nC Qgd GateChargeGatetoDrain 2.7 nC • PbFreeTerminalPlating VGS=4.5V 3.7 mΩ • RoHSCompliant RDS(on) DraintoSourceOnResistance VGS=10V 2.9 mΩ • HalogenFree VGS(th) ThresholdVoltage 1.3 V • SON5-mm×6-mmPlasticPackage ORDERINGINFORMATION APPLICATIONS Device Package Media Qty Ship • Point-of-LoadSynchronousBuckin SON5-mm×6-mm 13-Inch Tapeand CSD17505Q5A 2500 Networking,Telecom,andComputingSystems PlasticPackage Reel Reel • OptimizedforControlandSynchronousFET ABSOLUTEMAXIMUMRATINGS Applications TA=25°Cunlessotherwisestated VALUE UNIT DESCRIPTION VDS DraintoSourceVoltage 30 V The NexFET™ power MOSFET has been designed VGS GatetoSourceVoltage ±20 V tominimizelossesinpowerconversionapplications. ContinuousDrainCurrent,TC=25°C 100 A ID ContinuousDrainCurrent(1) 24 A TopView IDM PulsedDrainCurrent,TA=25°C(2) 153 A S 1 8 D PD PowerDissipation(1) 3.2 W TJ, OperatingJunctionandStorage –55to150 °C TSTG TemperatureRange S 2 7 D AvalancheEnergy,singlepulse EAS ID=76A,L=0.1mH,RG=25Ω 290 mJ S 3 6 D (1) Typical R = 39°C/W on 1-inch2 (6.45-cm2), 2-oz. θJA D (0.071-mmthick)Cupadona0.06-inch(1.52-mm)thickFR4 G 4 5 D PCB. (2) Pulseduration≤300μs,dutycycle≤2% P0093-01 SPACE SPACE R vsV GATECHARGE DS(on) GS 16 10 Wm 14 ID = 20A V) 9 IVDD =D 2=0 1A5V e - 12 ge ( 8 anc olta 7 sist 10 e V 6 e c e R 8 our 5 n-Stat 6 e-to-S 4 O at 3 - ()Son 4 - GGS 2 RD 2 TC = 25°C V 1 TC = 125ºC 0 0 0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 18 20 VGS - Gate-to- Source Voltage - V Qg - Gate Charge - nC (nC) 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. NexFETisatrademarkofTexasInstruments. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2010–2011,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

CSD17505Q5A SLPS301A–DECEMBER2010–REVISEDJULY2011 www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ELECTRICAL CHARACTERISTICS (T =25°Cunlessotherwisestated) A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT StaticCharacteristics BV DraintoSourceVoltage V =0V,I =250μA 30 V DSS GS DS I DraintoSourceLeakageCurrent V =0V,V =24V 1 μA DSS GS DS I GatetoSourceLeakageCurrent V =0V,V =20V 100 nA GSS DS GS V GatetoSourceThresholdVoltage V =V ,I =250μA 1 1.3 1.8 V GS(th) DS GS DS V =4.5V,I =20A 3.7 4.6 mΩ GS DS R DraintoSourceOnResistance DS(on) V =10V,I =20A 2.9 3.5 mΩ GS DS g Transconductance V =15V,I =20A 82 S fs DS DS DynamicCharacteristics C InputCapacitance 1560 1980 pF iss V =0V,V =15V, C OutputCapacitance GS DS 1030 1330 pF oss f=1MHz C ReverseTransferCapacitance 65 85 pF rss R SeriesGateResistance 1 2 Ω G Q GateChargeTotal(4.5V) 10 13 nC g Q GateChargeGatetoDrain 2.7 nC gd V =15V,I =20A DS DS Q GateChargeGatetoSource 3.5 nC gs Q GateChargeatVth 1.9 nC g(th) Q OutputCharge V =13.7V,V =0V 26 nC oss DS GS t TurnOnDelayTime 8.3 ns d(on) tr RiseTime VDS=15V,VGS=4.5V, 11.5 ns td(off) TurnOffDelayTime IDS=20A,RG=2Ω 15 ns t FallTime 6.1 ns f DiodeCharacteristics V DiodeForwardVoltage I =20A,V =0V 0.8 1 V SD SD GS Q ReverseRecoveryCharge 30 nC rr V =13.7V,I =20A,di/dt=300A/μs DD F t ReverseRecoveryTime 28 ns rr THERMAL CHARACTERISTICS (T =25°Cunlessotherwisestated) A PARAMETER MIN TYP MAX UNIT R ThermalResistanceJunctiontoCase(1) 1.3 °C/W θJC R ThermalResistanceJunctiontoAmbient(1)(2) 50 °C/W θJA (1) R isdeterminedwiththedevicemountedona1-inch2(6.45-cm2),2-oz.(0.071-mmthick)Cupadona1.5-inch×1.5-inch(3.81-cm× θJC 3.81-cm),0.06-inch(1.52-mm)thickFR4PCB.R isspecifiedbydesign,whereasR isdeterminedbytheuser’sboarddesign. θJC θJA (2) DevicemountedonFR4materialwith1-inch2(6.45-cm2),2-oz.(0.071-mmthick)Cu. 2 Copyright©2010–2011,TexasInstrumentsIncorporated

CSD17505Q5A www.ti.com SLPS301A–DECEMBER2010–REVISEDJULY2011 GATE Source GATE Source N N - - C C h h a a n n MaxR =50°C/W MaxR =120°C/W 5x θJA 5x θJA 6 whenmountedon 6 whenmountedona Q Q FN 1inch2(6.45cm2)of FN minimumpadareaof TT 2-oz.(0.071-mmthick) TT 2-oz.(0.071-mmthick) A A M Cu. M Cu. A I X N R R e e v v 3 DRAIN 3 DRAIN M0137-01 M0137-02 TYPICAL MOSFET CHARACTERISTICS (T =25°Cunlessotherwisestated) A e c n a d 0.5 e p 0.3 m al I 0.1 m er 0.05 h T Duty Cycle = t /t 0.02 1 2 d e 0.01 z ali P m or N Single Pulse t1 - t A 2 ZqJ Typical RqJA= 98°C/W (min Cu) TJ= P´ZqJA´RqJA Figure1. TransientThermalImpedance Copyright©2010–2011,TexasInstrumentsIncorporated 3

CSD17505Q5A SLPS301A–DECEMBER2010–REVISEDJULY2011 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (T =25°Cunlessotherwisestated) A TEXTADDEDFORSPACING TEXTADDEDFORSPACING 80 100 VDS = 5V 70 A A nt - 60 nt - 10 e e urr urr C 50 C e e 1 c c our 40 our S S o- o- 0.1 n-t 30 n-t ai ai - DrS 20 VVGGSS == 34..05VV - DrS0.01 TC = 125°C ID 10 VGS = 6.0V ID TC = 25°C VGS = 10V TC = −55°C 0 0.001 0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.5 1 1.5 2 2.5 3 3.5 4 VDS - Drain-to-Source Voltage - V VGS - Gate-to-Source Voltage - V Figure2.SaturationCharacteristics Figure3.TransferCharacteristics TEXTADDEDFORSPACING TEXTADDEDFORSPACING 10 100 e (V) 89 IVDD =D 2=0 1A5V CCCiorssssss === C CCgdgdsd ++ CCggsd e-to-Source Voltag 4567 Capacitance − nF 110 at 3 − - GS 2 C 0.1 G V 1 0 0.01 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 Qg - Gate Charge - nC (nC) VDS - Drain-to-Source Voltage - V Figure4.GateCharge Figure5.Capacitance TEXTADDEDFORSPACING TEXTADDEDFORSPACING 2.1 16 ID = 250µA ID = 20A V 1.8 Wm 14 e - e - 12 d Voltag 11..25 esistanc 10 V - Threshol()GSth 000...369 R - On-State R()DSon 2468 TC = 25°C TC = 125ºC 0 0 −75 −25 25 75 125 175 0 1 2 3 4 5 6 7 8 9 10 TC - Case Temperature - ºC VGS - Gate-to- Source Voltage - V Figure6.ThresholdVoltagevs.Temperature Figure7.On-StateResistancevs.Gate-to-SourceVoltage 4 Copyright©2010–2011,TexasInstrumentsIncorporated

CSD17505Q5A www.ti.com SLPS301A–DECEMBER2010–REVISEDJULY2011 TYPICAL MOSFET CHARACTERISTICS (continued) (T =25°Cunlessotherwisestated) A TEXTADDEDFORSPACING TEXTADDEDFORSPACING 1.8 100 ID = 20A TC = 25°C stance 11..46 VGS = 10V ent - A 10 TC = 125°C esi urr 1 e R 1.2 n C Stat 1 Drai 0.1 n- o- d O 0.8 ce-t alize 0.6 Sour 0.01 m − or D 0.001 N 0.4 IS 0.2 0.0001 −75 −25 25 75 125 175 0 0.2 0.4 0.6 0.8 1 TC - Case Temperature - ºC VSD − Source-to-Drain Voltage - V Figure8.NormalizedOn-StateResistancevs.Temperature Figure9.TypicalDiodeForwardVoltage TEXTADDEDFORSPACING TEXTADDEDFORSPACING 200 1000 100 TC = 125°C Source Current - A 110 1ms alanche Current - A 100 TC = 25°C Drain-to- 0.1 11100sm0mss Peak Av 10 I - DS0.01 SingleD PCulse, Min Cu Area I - ()AV Typical RthJA = 98ºC/W 0.001 1 0.01 0.1 1 10 100 0.01 0.1 1 10 VDS - Drain-to-Source Voltage - V t(AV) - Time in Avalanche - ms Figure10.MaximumSafeOperatingArea Figure11.SinglePulseUnclampedInductiveSwitching TEXTADDEDFORSPACING TEXTADDEDFORSPACING 120 A nt - 100 e Curr 80 e c ur o 60 S o- n- t 40 ai Dr - S 20 D I 0 −50 −25 0 25 50 75 100 125 150 175 TC - Case Temperature - ºC Figure12. MaximumDrainCurrentvs.Temperature Copyright©2010–2011,TexasInstrumentsIncorporated 5

CSD17505Q5A SLPS301A–DECEMBER2010–REVISEDJULY2011 www.ti.com MECHANICAL DATA Q5A Package Dimensions E2 L H K q 1 8 8 1 2 7 7 2 e D1 D2 3 6 6 3 5 4 5 4 b L1 Top View Side View Bottom View q A c E1 E Front View M0135-01 MILLIMETERS DIM MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.34 D1 4.80 4.90 5.00 D2 3.61 3.81 4.02 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 e 1.17 1.27 1.37 H 0.41 0.56 0.71 K 1.10 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 θ 0° 12° 6 Copyright©2010–2011,TexasInstrumentsIncorporated

CSD17505Q5A www.ti.com SLPS301A–DECEMBER2010–REVISEDJULY2011 Recommended PCB Pattern 4.900 (0.193) 0.630 (0.025) 0.605 (0.024) 5 4 0.620 (0.024) 4.460 1.270 (0.176) (0.050) 0.650 (0.026) 8 1 3.102 (0.122) 1.798 (0.071) 0.700 (0.028) M0139-01 NOTE: Dimensionsareinmm(inches). TEXT ADDED FOR SPACING Stencil Recommendation 0.500 (0.020) 1.235 (0.049) 1.585 (0.062) 0.500 (0.020) 5 4 0.450 (0.018) 1.570 (0.062) 0.620 (0.024) 1.270 4.260 (0.050) (0.168) 1.570 (0.062) PCB Pattern 8 1 0.632 (0.025) 1.088 (0.043) 3.037 (0.120) Stencil Opening M0209-01 NOTE: Dimensionsareinmm(inches). TEXT ADDED FOR SPACING For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCBLayoutTechniques. Copyright©2010–2011,TexasInstrumentsIncorporated 7

CSD17505Q5A SLPS301A–DECEMBER2010–REVISEDJULY2011 www.ti.com Q5A Tape and Reel Information K0 0.30 ±0.05 4.00 ±0.10 (See Note 1) 2.00 ±0.05 Ø 1.50 +0.10 –0.00 1.75 ±0.10 5.50 ±0.05 12.00 ±0.30 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN R 0.30TYP A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 M0138-01 NOTES: 1.10-sprockethole-pitchcumulativetolerance±0.2 2.Cambernottoexceed1mmin100mm,noncumulativeover250mm 3.Material:blackstatic-dissipativepolystyrene 4.Alldimensionsareinmm(unlessotherwisespecified) 5.A0andB0measuredonaplane0.3mmabovethebottomofthepocket Spacer REVISION HISTORY ChangesfromOriginal(December2010)toRevisionA Page • ChangedV intheAbsMaxRatingstableFrom:+20/-12VTo:±20V ............................................................................... 1 GS • Changedfrom+20/-12Vto20V ............................................................................................................................................ 2 8 Copyright©2010–2011,TexasInstrumentsIncorporated

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CSD17505Q5A ACTIVE VSONP DQJ 8 2500 Pb-Free (RoHS SN Level-1-260C-UNLIM -55 to 150 CSD17505 Exempt) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

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