CS8952 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Features Description (cid:122)Single-Chip IEEE 802.3 Physical Interface IC for The CS8952 uses CMOS technology to deliver a high- 100BASE-TX, 100BASE-FX and 10BASE-T performance, low-cost 100BASE-X/10BASE-T Physical (cid:122)Adaptive Equalizer provides Extended Length Layer (PHY) line interface. It makes use of an adaptive Operation (>160 m) with Superior Noise equalizer optimized for noise and near end crosstalk Immunity and NEXT Margin (NEXT) immunity to extend receiver operation to cable (cid:122)Extremely Low Transmit Jitter (<400 ps) lengths exceeding 160m. In addition, the transmit cir- (cid:122)Low Common Mode Noise on TX Driver for cuitry has been designed to provide extremely low Reduced EMI Problems transmit jitter (<400ps) for improved link partner perfor- (cid:122)Integrated RX and TX Filters for 10BASE-T mance. Transmit driver common mode noise has been (cid:122)Compensation for Back-to-Back “Killer Packets” minimized to reduce EMI for simplified FCC certification. (cid:122)Digital Interfaces Supported The CS8952 incorporates a standard Media Indepen- – Media Independent Interface (MII) for 100BASE-X dent Interface (MII) for easy connection to a variety of 10 and 10BASE-T and 100Mb/s Media Access Controllers (MACs). The – Repeater 5-bit code-group interface (100BASE-X) CS8952 also includes a pseudo-ECL interface for use – 10BASE-T Serial Interface with 100Base-FX fiber interconnect modules. (cid:122) Register Set Compatible with DP83840A (cid:122)IEEE 802.3 Auto-Negotiation with Next Page ORDERING INFORMATION Support See “Ordering Information” on page80. (cid:122)Six LED drivers (LNK, COL, FDX, TX, RX, and SPD) (cid:122)Low power (135 mA Typ) CMOS design operates on a single 5 V supply CS8952 10BaseT/100Base-X Transceiver 10/100 TX_ETTRXTX/DXT_[C_X3EDL:0NK4] E4nBc/o5dBer MSEacnnraccmhoedbseletrerr EMnLcoTd-3er S1lC0eFBowinla tRtesrroealTte MUX TTXX+-, MIMI_MCDIRDRIOQCS Media Independent Interface(MII) 10M/UX100 D4eBc/o5dBer DFeIinbstceerrra fNmaRcbeZleIr FIDinbMeteecLrr oTfNad-R3ceerZI 10S0BlicaesreT BACaEdsoECaemCLpli npLtRieev Dee nWcr siEevaaiqetvni.roe d&nrer RRTTRRXXXXXX____+-NNNN,RRRRZZZZ+-+-,, COL Manchester 10BaseT 10BaseT RX_ER/RXD4 Decoder Slicer Filter RX_DV RXD[3:0] LED1 RRXX__CELNK CoRnetrgoMils/ISItetrastus ManaLginekment RTeicmoivnegry NegAoutitaotion DLriEveDrs LLLEEEDDD234 LED5 Copyright © Cirrus Logic, Inc. 2007 http://www.cirrus.com (All Rights Reserved) JAN ‘07 DS206F1

CS8952 TABLE OF CONTENTS 1. SPECIFICATIONS AND CHARACTERISTICS......................................................... 3 2. INTRODUCTION .....................................................................................................18 2.1 High Performance Analog.............................................................................18 2.2 Low Power Consumption..............................................................................18 2.3 Application Flexibility.....................................................................................18 2.4 Typical Connection Diagram.........................................................................18 3. FUNCTIONAL DESCRIPTION ................................................................................18 3.1 Major Operating Modes.................................................................................20 3.1.1 100BASE-X MII Application (TX and FX) ...........................................20 Symbol Encoding and Decoding ...........................................................20 100Mb/s Loopback ...............................................................................22 3.1.2 100BASE-X Repeater Application ......................................................22 3.1.3 10BASE-T MII Application ..................................................................23 Full and Half Duplex operation ..............................................................23 Collision Detection ................................................................................23 Jabber ...................................................................................................23 Link Pulses ............................................................................................23 Receiver Squelch ..................................................................................23 10BASE-T Loopback .............................................................................23 Carrier Detection ...................................................................................24 3.1.4 10BASE-T Serial Application ..............................................................24 3.2 Auto-Negotiation...........................................................................................24 3.3 Reset Operation............................................................................................25 3.4 LED Indicators...............................................................................................25 4. MEDIA INDEPENDENT INTERFACE (MII) .............................................................25 4.1 MII Frame Structure......................................................................................26 4.2 MII Receive Data...........................................................................................26 4.3 MII Transmit Data..........................................................................................27 4.4 MII Management Interface............................................................................27 4.5 MII Management Frame Structure................................................................28 5. CONFIGURATION ..................................................................................................29 5.1 Configuration At Power-up/Reset Time.........................................................29 5.2 Configuration Via Control Pins......................................................................29 5.3 Configuration via the MII...............................................................................29 6. CS8952 REGISTERS ..............................................................................................30 7. DESIGN CONSIDERATIONS ..................................................................................62 7.1 Twisted Pair Interface...................................................................................62 7.2 100BASE-FX Interface..................................................................................62 7.3 Internal Voltage Reference...........................................................................63 7.4 Clocking Schemes........................................................................................63 7.5 Recommended Magnetics............................................................................64 7.6 Power Supply and Decoupling......................................................................64 7.7 General Layout Recommendations...............................................................65 8. PIN DESCRIPTIONS ...............................................................................................67 9. PACKAGE DIMENSIONS....................................................................................... 79 10. ORDERING INFORMATION .................................................................................80 11. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ...........80 12. REVISION HISTORY ............................................................................................81 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 2 DS206F1

CS8952 1. SPECIFICATIONS AND CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS = 0 V, all voltages with respect to 0 V.) Parameter Symbol Min Max Unit Power Supply V -0.3 6.0 V DD V -0.3 6.0 DD_MII Input Current Except Supply Pins - +/-10.0 mA Input Voltage -0.3 V + 0.3 V DD Ambient Temperature Power Applied -55 +125 °C Storage Temperature -65 +150 °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS = 0 V, all voltages with respect to 0 V.) Parameter Symbol Min Max Unit Power Supply Core V 4.75 5.25 V DD MII V 3.0 5.25 V DD_MII Operating Ambient Temperature T 0 70 °C A QUARTZ CRYSTAL REQUIREMENTS (If a 25 MHz quartz crystal is used, it must meet the fol- lowing specifications.) Parameter Min Typ Max Unit Parallel Resonant Frequency - 25.0 - MHz Resonant Frequency Error (CL = 15 pF) -50 - +50 ppm Resonant Frequency Change Over Operating Temperature -40 - +40 ppm Crystal Load Capacitance - 15 - pF Motional Crystal Capacitance - 0.021 - pF Series Resistance - - 18 Ω Shunt Capacitance - - 7 pF CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 3 DS206F1

CS8952 DC CHARACTERISTICS (Over recommended operating conditions) Parameter Symbol Min Typ Max Unit External Oscillator XTAL_I Input Low Voltage V -0.3 - 0.5 V IXH XTAL_I Input High Voltage V 3.5 - VDD+0.5 V IXH XTAL_I Input Low Current I -40 - - µA IXL XTAL_I Input High Current I - - 40 µA IXH XTAL_I Input Capacitance C - 35 pF L XTAL_I Input Cycle Time t 39.996 - 40.004 ns IXC XTAL_I Input Low Time t 18 - 22 ns IXL XTAL_I Input High Time t 18 - 22 ns XH Power Supply Power Supply Current 100BASE-TX (Note 1) I - 135 145 mA DD 100BASE-FX (Note 1) - 90 - 10BASE-T (Note 1) - 80 - Hardware Power-Down (Note 1) I - 900 - µA DDHPDN Software Power-Down (Note 1) I - 20 - mA DDSPDN Low Power Power-Up (Note 1) I - 900 - µA DDSLPUP Digital I/O Output Low Voltage V V OL CLK25, MII_IRQ, SPD10, SPD100 I = 4.0mA - - 0.4 OL - - 0.4 LED[4:0] I = 10.0mA OL Output Low Voltage (MII_DRV = 1) V V OL COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK I = 4.0mA - - 0.4 OL VDD_MII = 5V; I = 43.0mA - - 3.05 OL - - 2.1 VDD_MII = 3.3V, I = 26.0mA OL Output Low Voltage (MII_DRV = 0) V V OL COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK I = 4.0mA - - 0.4 OL Output High Voltage V V OH CLK25, SPD10, SPD100 I = -4.0mA 2.4 - - OH Output High Voltage (MII_DRV = 1) V V OH COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK I = -4.0mA 2.4 - - OH VDD_MII = 5V; I = -20.0mA 1.1 - - OH 1.1 - - VDD_MII = 3.3V, I = -20.0mA OH CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 4 DS206F1

CS8952 DC CHARACTERISTICS (CONTINUED) (Over recommended operating conditions) Parameter Symbol Min Typ Max Unit Output High Voltage (MII_DRV = 0) V V OH COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK I = -4.0mA 2.4 - - OH Input Low Voltage V - - 0.8 V IL All Inputs Except AN[1:0], TCM, TXSLEW[1:0] Input High Voltage V 2.0 - - V IH All Inputs Except AN[1:0], TCM, TXSLEW[1:0] Tri-Level Input Voltages V - - 1/3 V V IL DD_MII AN[1:0], TCM, TXSLEW[1:0] - 20% V 1/3 V - 2/3 V IM DD_MII DD_MII + 20% - 20% V 2/3 V - - IH DD_MII + 20% Input Low Current I µA IL MDC, TXD[3:0], TX_CLK, TX_EN, TX_ER V = 0.0V -20 - - I -3800 - - MDIO V = 0.0V I Input High Current I µA IH MDC, TXD[3:0], TX_CLK, TX_EN, TX_ER V = 5.0V - - 200 I - - 20 MDIO V = 5.0V I Input Leakage Current I µA LEAK All Other Inputs 0<=V<=V -10 - +10 DD Notes: 1. With digital outputs connected to CMOS loads. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 5 DS206F1

CS8952 10BASE-T CHARACTERISTICS Parameter Symbol Min Typ Max Unit 10BASE-T Interface Transmitter Differential Output Voltage (Peak) V 2.2 - 2.8 V OD Receiver Normal Squelch Level (Peak) V 300 - 525 mV ISQ Receiver Low Squelch Level (LoRxSquelch bit V 125 - 290 mV SQL set) 10BASE-T Transmitter TXD Pair Jitter into 100 Ω Load t - - 8 ns TTX1 TXD Pair Return to ≤ 50 mV after Last Positive t - - 4.5 µs TTX2 Transition TXD Pair Positive Hold Time at End of Packet t 250 - - ns TTX3 10BASE-T Receiver Allowable Received Jitter at Bit Cell Center t - - +/-13.5 ns TRX1 Allowable Received Jitter at Bit Cell Boundary t - - +/-13.5 ns TRX2 10BASE-T Link Integrity First Transmitted Link Pulse after Last Transmit- t 15 16 17 ms LN1 ted Packet Time Between Transmitted Link Pulses t 15 16 17 ms LN2 Width of Transmitted Link Pulses t 60 - 200 ns LN3 Minimum Received Link Pulses Separation t 2 5 7 ms LN4 Maximum Received Link Pulse Separation t 25 52 150 ms LN5 Last Receive Activity to Link Fail (Link Loss t 50 52 150 ms LN6 Timer) 10Base-T Jabber/Unjabber Timing Maximum Transmit Time - 105 - ms Unjabber Time - 406 - ms t TTX2 TXD± t TTX1 t TTX3 RXD± t t t RTX1 RTX2 RTX3 tRTX4 Carrier Sense (Internal) t t t LN1 LN2 LN3 TXD± t t LN4 LN5 RXD± t LN6 LINKLED CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 6 DS206F1

CS8952 100BASE-X CHARACTERISTICS Parameter Symbol Min Typ Max Unit 100BASE-TX Transmitter TX Differential Output Voltage (Peak) V 0.95 - 1.05 V OP Signal Amplitude Symmetry V 98 - 102 % SYM Signal Rise/Fall Time t 3.0 - 5.0 ns RF Rise/Fall Symmetry t - - 0.5 ns RFS Duty Cycle Distortion t - - +/-0.5 ns DCD Overshoot/Undershoot t - - 5 % OS Transmit Jitter t - 400 1400 ps JT TX Differential Output Impedance Z - 100 - ohms OUT 100BASE-TX Receiver Receive Signal Detect Assert Threshold - - 1.0 V p-p Receive Signal Detect De-assert Threshold 0.2 - - V p-p Receive Signal Detect Assert Time - - 1000 µs Receive Signal Detect De-assert Time - - 350 µs 100BASE-FX Transmitter TX_NRZ+/- Output Voltage - Low V -1.830 - -1.605 V 1 TX_NRZ+/- Output Voltage - High V -1.035 - -0.880 V 2 Signal Rise/Fall Time T - - 1.6 ns RF 100Base-FX Receiver RX_NRZ+/- Input Voltage - Low V -1.830 - -1.605 V 3 RX_NRZ+/- Input Voltage - High V -1.035 - -0.880 V 4 Common Mode Input Range V - 3.56 - V CMIP RX/TX Signaling for 100Base-FX V DD V V 2 4 V V 1 3 TX_NRZ+/- RX_NRZ+/- 0 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 7 DS206F1

CS8952 100BASE-TX MII RECEIVE TIMING - 4B/5B ALIGNED MODES Parameter Symbol Min Typ Max Unit RX_CLK Period t - 40 - ns P RX_CLK Pulse Width t t - 20 - ns WL, WH RXD[3:0],RX_ER/RXD4,RX_DV setup to rising t 10 - - ns SU edge of RX_CLK RXD[3:0],RX_ER/RXD4,RX_DV hold from rising t 10 - - ns HD edge of RX_CLK CRS to RXD latency 4B Aligned t 2 3 - 6 8 BT DLAT 5B Aligned 2 3 - 6 8 “Start of Stream” to CRS asserted t - 10 11 BT CRS1 “End of Stream” to CRS de-asserted t - - 21 BT CRS2 “Start of Stream” to COL asserted t - - 11 BT COL1 “End of Stream” to COL de-asserted t - - 21 BT COL2 RX_EN asserted to RX_DV, RXD[3:0] valid t - TBD - ns EN RX_EN de-asserted to RX_DV, RXD[3:0]. t - TBD - ns DIS RX_ER/RXD4 in high impedance state RX+/- SSttarerta omf SEtnrde aomf IN t CRS2 t CRS1 CRS t OUT COL2 t COL1 COL OUT t EN t DIS RX_EN IN t RLAT RX_DV OUT t t SU HD RXD[3:0], OUT RX_ER/RXD4 t P RX_CLK OUT t t WL WH CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 8 DS206F1

CS8952 100BASE-TX MII RECEIVE TIMING - 5B BYPASS ALIGN MODE Parameter Symbol Min Typ Max Unit RX_CLK Period t - 40 - ns P RX_CLK Pulse Width t t - 20 - ns WL, WH RXD[4:0] setup to rising edge of RX_CLK t 10 - - ns SU RXD[4:0] hold after rising edge of RX_CLK t 10 - - ns HD Start of 5B symbol to symbol output on RX[4:0] t 5 - 9 BT RLAT 5B Mode RX+/- RX Sy0mbol RX SNy-m1bol RX SNymbol IN tRLAT tSU tHD RXD[4:0], RX Data RX Data OUT 0 1 t P RX_CLK OUT t t WL WH CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 9 DS206F1

CS8952 100BASE-TX MII TRANSMIT TIMING - 4B/5B ALIGN MODES Parameter Symbol Min Typ Max Unit TXD[3:0] Setup to TX_CLK High t 10 - - ns SU1 TX_EN Setup to TX_CLK High t 10 - - ns SU2 TXD[3:0] Hold after TX_CLK High t 0 - - ns HD1 TX_ER Hold after TX_CLK High t 0 - - ns HD2 TX_EN Hold after TX_CLK High t 0 - - ns HD3 TX_EN “high” to CRS asserted latency t - 8 BT CRS1 TX_EN “low” to CRS de-asserted latency t - 8 BT CRS2 TX_EN “high” to TX+/- output (TX Latency) t 6 7 8 BT LAT TX_CLK Input/Output t t SU2 HD2 TX_EN Input tSU1 tHD1 TXD[3:0], Data Input TX_ER/TXD4 IN tCRS1 tCRS2 CRS Output t LAT TX+/- Symbol Output Out CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 10 DS206F1

CS8952 100BASE-TX MII TRANSMIT TIMING - 5B BYPASS ALIGN MODE Parameter Symbol Min Typ Max Unit TXD[4:0] Setup to TX_CLK High t 10 - - ns SU1 TXD[4:0] Hold after TX_CLK High t 0 - - ns HD1 TX_ER Hold after TX_CLK High t 0 - - ns HD2 TXD[4:0] Sampled to TX+/- output (TX Latency) t - 6 7 ns LAT TX_CLK Input/Output tSU1 tHD1 TXD[4:0] Data Input IN t LAT TX+/- Symbol Output OUT CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 11 DS206F1

CS8952 10BASE-T MII RECEIVE TIMING Parameter Symbol Min Typ Max Unit RX_CLK Period t - 400 - ns P RX_CLK Pulse Width t t - 200 - ns WL, WH RXD[3:0], RX_ER, RX_DV setup to rising edge of t 30 - - ns SU RX_CLK RXD[3:0], RX_ER, RX_DV hold from rising edge t 30 - - ns HD of RX_CLK RX data valid from CRS t - 8 10 BT RLAT RX+/- preamble to CRS asserted t - 5 7 BT CRS1 RX+/- end of packet to CRS de-asserted t 2.5 3 BT CRS2 RX+/- preamble to COL asserted t 0 - 7 BT COL1 RX+/- end of packet to COL de-asserted t - - 3 BT COL2 RX_EN asserted to RX_DV, RXD[3:0], RX_ER t - - 60 ns EN valid RX_EN de-asserted to RX_DV, RXD[3:0]. RX_ER t - - 60 ns DIS in high impedance state RX+/- IN t CRS2 t CRS1 CRS t OUT COL2 t COL1 COL OUT t EN t DIS RX_EN IN t RLAT RX_DV t t OUT SU HD RXD[3:0], OUT RX_ER RX_CLK tWL OUT t WH t P CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 12 DS206F1

CS8952 10BASE-T MII TRANSMIT TIMING Parameter Symbol Min Typ Max Unit TXD[3:0] Setup to TX_CLK High t 10 - - ns SU1 TX_ER Setup to TX_CLK High t 10 - - ns SU2 TX_EN Setup to TX_CLK High t 10 - - ns SU3 TXD[3:0] Hold after TX_CLK High t 0 - - ns HD1 TX_ER Hold after TX_CLK High t 0 - - ns HD2 TX_EN Hold after TX_CLK High t 0 - - ns HD3 TX_EN “high” to CRS asserted latency t 0 - 4 BT CRS1 TX_EN “low” to CRS de-asserted latency t 0 - 16 BT CRS2 TX_EN “high” to TX+/- output (TX Latency) t 6 - 14 BT LAT SQE Timing COL (SQE) Delay after CRS de-asserted t 0.65 0.9 1.6 µs COL COL (SQE) Pulse Duration t 0.65 1.0 1.6 µs COLP 10BASE-T Transmit Timing TX_CLK Input/Output t t SU3 HD3 TX_EN Input t t SU2 HD2 TX_ER Input tSU1 tHD1 Input TXD[3:0] tCRS1 tCRS2 CRS Output t LAT TX+/- Valid Output Data SQE Timing TX_CLK Input/Output t COL SQE Output t SQEP CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 13 DS206F1

CS8952 10BASE-T SERIAL RECEIVE TIMING Parameter Symbol Min Typ Max Unit RX+/- active to RXD[0] active t - - 1200 ns DATA RX+/- active to CRS active t - - 600 ns CRS RXD[0] setup from RX_CLK t 35 - - ns RDS RXD[0] hold from RX_CLK t 50 - - ns RDH RX_CLK hold after CRS off t 5 - - ns RCH RXD[0] throughput delay t - - 250 ns RD CRS turn off delay t - - 400 ns CRSOFF RX+/- IN tCRSOFF tRCH t CRS CRS tRD OUT RX_CLK OUT tDATA tSU tHD RXD[0] OUT CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 14 DS206F1

CS8952 10BASE-T SERIAL TRANSMIT TIMING Parameter Symbol Min Typ Max Unit TX_EN Setup from TX_CLK t 10 - - ns EHCH TX_EN Hold after TX_CLK t 10 - - ns CHEL TXD[0] Setup from TX_CLK t 10 - - ns DSCH TXD[0] Hold after TX_CLK t 10 - - ns CHDU Transmit start-up delay t - - 500 ns STUD Transmit throughput delay t - - 500 ns TPD TX_CLK Input/Output t EHCH t CHEL TX_EN Input t DSCH t CHDU Input TXD[0] tSTUD tPD TX+/- Valid Output Data CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 15 DS206F1

CS8952 AUTO NEGOTIATION / FAST LINK PULSE TIMING Parameter Symbol Min Typ Max Unit FLP burst to FLP burst t 15 16 17 ms BTB FLP burst width t - 2 - ms FLPW Clock/Data pulses per burst 17 - 33 ea. - Clock/Data pulse width t - 100 - ns PW Clock pulse to Data pulse t 55.5 64 69.5 µs CTD Clock pulse to clock pulse t 111 128 139 µs CTC TX+/- t FLPW t BTB Clock Data Clock Pulse Pulse Pulse TX+/- t t PW PW t CTD t CTC CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 16 DS206F1

CS8952 SERIAL MANAGEMENT INTERFACE TIMING Parameter Symbol Min Typ Max Unit MDC Period t 60 - - ns p MDC Pulse Width t t 40 - 60 % WL,WH MDIO Setup to MDC (MDIO as input) t 10 - - ns MD1 MDIO Hold after MDC (MDIO as input) t 10 - - ns MD2 MDC to MDIO valid (MDIO as output) t 0 - 40 ns MD3 DIRECTION: IN or OUT of chip MDC IN t t MD1 MD2 MDIO Valid DataValid Data IN t MD3 MDIO Valid Data OUT CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 17 DS206F1

CS8952 2. INTRODUCTION to the Analog Design Considerations section for detailed information on power supply requirements The CS8952 is a complete physical-layer transceiv- and decoupling, crystal and magnetics require- er for 100BASE-TX and 10BASE-T applications. ments, and twisted-pair and fiber transceiver con- Additionally, the CS8952 can be used with an ex- nections. ternal optical module for 100BASE-FX. 3. FUNCTIONAL DESCRIPTION 2.1 High Performance Analog The CS8952 is a complete physical-layer transceiv- The highly integrated mixed-signal design of the er for 100BASE-TX and 10BASE-T applications. CS8952 eliminates the need for external analog cir- It provides a Physical Coding Sub-layer for com- cuitry such as external transmit or receive filters. munication with an external MAC (Media Access The CS8952 builds upon Cirrus Logic’s experience Controller). The CS8952 also includes a complete in pioneering the high-volume manufacturing of Physical Medium Attachment layer and a 10BASE-T integrated circuits with “true” internal 100BASE-TX and 10BASE-T Physical Medium filters. The CS8952, CS8920, CS8904, and Dependent layer. Additionally, the CS8952 pro- CS8900 include fifth-order, continuous-time But- vides a PECL interface to an external optical mod- terworth 10BASE-T transmit and receive filters, al- ule for 100BASE-FX applications. lowing those products to meet 10BASE-T wave shape, emission, and frequency content require- The primary digital interface to the CS8952 is an ments without external filters. enhanced IEEE 802.3 Media Independent Interface (MII). The MII supports parallel data transfer, ac- 2.2 Low Power Consumption cess to the CS8952 Control and Status registers, The CS8952 is implemented in low power CMOS, and several status and control pins. The CS8952's consuming only 135 mA typically. Three low-pow- operating modes can be tailored to support a wide er modes are provided to make the CS8952 ideal variety of applications, including low-latency for power sensitive applications such as CardBus. 100BASE-TX repeaters, switches and MII-based network interface cards. 2.3 Application Flexibility For 100BASE-TX applications, the digital data in- The CS8952’s digital interface and operating terface can be either 4-bit parallel (nibbles) or 5-bit modes can be tailored to efficiently support a wide parallel (code-groups). For 10BASE-T applica- variety of applications. For example, the Media In- tions, the digital data format can be either 4-bit par- dependent Interface (MII) supports 100BASE-TX, allel (nibbles) or one-bit serial. 100BASE-FX and 10BASE-T NIC cards, switch ports and router ports. Additionally, the low-laten- The CS8952 is controlled primarily by configura- cy “repeater” interface mode minimizes data delay tion registers via the MII Management Interface. through the CS8952, facilitating system compli- Additionally, a number of the most fundamental ance with overall network delay budgets. To sup- register bits can be set at power-up and reset time port 10BASE-T applications, the CS8952 provides by connecting pull-up or pull-down resistors to ex- a 10BASE-T serial port (Seven-wire ENDEC inter- ternal pins. face). The CS8952's MII interface is enhanced beyond IEEE requirements by register extensions and the 2.4 Typical Connection Diagram addition of pins for MII_IRQ, RX_EN, and ISO- Figure 1 illustrates a typical MII to CS8952 appli- DEF signals. The MII_IRQ pin provides an inter- cation with twisted-pair and fiber interfaces. Refer CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 18 DS206F1

CS8952 VDD_MII 4.99 kΩ 25 MHz 0.1 µF 4.7 kΩ 4.7 kΩ 1.5 kΩ XTAL_IXTAL_O VSS18 RES VSS17 MDIO 49.9 Ω 49.9 Ω MDC 4 TXD RX+ SHLD TX_ER/TXD[4] 75 Ω 51 Ω 51 Ω 8 33 Ω TX_EN 51 Ω 7 MI/FII 333333 ΩΩΩ TRRXXX__DCC[0LL]KK RX- 75 Ω 51 Ω 5511 ΩΩ 654 RJ45 33 Ω RXD[1]/PHYAD[1] TX+ 3 33 Ω RXD[2] 2 33 Ω RXD[3]/PHYAD[3] 1 33 Ω RX_ER/RXD[4]/PHYAD[4] SHLD 33 Ω RX_DV/MII_DRV TX- COL/PHYAD0 33 Ω CRS/PHYAD[2] 0.1 µF 0.1 µF 0.01 µF 2KV CS8952 VDD_MII 4.7 k LPSTRT +5 V RX_EN PWRDN REPEATER 0.1 µF BPSCR 130 Ω 0.1 µF CONTROL BP4B5B SIGNAL+ 191 Ω I/F BPALIGN SIGNAL- LPBK +5 V 82 Ω 68 Ω ISODEF 10BT_SER RMEIIS_IERTQ 82 Ω 82 Ω0.1 µF63.4 Ω TRANFISBCEERIVER VEE 680 Ω SD+ SPEED10 49.9 Ω 49.9 Ω TD- 680 Ω TD+ SPEED100 TX_NRZ- VCC TX_NRZ+ VCC RX_NRZ- RD- RX_NRZ+ RD+ VDD_MII 130 Ω 130 Ω +5 V VEE 680 Ω LED1 680 Ω 0.1 µF 0.1 µF LED2 680 Ω LED3 680 Ω TXSLEW0 NC LED4 TXSLEW1 NC 680 Ω LED5 AN0 NC AN1 NC 3 VDD_MII TCM +5 V 10 µF 0.1 µF 11 VDD 10 µF 0.1 µF RSVD VSS TEST0 TEST1 7 21 Figure 1. Typical Connection Diagram CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 19 DS206F1

CS8952 rupt signal to the controller when a change of state Operating Mode BPALIGN BP4B5B 10BT_SER has occurred in the CS8952, eliminating the need 100BASE-X 1 Don’t 0 for the system to poll the CS8952 for state changes. Repeater Care The RX_EN signal allows the receiver outputs to 0 1 0 10BASE-T Serial Don’t Don’t 1 be electrically isolated. The ISODEF pin controls Care Care the value of register bit ISOLATE in the Basic Table 1. Mode Control Register (address 00h) which in turn electrically isolates the CS8952's MII data path. 3.1.1 100BASE-X MII Application (TX and FX) 3.1 Major Operating Modes The CS8952 provides an IEEE 802.3-compliant The following sections describe the four major op- MII interface. Data is transferred across the MII in erating modes of the CS8952: four-bit parallel (nibble) mode. TX_CLK and - 100BASE-X MII Modes (TX and FX) RX_CLK are nominally 25MHz for 100BASE-X. - 100BASE-X Repeater Modes The 100BASE-X mode includes both the TX and - 10BASE-T MII Mode FX modes, as determined by pin BPSCR (bypass scrambler), or the BPSCR bit (bit 13) in the Loop- - 10BASE-T Serial Mode back, Bypass, and Receiver Error Mask Register The choice of operating speed (10 Mb/s versus (address 18h). In FX mode, an external optical 100Mb/s) is made using the auto-negotiation input module is connected to the CS8952 via pins pins (AN0, AN1) and/or the auto-negotiation MII TX_NRZ+, TX_NRZ-, RX_NRZ+, RX_NRZ-, registers. The auto-negotiation capability also is SIGNAL+, and SIGNAL-. In FX mode, the MLT- used to select a duplex mode (full or half duplex). 3/NRZI conversion blocks and the scrambler/de- Both speed and duplex modes can either be forced scrambler are bypassed. or negotiated with the far-end link partner. 3.1.1.1 Symbol Encoding and Decoding The digital interface mode (MII, repeater, or 10BASE-T serial) is selected by input pins In 100BASE-X modes, 4-bit nibble transmit data is BPALIGN, BP4B5B and 10BT_SER as shown in encoded into 5-bit symbols for transmission onto Table 1. Speed and duplex selection are made the media as shown in Tables 2 and 3. The encod- through the AN[1:0] pins as shown in Table 5. ing is necessary to allow data and control symbols to be sent consecutively along the same media Operating Mode BPALIGN BP4B5B 10BT_SER transparent to the MAC layer. This encoding caus- 100BASE-X MII 0 0 0 es the symbol rate transmitted across the wire (125 10BASE-T MII 0 0 0 symbols/second) to be greater than the actual data Table 1. rate of the system (100 symbols/second). DATA and CONTROL Codes (RX_ER = 0 or TX_ER = 0) Name 5-bit Symbol 4-bit Nibble Comments DATA (Note 1) 0 11110 0000 1 01001 0001 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 20 DS206F1

CS8952 DATA and CONTROL Codes (RX_ER = 0 or TX_ER = 0) Name 5-bit Symbol 4-bit Nibble Comments 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010 B 10111 1011 C 11010 1100 D 11011 1101 E 11100 1110 F 11101 1111 CONTROL (Note 2) I 11111 0101 IDLE (Note 3) J 11000 0101 First Start of Stream Symbol K 10001 0101 Second Start of Stream Symbol T 01101 0000 First End of Stream Symbol R 00111 0000 Second End of Stream Symbol 1. DATA code groups are indicated by RX_DV = 1 2. CONTROL code groups are inserted automatically during transmission in response to TX_EN. They are not generated through any combination of TXD[3:0] or TX_ER. 3. IDLE is indicated by RX_DV = 0. Table 2. 4B5B Symbol Encoding/Decoding Code Violations (RX_ER = 1 or TX_ER = 1) Error Report Normal Mode 4-bit Mode 4-bit Name 5-bit Symbol Nibble Nibble Comments CONTROL (Note 1) I 11111 0000 0000 This portion of the table relates received J 11000 0000 0000 5-bit symbols to received 4-bit nibbles only. The control code groups may not K 10001 0000 0000 be transmitted in the data portion of the T 01101 0000 0000 frame. R 00111 0000 0000 CODE VIOLATIONS H 00100 0000 0000 V0 00000 0110 or 0101 (Note 2) 0001 V1 00001 0110 or 0101 (Note 2) 0111 V2 00010 0110 or 0101 (Note 2) 1000 V3 00011 0110 or 0101 (Note 2) 1001 V4 00101 0110 or 0101 (Note 2) 1010 V5 00110 0110 or 0101 (Note 2) 1011 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 21 DS206F1

CS8952 Code Violations (RX_ER = 1 or TX_ER = 1) Error Report Normal Mode 4-bit Mode 4-bit Name 5-bit Symbol Nibble Nibble Comments V6 01000 0110 or 0101 (Note 2) 1100 V7 01100 0110 or 0101 (Note 2) 1101 V8 10000 0110 or 0101 (Note 2) 1110 V9 11001 0110 or 0101 (Note 2) 1111 1. CONTROL code groups become violations when found in the data portion of the frame. 2. Invalid code groups are mapped to 5h unless the Code Error Report select bit in the Loopback, Bypass, and Receiver Error Mask Register (address 18h) is set, in which case invalid code groups are mapped to 6h. Table 3. 4B5B Code Violation Decoding 3.1.1.2 100 Mb/s Loopback 3.1.2 100BASE-X Repeater Application One of two internal 100BASE-TX loopback modes The CS8952 provides two low latency modes for can be selected. Local loopback redirects the repeater applications. These are selected by assert- TXD[3:0] input data to RXD[3:0] data outputs ing either pin BPALIGN or BP4B5B. Both pins through the 4B5B coders and scramblers. Local have the effect of bypassing the 4B5B encoder and loopback is selected by asserting pin LPBK, by set- decoder. Bypassing the coders decreases latency, ting the LPBK bit (bit 14) in the Basic Mode Con- and uses a 5-bit wide parallel code group interface trol Register (address 00h) or by setting bits 8 and on pins RXD[4:0] and TXD[4:0] instead of the 4- 11 in the Loopback, Bypass, and Receiver Error bit wide MII nibble interface on pins RXD[3:0] and Mask Register (address 18h) as shown in Table 4. TXD[3:0]. In repeater mode, pin RX_ER is rede- fined as the fifth receive data bit (RXD4), and pin Remote loopback redirects the analog line interface TX_ER is redefined as the fifth transmit data bit inputs to the analog line driver outputs. Remote (TXD4). loopback is selected by setting bit 9 in the Loop- back, Bypass, and Receiver Error Mask Register BPALIGN can also be selected by setting bit 12 in (address 18h) as shown in Table 4. Loopback, Bypass, and Receiver Error Mask Reg- ister (address 18h). BP4B5B can be selected by set- Remote PMD Function ting bit 14 of the same register. Loopback Loopback (bit 9) (bit 8) Pin BPALIGN causes more of the CS8952 to be 0 0 No Loopback bypassed than the BP4B5B pin. BPALIGN also by- 0 1 Local Loopback (toward MII) passes the scrambler/descrambler, and the NRZI to 1 0 Remote Loopback (toward line) NRZ converters (see Figure 1). Also, for repeater 1 1 Operation is undefined applications, pin REPEATER should be asserted to Table 4. redefine the function of the CRS (carrier sense) pin. The REPEATER function may also be invoked by When changing between local and non-loopback setting bit 12 in the PCS Sublayer Configuration modes, the data on RXD[3:0] will be undefined for Register (address 17h). approximately 330 µs. For repeater applications, the RX_EN pin can be used to gate the receive data pins (RXD[4:0], CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 22 DS206F1

CS8952 RX_CLK, RX_DV, COL, and CRS) onto a shared, packet transmission to prevent “blind” transmis- external repeater system bus. sions onto the network (link pulses are still sent while packet transmission is disabled). To reactivate 3.1.3 10BASE-T MII Application transmission, the receiver must detect a single pack- The digital interface used in this mode is the same et (the packet itself is ignored), or two normal link as that used in the 100BASE-X MII mode except pulses separated by more than 6ms and no more that TX_CLK and RX_CLK are nominally than 50ms. 2.5MHz. The CS8952 automatically checks the polarity of The CS8952 includes a full-featured 10BASE-T in- the receive half of the twisted pair cable. To detect terface, as described in the following sections. a reversed pair, the receiver examines received link pulses and the End-of-Frame (EOF) sequence of 3.1.3.1 Full and Half Duplex operation incoming packets. If it detects at least one reversed The 10BASE-T function supports full and half du- link pulse and at least four frames in a row with plex operation as determined by pins AN[1:0] negative polarity after the EOF, the receive pair is and/or the corresponding MII register bits. (See Ta- considered reversed. If the polarity is reversed and ble 5). bit 1 of the 10BASE-T Configuration Register (ad- dress 1Ch), is set, the CS8952 automatically cor- 3.1.3.2 Collision Detection rects a reversal. If half duplex operation is selected, the CS8952 de- In the absence of transmit packets, the transmitter tects a 10BASE-T collision whenever the receiver generates link pulses in accordance with and transmitter are active simultaneously. When a Section14.2.1.1 of the Ethernet standard. Trans- collision is present, the collision is reported on pin mitted link pulses are positive pulses, one bit time COL. Collision detection is undefined for full-du- wide, typically generated at a rate of one every plex operation. 16ms. The 16 ms timer also starts whenever the 3.1.3.3 Jabber transmitter completes an End-of-Frame (EOF) se- quence. Thus, a link pulse will be generated 16 ms The jabber timer monitors the transmitter and dis- after an EOF unless there is another transmitted ables the transmission if the transmitter is active for packet. greater than approximately 105 ms. The transmitter stays disabled until approximately 406ms after the 3.1.3.5 Receiver Squelch internal transmit request is no longer enabled. The 10BASE-T squelch circuit determines when 3.1.3.4 Link Pulses valid data is present on the RXD+/RXD- pair. In- coming signals passing through the receive filter To prevent disruption of network operation due to a are tested by the squelch circuit. Any signal with faulty link segment, the CS8952 continually moni- amplitude less than the squelch threshold (either tors the 10BASE-T receive pair (RXD+ and RXD-) positive or negative, depending on polarity) is re- for packets and link pulses. After each packet or link jected. pulse is received, an internal Link-Loss timer is started. As long as a packet or link pulse is received 3.1.3.6 10BASE-T Loopback before the Link-Loss timer finishes (between 50 and When Loopback is selected, the TXD[3:0] pins are 100ms), the CS8952 maintains normal operation. If looped back into the RXD[3:0] pins through the no receive activity is detected, the CS8952 disables CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 23 DS206F1

CS8952 Manchester Encoder and Decoder. Selection is a 10MHz RX_CLK and TX_CLK. Receive data is made via: framed by CRS rather than RX_DV. - setting bit 14 in the Basic Mode Control 3.2 Auto-Negotiation Register (address 00h) or The CS8952 supports auto-negotiation, which is - setting bits 8 and 11 in the Loopback, By- the mechanism that allows the two devices on ei- pass, and Receiver Error Mask Register ther end of an Ethernet link segment to share infor- (address 18h) or mation and automatically configure both devices - asserting the LPBK pin. for maximum performance. When configured for auto-negotiation, the CS8952 will detect and auto- 3.1.3.7 Carrier Detection matically operate full-duplex at 100 Mb/s if the de- The carrier detect circuit informs the MAC that val- vice on the other end of the link segment also id receive data is present by asserting the Carrier supports full-duplex, 100Mb/s operation, and Sense signal (CRS) as soon it detects a valid bit pat- auto-negotiation. The CS8952 auto-negotiation ca- tern (1010b or 0101b for 10BASE-T). During nor- pability is fully compliant with the relevant por- mal packet reception, CRS remains asserted while tions of section 28 of the IEEE 802.3u standard. the frame is being received, and is de-asserted The CS8952 can auto-negotiate both operating within 2.3 bit times after the last low-to-high tran- speed (10 versus 100Mb/s), duplex mode (half du- sition of the End-of-Frame (EOF) sequence. When- plex versus full duplex), and flow control (pause ever the receiver is idle (no receive activity), CRS frames), or alternatively can be set not to negotiate. is de-asserted. At power-up and reset times, the auto-negotiation mode is selected via the auto-negotiation input pins 3.1.4 10BASE-T Serial Application (AN[1:0]). This selection can later be changed us- This mode is selected when pin 10BT_SERis as- ing the Auto-Negotiation Advertisement Register serted during power-up or reset, and operates simi- (address 04h). lar to the 10BASE_T MII mode except that data is Pins AN[1:0] are three level inputs, and have the transferred serially on pins RXD0 and TXD0 using function shown in Table 5. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 24 DS206F1

CS8952 SET bit (bit 15 of the Basic Mode Control Reg- ister (address 00h)) is set. AN1 AN0 Forced/ Speed Full/Half 4) Digital circuitry is reset whenever bit 0 of the Auto (Mb/s) Duplex PCS Sub-Layer Configuration Register (ad- Low Floating Forced 10 Half High Floating Forced 10 Full dress 17h) is set. Analog circuitry is unaffected. Floating Low Forced 100 Half 5) Analog circuitry is reset and recalibrated when- Floating High Forced 100 Full ever the CS8952 enters or exits the power- Floating Floating Auto-Neg 100/10 Full/Half down state, as requested by pin PWRDN. Low Low Auto-Neg 10 Half Low High Auto-Neg 10 Full 6) Analog circuitry is reset and recalibrated when- High Low Auto-Neg 100 Half ever the CS8952 changes between 10Mb/s and High High Auto-Neg 100 Full 100Mb/s modes. Table 5. After a reset, the CS8952 latches the signals on var- Auto-Negotiation encapsulates information within ious input pins in order to initialize key registers a burst of closely spaced Link Integrity Test Pulses, and goes through a self configuration. This in- referred to as a Fast Link Pulse (FLP) Burst. The cludes calibrating on-chip analog circuitry. Time FLP Burst consists of a series of Link Integrity required for the reset calibration is typically 40 ms. Pulses which form an alternating clock / data se- External circuitry may access registers internal to quence. Extraction of the data bits from the FLP the CS8952 during this time. Reset and calibration Burst yields a Link Code Word which identifies the complete is indicated when bit 15 of the Basic capability of the remote device. Mode Control Register (address 00h) is clear. In order to support legacy 10 and 100Mb/s devic- 3.4 LED Indicators es, the CS8952 also supports parallel detection. In The LEDx, SPD100, and SPD10 output pins pro- parallel detection, the CS8952 monitors activity on vide status information that can be used to drive the media to determine the capability of the link LEDs or can be used as inputs to external control partner even without auto-negotiation having oc- circuitry. Indication options include: receive activ- curred. ity, transmit activity, collision, carrier sense, polar- 3.3 Reset Operation ity OK, descrambler synchronization status, auto- Reset occurs in response to six different conditions: negotiation status, speed (10 vs. 100), and duplex mode. 1) There is a chip-wide reset whenever the RE- SET pin is high for at least 200 ns. During a 4. MEDIA INDEPENDENT INTERFACE chip-wide reset, all circuitry and registers in the (MII) CS8952 are reset. The Media Independent Interface (MII) provides a 2) When power is applied, the CS8952 maintains simple interconnect to an external Media Access reset until the voltage at the VDD supply pins Controller (MAC). This connection may be chip to reaches approximately 3.6V. The CS8952 chip, motherboard to daughterboard, or a connec- comes out of reset once VDD is greater than ap- tion between two assemblies attached by a limited proximately 3.6V and the crystal oscillator has length of shielded cable and an appropriate connec- stabilized. tor. 3) There is a chip-wide reset whenever the RE- The MII interface uses the following pins: CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 25 DS206F1

CS8952 STATUS Pins 4.1 MII Frame Structure - COL - Collision indication, valid only for Data frames transmitted through the MII have the half duplex modes. following format: - CRS - Carrier Sense indication Preamble Start of Data End of SERIAL MANAGEMENT Pins (7 Bytes) Frame Frame Delimiter Delimiter - MDIO - a bi-directional serial data path (1 Byte) - MDC - clock for MDIO (16.7MHz max) Each frame is preceded by an inter-frame gap. The - MII_IRQ - Interrupt indicating change in inter-frame gap is an unspecified time during the Interrupt Status Register (address 11h) which no data activity occurs on the media as indi- RECEIVE DATA Pins cated by the de-assertion of CRS for the receive path and TX_EN for the transmit path. - RXD[3:0] - Parallel data output path The Preamble consists of seven bytes of 10101010. - RX_CLK - Recovered clock output The Start of Frame Delimiter consists of a single - RX_DV - Indicates when receive data is byte of 10101011. present and valid Data may be any number of bytes. - RX_ER - Indicates presence of error in re- ceived data The End of Frame Delimiter is conveyed by the de- assertion of RX_DV and TX_EN for receive and - RX_EN - Can be used to tri-state receiver transmit paths, respectively. output pins Transmission and/or reception of each byte of data TRANSMIT DATA Pins is done one nibble at a time in the following order: - TXD[3:0] - Parallel data input path MAC’s Serial Bit Stream - TX_CLK - Transmit clock First Bit LSB D0D1D2D3D4D5D6D7 MSB - TX_EN - Indicates when transmit data is present and valid First Second Nibble Nibble - TX_ER - Request to transmit a 100BASE- LSB T HALT symbol, ignored for 10BASE-T D0 MII operation. D1 Nibble D2 Stream The interface uses TTL signal levels, which are MSB D3 compatible with devices operating at a nominal supply voltage of either 5.0 or 3.3 volts. It is capa- 4.2 MII Receive Data ble of supporting either 10Mb/s or 100Mb/s data The presence of recovered data on the RXD[3:0] rates transparently. That is, all signaling remains bus is indicated by the assertion of RX_DV. identical at either data rate; only the nominal clock RX_DV will remain asserted from the beginning of frequency is changed. the preamble (or Start of Frame Delimiter if pream- ble is not used) to the End of Frame Delimiter. Once RX_DV is asserted, valid data will be driven CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 26 DS206F1

CS8952 onto RXD[3:0] synchronously with respect to presented to the CS8952. When TX_EN is not as- RX_CLK. serted, data on TXD[3:0] is ignored. Receive errors are indicated during frame reception Transmit errors should be signaled by the MAC by by the assertion of RX_ER. It indicates that an error asserting TX_ER for one or more TX_CLK cycles. was detected somewhere in the frame currently be- TX_ER must be synchronous with TX_CLK. This ing transferred across the MII. RX_ER will transi- will cause the CS8952 to replace the nibble with a tion synchronously with respect to the RX_CLK, HALT symbol in the frame being transmitted. This and will be held high for one cycle for each error re- invalid data will be detected by the receiving PHY ceived. It is up to the MAC to ensure that a CRC er- and flagged as a bad frame. Figure 4 illustrates ror is detected in that frame by the Logical Link transmission without errors, and Figure 5 illustrates Control. Figure 2 illustrates reception without er- transmission with errors. rors, and Figure 3 illustrates reception with errors. 4.4 MII Management Interface 4.3 MII Transmit Data The CS8952 provides an enhanced IEEE 802.3 MII TX_EN is used by the MAC to signal to the Management Interface. The interface consists of CS8952 that valid nibbles of data are being present- three signals: a bi-directional serial data line ed across the MII via TXD[3:0]. TX_EN must be (MDIO), a data clock (MDC), and an optional in- asserted synchronously with the first nibble of pre- terrupt signal (MII_IRQ). The Management Inter- amble, and must remain asserted as long as valid face can be used to access status and control data is being presented to the MII. registers internal to the CS8952. The CS8952 im- plements an extended set of 16-bit MII registers. TX_EN must be de-asserted within one TX_CLK Eight of the registers are defined by the IEEE 802.3 cycle after the last nibble of data (CRC) has been RX_CLK RX_DV RXD[3:0] Preamble/SFD DATA RX_ER Figure 2. Reception without errors RX_CLK RX_DV RXD[3:0] XX Preamble/SFD DATA DATA RX_ER Figure 3. Reception with errors CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 27 DS206F1

CS8952 TX_CLK TX_EN TXD[3:0] Preamble/SFD DATA TX_ER Figure 4. Transmission without errors TX_CLK TX_EN TXD[3:0] HALT Preamble/SFD DATA TX_ER Figure 5. Transmission with errors specification, while the remaining registers provide When the management interface is idle, the MDIO enhanced monitoring and control capabilities. signal will be tri-stated, and the MAC is required to keep MDIO pulled to a logic ONE. As many as 31 devices may share a single Manage- ment Interface. A unique five-bit PHY address is At the beginning of each transaction, the MAC will associated with each device, with all devices re- typically send a sequence of 32 contiguous logic sponding to PHY address 00000. The CS8952 de- ONE bits on MDIO with 32 corresponding clock termines its PHY address at power-up or reset cycles on MDC to provide the CS8952 with a pat- through the PHYAD[4:0] pins. tern that it can use to establish synchronization. Optionally, the CS8952 may be configured to oper- 4.5 MII Management Frame Structure ate without the preamble through bit 9 of the PCS Frames transmitted through the MII Management Sub-Layer Configuration Register (address 17h). Interface have the following format (Table 6): Preamble Start of Opcode PHY Register Turnaround Data Idle (32 bits) Frame (2 bits) Address Address (2 bits) (16 bits) (2 bits) (5 bits) (5 bits) Table 6. Format for Frame Transmitted through the MII Management Interface The Start of Frame is indicated by a 01 bit pattern. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 28 DS206F1

CS8952 A read transaction is indicated by an Opcode of 10 Time and a write by 01. At power-up and reset time, the following pins are The PHY Address is five bits, with the most signif- used to configure the CS8952. icant bit sent first. If the PHY address included in the frame is not 00000 or does not match the PHY- Pin Name Function 10BT_SER Select 10BASE-T serial mode AD field of the Self Status Register (address 19h), AN[1:0] Select auto-negotiation mode the rest of the frame is ignored. BP4B5B Bypass 4B5B coders The register address is five bits, with the most sig- BPALIGN Bypass 4B5B coders and scramblers nificant bit sent first, and indicates the CS8952 reg- BPSCR Bypass scramblers, enter FX mode ISODEF Electrically isolate MII after reset ister to be written to/read from. LPSTRT Start in low power mode The Turnaround time is a two bit time spacing be- PHYAD[4:0] Set MII PHY address tween when the MAC drives the last register ad- REPEATER Control definition of CRS pin, enable dress bit onto MDIO and the data field of a carrier integrity monitor and SQE func- tion management frame in order to avoid contention MII_DRV Set MII driver strength during a read transaction. For a read transaction, TCM Set TX_CLK mode the MAC should tri-state the MDIO pin beginning TXSLEW[1:0] Set 100BASE-TX transmitter output on the first bit time, and the CS8952 will begin slew rate driving the MDIO signal to a logic ZERO during 5.2 Configuration Via Control Pins the second bit time. During write transactions, since the MDIO direction does not need to be re- The following pins are for dedicated control signals versed, the MAC will drive the MDIO to a logic and can be used at any time to configure the ONE for the first bit time and a logic ZERO for the CS8952. second. Pin Name Function The data field is always 16 bits in length, with the LPBK Enter loopback mode most significant bit sent first. PWRDN Enter power-down mode RESET Reset 5. CONFIGURATION The CS8952 can be configured in a variety of ways. 5.3 Configuration via the MII All control and status information can be accessed The CS8952 supports configuration by software via the MII Serial Management Interface. Addi- control through the use of 16-bit configuration and tionally, many configuration options can be set at status registers accessed via the MDIO/MDC pins power-up or reset times via individual control lines. (MII Management Interface). The first seven regis- Some configuration capabilities are available at ters are defined by the IEEE 802.3 specification. any time via individual control lines. Additional registers extend the register set to pro- vide enhanced monitoring and control capabilities. 5.1 Configuration At Power-up/Reset CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 29 DS206F1

CS8952 6. CS8952 REGISTERS The CS8952 register set is comprised of the 16-bit status and control registers described below. A de- tailed description each register follows. Register Address Description Type 0h Basic Mode Control Register Read/Write 1h Basic Mode Status Register Read-Only 2h PHY Identifier #1 Read-Only 3h PHY Identifier #2 Read-Only 4h Auto-Negotiation Advertisement Register Read/Write 5h Auto-Negotiation Link Partner Ability Register Read-Only 6h Auto-Negotiation Expansion Register Read-Only 7h Auto-Negotiation Next Page Transmit Register Read/Write 8h through Fh Reserved by IEEE 802.3 Working Group - 10h Interrupt Mask Register Read/Write 11h Interrupt Status Register Read-Only 12h Disconnect Count Register Read-Only 13h False Carrier Count Register Read-Only 14h Scrambler Key Initialization Register Read/Write 15h Receive Error Count Register Read-Only 16h Descrambler Key Initialization Register Read/Write 17h PCS Sub-Layer Configuration Register Read/Write 18h Loopback, Bypass and Receiver Error Mask Register Read/Write 19h Self-Status Register Read/Write 1Ah Reserved - 1Bh 10BASE-T Status Register Read-Only 1Ch 10BASE-T Configuration Register Read/Write 1Dh through 1Fh Reserved - CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 30 DS206F1

CS8952 6.1 Basic Mode Control Register - Address 00h 15 14 13 12 11 10 9 8 Software Speed Auto-Neg Restart Loopback Power Down Isolate Duplex Mode Reset Selection Enable Auto-Neg 7 6 5 4 3 2 1 0 Collision Test Reserved BIT NAME TYPE RESET DESCRIPTION 15 Software Reset Read/Set 0 Setting this bit performs a chip-wide reset. All status and control registers are set to their default states, and the analog circuitry is re-calibrated. This bit is an Act-Once bit which is cleared once the reset and re- calibration have completed. This bit will also be set automatically while the analog circuitry is reset and re-calibrated during mode changes. 14 Loopback Read/Write 0 When set, the CS8952 is placed in a loop back mode. Any data sent on the transmit data path is returned on the receive data path. Loopback mode is entered regardless of whether 10Mb/s or 100Mb/s operation has been configured. This bit will be set upon the assertion of the LPBK pin, and will be automatically cleared upon its deas- sertion. 13 Speed Selection Read/Write If auto-negotiation When bit 12 is clear, setting this bit configures the is enabled via the CS8952 for 100Mb/s operation. Clearing this bit sets AN[1:0] pins, reset the configuration at 10Mb/s. When bit 12 is set, this to 1; otherwise, bit is ignored. reset to 0 12 Auto-Neg Enable Read/Write If auto-negotiation Setting this bit enables the auto-negotiation process. is enabled via the When this bit is set, bits 13 and 8 have no affect on AN[1:0] pins, reset the link configuration. The link configuration is deter- to 1; otherwise, mined by the auto-negotiation process. Clearing this reset to 0 bit disables auto-negotiation. 11 Power Down Read/Write 0 When this bit is set, the CS8952 enters a low power consumption state. Clearing this bit allows normal operation. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 10 Isolate Read/Write If PHYAD = Setting this bit causes the MII data path to be electri- 00000, reset to 1; cally isolated by tri-stating all data outputs (i.e. otherwise reset to TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, the value on the and CRS). In addition the CS8952 will not respond to ISODEF pin the TXD[3:0], TX_EN, and TX_ER inputs. It will, how- ever, respond to MDIO and MDC. Clearing this bit allows normal operation. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 31 DS206F1

CS8952 BIT NAME TYPE RESET DESCRIPTION 9 Restart Auto-Neg Read/Set 0 Setting this bit causes auto-negotiation to be restarted. It is an Act-Once bit which is cleared once auto-negotiation has begun. Clearing this bit has no effect on the auto-negotiation process. 8 Duplex Mode R/W If auto-negotiation When bit 12 is clear, this bit controls the Full- is enabled via the Duplex/Half-Duplex operation of the part. When set, AN[1:0] pins, reset the part is configured for Full-Duplex operation, and to 0; otherwise, when clear the part is configured for Half Duplex reset to 1 operation. The setting of this bit is superseded by auto-negotiation, and thus has no effect if bit 12 is set. 7 Collision Test R/W 0 When set, the COL pin will be asserted within 10 bit times in response to the assertion of TX_EN. Upon the deassertion of TX_EN, COL will be deasserted within 4 bit times. When Collision Test is clear, COL functions normally. 6:0 Reserved Read Only 000 0000 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 32 DS206F1

CS8952 6.2 Basic Mode Status Register - Address 01h 15 14 13 12 11 10 9 8 100BASE-TX/ 100BASE-TX/ 10BASE-T/ 10BASE-T/ 100BASE-T4 Reserved Full Duplex Half Duplex Full Duplex Half Duplex 7 6 5 4 3 2 1 0 MF Preamble Auto-Neg Auto-Neg Extended Reserved Remote Fault Link Status Jabber Detect Suppression Complete Ability Capability BIT NAME TYPE RESET DESCRIPTION 15 100BASE-T4 Read Only 0 The CS8952 does not support 100BASE-T4 opera- tion, so this bit will always read 0. 14 100BASE-TX/Full Read Only 1 When this bit is set, it indicates that the CS8952 is Duplex capable of 100BASE-TX Full-Duplex operation. This bit reflects the status of the 100BASE-TX/Full-Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). 13 100BASE-TX/Half Read Only 1 When this bit is set, it indicates that the CS8952 is Duplex capable of 100BASE-TX Half-Duplex operation. This bit reflects the status of the 100BASE-TX/Half Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). 12 10BASE-T/Full Read Only 1 When this bit is set, it indicates that the CS8952 is Duplex capable of 10BASE-T Full-Duplex operation. This bit reflects the status of the 10BASE-T/Full Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). 11 10BASE-T/Half Read Only 1 When this bit is set, it indicates that the CS8952 is Duplex capable of 10BASE-T Half-Duplex operation. This bit reflects the status of the 10BASE-T/Half Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). 10:7 Reserved Read Only 0000 6 MF Preamble Sup- Read Only 1 When set, this bit indicates that the CS8952 is capa- pression ble of accepting management frames regardless of whether they are preceded by the preamble pattern. When clear, it indicates that the management frame must be preceded by the preamble pattern to be con- sidered valid. This bit reflects the status of the MR Preamble Enable bit in the PCS Sub-Layer Configu- ration Register (address 17h). 5 Auto-Neg Complete Read Only 0 This bit is set to a 1 when the auto-negotiation pro- cess has completed. This is an indication that data is valid in the Auto-Negotiation Advertisement Register (address 04h), the Auto-Negotiation Link Partner Ability Register (address 05h), and the Auto-Negotia- tion Expansion Register (address 06h). 4 Remote Fault Read Only 0 When auto-negotiation is enabled, this bit is set if the Remote Fault bit is set in the Auto-Negotiation Link Partner Ability Register (address 05h). When auto- negotiation is disabled, this bit will be set when a Far- End Fault Indication for 100BASE-TX is detected. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 33 DS206F1

CS8952 BIT NAME TYPE RESET DESCRIPTION 3 Auto-Neg Ability Read Only 1 This bit indicates that the CS8952 has auto-negotia- tion capability. Therefore this bit will always read back a value of 1. 2 Link Status Read Only 0 When set, this bit indicates that a valid link has been established. Upon a link failure, this bit is cleared and latched. It will remain cleared until this register is read. 1 Jabber Detect Read Only 0 In 10BASE-T mode, if the last transmission is longer than 105ms, then the packet output is terminated by the jabber logic and this bit is set. If JabberiE (Inter- rupt Mask Register (address 10h), bit 3) is set, an MII Interrupt will be generated. This bit is implemented with a latching function so that the occurrence of a jabber condition causes it to become set until it is cleared by a read to this regis- ter, a read to the Interrupt Status Register (address 11h), or a reset. No jabber detect function has been defined for 100BASE-TX. 0 Extended Capability Read Only 1 This bit indicates that an extended register set may be accessed (registers beyond address 01h). This bit always reads back a value of 1. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 34 DS206F1

CS8952 6.3 PHY Identifier, Part 1 - Address 02h 15 14 13 12 11 10 9 8 Organizationally Unique Identifier: Bits[3:10] 7 6 5 4 3 2 1 0 Organizationally Unique Identifier: Bits[11:18] BIT NAME TYPE RESET DESCRIPTION 15:0 Organizationally Read/Write 001Ah This identifier is assigned to PHY manufacturers by Unique Identifier the IEEE. Its intention is to provide sufficient informa- (bits 3:18) tion to support 10/100 Management as defined in Clause 30.1.2 of the IEEE 802.3 specification. This register contains bits [3:18] of the OUI. Bit 3 of the OUI is located in bit 15 of the PHY Identifier, bit 4 of the OUI is in bit 14, and so on. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 35 DS206F1

CS8952 6.4 PHY Identifier, Part 2 - Address 03h 15 14 13 12 11 10 9 8 Organizationally Unique Identifier - Bits[19:24] Part Number 7 6 5 4 3 2 1 0 Part Number Revision Number BIT NAME TYPE RESET DESCRIPTION 15:10 Organizationally Read/Write 00 1000 This identifier is assigned to PHY manufacturers by Unique Identifier the IEEE. Its intention is to provide sufficient informa- (bits 19:24) tion to support 10/100 Management as defined in Clause 30.1.2 of the IEEE 802.3 specification. This register contains bits [19:24] of the OUI. Bit 19 of the OUI is located in bit 15 of this register, bit 20 of the OUI is in bit 14, and so on. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 9:4 Part Number Read/Write 10 0000 These bits indicate the CS8952 part number. It has been set to a value of 100000. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 3:0 Revision Number Read/Write 0001 These bits indicate the CS8952 part revision. Rev. A 0000 Rev. B 0001 etc. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 36 DS206F1

CS8952 6.5 Auto-Negotiation Advertisement Register - Address 04h 15 14 13 12 11 10 9 8 Next Page Acknowledge Remote Fault Technology Ability Field 7 6 5 4 3 2 1 0 Technology Ability Field Protocol Selector Field BIT NAME TYPE RESET DESCRIPTION 15 Next Page Read/Write 0 When set, this bit enables the ability to exchange Next-Pages with the link partner. This bit should be cleared if it is not desired to engage in Next Page exchange. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 14 Acknowledge Read Only 0 When set, this bit indicates consistent reception of the link partner’s data. 13 Remote Fault Read/Write 0 This bit may be used to indicate a fault condition to the link partner. Setting this bit will signal to the link partner that a fault condition has occurred. 12:5 Technology Ability Read/Write 0000 1111 This field determines the advertised capabilities of Field the CS8952 as shown below. When the bit is set, the corresponding technology will be advertised during auto-negotiation. BIT Capability 12 Reserved 11 Reserved 10 PAUSE operation for full duplex links. Set only if supported by the host MAC. 9 100BASE-T4 (Note: this technology is not supported and can not be set. 8 100BASE-TX Full Duplex 7 100Base-TX Half Duplex 6 10BASE-T Full Duplex 5 10BASE-T Half Duplex 4:0 Protocol Selector Read/Write 0 0001 This field is used to identify the type of message Field being sent by auto-negotiation. This field defaults to a value of “00001” for IEEE 802.3 messages. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 37 DS206F1

CS8952 6.6 Auto-Negotiation Link Partner Ability Register - Address 05h 15 14 13 12 11 10 9 8 Next Page Acknowledge Remote Fault Technology Ability Field 7 6 5 4 3 2 1 0 Technology Ability Field Protocol Selector Field BIT NAME TYPE RESET DESCRIPTION 15 Next Page Read Only 0 When set, this bit indicates that the link partner is capable of participating in the Next Page exchange. 14 Acknowledge Read Only 0 When set, this bit indicates that the link partner has received consistent data from the CS8952. 13 Remote Fault Read Only 0 This bit indicates that a fault condition occurred on the far end. When this bit is set and auto-negotiation is enabled, the Remote Fault bit in the Basic Mode Status Register (address 01h) will also be set. 12:5 Technology Ability Read Only 0000 0000 This field indicates the advertised capabilities of the Field link partner as shown below. When the bit is set, the corresponding technology has been advertised dur- ing auto-negotiation. BIT Capability 12 Reserved 11 Reserved 10 PAUSE operation for full duplex links. 9 100BASE-T4 (Note: this technology is not 8 100BASE-TX Full Duplex 7 100Base-TX Half Duplex 6 10BASE-T Full Duplex 5 10BASE-T Half Duplex 4:0 Protocol Selector Read Only 0 0000 This field is used to identify the type of message Field being received during auto-negotiation. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 38 DS206F1

CS8952 6.7 Auto-Negotiation Expansion Register - Address 06h 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Link Partner Parallel Next Page Link Partner Reserved Next Page Page Received Detection Fault Able Auto-Neg Able Able BIT NAME TYPE RESET DESCRIPTION 15:5 Reserved Read Only 000 0000 0000 4 Parallel Detection Read Only 0 When set, this bit indicates an error condition in Fault which both the 10BASE-T and 100BASE-TX links came up valid, or that one of the technologies estab- lished a link but was unable to maintain the link. This bit is self-clearing. 3 Link Partner Next Read Only 0 When set, this bit indicates that the link partner is Page Able capable of Next Page exchange. 2 Next Page Able Read Only 1 This bit is a status bit which indicates to the Manage- ment Layer that the CS8952 supports Next Page capability. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 1 Page Received Read Only 0 When set, this bit indicates that a valid word of auto- negotiation data has been received and its integrity verified. The first page of data will consist of the Base Page, and all successive pages will consist of Next Page data. This bit is self-clearing. 0 Link Partner Auto- Read Only 0 When set, this bit indicates that the link partner has Neg Able auto-negotiation capability. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 39 DS206F1

CS8952 6.8 Auto-Negotiation Next-Page Transmit Register - Address 07h 15 14 13 12 11 10 9 8 Next Page Acknowledge Message PageAcknowledge 2 Toggle Message/Unformatted Code Field 7 6 5 4 3 2 1 0 Message/Unformatted Code Field BIT NAME TYPE RESET DESCRIPTION 15 Next Page Read/Write 0 When set, this bit indicates that more Next Pages fol- low. When clear, the current page is the last page of data to be sent. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 14 Acknowledge Read Only 0 This bit is used for Link Code Word verification. When set, it indicates that consistent data has been successfully read from the link partner. 13 Message Page Read/Write 1 When set, this bit indicates that the data in the Mes- sage/Unformatted Code Field is one of the pre- defined message pages. When low, the data is unformatted data. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 12 Acknowledge 2 Read/Write 0 When set, this bit indicates to the link partner that the CS8952 can comply with the last received message. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 11 Toggle Read Only 0 This bit is used to maintain synchronization with the link partner during Next Page exchange. 10:0 Message/Unformat- Read/Write 000 0000 0001 This field contains the 11 bit data for the Message or ted Code Field Unformatted Page. It defaults to the Null Message. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 40 DS206F1

CS8952 6.9 Interrupt Mask Register - Address 10h 15 14 13 12 11 10 9 8 Remote CIM Link Link Status Descrambler Premature End DCR FCCR RECR Loopback Unstable Change Lock Change Error Rollover Rollover Rollover Fault 7 6 5 4 3 2 1 0 Reset Jabber Auto-Neg Parallel Parallel Remote Page Reserved Complete Detect Complete Detection Fault Fail Fault Received This register indicates which events will cause an interrupt event on the MII_IRQ pin. Each bit acts as an enable to the interrupt. Thus, when set, the event will cause the MII_IRQ pin to be asserted. When clear, the event will not affect the MII_IRQ pin, but the status will still be reported via the Interrupt Sta- tus Register (address 11h). BIT NAME TYPE RESET DESCRIPTION 15 CIM Link Unstable Read/Write 0 When set, an interrupt will be generated if an unsta- ble link condition is detected by the Carrier Integrity Monitor function. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 14 Link Status Change Read Write 1 When set, an interrupt will be generated each time the CS8952 detects a change in the link status. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 13 Descrambler Lock Read/Write 0 When set, an interrupt will be generated each time Change the 100BASE-TX receive descrambler loses or regains synchronization with the far-end. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 12 Premature End Read/Write 0 When set, an interrupt will be generated when two Error consecutive IDLES are detected in a 100BASE-TX frame without the ESD sequence. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 41 DS206F1

CS8952 BIT NAME TYPE RESET DESCRIPTION 11 DCR Rollover Read/Write 0 When set, an interrupt will be generated if the MSB in the DCR counter becomes set. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 10 FCCR Rollover Read/Write 0 When set, an interrupt will be generated if the MSB in the FCCR counter becomes set. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 9 RECR Rollover Read/Write 0 When set, an interrupt will be generated if the MSB in the RECR counter becomes set. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 8 Remote Loopback Read/Write 0 When set, an interrupt will be generated if the elastic Fault buffer in the PMA is under-run or over-run during Remote Loopback. This should not occur for normal length 802.3 frames. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 7 Reset Complete Read/Write 1 When set, an interrupt will be generated once the digital and analog sections have been reset, and a calibration cycle has been performed. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 6 Jabber Detect Read/Write 0 When set, an interrupt will be generated when a Jab- ber condition is detected by the 10BASE-T MAU. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 42 DS206F1

CS8952 BIT NAME TYPE RESET DESCRIPTION 5 Auto-Neg Complete Read/Write 0 When set, an interrupt will be generated once auto- negotiation has completed successfully. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 4 Parallel Detection Read/Write 0 When set, an interrupt will be generated if auto-nego- Fault tiation determines that unstable legacy link signaling was received. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 3 Parallel Fail Read/Write 0 When set, an interrupt will be generated when paral- lel detection has occurred for a technology that is not currently advertised by the local device. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 2 Remote Fault Read/Write 0 When set, an interrupt will be generated if a remote fault condition is detected either by auto-negotiation or by the Far-End Fault Detect state machine. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 1 Page Received Read/Write 0 When set, an interrupt is generated each time a page is received during auto-negotiation. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 0 Reserved Read Only 0 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 43 DS206F1

CS8952 6.10 Interrupt Status Register - Address 11h 15 14 13 12 11 10 9 8 Remote CIM Link Link Status Descrambler Premature End DCR FCCR RECR Loopback Unstable Change Lock Change Error Rollover Rollover Rollover Fault 7 6 5 4 3 2 1 0 Reset Jabber Auto-Neg Parallel Parallel Remote Page Reserved Complete Detect Complete Detection Fault Fail Fault Received This register indicates which event(s) caused an interrupt event on the MII_IRQ pin. All bits are self- clearing, and will thus be cleared upon readout. BIT NAME TYPE RESET DESCRIPTION 15 CIM Link Unstable Read Only 0 When set, this bit indicates that an unstable link con- dition was detected by the Carrier Integrity Monitor function. 14 Link Status Change Read Only 0 When set, this bit indicates that a change has occurred to the status of the link. The Self Status Register (address 19h) may be read to determine the current status of the link. 13 Descrambler Lock Read Only 0 When set, this bit indicates that a change has Change occurred in the status of the descrambler. The Self Status Register (address 19h) may be read to deter- mine the current status of the scrambler lock. 12 Premature End Read Only 0 This bit is set when a premature end of frame is Error detected for 100Mb/s operation. A premature end is defined as two consecutive IDLE patterns detected in a frame prior to the End of Stream Delimiter. 11 DCR Rollover Read Only 0 This bit is set when the MSB of the Disconnect Count Register (address 12h) becomes set. This should provide ample warning to the management layer so that the DCR may be read before rolling over. 10 FCCR Rollover Read Only 0 This bit is set when the MSB of the False Carrier Count Register (address 13h) becomes set. This should provide ample warning to the management layer so that the FCCR may be read before saturat- ing. 9 RECR Rollover Read Only 0 This bit is set when the MSB of the Receive Error Count Register (address 15h) becomes set. This should provide ample warning to the management layer so that the RECR may be read before rolling over. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 44 DS206F1

CS8952 BIT NAME TYPE RESET DESCRIPTION 8 Remote Loopback Read Only 0 When set, this bit indicates that the Elastic Buffer has Fault detected an over-run or an under-run condition. In any case, the frame generating this fault will be ter- minated. This should never happen since the depth of the elastic buffer (10 bits) is greater than twice the maxi- mum number of bit times the receive and transmit clocks may slip during a maximum length packet assuming clock frequency tolerances of 100ppm or less. 7 Reset Complete Read Only 0 When set, this bit indicates that the internal analog calibration cycle has completed, and all analog and digital circuitry is ready for normal operation. 6 Jabber Detect Read Only 0 In 10BASE-T mode, if the last transmission is longer than 105ms, then the packet output is terminated by the jabber logic and this bit is set. This bit is implemented with a latching function so that the occurrence of a jabber condition causes it to become set until it is cleared by a read to this regis- ter, a read to the Basic Mode Status Register (address 01h), or a reset. No jabber detect function has been defined for 100BASE-TX. This bit is the same as in the Basic Mode Status Reg- ister (address 01h). 5 Auto-Neg Complete Read Only 0 This bit is set when the auto-negotiation process has completed. This is an indication that the Auto-Negoti- ation Advertisement Register (address 04h), the Auto-Negotiation Link Partner Ability Register (address 05h), and the Auto-Negotiation Expansion Register (address 06h) are valid. This bit is the same as in the Basic Mode Status Reg- ister (address 01h). 4 Parallel Detection Read Only 0 When set, this bit indicates an error condition in Fault which auto-negotiation has detected that unstable 10BASE-T or 100BASE-TX link signalling was received. This bit is self-clearing. This bit is the same as in the Auto-Negotiation Expansion Register (address 06h) 3 Parallel Fail Read Only 0 When set, this bit indicates that a parallel detection has occurred for a technology that is not currently advertised by the local device. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 45 DS206F1

CS8952 BIT NAME TYPE RESET DESCRIPTION 2 Remote Fault Read Only 0 When auto-negotiation is enabled, this bit is set if the Remote Fault bit is set in the Auto-Negotiation Link Partner Ability Register (address 05h). When auto- negotiation is disabled, this bit will be set when the Far-End Fault Indication for 100BASE-TX is detected. 1 Page Received Read Only 0 When set, this bit indicates that a valid word of auto- negotiation data has been received and its integrity verified. The first page of data will consist of the Base Page, and all successive pages will consist of Next Page data. This bit is self-clearing. This bit is the same as in the Auto-Negotiation Expansion Register (address 06h). 0 Reserved Read Only 0 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 46 DS206F1

CS8952 6.11 Disconnect Count Register - Address 12h 15 14 13 12 11 10 9 8 Disconnect Counter 7 6 5 4 3 2 1 0 Disconnect Counter BIT NAME TYPE RESET DESCRIPTION 15:0 Disconnect Counter Read/Write 0000h This field contains a count of the number of times the CS8952 has lost a Link OK condition. This counter is cleared upon readout and will roll-over to 0000h. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 47 DS206F1

CS8952 6.12 False Carrier Count Register - Address 13h 15 14 13 12 11 10 9 8 False Carrier Counter 7 6 5 4 3 2 1 0 False Carrier Counter BIT NAME TYPE RESET DESCRIPTION 15:0 False Carrier Read Only 0000h This field contains a count of the number of times the Counter CS8952 has detected a false-carrier -- that is, the reception of a poorly formed Start-of-Stream Delim- iter (SSD). The counter is incremented at the end of such events to prevent multiple increments. This counter is cleared upon readout and will saturate at FFFFh. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 48 DS206F1

CS8952 6.13 Scrambler Key Initialization Register - Address 14h 15 14 13 12 11 10 9 8 Load Reserved Scrambler Initialization Key 7 6 5 4 3 2 1 0 Scrambler Initialization Key BIT NAME TYPE RESET DESCRIPTION 15 Load Read/Set 0 When this bit is set, the scrambler will be loaded with the value in the Scrambler Initialization Key field. When the load is complete, this bit will clear automat- ically. 14:11 Reserved Read Only 0000 These bits should be read as don’t cares and, when written, should be written to 0. 10:0 Scrambler Initializa- Read/Write Reset value is This field allows the Scrambler to be loaded with a tion Key dependent on the user-definable key sequence. A value of 000h has PHY Address field the effect of bypassing the scrambler function. of the Self Status Register (address This is valuable for testing purposes to allow a deter- 19h). ministic response to test stimulus without a synchro- nization delay. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 49 DS206F1

CS8952 6.14 Receive Error Count Register - Address 15h 15 14 13 12 11 10 9 8 Receive Error Counter 7 6 5 4 3 2 1 0 Receive Error Counter BIT NAME TYPE RESET DESCRIPTION 15:0 Receive Error Read Only 0000h This counter increments for each packet in which one Counter or more receive errors is detected that is not due to a collision event. This counter is cleared upon readout and will roll-over to 0000h. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 50 DS206F1

CS8952 6.15 Descrambler Key Initialization Register - Address 16h 15 14 13 12 11 10 9 8 Load Reserved Descrambler Initialization Key 7 6 5 4 3 2 1 0 Descrambler Initialization Key BIT NAME TYPE RESET DESCRIPTION 15 Load Read/Set 0 When this bit is set, the descrambler will be loaded with the value in the Descrambler Initialization Key field. When the load is complete, this bit will clear automatically. 14:11 Reserved Read Only 0000 These bits should be read as don’t cares and, when written, should be written to 0. 10:0 Descrambler Initial- Read/Write Reset value is This register allows the Descrambler to be loaded ization Key dependent on the with a user-definable key sequence. A value of 000h PHY Address field has the effect of bypassing the descrambler function. of the Self Status Register (address This is valuable for testing purposes to allow a deter- 19h). ministic response to test stimulus without a synchro- nization delay. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 51 DS206F1

CS8952 6.16 PCS Sub-Layer Configuration Register - Address 17h 15 14 13 12 11 10 9 8 Time-Out Time-Out Repeater MR Preamble NRZI Enable LED5 Mode Unlock Regs Fast Test Select Disable Mode Enable 7 6 5 4 3 2 1 0 CLK25 Disable Enable LT/100 CIM Disable Tx Disable Rx Disable LED1 Mode LED4 Mode Digital Reset BIT NAME TYPE RESET DESCRIPTION 15 NRZI Enable Read/Write 1 When this bit is set, the NRZI encoder and decoder are enabled. When this bit is clear, NRZI encoding and decoding are disabled. 14 Time-Out Select Read/Write 0 When this bit is set, the time-out counter in the receive descrambler is set to time-out after 2ms without IDLES. When clear the counter is set to time- out after 722µs without IDLES. 13 Time-Out Disable Read/Write 0 When this bit is set, the time-out counter in the receive descrambler is disabled. When this bit is clear, the time-out counter is enabled. 12 Repeater Mode Read/Write Reset to the value This bit defines the mode of the Carrier Sense (CRS) on the signal. When this bit is set, CRS is asserted due to REPEATER pin. receive activity only. When this bit is clear, CRS is asserted due to either transmit or receive activity. 11 LED5 Mode Read/Write 0 This bit defines the mode of Pin LED5. When this bit is set, pin LED5 indicates the synchronization status of the 100BASE-TX descrambler. When this bit is clear, LED5 indicates a collision. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 10 Unlock Regs Read/Write 0 When set, this bit unlocks certain read only control registers for factory testing. Leave clear for proper operation. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 52 DS206F1

CS8952 BIT NAME TYPE RESET DESCRIPTION 9 MF Preamble Read/Write 0 When set, this bit will force all management frames Enable (via MDIO, MDC) to be preceded by a 32 bit pream- ble pattern of contiguous ones to be considered valid. When cleared, it allows management frames with or without the preamble pattern. The status of this register is (inversely) reflected in the MF Pream- ble bit in the Basic Mode Status Register (address 01h). Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 8 Fast Test Read/Write 0 When set, internal timers are sped up significantly in order to facilitate production test. Leave clear for proper operation. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 7 CLK25 Disable Read/Write When TCM pin is Setting this bit will disable (tri-state) the CLK25 out- low, reset to 1; put pin, reducing digital noise and power consump- otherwise, reset to tion. 0 6 Enable LT/100 Read/Write 1 When set, normal link status checking is enabled. When clear, this bit forces the link status to Link OK (at 100Mb/s), and will assert the LINK_OK LED. 5 CIM Disable Read/Write Reset to the logic When set, this bit forces the Carrier Integrity Monitor inverse of the function to be disabled. When low, the Carrier Integ- value on the rity Monitor function is enabled, and detection of an REPEATER pin. unstable link will disable the receive and transmit functions. 4 Tx Disable Read/Write 0 When set, this bit forces the 10Mb/s and 100Mb/s outputs to be inactive. When clear, normal transmis- sion is enabled. If Tx Disable is set while a packet is being transmit- ted, transmission is completed and no subsequent packets are transmitted until Tx Disable is cleared again. Also, if Tx Disable is cleared while TX_EN is high, the transmitter will remain disabled until TX_EN is deasserted. This prevents fragments from being transmitted onto the network. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 53 DS206F1

CS8952 BIT NAME TYPE RESET DESCRIPTION 3 Rx Disable Read/Write 0 When set, the receiver is disabled and no incoming packets pass through the receiver. The link will remain established and, if operating at 100Mb/s, the descrambler will remain locked. When clear, the receiver is enabled. If Rx Disable is set while a packet is being received, reception is completed and no subsequent receive packets are allowed until Rx Disable is cleared again. Also, if Rx Disable is cleared while a packet is being received, the receiver will remain disabled until the end of the incoming packet. This prevents fragments from being sent to the MAC. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 2 LED1 Mode Read/Write 0 This bit defines the mode of Pin LED1. When this bit is set, pin LED1 indicates Carrier Integrity Monitor status as determined by the CIM Status bit in the Self Status Register (address 19h). When this bit is clear, LED1 indicates 10Mb/s or 100Mb/s transmission activity. 1 LED4 Mode Read/Write 0 This bit defines the mode of Pin LED4. When this bit is set, pin LED4 indicates full duplex mode for 10Mb/s or 100Mb/s. When this bit is clear, LED4 indicates Polarity in 10Mb/s mode or full-duplex in 100Mb/s mode. 0 Digital Reset Read/Write 0 When set, this bit will reset all digital logic and regis- ters to their initial values. The analog circuitry will not be affected. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 54 DS206F1

CS8952 6.17 Loopback, Bypass, and Receiver Error Mask Register - Address 18h 15 14 13 12 11 10 9 8 Bypass Bad SSD Bypass ENDEC Remote PMD Bypass 4B5B Symbol FX Drive Enable Scrambler Loopback Loopback Loopback Alignment 7 6 5 4 3 2 1 0 Loopback Premature End Alternate FDX Code Error Link Error Packet Error Code Error Strip Preamble Transmit Error Report CRS Report Select Report Enable Report Enable Report Enable Disable Select BIT NAME TYPE RESET DESCRIPTION 15 Bad SSD Enable Read/Write 1 When set, this bit enables the reporting of a bad SSD (False-Carrier event) on the MII. These events will be reported by setting RX_ER=1, RX_DV=0, and RXD[3:0]=1110. If the 4B5B encoders are being bypassed, this event will be reported by setting RX_DV=0 and RXD[4:0]=11110. If symbol alignment is bypassed, the CS8952 does not detect carrier, and thus will not report bad SSD events. 14 Bypass 4B5B Read/Write Reset to the value When set, this bit causes the receive 5B4B decoder on the BP4B5B and the transmit 4B5B encoder to be bypassed. pin. 13 Bypass Scrambler Read/Write Reset to the value When set, this bit causes the receive descrambler on the BPSCR and the transmit scrambler blocks to be bypassed, pin. and the CS8952 accepts NRZI data from an external 100BASE-FX optical module through pins RX_NRZ+ and RX_NRZ-. 12 Bypass Symbol Read/Write Reset to the value When set, this bit causes the following functions to Alignment on the BPALIGN be bypassed: receiver descrambling, symbol align- pin. ment and decoding, transmit symbol encoding, and transmit scrambling. 11 ENDEC Loopback Read/Write 0 When set, the 10BASE-T internal Manchester encoder output is connected to the decoder input. When clear, the CS8952 is configured for normal operation. 10 FX Drive Read/Write 0 This bit controls the drive strength of the 100BASE- FX PECL interface drivers. When clear, the drivers are optimized for a 50Ω load. When set, the drivers are optimized for a 150Ω load. 9 Remote Loopback Read/Write 0 When set, data received from the link is looped back at the MII and sent back out to the link. Received data will be presented on the MII pins. Transmit data at the MII will be ignored. Note: Setting Remote Loopback and PMD Loopback simultaneously will cause neither loopback mode to be entered, and should not be done. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 55 DS206F1

CS8952 BIT NAME TYPE RESET DESCRIPTION 8 PMD Loopback Read/Write 0 When set, the scrambled NRZI transmit data is con- nected directly to the NRZI receive port on the descrambler. The loopback includes all of the 100BASE-TX functionality except for the MLT-3 encoding/decoding and the analog line-interface blocks. When clear, the CS8952 is configured for normal operation. Note: Setting Remote Loopback and PMD Loopback simultaneously will cause neither loopback mode to be entered, and should not be done. 7 Strip Preamble Read/Write 0 When set this bit causes the 7 bytes of MAC pream- ble to be stripped off of incoming 100Mb/s frames. The data received across the MII will begin with the 1 byte Start of Frame Delimiter (SFD). Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 6 Alternate FDX CRS Read/Write 0 This bit changes the behavior of the CRS pin only in the full-duplex (FDX) mode of operation. When set, CRS will be asserted for transmit data only. When clear, CRS will be asserted only for receive data. 5 Loopback Transmit Read/Write 1 This bit controls whether loopback data is transmitted Disable onto the network. When set, any data transmitted during PMD or ENDEC loopback mode will NOT be transmitted onto the network. When clear, data will be transmitted on the TX+/- pins as well as looped back onto the MII pins. 4 Code Error Report Read/Write 0 When set, this bit causes code errors to be reported Select by a value of 5h on RXD[3:0] and the assertion of RX_ER. When clear, this bit causes code errors to be reported by a value of 6h on RXD[3:0] and the asser- tion of RX_ER. This bit is superseded by the Code Error Report Enable bit. 3 Premature End Read/Write 0 When set, this bit causes premature end errors to be Error Report Select reported by a value of 4h on RXD[3:0] and the asser- tion of RX_ER. When clear, this bit causes premature end errors to be reported by a value of 6h on RXD[3:0] and the assertion of RX_ER. A premature end error is caused by the detection of two IDLE symbols in the 100Mb/s receive data stream prior to the End of Stream Delimiter. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 56 DS206F1

CS8952 BIT NAME TYPE RESET DESCRIPTION 2 Link Error Report Read/Write 0 When set, this bit causes link errors to be reported by Enable a value of 3h on RXD[3:0] and the assertion of RX_ER. When clear, link errors are not reported across the MII. 1 Packet Error Report Read/Write 0 When set, this bit causes packet errors to be Enable reported by a value of 2h on RXD[3:0] and the asser- tion of RX_ER. When clear, packet errors are not reported across the MII. 0 Code Error Report Read/Write 0 When set, code errors are reported and transmitted Enable on RXD[3:0]. When clear, this bit enables the Code Error Report values on RXD[3:0] as selected by the Code Error Report Select bit and also causes the assertion of TX_ER to transmit a HALT code group. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 57 DS206F1

CS8952 6.18 Self Status Register - Address 19h 15 14 13 12 11 10 9 8 Power Receiving Descrambler Disable CRS Auto-Neg Link OK PAUSE FEFI Enable Down Data Lock on Time-out Enable Status 7 6 5 4 3 2 1 0 10BASE-T Full Duplex CIM Status PHY Address Mode BIT NAME TYPE RESET DESCRIPTION 15 Link OK Read Only 0 When set, this bit indicates that a valid link connec- tion has been detected. The type of link established may be determined from bits 6, 7, and 9. When clear, this bit indicates that a valid link connection does not exist. This bit may be used to determine the current status of the link. 14 Power Down Read Only 1 When high, this bit indicates that the CS8952 is in a low power state. 13 Receiving Data Read Only 0 This bit is high whenever the CS8952 is receiving valid data. It is a direct copy of the state of the RX_DV pin accessible by software. 12 Descrambler Lock Read Only 0 When high, this bit indicates that the descrambler has successfully locked to the scrambler seed of the far-end transmitter and is able to descramble received data. 11 Disable CRS on Read/Write Reset to the logic This bit controls the state of the CRS pin upon a Time-out inverse of the descrambler time-out. When set, CRS will be forced value on the low upon a descrambler time-out, and will not be REPEATER pin. released until the descrambler has re-acquired syn- chronization. 10 Auto-Neg Enable Read Only If auto-negotiation This bit reflects the value of bit 12 in the Basic Mode Status is enabled via the Control Register (address 00h). When set, it indi- AN[1:0] pins, reset cates that auto-negotiation has been enabled. When to 1; otherwise, clear, this bit indicates that the mode of the CS8952 reset to 0. has been forced to that indicated by bits 6, and 7. 9 PAUSE Read Only 0 When set, this bit indicates that the Flow-Control PAUSE function has been negotiated. This indicates that both the local device and the link partner have advertised this capability. 8 FEFI Enable Read/Write 0 This bit controls the Far-End Fault Generate and Detect state machines. When this bit is set and auto- negotiation is disabled (bit 10 is clear), both state machines are enabled. When clear, this bit disables both state machines. 7 Full Duplex Read Only If a full duplex When set, this bit indicates that the CS8952 has mode is enabled been configured for Full-Duplex operation. via the AN[1:0] pins, reset to 1; otherwise, reset to 0. 6 10BASE-T Mode Read Only 0 When set, this bit indicates that the CS8952 has been configured for 10Mb/s operation. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 58 DS206F1

CS8952 BIT NAME TYPE RESET DESCRIPTION 5 CIM Status Read Only 0 When clear, this bit indicates that a stable link con- nection has been detected. When an unstable link is detected and the Carrier Integrity Monitor Disable bit in the PCS Sub-Layer Configuration Register (address 17h) is clear, this bit is set and latched. It will remain set until this register is read. 4:0 PHY Address Field Read/Write Reset to the val- The value on pins PHYAD[4:0] are latched into this ues on the field at power-up or reset. These bits define the PHY PHYAD[4:0] pins. address used by the management layer to address the PHY. The external logic must know this address in order to select this particular CS8952’s registers individually via the MDIO and MDC pins. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 59 DS206F1

CS8952 6.19 10BASE-T Status Register - Address 1Bh 15 14 13 12 11 10 9 8 10BASE-T Reserved Polarity OK Reserved Serial 7 6 5 4 3 2 1 0 Reserved BIT NAME TYPE RESET DESCRIPTION 15:11 Reserved Read Only 0 0000 10 Polarity OK Read Only 0 When high, the polarity of the receive signal (at the RXD+/RXD- inputs) is correct. If clear, the polarity is reversed. If the Polarity Disable bit of 10BASE-T Configuration Register (address 1Ch) is clear, then the polarity is automatically corrected, if needed. The Polarity OK status bit shows the true state of the incoming polarity independent of the Polarity Disable bit. 9 10BASE-T Serial Read/Write Reset to the value When set, this bit selects 10BASE-T serial mode. on the 10BT_SER When low, this bit selects 10BASE-T nibble mode. pin. This bit will only affect the CS8952 if it has been con- figured for 10Mb/s operation. 8:0 Reserved Read Only 0 0000 0000 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 60 DS206F1

CS8952 6.20 10BASE-T Configuration Register - Address 1Ch 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 National LED3 Blink Low Rx Polarity Compatibility Enable LT/10 SQE Enable Reserved Jabber Enable Enable Squelch Disable Mode BIT NAME TYPE RESET DESCRIPTION 15:8 Reserved Read Only 0000 0000 7 National Compati- Read/Write 1 When set, registers and bits that are not compatible bility Mode with the National DP83840 are disabled and writes to these registers are ignored. 6 LED3 Blink Enable Read/Write 0 When set, LED3 will blink during auto-negotiation and will indicate Link Good status upon completion of auto-negotiation. When clear, LED3 indicates Link Good status only. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit (bit 7) is set. 5 Enable LT/10 Read/Write 1 When set, this bit enables the transmission of link pulses. When clear, link pulses are disabled and a good link condition is forced. If link pulses are disabled during 100Mb/s operation with auto-negotiation enabled, the CS8952 will go into 10Mb/s mode. If operating in 100Mb/s mode with no auto-negotiation, then clear- ing this bit has no effect. 4 SQE Enable Read/Write Reset to the logic When set, and if the CS8952 is in half-duplex mode, inverse of the this bit enables the 10BASE-T SQE function. When value on the the part is in repeater mode, this bit is cleared and REPEATER pin. may not be set. 3 Reserved Read Only 1 This bit should be read as a don’t care and, when written, should be written to 1. 2 Low Rx Squelch Read/Write 0 When clear, the 10BASE-T receiver squelch thresh- olds are set to levels defined by the ISO/IEC 8802-3 specification. When set, the thresholds are reduced by approximately 6dB. This is useful for operating with “quiet” cables that are longer than 100 meters. 1 Polarity Disable Read/Write 0 The 10BASE-T receiver automatically determines the polarity of the received signal at the RXD+/RXD- input. When this bit is clear, the polarity is corrected, if necessary. When set, no effort is made to correct the polarity. Polarity correction will only be performed during 10BASE-T packet reception. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit (bit 7) is set. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 61 DS206F1

CS8952 BIT NAME TYPE RESET DESCRIPTION 0 Jabber Enable Read/Write 1 When set, the jabber function is enabled. When clear, and if the CS8952 is in 10BASE-T full-duplex or 10BASE-T ENDEC loopback mode, the jabber function is disabled. Note: When the National Compatibility Mode bit (bit 7) is set, the Jabber function may also be disabled for 10BASE-T half-duplex, although this is not rec- ommended. 7. DESIGN CONSIDERATIONS and TX input circuits to the DC-isolated ground plane. The 0.01 µF capacitor C1 must provide 2kV The CS8952 is a mixed-signal device containing (1,500Vrms for 60 seconds) of isolation to meet the high-speed digital and analog circuits required 802.3 requirements. If a shielded RJ45 connector is to implement Fast Ethernet communication. It is used (recommended), the shield should be connect- important the designer adhere to the following ed to chassis ground. guidelines and recommendations for proper and re- liable operation of the CS8952. These guidelines 7.2 100BASE-FX Interface will also benefit the design with good EMC perfor- Figure 7 shows the recommended connection for a mance. 100BASE-FX interface to a Hewlett-Packard 7.1 Twisted Pair Interface HFBR-5103 fiber transceiver. Termination circuit- ry may need to be revised for other fiber transceiv- The recommended connection of the twisted-pair ers. The FX Drive bit in the Loopback, Bypass, and interface is shown if Figure 6. The unused cable Receiver Error Mask Register (address 18h) may pairs are terminated to increase the common-mode be used to tailor the PECL interface for 50Ω or performance. Common-mode performance is also 150Ω loads. improved by connecting the center taps of the RX T1 TG22-3506 80 16 10 TX+ 1 SHLD 2 14 12 CS8952 3 51 Ω 4 81 15 11 TX- 51 Ω 5 91 2 6 RJ-45 RX+ 6 5 51 Ω 7 92 1 7 51 Ω 8 RX- SHLD 75 Ω 49.9 Ω 49.9 Ω 3 75 Ω 51 Ω 51 Ω NC 0.1 µF 0.1 µF 0.01 µF 2KV Figure 6. Recommended Connection of Twisted-Pair Ports (Network Interface Card) CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 62 DS206F1

CS8952 +5 CS8952 68 Ω 82 Ω HFBR-5103 FIBER TRANS. 8 SIGNAL- 9 4 SIGNAL+ SD 191 Ω 130 Ω +5 1 µH Ferrite Bead 5 RxV CC +5 0.1 µF 0.1 µF 1 µH 0.1 µF 63.4 Ω Ferrite Bead 6 TxV CC 49.9 Ω 49.9 Ω 0.1 µF 0.1 µF 4 7 TX_NRZ- TD- 5 8 TX_NRZ+ TD+ +5 82 Ω 82 Ω 6 3 RX_NRZ- RD- 7 2 RX_NRZ+ RD+ 130 Ω 130 Ω 1 RxV EE 9 TxV EE Figure 7. Recommended Connection of Fiber Port TX_NRZ+/- termination components should be tor biases the internal analog circuits of the CS8952 placed as close to the fiber transceiver as possible, and should be placed as close as possible to RES while RX_NRZ+/- and SIGNAL+/- termination pin. Connect the other end of this resistor directly components should be placed close to the CS8952. to the ground plane. Connect the adjacent CS8952 ground pins (pins 85 and 87) to the grounded end of The CS8952 100BASE-FX interface IO pins the resistor forming a “shield” around the RES con- (TX_NRZ+, TX_NRZ-, RX_NRZ+, RX_NRZ-, nection. SIGNAL+, and SIGNAL-) may be left unconnect- ed if a fiber interface is not used. 7.4 Clocking Schemes 7.3 Internal Voltage Reference The CS8952 may be clocked using one of three A 4.99 kΩ biasing resistor must be connected be- possible schemes: using a 25MHz crystal and the internal oscillator, using an external oscillator sup- tween the CS8952 RES pin and ground. This resis- CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 63 DS206F1

CS8952 with transformers meeting these requirements. However, the designer should evaluate the magnet- ics for suitability in their specific design. CS8952 7.6 Power Supply and Decoupling 87 VSS 4.99 kΩ The CS8952 supports connection to either a 3.3 V 86 Via to R ES Ground Plane or 5.0V MII. When connected to a +5.0 V MII, all 85 VSS power pins should be provided +5.0 V +/- 5%, and all signal inputs should be referenced to +5.0V. When interfaced with a 3.3 V MII, VDD_MII pow- er pins should be provided +3.3 V +/- 5%, VDD Figure 8. Biasing Resistor Connection and Layout power pins should be provided +5.0 V +/- 5%, and plied through the XTAL_I pin, or using an external all signal inputs should be referenced to +3.3V. clock source supplied through the TX_CLK pin. When a 25 MHz crystal is used, it should be placed Component Manufacturer Part Number within one inch of the XTAL_I and XTAL_O pins Raltron Electronics Corp. AS-25.000-15-F- 10651 NW 19th St. EXT-SMD-TR- of the CS8952. The crystal traces should be short, Crystal Miami, FL 33172 CIR have no vias, and run on the component side. (305) 593-6033 www.raltron.com Table 7 lists examples of manufacturers of suitable Halo Electronics, Inc. TG22-3506ND crystals. The designer should evaluate their crystal P.O. Box 5826 selection for suitability in their specific design. Redwood City, CA 94063 USA An external CMOS clock source may be connected (650) 568-5800 www.haloelectronics.com to the XTAL_I pin, with the XTAL_O pin left Bel Fuse, Inc. S5558-5999-46 open. The input capacitance of the XTAL_I pin is 198 Van Vorst Street Jersey City, NJ 07302 larger than the other inputs (a maximum of 35pF), Transformer USA since it includes the additional load capacitance of (201) 432-0463 www.belfuse.com the crystal oscillator. Care should be taken to as- Pulse Engineering PE-68515 sure any external clock source attached to XTAL_I 12220 World Trade Drive San Diego, CA 92128 is capable of driving higher capacitive loads. The USA clock signal should be 25MHz ±0.01% with a duty (619) 674-8100 www.pulseeng.com cycle between 45% and 55%. Hewlett Packard HFBR-5103 When the XTAL_I pin load is a problem, or only a Fiber Component Sales Response Center TTL level clock source is available, the CS8952 Interface (408) 654-8675 can be clocked through the TX_CLK pin, provid- www.hp.com/HP-COMP ing the TX_CLK mode is set appropriately using Table 7. Support Component Manufactures the TCM pin. The clock frequency will be depen- Each CS8952 power pin should be connected to a dent on the operating mode. 0.1µF bypass capacitor and then to the power plane. The bypass capacitors should be located as 7.5 Recommended Magnetics close to its corresponding power pin as possible. The CS8952 requires an isolation transformer with Connect ground pins directly to the ground plane. a 1:1 turns ratio for both the transmit and receive signals. Table 7 lists examples of manufacturers CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 64 DS206F1

CS8952 7.7 General Layout Recommendations transmission lines (100 Ω differential, 50Ω single-ended). The MII signals should be 68Ω The following PCB layout recommendations will microstrip transmission lines. (For short MII help ensure reliable operation of the CS8952 and signal paths one may standardize on a given good EMC performance. trace width for all traces without significant • Use a multilayer Printed Circuit Board with at degradation in signal integrity.) least one ground and one power plane. A typi- • Avoid routing traces other than the TX and RX cal +5V MII application would be as follows: signals under transformer T1 and the RJ45 con- Layer 1: (top) Components and first choice sig- nector. Signals may run on the bottom side un- nal routing derneath the CS8952 as long as they stay away Layer 2: Ground from critical analog traces. Layer 3: Power (+5V) Layer 4: (bottom) Second choice signal rout- • Connect all CS8952 ground and power pins di- ing, bypass components rectly to the ground and power planes, respec- • Place transformer TI as close to the RJ45 connec- tively. Note: The VDD_MII power pins may tor as possible with the secondary (network) side need their own power plane or plane segment in facing the RJ45 and the primary (chip) side facing +3.3V MII applications. the analog side (pins 76-100) of CS8952. Place • Depending on the orientation and location of the CS8952 in turn as close to T1 as possible. the transformer, the CS8952, and the RJ-45, • Use the bottom layer for signal routing as a sec- and on whether the application is for a NIC or a ond choice. You may place all components on switch, the RX and TX pairs may need to cross. the top layer. However, bypass capacitors are This should be done by changing layers on a optimally placed as close to the chip as possible pair by pair basis only, using the minimum and may be best located underneath the number of vias, and making sure that each trace CS8952 on the bottom layer. Termination com- within a pair “sees” the same path as its peer. ponents at the RJ-45 and fiber transceiver may also be optimally placed on the bottom layer. Figure 6 shows the CS8952 in a NIC or adapter • Connect a 0.1µF bypass capacitor to each configuration. It may be configured for a hub or repeater application by changing the wiring to CS8952 VDD and VDD_MII pin. Place it as the RJ-45 as shown in Table 8. close to its corresponding power pin as possible and connect the other lead directly to the • Differential pair transmission lines should be ground plane. routed close together (one trace width spacing edge-to-edge) and kept at least two trace widths • The 4.99k reference resistor should be placed away from other traces, components, etc. TX as close to the RES pin as possible. Connect the and RX pairs should be routed away from each other end of this resistor to the ground plane us- other and may use opposite sides of the PCB as ing a via. Connect the adjacent VSS pins (pins necessary, Each member of the differential pair 85 and 87) to the grounded end of the resistor should “see” the same PCB terrain as its peer. forming a shield as illustrated in Figure 8. • Unused spaces on the signal layers should be • Controlled impedance is necessary for critical filled with ground fill (pour). Vias should con- signals TX+/-, RX+/-, TX_NRZ+/-, and nect the ground patches to the ground plane. RX_NRZ+/-. These should be run as microstrip This is especially recommended (symmetrical- CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 65 DS206F1

CS8952 ly) on both sides of the TX+/- traces. CS8952 Pin T1 Primary Pin T1 Secondary RJ-45 Pin Assignment Assignment Assignment Pin Assignment Adapter/NIC Hub/Repeater Configuration Configuration 91 (RX+) 1 (RX+) 7 (RX+) 3 (RD+) 1 (RD+) 92 (RX-) 2 (RX-) 6 (RX-) 6 (RD-) 2 (RD-) 81 (TX-) 16 (TX-) 10 (TX-) 2 (TD+) 6 (TD-) 80 (TX+) 15 (TX+) 11 (TX+) 1 (TD+) 3 (TD+) Table 8. RJ-45 Wiring • No signal current carrying planes, i.e. no transceiver, and the RX_NRZ+/- and SIG- ground or power plane, should be present un- NAL+/- termination components must be kept derneath the region between the transformer close to the CS8952. secondary (network) side and the RJ-45. How- • Locate the crystal as close to the CS8952 as ever, a chassis plane may be added in this re- possible, running short traces on the component gion to pick up the metal tabs of a shielded RJ- side in order to reduce parasitic load capaci- 45. This chassis plane should be separated from tance. the ground and power planes by at least • Add bulk capacitance at each connector where 50mils. That is, all other ground and power power may be supplied. For example, MII pow- planes should be “cookie cuttered” so they are er may be provided at the MII connector and at voided in the area of the chassis plane. Gener- a separate connector for test purposes. If so, and ally speaking, parts should not cross the moat the two connectors are not adjacent, then the except for the transformer. bulk capacitors should be duplicated in each lo- • Proper termination practices must be used with cations. all transmission lines, especially if sending and • Use wide traces to connect the “Bob Smith” ter- receiving high speed signals on and off the mination resistors at T1 and the RJ-45 to the board. Series terminations must be kept close to 2 kV capacitor or capacitors in order to mini- the source and load terminations close to the mize their lead inductance. load. Thus the TX_NRZ+/- termination com- ponents must be kept close to the fiber optic CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 66 DS206F1

CS8952 8. PIN DESCRIPTIONS Pin Diagram O DD__I D DD LL DDSVSVTATASSDDSSX-X+SSDDDDSSESSSSVSSDDX-X+DDSSSVSV VRRXXVVVRRVVVVRVRVVTTVVRR 0987654321098765432109876 0999999999988888888887777 VSS 1 1 75 RSVD VDD 2 74 RSVD VSS 3 73 LED5 TX_NRZ- 4 72 LED4 TX_NRZ+ 5 71 LED3 RX_NRZ- 6 70 LED2 RX_NRZ+ 7 69 LED1 SIGNAL- 8 68 SPD10 SIGNAL+ 9 67 SPD100 VSS 10 66 VDD_MII VDD 11 CS8952 100-pin 65 VSS VSS 12 64 PWRDN TQFP VSS 13 63 ISODEF RX_EN 14 (14 mm x 14 mm) 62 BPSCR RESET 15 61 TXSLEW1 REPEATER 16 60 TXSLEW0 CLK25 17 59 TCM VSS 18 58 AN1 VDD 19 57 AN0 VSS 20 56 BP4B5B VDD_MII 21 55 VSS VSS 22 54 VDD 10BT_SER 23 53 VSS TEST0 24 52 BPALIGN TEST1 25 51 LPBK 6789012345678901234567890 2222333333333344444444445 _IRQMDIOMDCYAD3RXD2YAD1RXD0_DRVD_MIIVSS_CLKYAD4TXD4VSSVDDVSS_CLKX_ENTXD0TXD1TXD2TXD3YAD0YAD2STRT MII 3/PH 1/PH V/MIIVD RX4/PH_ER/ TXT L/PHS/PHLP D D D DX OR X X _ XT CC R R X R R R/ E _ X R CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 67 DS206F1

CS8952 MII Interface Pins COL/PHYAD0 - Collision Detect/PHY Address 0. Input/Tri-State Output, Pin 48. Asserted active-high to indicate a collision on the medium during half-duplex operation. In full-duplex operation, COL is undefined and should be ignored. When configured for 10Mb/s operation, COL is also used to indicate a Signal Quality Error (SQE) condition. At power-up or at reset, the logic value on this pin is latched into bit 0 of the PHY Address field of the Self Status Register (address 19h). This pin includes a weak internal pull-down (>20kΩ), or the value may be set by an external 4.7kΩ pull-up or pull-down resistor. CRS/PHYAD2 - Carrier Sense/PHY Address 2. Input/Tri-State Output, Pin 49. The operation of CRS is controlled by the REPEATER pin as follows: REPEATER pin DUPLEX mode CRS Indicates high don’t care receive activity only low full duplex receive activity only low half duplex receive or transmit activity At power-up or at reset, the logic value of this pin is latched into bit 2 of the PHY Address Field of the Self Status Register (address 19h). This pin includes a weak internal pull-down (>20kΩ), or the value may be set by an external 4.7kΩ pull-up or pull-down resistor. MDC - Management Data Clock. Input, Pin 28. Input clock used to transfer serial data on MDIO. The maximum clock rate is 16.67MHz. This clock may be asynchronous to RX_CLK and TX_CLK. MDIO - Management Data Input/Output. Bi-Directional, Pin 27. Bi-directional signal used to transfer management data between the CS8952 and the Ethernet controller. In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the MDIO pin should have an external 1.5kΩ pull-up resistor. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, the external pull-up resistor may not be necessary. MII_IRQ - MII Interrupt. Open Drain Output, Pin 26. Asserted low to indicate the status corresponding to one of the unmasked interrupt status bits in the Interrupt Status Register (address 11h) has changed. It will remain low until the ISR is read, clearing all status bits. This open drain pin requires a 4.7kΩ pull-up resistor. RX_CLK - Receive Clock. Tri-State Output, Pin 36 Continuous clock output used as a reference clock for sampling RXD[3:0], RX_ER, and RX_DV. RX_CLK will have the following nominal frequency: Speed 10BT_SER pin Nominal frequency 100Mb/s n/a 25MHz 10Mb/s low (parallel) 2.5MHz 10Mb/s high (serial) 10MHz CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 68 DS206F1

CS8952 In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the RX_CLK pin should have an external 33Ω series resistor. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, the external series resistor may not be necessary. RX_DV/MII_DRV - Receive Data Valid/MII Drive Strength. Input/Tri-State Output, Pin 33. Asserted high to indicate valid data nibbles are present on RXD[3:0]. At power-up or at reset, this pin is used as an input to determine the drive strength of the MII output drivers. When the pin is low, all MII output drivers will be standard 4 mA CMOS drivers. When high, additional drive strength will be added to the MII output drivers. This pin includes a weak internal pull- down (>20kΩ), or the value may be set by an external 4.7kΩ pull-up or pull-down resistor. In order to conform with Annex 22B of the IEEE 802.3u specification, this pin should be pulled high during power-up or reset and should have an external 33Ω series resistor. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, it may be possible to reduce overall power consumption by pulling the pin low at power-up or reset, and the external series resistor may not be necessary. RX_EN - Receive Enable. Input, Pin 14. When high, signals RXD[3:0], RX_CLK, RX_DV, and RX_ER are enabled. When low, these signals are tri-stated. RX_EN allows the received data signals of multiple PHY transceivers to share the same MII bus. This pin includes a weak internal pull-up (>150kΩ), or the value may be set by an external 10kΩ pull- up or pull-down resistor. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 69 DS206F1

CS8952 RX_ER/PHYAD4/RXD4 - Receive Error/PHY Address 4/Receive Data 4. Input/Tri-State Output, Pin 37. During normal MII operation, this pin is defined as RX_ER (Receive Error). When RX_DV is high, RX_ER asserted high indicates that an error has been detected in the current receive frame. When RX_DV is low and RXD[3:0] = “1110”, RX_ER high indicates a False Carrier condition. If either BPALIGN or BP4B5B is asserted, then this pin is re-defined as RXD4 (Receive Data4), the most-significant bit of the received five-bit code-group. If the 4B5B encoder is being bypassed, receive data is present when RX_DV is asserted. If alignment is being bypassed, data reception is continuous. At power-up or at reset, the logic value on this pin is latched into bit 4 of the PHY Address field of the Self Status Register (address 19h). This pin includes a weak internal pull-down (>20kΩ), or the value may be set by an external 4.7kΩ pull-up or pull-down resistor. In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the RX_ER pin should have an external 33Ω series resistor. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, the external series resistor may not be necessary. RXD3/PHYAD3 - Receive Data 3/PHY Address 3. Tri-State Output, Pin 29. RXD2 - Receive Data 2. Tri-State Output, Pin 30. RXD1/PHYAD1 - Receive Data 1/PHY Address 1. Tri-State Output, Pin 31. RXD0 - Receive Data 0. Tri-State Output, Pin 32. Receive data output. Receive data is present when RX_DV is asserted. RXD0 is the least-significant bit. For MII modes, nibble-wide data (synchronous to RX_CLK) is transferred on pins RXD[3:0]. In 10Mb/s serial mode, pin RXD0 is used as the serial output pin, and RXD[3:1] are ignored. When either BP4B5B or BPALIGN is selected, pin RXD4 contains the most-significant bit of the five-bit code-group. At power-up or at reset, the value on RXD1/PHYAD1 is latched into bit 1 of the PHY Address field of the Self Status Register (address 19h). This pin includes a weak internal pull-down (>20kΩ), or the value may be set by an external 4.7kΩ pull-up or pull-down resistor. At power-up or at reset, the logic value on RXD3/PHYAD3 is latched into bit 3 of the PHY Address field of the Self Status Register (address 19h). This pin includes a weak internal pull-down (>20kΩ), or the value may be set by an external 4.7kΩ pull-up or pull-down resistor. In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the RXD[3:0] pins should have external 33Ω series resistors. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, the external series resistors may not be necessary. TX_CLK - Transmit Clock. Input/Tri-State Output, Pin 42. Continuous clock signal used by the CS8952 as a reference clock to sample TXD[3:0], TX_ER, and TX_EN. TX_CLK can be referenced either internally (Output Mode) or externally (Input Mode) based upon the value of the TCM pin at power-up or at reset. TCM pin TX_CLK mode CLK25 status high TX_CLK is input CLK25 pin is an output floating TX_CLK is input CLK25 is disabled low TX_CLK is output CLK25 is disabled CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 70 DS206F1

CS8952 When the TCM pin is high on power-up or reset, the CLK25 pin may be used as a source for the TX_CLK pin. When the TCM pin is floating on power-up or reset, TX_CLK must be supplied externally. TX_CLK should have the following nominal frequency: Speed 10BT_SER pin Nominal frequency 100Mb/s n/a 25MHz 10Mb/s low (parallel) 2.5MHz 10Mb/s high (serial) 10MHz TX_EN - Transmit Enable. Input, Pin 43. Asserted high to indicate valid data nibbles are present on TXD[3:0]. When BPALIGN is selected, TX_EN must be pulled up to VDD_MII. TX_ER/TXD4 - Transmit Error Encoding/Transmit Data 4. Input, Pin 38. When high, TX_ER indicates to the CS8952 that a transmit error has occurred. If TX_ER is asserted simultaneously with TX_EN in 100Mb/s mode, the CS8952 will ignore the data on the TXD[3:0] pins and transmit one or more 100Mb/s HALT symbols in its place. In 10Mb/s mode, TX_ER has no effect on the transmitted data. If BP4B5B or BPALIGN are set, TX_ER/TXD4 is used to transmit the most-significant bit of the five-bit code group. TXD[3:0] - Transmit Data. Input, Pins 47, 46, 45, and 44. Transmit data input pins. For MII modes, nibble-wide data (synchronous to TX_CLK) must be presented on pins TXD[3:0] when TX_EN is asserted high. TXD0 is the least significant bit. In 10Mb/s serial mode, pin TXD0 is used as the serial input pin, and TXD[3:1] are ignored. When either BP4B5B or BPALIGN is selected, pin TXD4 contains the most significant bit of the five-bit code-group. Control and Status Pins 10BT_SER - 10Mb/s Serial Mode Select. Input, Pin 23. When asserted high during power-up or reset and 10Mb/s operation is selected, serial data will be transferred on pins RXD0 and TXD0. When low during power-up or reset and 10Mb/s operation is selected, data is transferred a nibble at a time on RXD[3:0] and TXD[3:0]. This pin is ignored during 100Mb/s operation. 10Mb/s serial mode may also be entered under software control through bit 9 of the 10BASE-T Status Register (address 1Bh). At power-up or at reset, the value on this pin is latched into bit 9 of the 10BASE-T Status Register (address 1Bh). This pin includes a weak internal pull-down (>20kΩ), or the value may be set by an external 4.7kΩ pull-up or pull-down resistor. AN[1:0] - Auto-Negotiate Control. Input, Pins 58 and 57. These three-level input pins are sampled during power-up or reset. They control the forced or advertised auto-negotiation operating modes. If one of these pins is left unconnected, internal logic pulls its signal to a mid-range value, 'M'. AN1 pin AN0 pin Speed Forced/Auto Full/Half Duplex 0 M 10Mb/s Forced Half CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 71 DS206F1

CS8952 AN1 pin AN0 pin Speed Forced/Auto Full/Half Duplex 1 M 10Mb/s Forced Full M 0 100Mb/s Forced Half M 1 100Mb/s Forced Full M M 100/10Mb/s Auto-Neg Full/Half 0 0 10Mb/s Auto-Neg Half 0 1 10Mb/s Auto-Neg Full 1 0 100Mb/s Auto-Neg Half 1 1 100Mb/s Auto-Neg Full Auto-Negotiation may also be enabled and the advertised capabilities modified under software control through bit 8 of the Basic Mode Control Register (address 00h), and bits 5, 6, 7, 8, and 10 of the Auto- Negotiation Advertisement Register (address 04h). These pins are pulled to ‘M’ through weak internal resistors (>150kΩ). Other values may be set by tying them directly to VDD_MII or VSS, or through external 10kΩ pull-up or pull-down resistors. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 72 DS206F1

CS8952 BP4B5B - Bypass 4B5B Coders. Input, Pin 56. When driven high during power-up or reset, the transmit 4B5B encoder and receiver 5B4B decoder are bypassed. Five-bit code groups are output and input on pins RXD[4:0] and TXD[4:0]. The 4B5B Coders may also be bypassed under software control through bit 14 of the Loopback, Bypass, and Receiver Error Mask Register (address 18h). At power-up or at reset, the value on this pin is latched into bit 14 of the Loopback, Bypass and Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down (>20kΩ), or the value may be set by an external 4.7kΩ pull-up or pull-down resistor. BPALIGN - Bypass Symbol Alignment. Input, Pin 52. When driven high during power-up or reset, the following blocks are bypassed: 4B5B encoder, 5B4B decoder, scrambler, descrambler, NRZI encoder, and NRZI decoder. Five-bit code groups are output and input on pins RXD[4:0] and TXD[4:0]. The receiver will output five-bit data with no attempt to identify code-group boundaries; therefore, the data in one RXD[4:0] word may contain data from two code groups. Symbol alignment may also be bypassed under software control through bit 12 of the Loopback, Bypass, and Receiver Error Mask Register (address 18h). At power-up or at reset, the value on this pin is latched into bit 12 of the Loopback, Bypass and Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down (>20kΩ), or the value may be set by an external 4.7kΩ pull-up or pull-down resistor. BPSCR - Bypass Scrambler. Input, Pin 62. When driven high during power-up or reset, the scrambler and descrambler is bypassed and NRZI FX mode is selected. The 100BASE-FX mode may also be entered under software control through bit 13 of the Loopback, Bypass, and Receiver Error Mask Register (address 18h). At power-up or at reset, the value on this pin is latched into bit 13 of the Loopback, Bypass and Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down (>20kΩ), or the value may be set by an external 4.7kΩ pull-up or pull-down resistor. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 73 DS206F1

CS8952 ISODEF - Isolate Default. Input, Pin 63. When asserted high during power-up or reset, the MII will power-up electrically isolated except for the MDIO and MDC pins. When low, the part will exit reset fully electrically connected to the MII. The MII may also be isolated under software control through bit 10 of the Basic Mode Control Register (address 00h). At power-up or at reset, the value on this pin is latched into bit 10 of the Basic Mode Control Register (address 00h). This pin includes a weak internal pull-down (>20kΩ), or the value may be set by an external 4.7kΩ pull-up or pull-down resistor. LED1 - Transmit Active LED. Open Drain Output, Pin 69. This active-low output indicates transmit activity. It contains a pulse stretcher to insure that the transmit events are visible when the pin is used to drive an LED. The definition of this pin may be modified to indicate Disconnect Detection (bit 5 of the Self Status Register (address 19h)) by setting bit 2 of the PCS Sub-layer Configuration Register (address 17h). This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin. LED2 - Receive Activity LED. Open Drain Output, Pin 70. This active-low output indicates receive activity. It contains a pulse stretcher to insure that the receive events are visible when the pin is used to drive an LED. This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin. LED3 - Link Good LED. Open Drain Output, Pin 71. This active-low output indicates the CS8952 has detected a valid link. This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin. LED4 - Polarity/Full Duplex LED. Open Drain Output, Pin 72. This active-low output indicates: 1) for 100Mb/s operation, the CS8952 is in full-duplex operation, 2) for 10Mb/s operation, either good polarity exists or full duplex is selected (see bit 1 in the PCS Sub- layer Configuration Register (address 17h)). This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin. LED5 - Collision/Descrambler Lock LED. Open Drain Output, Pin 73. This active-low output is asserted when either the CS8952 detects a collision (bit 11 of the PCS Sub- Layer Configuration Register (address 17h) is clear), or the 100BASE-TX descrambler is synchronized (bit 11 of the PCS Sub-Layer Configuration Register (address 17h) is set). It contains a pulse stretcher to insure that the collision events are visible when the pin is used to drive an LED. This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin. LPBK - Loopback Enable. Input, Pin 51. When this pin is asserted high and the CS8952 is operating in 100Mb/s mode, the CS8952 will perform a local loopback inside the PMD block, routing the scrambled NRZI output to the NRZI input port on the descrambler. The loopback includes all CS8952 100Mb/s functionality except the MLT-3 coders and the analog line interface blocks. When asserted high and the CS8952 is operating in 10Mb/s mode, the CS8952 will perform a local ENDEC loopback. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 74 DS206F1

CS8952 LPSTRT - Low Power Start. Input, Pin 50. When this active-low input is asserted during power-up or reset, the CS8952 will exit reset in a low power configuration, where the only circuitry enabled is that necessary to maintain the media impedance. The CS8952 will remain in a low power state until RESET pin is asserted or the MDC pin toggles. This pin includes a weak internal pull-down (>20kΩ), or the value may be set by an external 4.7kΩ pull-up or pull-down resistor. PWRDN - Power Down. Input, Pin 64. When this pin is asserted high, the CS8952 powers down all circuitry except that circuitry needed to maintain the network line impedance. This is the lowest power mode possible. The CS8952 will remain in low power mode until the PWRDN pin is deasserted. A slightly higher power power-down mode may also be entered under software control through bit 11 of the Basic Mode Control Register (address 00h). CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 75 DS206F1

CS8952 REPEATER - REPEATER Mode Select. Input, Pin 16. This pin controls the operation of the CRS (Carrier Sense) pin as shown below: REPEATER pin DUPLEX mode CRS Indicates high don’t care receive activity only low full duplex receive activity only low half duplex receive or transmit activity At power-up or at reset, the value on this pin is latched into bit 12 of the PCS Sub-Layer Configuration Register (address 17h). This pin includes a weak internal pull-down (>20kΩ), or the value may be set by an external 4.7kΩ pull-up or pull-down resistor. SPD10 - 10Mb/s Speed Indication. Output, Pin 68. This pin is asserted high when the CS8952 is configured for 10Mb/s operation. This pin can be used to drive a low-current LED to indicate 10Mb/s operation. SPD100 - 100Mb/s Speed Indication. Output, Pin 67. This pin is asserted high when the CS8952 is configured for 100Mb/s operation. This pin can be used to drive a low-current LED to indicate 100Mb/s operation. TCM - Transmit Clock Mode Initialization. Input, Pin 59. The logic value on this three-level pin during power-up or reset determines whether TX_CLK is used as an input or an output, and whether an external 25MHz clock reference is provided on the CLK25 output pin. TCM pin TX_CLK mode CLK25 status high TX_CLK is input CLK25 pin is an output floating TX_CLK is input CLK25 is disabled low TX_CLK is output CLK25 is disabled TEST[1:0] - Factory Test. Input, Pins 24 and 25. These pins are for factory test only. They include weak internal pull-downs (>20kΩ), and should be tied directly to VSS for normal operation. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 76 DS206F1

CS8952 TXSLEW[1:0] - Transmit Slew Rate Control. Input, Pins 61 and 60. These three-level pins allow adjustment to the rise and fall times of the 10BASE-TX transmitter output waveform. The rise and fall times are symmetric. TXSLEW0 pin TXSLEW1 mode Rise/Fall time low low 0.5 ns low floating 1.0 ns low high 1.5 ns floating low 2.0 ns floating floating 2.5 ns floating high 3.0 ns high low 3.5 ns high floating 4.0 ns high high 4.5 ns Media Interface Pins RX+, RX- - 10/100 Receive. Differential Input Pair, Pins 91 and 92. Differential input pair receives 10 or 100Mb/s data from the receive port of the transformer primary. TX+, TX- - 10/100 Transmit. Differential Output Pair, Pins 80 and 81. Differential output pair drives 10 or 100Mb/s data to the transmit port of the transformer primary. RX_NRZ+, RX_NRZ- - FX Receive. Differential Input Pair, Pins 6 and 7. PECL output pair receives 100Mb/s NRZI-encoded data from an external optical module. SIGNAL+, SIGNAL- - Signal Detect. Differential Input Pair, Pins 9 and 8. PECL input pair receives signal detection indication from an external optical module. TX_NRZ+, TX_NRZ- - FX Transmit. Differential Output Pair, Pins 5 and 4. PECL output pair drives 100Mb/s NRZI-encoded data to an external optical module. General Pins CLK25 - 25MHz Clock. Output, Pin 17. A 25MHz Clock is output on this pin when the CS8952 is configured to use an external reference transmit clock in TX_CLK IN MASTER mode. See the pin description for the Transmit Clock Mode Initialization pin (TCM) for more information on TX_CLK operating modes. CLK25 may also be enabled regardless of the TCM pin state by clearing bit 7 of the PCS Sub-layer Configuration Register (address 17h). RES - Reference Resistor. Input, Pin 86. This input should be connected to ground with a 4.99 kΩ +/-1% series resistor. The resistor is needed for the biasing of internal analog circuits. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 77 DS206F1

CS8952 RESET - Reset. Input, Pin 15. This active high input initializes the CS8952, and causes the CS8952 to latch the input signal on the following pins: COL/PHYAD0, CRS/PHYAD2, RX_ER/PHYAD4/RXD4, 10BT_SER, BP4B5B, BPALIGN, BPSCR, ISODEF, REPEATER, RXD[1]/PHYAD1, and RXD[3]/PHYAD3. XTAL_I - Crystal Input, Pin 96. XTAL_O - Crystal Output, Pin 97. A 25MHz crystal should be connected across pins XTAL_I and XTAL_O. If a crystal is not used, a 25MHz CMOS level clock may be connected to XTAL_I and XTAL_O left open. NOTE: The XTAL_I pin capacitive load may be as high as 35pF. Any external clock source connected to this pin must be capable of driving larger capacitive loads. RSVD - Reserved. Pins 74, 75, 76, 77, 84, 98, and 99. These seven pins are reserved and should be tied to VSS. VDD_MII - MII Power. Pins 21, 34, and 66. These pins provide power to the CS8952 MII interface. Typically VDD_MII will be either +5V or +3.3V. VDD - Core Power. Pins 2, 11, 19, 40, 54, 79, 82, 88, 89, 94, and 100. These pins provide power to the CS8952 core. Typically, VDD should be +5V. VSS - Ground. Pins 1, 3, 10, 12, 13, 18, 20, 22, 35, 39, 41, 53, 55, 65, 78, 83, 85, 87, 90, 93, and 95. These pins provide a ground reference for the CS8952. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 78 DS206F1

CS8952 9. PACKAGE DIMENSIONS. 100L TQFP PACKAGE DRAWING E E1 D D1 1 e B ∝ A A1 L INCHES MILLIMETERS DIM MIN MAX MIN MAX A --- 0.063 --- 1.60 A1 0.002 0.006 0.05 0.15 B 0.007 0.011 0.17 0.27 D 0.618 0.642 15.70 16.30 D1 0.547 0.555 13.90 14.10 E 0.618 0.642 15.70 16.30 E1 0.547 0.555 13.90 14.10 e* 0.016 0.024 0.40 0.60 L 0.018 0.030 0.45 0.75 ∝ 0.000° 7.000° 0.00° 7.00° * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 79 DS206F1

CS8952 10.ORDERING INFORMATION Part # Temperature Range Package Description CS8952-CQZ 0 °C to +70 °C 100-lead TQFP, Lead (Pb) Free CS8952-IQZ -40 °C to +85 °C 11.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS8952-CQZ 260 °C 3 7 Days CS8952-IQZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 80 DS206F1

CS8952 12.REVISION HISTORY Revision Date Changes PP3 OCT 2001 Initial Release. F1 JAN 2007 Added industrial temp range device. Added MSL data. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER- STOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, CrystalLAN, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 81 DS206F1

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