CS5521/22/23/24/28 16-bit or 24-bit, 2/4/8-channel ADCs with PGIA Features General Description Low Input Current (100 pA), Chopper- The CS5521/22/23/24/28 are highly integrated ΔΣ ana- stabilized Instrumentation Amplifier log-to-digital converters (ADCs) which use charge- balance techniques to achieve 16-bit (CS5521/23) and Scalable Input Span (Bipolar/Unipolar) 24-bit (CS5522/24/28) performance. The ADCs come as - 2.5V VREF: 25 mV, 55 mV, 100 mV, 1 V, either two-channel (CS5521/22), four-channel 2.5 V, 5 V (CS5523/24), or eight-channel (CS5528) devices and - External: 10 V, 100 V include a low-input-current, chopper-stabilized instru- mentation amplifier. To permit selectable input spans of Wide V Input Range (+1 to +5 V) REF 25mV, 55mV, 100mV, 1V, 2.5V, and 5V, the ADCs Fourth Order Delta-Sigma A/D Converter include a PGA (programmable gain amplifier). To ac- Easy to Use Three-wire Serial Interface Port commodate ground-based thermocouple applications, - Programmable/Auto Channel Sequencer with the devices include a charge pump drive which provides Conversion Data FIFO a negative bias voltage to the on-chip amplifiers. - Accessible Calibration Registers per Channel These devices also include a fourth-order ΔΣ modulator - Compatible with SPI™ and Microwire™ followed by a digital filter which provides eight selectable output word rates. The digital filters are designed to settle System and Self Calibration to full accuracy within one conversion cycle and when Eight Selectable Word Rates operated at word rates below 30Sps, they reject both - Up to 617 Sps (XIN = 200 kHz) 50Hz and 60Hz interference. - Single Conversion Settling These single-supply products are ideal solutions for - 50/60 Hz ±3 Hz Simultaneous Rejection measuring isolated and non-isolated, low-level signals in Single +5 V Power Supply Operation process control applications. - Charge Pump Drive for Negative Supply - +3 to +5 V Digital Supply Operation ORDERING INFORMATION Low Power Consumption: 6.0 mW See page53. VA+ AGND VREF+ VREF- DGND VD+ X1 X1 Controller, AAIINN11+- able Differential Digital Filter Setup R&egisters, AIN2+ +X20 ammGain 4thΔ OΣrder ChanLnoegli cScan r g AIN2- MUX X1 o Modulator Pr AIN3+ CS5524 Shown CS AIN3- Serial Port AIN4+ SCLK Interface AIN4- Clock Data FIFO & SDI Latch Gen. Calibration Registers SDO NBV CPD A0A1 XIN XOUT JUL ‘09 Copyright  Cirrus Logic, Inc. 2009 http://www.cirrus.com DS317F8 (All Rights Reserved)

CS5521/22/23/24/28 TABLE OF CONTENTS ANALOG CHARACTERISTICS................................................................................................5 TYPICAL RMS NOISE, CS5521/23..........................................................................................7 TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23....................................................7 TYPICAL RMS NOISE, CS5522/24/28.....................................................................................8 TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28...............................................8 5 V DIGITAL CHARACTERISTICS...........................................................................................9 3 V DIGITAL CHARACTERISTICS...........................................................................................9 DYNAMIC CHARACTERISTICS............................................................................................10 RECOMMENDED OPERATING CONDITIONS.....................................................................10 ABSOLUTE MAXIMUM RATINGS.........................................................................................10 SWITCHING CHARACTERISTICS........................................................................................11 1. GENERAL DESCRIPTION .....................................................................................................13 1.1 Analog Input .....................................................................................................................13 1.1.1 Instrumentation Amplifier .........................................................................................14 1.1.2 Coarse/Fine Charge Buffers ...............................................................................14 1.1.3 Analog Input Span Considerations ..........................................................................15 1.1.4 Measuring Voltages Higher than 5 V ..................................................................15 1.1.5 Voltage Reference ..............................................................................................16 1.2 Overview of ADC Register Structure and Operating Modes ............................................16 1.2.1 System Initialization ............................................................................................18 1.2.2 Command Register Quick Reference ...............................................................19 1.2.3 Command Register Descriptions ........................................................................20 1.2.4 Serial Port Interface ............................................................................................25 1.2.5 Reading/Writing the Offset, Gain, and Configuration Registers ..........................26 1.2.6 Reading/Writing the Channel-Setup Registers ...................................................26 1.2.6.1 Latch Outputs ......................................................................................28 1.2.6.2 Channel Select Bits .............................................................................28 1.2.6.3 Output Word Rate Selection ...............................................................28 1.2.6.4 Gain Bits ..............................................................................................28 1.2.6.5 Unipolar/Bipolar Bit .............................................................................28 1.2.7 Configuration Register ........................................................................................28 1.2.7.1 Chop Frequency Select .......................................................................28 1.2.7.2 Conversion/Calibration Control Bits ....................................................28 1.2.7.3 Power Consumption Control Bits ........................................................28 1.2.7.4 Charge Pump Disable .........................................................................29 1.2.7.5 Reset System Control Bits ..................................................................29 1.2.7.6 Data Conversion Error Flags ...............................................................29 1.3 Calibration ........................................................................................................................31 1.3.1 Self Calibration ....................................................................................................31 1.3.2 System Calibration ..............................................................................................32 1.3.3 Calibration Tips ...................................................................................................34 1.3.4 Limitations in Calibration Range .........................................................................34 1.4 Performing Conversions and Reading the Data Conversion FIFO ..................................34 1.4.1 Conversion Protocol ............................................................................................35 1.4.1.1 Single, One-Setup Conversion ............................................................35 1.4.1.2 Repeated One-Setup Conversions without Wait .................................35 1.4.1.3 Repeated One-Setup Conversions with Wait ......................................36 1.4.1.4 Single, Multiple-Setup Conversions ....................................................36 1.4.1.5 Repeated Multiple-Setup Conversions without Wait ...........................37 1.4.1.6 Repeated Multiple-Setup Conversions with Wait ................................37 1.4.2 Calibration Protocol .............................................................................................38 2 DS317F8

CS5521/22/23/24/28 1.4.3 Example of Using the CSRs to Perform Conversions and Calibrations ..............38 1.5 Conversion Output Coding ..............................................................................................40 1.5.1 Conversion Data FIFO Descriptions ...................................................................41 1.6 Digital Filter .....................................................................................................................42 1.7 Clock Generator ..............................................................................................................42 1.8 Power Supply Arrangements ...........................................................................................43 1.8.1 Charge Pump Drive Circuits ...............................................................................45 1.9 Digital Gain Scaling ........................................................................................................45 1.10 Getting Started ..............................................................................................................46 1.11 PCB Layout ...................................................................................................................48 2. PIN DESCRIPTIONS ..............................................................................................................49 2.1 Clock Generator ..............................................................................................................50 2.2 Control Pins and Serial Data I/O .....................................................................................50 2.3 Measurement and Reference Inputs ...............................................................................50 2.4 Power Supply Connections .............................................................................................51 3. SPECIFICATION DEFINITIONS .............................................................................................52 4. ORDERING INFORMATION ..................................................................................................53 5. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ............................53 6. PACKAGE DIMENSION DRAWINGS ....................................................................................54 7. REVISION HISTORY ..............................................................................................................56 DS317F8 3

CS5521/22/23/24/28 LIST OF FIGURES Figure 1. Continuous Running SCLK Timing (Not to Scale).........................................................12 Figure 2. SDI Write Timing (Not to Scale).....................................................................................12 Figure 3. SDO Read Timing (Not to Scale)...................................................................................12 Figure 4. Multiplexer Configurations..............................................................................................13 Figure 5. Input Models for AIN+ and AIN- pins, ≤100 mV Input Ranges.......................................14 Figure 6. Input Models for AIN+ and AIN- pins, >100 mV input ranges........................................14 Figure 7. Input Ranges Greater than 5 V......................................................................................16 Figure 8. Input Model for VREF+ and VREF- Pins........................................................................16 Figure 9. CS5523/24 Register Diagram........................................................................................17 Figure 10. Command and Data Word Timing................................................................................25 Figure 11. Self Calibration of Offset (Low Ranges).......................................................................32 Figure 12. Self Calibration of Offset (High Ranges)......................................................................32 Figure 13. Self Calibration of Gain (All Ranges)...........................................................................32 Figure 14. System Calibration of Offset (Low Ranges).................................................................32 Figure 15. System Calibration of Offset (High Ranges)................................................................33 Figure 16. System Calibration of Gain (Low Ranges)...................................................................33 Figure 17. System Calibration of Gain (High Ranges)..................................................................33 Figure 18. Filter Response (Normalized to Output Word Rate = 15 Sps).....................................42 Figure 19. Typical Linearity Error for CS5521/23..........................................................................42 Figure 20. Typical Linearity Error for CS5522/24/28.....................................................................42 Figure 21. CS5522 Configured to use on-chip charge pump to supply NBV................................43 Figure 22. CS5522 Configured for ground-referenced Unipolar Signals.......................................44 Figure 23. CS5522 Configured for Single Supply Bridge Measurement.......................................44 Figure 24. Charge Pump Drive Circuit for VD+ = 3 V....................................................................45 Figure 25. Alternate NBV Circuits.................................................................................................45 LIST OF TABLES Table 1. Relationship between Full Scale Input, Gain Factors, and Internal Analog Signal Limitations.............................................................................................................15 Table 2. Command Register Quick Reference..............................................................................19 Table 3. Channel-Setup Registers................................................................................................27 Table 4. Configuration Register.....................................................................................................30 Table 5. Offset and Gain Registers...............................................................................................31 Table 6. Output Coding for 16-bit CS5521/23 and 24-bit CS5522/24/28......................................40 4 DS317F8

CS5521/22/23/24/28 CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (T = 25° C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND, A NBV = -2.1 V, XIN = 32.768 kHz, CFS1-CFS0 = ‘00’, OWR (Output Word Rate) = 15 Sps, Bipolar Mode, Input Range = ±100 mV; See Notes 1 and 2.) CS5521/23 CS5522/24/28 Parameter Min Typ Max Min Typ Max Unit Accuracy Resolution - - 16 - - 24 Bits Linearity Error - ±0.0015 ±0.003 - ±0.0007 ±0.0015 %FS Bipolar Offset (Note 3) - ±1 ±2 - ±16 ±32 LSB N Unipolar Offset (Note 3) - ±2 ±4 - ±32 ±64 LSB N Offset Drift (Notes 3 and 4) - 20 - - 20 - nV/°C Bipolar Gain Error - ±8 ±31 - ±8 ±31 ppm Unipolar Gain Error - ±16 ±62 - ±16 ±62 ppm Gain Drift (Note 4) - 1 3 - 1 3 ppm/°C Power Supplies Power Supply Currents (Normal Mode) I - 1.2 1.6 - 1.5 2.1 mA A+ (Note 5)I - 110 150 - 110 150 µA D+ I - 400 570 - 525 700 µA NBV Power Consumption (Note 6) Normal Mode - 7.0 10 - 10.1 14.8 mW Low Power Mode N/A N/A N/A - 5.5 7.5 mW Sleep - 500 - - 500 - µW Power Supply Rejection Positive Supplies - 120 - - 120 - dB dc NBV - 110 - - 110 - dB Notes: 1. Applies after system calibration at any temperature within -40° C ~ +85° C. 2. Specifications guaranteed by design, characterization, and/or test. 3. Specification applies to the device only and does not include any effects by external parasitic thermocouples. LSB : N is 16 for the CS5521/23 and N is 24 for the CS5522/24/28 N 4. Drift over specified temperature range after calibration at power-up at 25° C. 5. Measured with Charge Pump Drive off. 6. All outputs unloaded. All input CMOS levels and the CS5521/23 do not have a low power mode. DS317F8 5

CS5521/22/23/24/28 ANALOG CHARACTERISTICS (Continued) Parameter Min Typ Max Unit Analog Input Common Mode + Signal on AIN+ or AIN- Bipolar/Unipolar Mode NBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mV -0.150 - 0.950 V Range = 1 V, 2.5 V, or 5 V NBV - VA+ V NBV = AGND Range = 25 mV, 55 mV, or 100 mV (Note 7) 1.85 - 2.65 V Range = 1 V, 2.5 V, or 5 V 0.0 - VA+ V CVF Current on AIN+ or AIN- (Note 8) Range = 25 mV, 55 mV, or 100 mV - 100 300 pA Range = 1 V, 2.5 V, or 5 V - 10 - nA Input Current Drift (Note 8) Range = 25 mV, 55 mV, or 100 mV - 1 - pA/°C Input Leakage for Multiplexer when Off - 10 - pA Common Mode Rejection dc - 120 - dB 50, 60 Hz - 120 - dB Input Capacitance - 10 - pF Voltage Reference Input Range (VREF+) - (VREF-) 1 2.5 VA+ V VREF+ (VREF-)+1 - VA+ V VREF- NBV - (VREF+)-1 V CVF Current (Note 8) - 5.0 - nA Common Mode Rejection dc - 110 - dB 50, 60 Hz - 130 - dB Input Capacitance - 16 - pF System Calibration Specifications Full Scale Calibration Range (VREF = 2.5V) Bipolar/Unipolar Mode 25 mV 10 - 32.5 mV 55 mV 25 - 71.5 mV 100 mV 40 - 105 mV 1 V 0.40 - 1.30 V 2.5 V 1.0 - 3.25 V 5 V 2.0 - VA+ V Offset Calibration Range Bipolar/Unipolar Mode 25 mV - - ±12.5 mV 55 mV - - ±27.5 mV 100 mV (Note 9) - - ±50 mV 1 V - - ±0.5 V 2.5 V - - ±1.25 V 5 V - - ±2.50 V Notes: 7. For the CS5528, the 25mV, 55mV and 100mV ranges cannot be used unless NBV is powered at -1.8 to -2.5V 8. See the section of the data sheet which discusses input models. Chop clock is 256Hz (XIN/128) for PGIA (programmable gain instrumentation amplifier). XIN = 32.768kHz. 9. The maximum full scale signal can be limited by saturation of circuitry within the internal signal path. 6 DS317F8

CS5521/22/23/24/28 TYPICAL RMS NOISE, CS5521/23 (Notes 10 and 11) Output Rate -3 dB Filter Input Range, (Bipolar/Unipolar Mode) (Sps) Frequency 25 mV 55 mV 100 mV 1 V 2.5 V 5 V 1.88 1.64 90 nV 148 nV 220 nV 1.8 µV 3.9 µV 7.8 µV 3.76 3.27 122 nV 182 nV 310 nV 2.6 µV 5.7 µV 11.3 µV 7.51 6.55 180 nV 267 nV 435 nV 3.7 µV 8.5 µV 18.1 µV 15.0 12.7 280 nV 440 nV 810 nV 5.7 µV 14 µV 28 µV 30.0 25.4 580 nV 1.1 µV 2.1 µV 18.2 µV 48 µV 96 µV 61.6 (Note 12) 50.4 2.6 µV 4.9 µV 8.5 µV 92 µV 238 µV 390 µV 84.5 (Note 12) 70.7 11 µV 27 µV 43 µV 458 µV 1.1 mV 2.4 mV 101.1 (Note 12) 84.6 41 µV 72 µV 130 µV 1.2 mV 3.4 mV 6.7 mV Notes:10. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25° C. 11. To estimate Peak-to-Peak Noise, multiply RMS noise by 6.6 for all ranges and output rates. 12. For input ranges <100mV and output rates ≥60Sps, 16.384kHz chopping frequency is used. TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 (Note 13) Output Rate -3 dB Filter Input Range, (Bipolar Mode) (Sps) Frequency 25 mV 55 mV 100 mV 1 V 2.5 V 5 V 1.88 1.64 16 16 16 16 16 16 3.76 3.27 16 16 16 16 16 16 7.51 6.55 15 16 16 16 16 16 15.0 12.7 15 15 15 16 16 16 30.0 25.4 14 14 14 14 14 14 61.6 (Note 12) 50.4 12 12 12 12 12 12 84.5 (Note 12) 70.7 9 9 9 9 9 9 101.1 (Note 12) 84.6 8 8 8 8 8 8 Notes:13. For bipolar mode, the number of bits of Noise Free Resolution is LOG((2XInput Range)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. For unipolar mode, the number of bits of Noise Free Resolution is LOG((Input Range)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. Also, the CS5521/23’s output conversions are 16 bits. Noise free Resolution numbers are based upon VREF=2.5V and XIN=32.768kHz. The values will be affected directly by changes in VREF, but the effects due to changes in the XIN frequency will be minor. DS317F8 7

CS5521/22/23/24/28 TYPICAL RMS NOISE, CS5522/24/28 (Notes 14 and 15) Output Rate -3 dB Filter Input Range, (Bipolar/Unipolar Mode) (Sps) Frequency 25 mV 55 mV 100 mV 1 V 2.5 V 5 V 1.88 1.64 90 nV 95 nV 140 nV 1.5 µV 3 µV 6 µV 3.76 3.27 110 nV 130 nV 190 nV 2 µV 4 µV 8 µV 7.51 6.55 170 nV 200 nV 275 nV 2.5 µV 6 µV 11.5 µV 15.0 12.7 250 nV 330 nV 580 nV 4.5 µV 10 µV 20 µV 30.0 25.4 500 nV 1 µV 1.5 µV 16 µV 45 µV 85 µV 61.6 (Note 16) 50.4 2 µV 4 µV 8 µV 72 µV 195 µV 350 µV 84.5 (Note 16) 70.7 10 µV 20 µV 35 µV 340 µV 900 µV 2 mV 101.1 (Note 16) 84.6 30 µV 60 µV 105 µV 1.1 mV 3 mV 5.3 mV Notes:14. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25° C. 15. To estimate Peak-to-Peak Noise, multiply RMS noise by 6.6 for all ranges and output rates. 16. For input ranges <100mV and output rates ≥60Sps, 16.384kHz chopping frequency is used. TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 (Note 17) Output Rate -3 dB Filter Input Range, (Bipolar Mode) (Sps) Frequency 25 mV 55 mV 100 mV 1 V 2.5 V 5 V 1.88 1.64 16 17 18 18 18 18 3.76 3.27 16 17 17 17 18 18 7.51 6.55 15 16 17 17 17 17 15.0 12.7 15 16 16 16 16 16 30.0 25.4 14 14 14 14 14 14 61.6 (Note 16) 50.4 12 12 12 12 12 12 84.5 (Note 16) 70.7 10 10 10 10 10 10 101.1 (Note 16) 84.6 8 8 8 8 8 8 Notes:17. For bipolar mode, the number of bits of Noise Free Resolution is LOG((2XInput Range)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. For unipolar mode, the number of bits of Noise Free Resolution is LOG((Input Range)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. Also, the CS5522/24/28’s output conversions are 24 bits. Noise free Resolution numbers are based upon VREF=2.5V and XIN=32.768kHz. The values will be affected directly by changes in VREF, but the effects due to changes in the XIN frequency will be minor. 8 DS317F8

CS5521/22/23/24/28 5 V DIGITAL CHARACTERISTICS (T = 25° C; VA+, VD+ = 5 V ±5%; GND = 0; A See Notes 2 and 18.)) Parameter Symbol Min Typ Max Unit High-level Input Voltage All Pins Except XIN and SCLK V 0.6 VD+ - - V IH XIN (VD+)-0.5 - - V SCLK (VD+) - 0.45 - - V Low-level Input Voltage All Pins Except XIN and SCLK V - - 0.8 V IL XIN - - 1.5 V SCLK - - 0.6 V High-level Output Voltage V OH All Pins Except CPD and SDO (Note 19) (VA+) - 1.0 - - V CPD, I = -4.0 mA (VD+) - 1.0 - - V out SDO, I = -5.0 mA (VD+) - 1.0 - - V out Low-level Output Voltage V OL All Pins Except CPD and SDO, I = 1.6 mA - - 0.4 V out CPD, I = 2 mA - - 0.4 V out SDO, I = 5.0 mA - - 0.4 V out Input Leakage Current I - ±1 ±10 µA in 3-state Leakage Current I - - ±10 µA OZ Digital Output Pin Capacitance C - 9 - pF out Notes:18. All measurements performed under static conditions. 19. I = -100µA unless stated otherwise. (V = 2.4 V @ I = -40µA.) out OH out 3 V DIGITAL CHARACTERISTICS (T = 25° C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10%; GND = 0; A See Notes 2 and 18.) Parameter Symbol Min Typ Max Unit High-level Input Voltage All Pins Except XIN and SCLK V 0.6 VD+ - - V IH XIN (VD+)-0.5 - - V SCLK (VD+) - 0.45 - - V Low-level Input Voltage All Pins Except XIN and SCLK V - - 0.16 VD+ V IL XIN - - 0.3 V SCLK - - 0.6 V High-level Output Voltage V OH All Pins Except CPD and SDO, I = -400 µA (VA+) - 0.3 - - V out CPD, I = -4.0 mA (VD+) - 1.0 - - V out SDO, I = -5.0 mA (VD+) - 1.0 - - V out Low-level Output Voltage V OL All Pins Except CPD and SDO, I = 400 µA - - 0.3 V out CPD, I = 2 mA - - 0.4 V out SDO, I = 5.0 mA - - 0.4 V out Input Leakage Current I - ±1 ±10 µA in 3-state Leakage Current I - - ±10 µA OZ Digital Output Pin Capacitance C - 9 - pF out DS317F8 9

CS5521/22/23/24/28 DYNAMIC CHARACTERISTICS Parameter Symbol Ratio Unit Modulator Sampling Frequency f XIN/4 Hz s Filter Settling Time to 1/2 LSB (Full-scale Step) t 1/f s s out RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V; See Note 20.) Parameter Symbol Min Typ Max Unit DC Power Supplies Positive Digital VD+ 2.7 5.0 5.25 V Positive Analog VA+ 4.75 5.0 5.25 V Analog Reference Voltage (VREF+) - (VREF-) VRef 1.0 2.5 VA+ V diff Negative Bias Voltage NBV -1.8 -2.1 -2.5 V Notes:20. All voltages with respect to ground. ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; See Note 20.) Parameter Symbol Min Typ Max Unit DC Power Supplies (Note 21) Positive Digital VD+ -0.3 - +6.0 V Positive Analog VA+ -0.3 - +6.0 V Negative Bias Voltage Negative Potential NBV +0.3 -2.1 -3.0 V Input Current, Any Pin Except Supplies (Note 22 and 23) I - - ±10 mA IN Output Current I - - ±25 mA OUT Power Dissipation (Note 24) PDN - - 500 mW Analog Input Voltage VREF pins V NBV -0.3 - (VA+) + 0.3 V INR AIN Pins V NBV -0.3 - (VA+) + 0.3 V INA Digital Input Voltage V -0.3 - (VD+) + 0.3 V IND Ambient Operating Temperature T -40 - 85 °C A Storage Temperature T -65 - 150 °C stg Notes:21. No pin should go more negative than NBV - 0.3V. 22. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins. 23. Transient current of up to 100mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50mA. 24. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 10 DS317F8

CS5521/22/23/24/28 SWITCHING CHARACTERISTICS (T = 25° C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; A Levels: Logic 0 = 0 V, Logic 1 = VD+; C = 50 pF.)) L Parameter Symbol Min Typ Max Unit Master Clock Frequency (Note 25) XIN External Clock or Internal Oscillator (CS5522/24/28) 30 32.768 200 kHz (CS5521/23) 30 32.768 130 kHz Master Clock Duty Cycle 40 - 60 % Rise Times (Note 26) t rise Any Digital Input Except SCLK - - 1.0 µs SCLK - - 100 µs Any Digital Output - 50 - ns Fall Times (Note 26) t fall Any Digital Input Except SCLK - - 1.0 µs SCLK - - 100 µs Any Digital Output - 50 - ns Start-up Oscillator Start-up Time XTAL = 32.768 kHz (Note 27) t - 500 - ms ost Serial Port Timing Serial Clock Frequency SCLK 0 - 2 MHz SCLK Falling to CS Falling for continuous running SCLK t 100 - - ns 0 (Note 28) Serial Clock Pulse Width High t 250 - - ns 1 Pulse Width Low t 250 - - ns 2 SDI Write Timing CS Enable to Valid Latch Clock t 50 - - ns 3 Data Set-up Time prior to SCLK rising t 50 - - ns 4 Data Hold Time After SCLK Rising t 100 - - ns 5 SCLK Falling Prior to CS Disable t 100 - - ns 6 SDO Read Timing CS to Data Valid t - - 150 ns 7 SCLK Falling to New Data Bit t - - 150 ns 8 CS Rising to SDO Hi-Z t - - 150 ns 9 Notes:25. Device parameters are specified with a 32.768kHz clock; however, clocks up to 200kHz (CS5522/24/28) or 130kHz (CS5521/23) can be used for increased throughput. 26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50pF. 27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. 28. Applicable when SCLK is continuously running. Specifications are subject to change without notice. DS317F8 11

CS5521/22/23/24/28 CS t0 t t 6 t 1 3 SCLK t 2 Figure 1. Continuous Running SCLK Timing (Not to Scale) CS t 3 SDI MSB MSB-1 LSB t t t t 4 5 1 6 SCLK t 2 Figure 2. SDI Write Timing (Not to Scale) CS t t 7 9 SDO MSB MSB-1 LSB t8 t2 SCLK t 1 Figure 3. SDO Read Timing (Not to Scale) 12 DS317F8

CS5521/22/23/24/28 1. GENERAL DESCRIPTION The CS5521/22/23/24/28 are highly integrated ΔΣ ters are designed to settle to full accuracy within Analog-to-Digital Converters (ADCs) which use one conversion cycle and simultaneously reject charge-balance techniques to achieve 16-bit both 50Hz and 60Hz interference when operated (CS5521/23) and 24-bit (CS5522/24/28) perfor- at word rates below 30Sps (assuming a XIN clock mance. The ADCs come as either two-channel frequency of 32.768kHz). (CS5521/22), four-channel (CS5523/24), or eight- To ease communication between the ADCs and a channel (CS5528) devices, and include a low input micro-controller, the converters include an easy to current, chopper-stabilized instrumentation ampli- use three-wire serial interface which is SPI™ and fier. To permit selectable input spans of 25mV, Microwire™ compatible. 55mV, 100mV, 1V, 2.5V, and 5V, the ADCs in- clude a PGA (programmable gain amplifier). To 1.1 Analog Input accommodate ground-based thermocouple applica- Figure4 illustrates a block diagram of the analog in- tions, the devices include a CPD (Charge Pump put signal path inside the CS5521/22/23/24/28. The Drive) which provides a negative bias voltage to front end consists of a multiplexer (break before the on-chip amplifiers. make configuration), a chopper-stabilized instru- These devices also include a fourth order DS mod- mentation amplifier with fixed gain of 20X, ulator followed by a digital filter which provides coarse/fine charge buffers, and a programmable gain eight selectable output word rates of 1.88Sps, section. For the 25mV, 55mV, and 100mV input 3.76Sps, 7.51Sps, 15Sps, 30Sps, 61.6Sps, ranges, the input signals are amplified by the 20X in- 84.5Sps, and 101.1Sps (XIN=32.768 kHz). The strumentation amplifier. For the 1V, 2.5V, and 5V devices are capable of producing output update input ranges, the instrumentation amplifier is by- rates up to 617Sps when a 200kHz clock is used passed and the input signals are connected to the (CS5522/24/28) or up to 401Sps using a 130kHz Programmable Gain block via coarse/fine charge clock (CS5521/23). Further note that the digital fil- buffers. CS5522 AIN2+ IN+ AIN2- M AIN1+ U VREF+ VREF- AIN1- X IN- AIN4+ CS5524 AIN4- * M IN+ Differential Digital ** UX IN+ X20 Programmable 4thorder Filter AIN1+ IN- Gain delta-sigma AIN1- IN- modulator AIN8+ CS5528 AIN7+ M IN+ * U * X * IN- NBV also supplies the negative AIN1+ supply voltage for the coarse/fine change buffers NBV Figure 4. Multiplexer Configurations DS317F8 13

CS5521/22/23/24/28 1.1.1 Instrumentation Amplifier CFS bits in their default states (cleared to logic 0s). Further note that the CVF current into the instru- The instrumentation amplifier is chopper stabilized mentation amplifier is less than 300 pA over -40°C and is activated any time conversions are performed to +85°C. Note that Figure 5 is for input current with the low-level input ranges, ≤100mV. The am- modeling only. For physical input capacitance see plifier is powered from VA+ and from the NBV ‘Input Capacitance’ specification under ANALOG (Negative Bias Voltage) pin allowing the CHARACTERISTICS. Also refer to Applications CS5521/22/23/24/28 to be operated in either of two Note AN30 - “Switched-Capacitor A/D Converter analog input configurations. The NBV pin can be bi- Input Structures” for more details on input models ased to a negative voltage between -1.8V and and input sampling currents. -2.5V, or tied to AGND (for the CS5528, NBV has to be between -1.8V and -2.5V for the ranges below Note: Residual noise appears in the converter’s baseband for 100mV when the amplifier is engaged). The com- output word rates greater than 61.6Sps if the CFS bits are logic 0 (chop clock=256Hz). For word rates of mon-mode-plus-signal range of the instrumentation 30Sps and lower, 256Sps chopping is recommended, amplifier is 1.85V to 2.65V with NBV grounded. and for 61.6Sps, 84.5Sps and 101.1Sps word rate set- The common-mode-plus-signal range of the instru- tings, 4096Hz chopping is recommended. mentation amplifier is -0.150V to 0.950V with 1.1.2 Coarse/Fine Charge Buffers NBV between -1.8V to -2.5V. Whether NBV is tied between -1.8V and -2.5V or tied to AGND, The unity gain buffers are activated any time conver- the (Common Mode + Signal) input on AIN+ and sions are performed with the high-level inputs rang- AIN- must stay between NBV and VA+. es, 1V, 2.5V, and 5V. The unity gain buffers are designed to accommodate rail-to-rail input signals. Figure 5 illustrates an analog input model for the The common-mode-plus-signal range for the unity ADCs when the instrumentation amplifier is en- gain buffer amplifier is NBV to VA+. gaged. The CVF (sampling) input current for each of the analog input pins depends on the CFS1 and Typical CVF (sampling) current for the unity gain CFS0 (Chop Frequency Select) bits in the configu- buffer amplifiers is about 10nA ration register (see Configuration Register for de- (XIN =32.768kHz, see Figure6). tails). Note that the CVF current is lowest with the 25 mV,55 mV,and 100 mV Ranges 1 V, 2.5 V, and 5 V Ranges φ1Fine AIN C = 48 pF φ Coarse V ≤25 mV 1 os AIN i = fV C n os CFS1/CFS0 = 00,f = 256 Hz V ≤25 mV C = 20 pF os CFS1/CFS0 = 01,f = 4096 Hz i = fV C n os CFS1/CFS0 = 10,f = 16.384 kHz f= 32.768 kHz CFS1/CFS0 = 11,f = 1024 Hz Figure 5. Input Models for AIN+ and AIN- pins, ≤100 Figure 6. Input Models for AIN+ and AIN- pins, >100 mV Input Ranges mV input ranges 14 DS317F8

CS5521/22/23/24/28 1.1.3 Analog Input Span Considerations is the differential input voltage and VOS is the ab- solute maximum offset voltage for the instrumenta- The CS5521/22/23/24/28 is designed to measure tion amplifier (VOS will not exceed 40mV). If the full-scale ranges of 25mV, 55mV, 100mV, 1V, differential output voltage from the amplifier ex- 2.5V, and 5V. Other full scale values can be ac- ceeds 2.8V, the amplifier may saturate, which will commodated by performing a system calibration cause a measurement error. within the limits specified. See the Calibration sec- tion for more details. Another way to change the The input voltage into the modulator must not full scale range is to increase or to decrease the cause the modulator to exceed a low of 20 percent voltage reference to a voltage other than 2.5 . See or a high of 80 percent 1's density. The nominal the Voltage Reference section for more details. full-scale input span of the modulator (from 30 per- cent to 70 percent 1’s density) is determined by the Three factors set the operating limits for the input VREF voltage divided by the Gain Factor. See span. They include: instrumentation amplifier satu- Table 1 to determine if the CS5521/22/23/24/28 is ration, modulator 1’s density, and a lower reference being used properly. For example, in the 55mV voltage. When the 25mV, 55mV, or 100mV range, to determine the nominal input voltage to the range is selected, the input signal (including the modulator, divide VREF (2.5V) by the Gain Fac- common-mode voltage and the amplifier offset tor (2.2727). voltage) must not cause the 20X amplifier to satu- rate in either its input stage or output stage. To pre- When a smaller voltage reference is used, the re- vent saturation, the absolute voltages on AIN+ and sulting code widths are smaller causing the con- AIN- must stay within the limits specified (refer to verter output codes to exhibit more changing codes the Analog Input section). Additionally, the differ- for a fixed amount of noise. Table 1 is based upon ential output voltage of the amplifier must not ex- a VREF= 2.5V. For other values of VREF, the ceed 2.8V. The equation values in Table1 must be scaled accordingly. ABS(VIN + VOS) x 20 = 2.8V 1.1.4 Measuring Voltages Higher than 5 V defines the differential output limit, where Some systems require the measurement of voltages VIN = (AIN+) - (AIN-) greater than 5V. The input current of the instru- Max. Differential Output Δ-Σ Nominal(1) Δ-Σ(1) Input Range(1) VREF Gain Factor 20X Amplifier Differential Input Max. Input ±25 mV 2.8 V (2) 2.5V 5 ±0.5 V ±0.75 V ±55 mV 2.8 V (2) 2.5V 2.272727... ±1.1 V ±1.65 V ±100 mV 2.8 V (2) 2.5V 1.25 ±2.0 V ±3.0 V ±1.0 V - 2.5V 2.5 ±1.0 V ±1.5 V ±2.5 V - 2.5V 1.0 ±2.5 V ±5.0 V ±5.0 V - 2.5V 0.5 ±5.0 V 0V, VA+ Table 1. Relationship between Full Scale Input, Gain Factors, and Internal Analog Signal Limitations Note: 1. The converter's actual input range, the delta-sigma's nominal full-scale input, and the delta-sigma's maximum full-scale input all scale directly with the value of the voltage reference. The values in the table assume a 2.5 V VREF voltage. 2. The 2.8V limit at the output of the 20X amplifier is the differential output voltage. DS317F8 15

CS5521/22/23/24/28 mentation amplifier with a gain range setting of Figure 8 illustrates the input models for the VREF 100mV or less, is typically 100 pA. This is low pins. The dynamic input current for each of the pins enough to permit large external resistors to divide can be determined from the models shown. down a large external signal without significant 1.2 Overview of ADC Register Structure loading. Figure 7 illustrates an example circuit. Re- and Operating Modes fer to Application Note 158 for more details on high-voltage (>5 V) measurement. The CS5521/22/23/24/28 ADCs have an on-chip controller, which includes a number of user-acces- 1.1.5 Voltage Reference sible registers. The registers are used to hold offset The CS5521/22/23/24/28 devices are specified for and gain calibration results, configure the chip's operation with a 2.5V reference voltage between operating modes, hold conversion instructions, and the VREF+ and VREF- pins of the device. For a to store conversion data words. Figure9 depicts a single-ended reference voltage, such as the block diagram of the on-chip controller’s internal LT1019-2.5, the reference voltage is input into the registers for the CS5523/24. VREF+ pin of the converter and the VREF- pin is Each of the converters has 24-bit registers to func- grounded. tion as offset and gain calibration registers for each The differential voltage between the VREF+ and channel. The converters with two channels have VREF- can be any voltage from 1.0V up to VA+, two offset and two gain calibration registers, the however, the VREF+ cannot go above VA+ and the converters with four channels have four offset and VREF- pin can not go below NBV. four gain calibration registers, and the eight chan- nel converter has eight offset and eight gain cali- bration registers. These registers hold calibration results. The contents of these registers can be read or written by the user. This allows calibration data to be off-loaded into an external EEPROM. The user can also manipulate the contents of these reg- 10 Ω isters to modify the offset or the gain slope of the +5 V 0.1 μF 0.1 μF converter. VA+ VD+ 2.5 V VREF+ The converters include a 24-bit configuration reg- VREF- ister of which 17 of the bits are used for setting op- 1 MΩ tions such as the conversion mode, operating power ±10V + Voltage 10 KΩ PGIA ΔΣ ADC options, setting the chop clock rate of the instru- Divider - PGIA set for φ Fine + 100 mV 1 chop clock = 256 Hz NBV Charge Pump Regulator φ2 Coarse CPD DGND VREF V ≈ -2.1 V 1N4148 0.033 μF V ≤ 25mV C = 10pF Charge Pump os BAT85 +10 μF 1N4148 Circuitry i n = fV o s C f = 32.768 kHz Figure 7. Input Ranges Greater than 5 V Figure 8. Input Model for VREF+ and VREF- Pins 16 DS317F8

CS5521/22/23/24/28 mentation amplifier, and providing a number of set up the registers to perform conversions using flags which indicate converter operation. different conversion options on each of the input channels. A group of registers, called Channel Set-up Regis- ters, are also included in the converters. These reg- The ADCs also include multiple-channel conver- isters are used to hold pre-loaded conversion sion capability. User bits in the configuration regis- instructions. Each channel set-up register is 24 bits ter of the ADCs can be configured to sequence wide and holds two 12-bit conversion instructions through the 12-bit command Setups, performing a (Setups). Upon power-up, these registers can be conversion according to the content of each 12-bit initialized by the user’s microcontroller with con- Setup. This channel scanning capability can be version instructions. The user can then use bits in configured to run continuously, or to scan through the configuration register to choose a conversion a specified number of Setup Registers and stop un- mode. til commanded to continue. In the multiple-channel scanning modes, the conversion data words are Several conversion modes are possible. Using the loaded into an on-chip data FIFO. The converter is- single conversion mode, an 8-bit command word sues a flag on the SDO pin when a scan cycle is can be written into the serial port. The command in- completed so the user can read the FIFO. More de- cludes pointer bits which ‘point’ to a 12-bit com- tails are given in the following pages. mand in one of the Channel Setup Registers which is to be executed. The 12-bit commands can be set- Instructions are provided on how to initialize the up to perform a conversion on any of the input converter, perform offset and gain calibrations, and channels of the converter. More than one of the 12- to configure the converter for the various conver- bit Setups can be used for the same analog input sion modes. Each of the bits of the configuration channel. This allows the user to convert on the register and of the Channel Setup Registers is de- same signal with either a different conversion scribed. A list of examples follows the description speed, a different gain range, or any of the other op- section. Table 2 can be used to decode all valid tions available in the Setup Register. The user can commands (the first 8 bits into the serial port). 4 (2 4) 4 (24) 4 (12 x 2) 8 x 24 AIN1 Off 1 Gain 1 Setup 1 Setup 2 AIN2 Off 2 Gain 2 Setup 3 Setup 4 DATA AIN3 Off 3 Gain 3 Setup 5 Setup 6 FIFO AIN4 Off 4 Gain 4 Setup 7 Setup 8 1 x 24 SDO Configuration Chop Frequency Latch Outputs Multiple Conversions Channel Select Depth Pointer Output Word Rate Loop PGA Selection Read Convert Unipolar/Bipolar Powerdown Modes Flags Etc. Figure 9. CS5523/24 Register Diagram DS317F8 17

CS5521/22/23/24/28 1.2.1 System Initialization logic 1 to the RS (Reset System) bit in the configu- ration register. After a reset the RV bit is set until After power is first applied to the the configuration register is read. The user must CS5521/22/2324/28 devices, the user should wait then write a logic 0 to the RS bit to take the part out for the oscillator to start before attempting to com- of reset mode. Any other bits written to the config- municate with the converter. If a 32.768 kHz crys- uration register at this time will be lost. The con- tal is used, this may be 500 milliseconds. figuration register must be written again once RS= The initialization sequence should be as follows: 0 to set any other bits to their desired settings. Initialize the serial port by sending the port initial- After a reset, the on-chip registers are initialized to ization sequence of 15 bytes of all 1's followed by the following states: one byte with the following bit contents '1111 110'. This sequence places the chip in the command mode where it waits for a valid command to be configuration register: 000040(H) written. The first command should be to perform a offset registers: 000000(H) system reset. This is accomplished by writing a gain registers: 400000(H) channel setup registers: 000000(H) 18 DS317F8

CS5521/22/23/24/28 1.2.2 Command Register Quick Reference D7(MSB) D6 D5 D4 D3 D2 D1 D0 CB CS2 CS1 CS0 R/W RSB2 RSB1 RSB0 BIT NAME VALUE FUNCTION D7 Command Bit, CB 0 Must be logic 0 for these commands. 1 See table below. D6-D4 Channel Select Bits, 000 CS2-CS0 provide the address of one of the eight physical CSB2-CSB0 . channels. These bits are used to access the calibration regis- . ters associated with respective channels. 111 Note: These bits are ignored when reading the data register. D3 Read/Write, R/W 0 Write to selected register. 1 Read from selected register. D2-D0 Register Select Bit, 000 Reserved RSB2-RSB0 001 Offset Register 010 Gain Register 011 Configuration Register 101 Channel Set-up Registers - register is 48-bits long for CS5521/22 - register is 96-bits long for CS5523/24 - register is 192-bits long for CS5528 110 Reserved 111 Reserved D7(MSB) D6 D5 D4 D3 D2 D1 D0 CB CSRP3 CSRP2 CSRP1 CSRP0 CC2 CC1 CC0 BIT NAME VALUE FUNCTION D7 Command Bit, CB 0 See table above. 1 Must be logic 1 for these commands. D6-D3 Channel Pointer Bits, 0000 These bits are used as pointers to the Setups. CSRP3-CSRP0 . Note: The MC bit, must be logic 0 for these bits to take effect. . When MC = 1, these bits are ignored. The LP, MC, and RC . bits in the configuration register are ignored during calibra- 1111 tion. D2-D0 Conversion/Calibration 000 Normal Conversion Bits, CC2-CC0 001 Self-Offset Calibration 010 Self-Gain Calibration 011 Reserved 100 Reserved 101 System-Offset Calibration 110 System-Gain Calibration 111 Reserved Table 2. Command Register Quick Reference DS317F8 19

CS5521/22/23/24/28 1.2.3 Command Register Descriptions READ/WRITE INDIVIDUAL OFFSET CALIBRATION REGISTER D7(MSB) D6 D5 D4 D3 D2 D1 D0 0 CS2 CS1 CS0 R/W 0 0 1 Function: These commands are used to access each offset register separately. CS1 - CS0 decode the registers accessed. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. CS[2:0] (Channel Select Bits) 000 Offset Register 1(All devices) 001 Offset Register 2 (All devices) 010 Offset Register 3 (CS5523/24/28 only) 011 Offset Register 4 (CS5523/24/28 only) 100 Offset Register 5 (CS5528 only) 101 Offset Register 6 (CS5528 only) 110 Offset Register 7 (CS5528 only) 111 Offset Register 8 (CS5528 only) READ/WRITE INDIVIDUAL GAIN REGISTER D7(MSB) D6 D5 D4 D3 D2 D1 D0 0 CS2 CS1 CS0 R/W 0 1 0 Function: These commands are used to access each gain register separately. CS1 - CS0 decode the reg- isters accessed. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. CS[2:0] (Channel Select Bits) 000 Gain Register 1(All devices) 001 Gain Register 2 (All devices) 010 Gain Register 3 (CS5523/24/28 only) 011 Gain Register 4 (CS5523/24/28 only) 100 Gain Register 5 (CS5528 only) 101 Gain Register 6 (CS5528 only) 110 Gain Register 7 (CS5528 only) 111 Gain Register 8 (CS5528 only) 20 DS317F8

CS5521/22/23/24/28 READ/WRITE CONFIGURATION REGISTER D7(MSB) D6 D5 D4 D3 D2 D1 D0 0 0 0 0 R/W 0 1 1 Function: These commands are used to read from or write to the configuration register. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. READ/WRITE CHANNEL-SETUP REGISTER(S) D7(MSB) D6 D5 D4 D3 D2 D1 D0 0 0 0 0 R/W 1 0 1 Function: These commands are used to access the channel-setup registers (CSRs). The number of CSRs accessed is determined by the device being used and the number of CSRs that are being accessed (i.e. the depth bits in the configuration register determine the number of levels ac- cessed). This register is 48-bits long (4 Setups) for the CS5521/22, 96-bits long (8 Setups) for the CS5523/24, and 192-bits (16 Setups) long for the CS5528. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. DS317F8 21

CS5521/22/23/24/28 PERFORM CONVERSION D7(MSB) D6 D5 D4 D3 D2 D1 D0 1 CSRP3 CSRP2 CSRP1 CSRP0 0 0 0 Function: These commands instruct the ADC to perform conversions on the physical input channel point- ed to by the pointer bits (CSRP2 - CSRP0) in the channel-setup registers. The particular type of conversion performed is determined by the states of the conversion control bits (the multiple conversion bit, the loop bit, read convert bit, and the depth pointer bits) in the configuration reg- ister. CSRP [3:0] (Channel Setup Register Pointer Bits) 0000 Setup 1 (All devices) 0001 Setup 2 (All devices) 0010 Setup 3 (All devices) 0011 Setup 4 (All devices) 0100 Setup 5 (CS5523/24/28) 0101 Setup 6 (CS5523/24/28) 0110 Setup 7 (CS5523/24/28) 0111 Setup 8 (CS5523/24/28) 1000 Setup 9 (CS5528 only) 1001 Setup 10 (CS5528 only) 1010 Setup 11 (CS5528 only) 1011 Setup 12 (CS5528 only) 1100 Setup 13 (CS5528 only) 1101 Setup 14 (CS5528 only) 1110 Setup 15 (CS5528 only) 1111 Setup 16 (CS5528 only) 22 DS317F8

CS5521/22/23/24/28 PERFORM CALIBRATION D7(MSB) D6 D5 D4 D3 D2 D1 D0 1 CSRP3 CSRP2 CSRP1 CSRP0 CC2 CC1 CC0 Function: These commands instruct the ADC to perform a calibration on the physical input channel refer- enced which is chosen by the command byte pointer bits (CSRP3 - CRSP0). CSRP [3:0] (Channel Setup Register Pointer Bits) 0000 Setup 1 (All devices) 0001 Setup 2 (All devices) 0010 Setup 3 (All devices) 0011 Setup 4 (All devices) 0100 Setup 5 (CS5523/24/28 only) 0101 Setup 6 (CS5523/24/28 only) 0110 Setup 7 (CS5523/24/28 only) 0111 Setup 8 (CS5523/24/28 only) 1000 Setup 9 (CS5528 only) 1001 Setup 10 (CS5528 only) 1010 Setup 11 (CS5528 only) 1011 Setup 12 (CS5528 only) 1100 Setup 13 (CS5528 only) 1101 Setup 14 (CS5528 only) 1110 Setup 15 (CS5528 only) 1111 Setup 16 (CS5528 only) CC [2:0] (Calibration Control Bits) 000 Reserved 001 Self-Offset Calibration 010 Self-Gain Calibration 011 Reserved 100 Reserved 101 System-Offset Calibration 110 System-Gain Calibration 111 Reserved DS317F8 23

CS5521/22/23/24/28 SYNC1 D7(MSB) D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 Function: Part of the serial port re-initialization sequence. SYNC0 D7(MSB) D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 0 Function: End of the serial port re-initialization sequence. NULL D7(MSB) D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Function: This command is used to clear a port flag and keep the converter in the continuous conversion mode. 24 DS317F8

CS5521/22/23/24/28 1.2.4 Serial Port Interface output will be held at high impedance any time CS is at logic 1. The CS5521/22/23/24/28’s serial interface consists of four control lines: CS, SCLK, SDI, SDO. SCLK (Serial Clock) is the serial bit clock which Figure 10 illustrates the serial sequence necessary controls the shifting of data to or from the ADC’s to write to, or read from the serial port’s registers. serial port. The CS pin must be held low (logic 0) before SCLK transitions can be recognized by the CS (Chip Select) is the control line which enables port logic. To accommodate opto-isolators SCLK access to the serial port. If the CS pin is tied low, is designed with a Schmitt-trigger input to allow an the port can function as a three-wire interface. opto-isolator with slower rise and fall times to di- SDI (Serial Data In) is the data signal used to trans- rectly drive the pin. Additionally, SDO is capable fer data to the converters. of sinking or sourcing up to 5 mA to directly drive SDO (Serial Data Out) is the data signal used to an opto-isolator LED. SDO will have less than a transfer output data from the converters. The SDO 400mV loss in the drive voltage when sinking or sourcing 5mA. CS SCLK SDI MSB LSB CommandTime DataTime24SCLKs 8SCLKs WriteCycle CS SCLK SDI CommandTime 8SCLKs SDO MSB LSB DataTime24SCLKs ReadCycle SCLK SDI Command Time t d * XIN/OWR Clock Cycles 8 SCLKs SDO 8 SCLKs Clear SDO Flag MSB LSB * td = XIN/OWR clock cycles for each conversion except the Data Time first conversion which will take XIN/OWR + 7 clock cycles 24 SCLKs Figure 10. Command and Data Word Timing DS317F8 25

CS5521/22/23/24/28 1.2.5 Reading/Writing the Offset, Gain, and Once programmed, they are used to determine the Configuration Registers mode (e.g. unipolar, 15Sps, 100mV range etc.) the ADC will operate in when future conversions or The CS5521/22/23/24/28’s offset, gain, and config- calibrations are performed. uration registers are accessed individually and can be read from or written to. To write to an offset, a To access the CSRs, the user must first initialize the gain, or the configuration register, the user must depth pointer bits in the configuration register as transmit the appropriate write command which ac- these bits determine the number of CSRs to read cesses the particular register and then follow that from or write to. For example, to write CSR1 command with 24 bits of data (refer to Figure10 for (Setup1 and Setup2), the user would first program details). For example, to write 0x800000 (hexadeci- the configuration register’s depth pointer bits with mal) to physical channel one’s gain register, the user ‘0001’ binary. This notifies the ADC’s serial port would transmit the command byte 0x02 (hexadeci- that only the first CSR is to be accessed. Then, the mal) and then follow that command byte with the user would transmit the write command, 0x05 data 0x800000 (hexadecimal). Similarly, to read (hexadecimal) and follow that command with 24 physical channel one’s gain register, the user must bits of data. Similarly, to read CSR1, the user must first transmit the command byte 0x0A (hexadeci- transmit the command byte 0x0D (hexadecimal) mal) and then read the 24 bits of data. Once an off- and then read the 24 bits of data. To write more set, a gain, or the configuration register is written to than one CSR, for instance CSR1 and CSR2 or read from, the serial port returns to the command (Setup1, Setup2, Setup3, and Setup4), the user mode. would first set the depth pointer bits in the configu- ration register to ‘0011’ binary. The user would then 1.2.6 Reading/Writing the Channel-Setup Reg- transmit the write CSR command 0x05 (hexadeci- isters mal) and follow that with the information for The CS5521/22 have two 24-bit channel-setup reg- Setup1, Setup2, Setup 3, and Setup 4 which is 48 isters (CSRs). The CS5523/24 have four CSRs, and bits of information. Note that while reading/writing the CS5528 has eight CSRs (refer to Table 3 for CSRs, two Setups are accessed in pairs as a single more detail on the CSRs). These registers are ac- 24-bit CSR register. Even if one of the Setups isn’t cessed in conjunction with the depth pointer bits in used, it must be written to or read. Further note that the configuration register. Each CSR contains two the CSRs are accessed as a closed array – the user 12-bit Setups which are programmed by the user to can not access CSR2 without accessing CSR1. This contain data conversion or calibration information requirement means that the depth bits in the config- such as: uration register can only be set to one of the follow- ing states when the CSRs are being read from or 1) state of the output latch pins written to: 0001, 0011, 0101, 0111, 1001, 1011, 2) output word rate 1101, 1111. Examples detailing the power of the 3) gain range CSRs are provided in the Performing Conversions and Reading the Data Conversion FIFO section. 4) polarity Once the CSRs are written to or read from, the serial 5) the address of a physical input channel to be port returns to the command mode. converted. 26 DS317F8

CS5521/22/23/24/28 CSR (Channel-Setup Register) CSR CSR #1 Setup1 Setup2 #1 Setup1 Setup2 #1 Setup1 Setup2 Bits <47:36> Bits <35:24> Bits <95:84> Bits <83:72> Bits <191:180> Bits <179:168> #2 Setup3 Setup4 Bits <23:12> Bits <11:0> #4 Setup7 Setup8 #8 Setup15 Setup16 Bits <23:12> Bits <11:0> Bits <23:12> Bits <11:0> CS5521/22 CS5523/24 CS5528 D23(MSB) D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 A1 A0 CS2 CS1 CS0 WR2 WR1 WR0 G2 G1 G0 U/B D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 CS2 CS1 CS0 WR2 WR1 WR0 G2 G1 G0 U/B BIT NAME VALUE FUNCTION D23-D22/ Latch Outputs, A1-A0 00 *R Latch Output Pins A1-A0 mimic D23/D11-D22/D10 register bits. D11-D10 D21-D19/ Channel Select, CS2- 000 R Select physical channel 1 (All devices) D9-D7 CS0 001 Select physical channel 2(All devices) 010 Select physical channel 3 (CS5523/24/28 only) 011 Select physical channel 4 (CS5523/24/28 only) 100 Select physical channel 5 (CS5528 only) 101 Select physical channel 6 (CS5528 only) 110 Select physical channel 7 (CS5528 only) 111 Select physical channel 8 (CS5528 only) D18-D16/ Word Rate, WR2-WR0 000 R 15.0 Sps (2180 XIN cycles). D6-D4 001 30.0 Sps (1092 XIN cycles). 010 61.6 Sps (532 XIN cycles). 011 84.5 Sps (388 XIN cycles). 100 101.1 Sps (324 XIN cycles). 101 1.88 Sps (17444 XIN cycles). 110 3.76 Sps (8724 XIN cycles). 111 7.51 Sps (4364 XIN cycles). D15-D13/ Gain Bits, G2-G0 000 R 100 mV (assumes VREF Differential = 2.5 V) D3-D1 001 55 mV 010 25 mV 011 1.0 V 100 5.0 V 101 2.5 V 110 Not used. 111 Not used. D12/D0 Unipolar/Bipolar, U/B 0 R Bipolar measurement mode. 1 Unipolar measurement mode. * R indicates the bit value after the part is reset Table 3. Channel-Setup Registers DS317F8 27

CS5521/22/23/24/28 1.2.6.1 Latch Outputs 1.2.7 Configuration Register The A1-A0 pins mimic the latch output, D23/D11- The configuration register is 24 bits long. The fol- D22/D10, bits of the channel-setup registers. A1-A0 lowing subsections detail the bits in the configura- can be used to control external multiplexers and oth- tion register. Table 4 summarizes the configuration er logic functions outside the converter. The outputs register. can sink or source at least 1mA, but it is recom- 1.2.7.1 Chop Frequency Select mended to limit drive currents to less than 20μA to reduce self-heating of the chip. These outputs are The chop frequency select (CFS1-CFS0) bits are powered from VA+, hence their output voltage for used to set the rate at which the instrumentation a logic 1 will be limited to the VA+ supply voltage. amplifier’s chop switches modulate the input sig- nal. The 256Hz rate is desirable as it provides the 1.2.6.2 Channel Select Bits lowest input CVF (sampling) current, <300pA The channel select, CS1-CS0, bits are used to de- over -40 to 85 °C. The higher rates can be used to termine which physical input channel will be used eliminate modulation/aliasing effects as the fre- when a conversion is performed with a particular quency of the input signal increases. Setup. 1.2.7.2 Conversion/Calibration Control Bits 1.2.6.3 Output Word Rate Selection The conversion/calibration control bits in the con- The word rate, WR2-WR0, bits of the channel-set- figuration register are used to control the particular up registers set the output conversion word rate of type of conversion required for the users applica- the converter when a conversion is performed with tions. In short, the depth pointer (DP3-DP0) bits a particular Setup. The word rates indicated in determine the number of Setups that will be refer- Table 3 assume a master clock of 32.768kHz, and enced when conversions are performed. The multi- scale linearly when using other master clock fre- ple conversion (MC) bit instructs the converter to quencies. Upon reset the converter is set to operate perform conversions on the number of Setups in the with an output word rate of 15.0Sps. channel-setup registers which are referenced by the depth pointer bits. The converter begins with 1.2.6.4 Gain Bits Setup1 and moves sequentially through the Setups The gain bits, G2-G0, of the channel-setup regis- in this mode. The Loop (LP) bit instructs the con- ters set the full-scale differential input range for the verter to continuously perform conversions until a ADC when a conversion is performed with a partic- Stop command is sent to the converter. The read ular Setup. The input ranges in the table assume a convert (RC) bit instructs the converter to wait until 2.5V reference voltage, and scale linearly when the conversion data is read before performing the using other reference voltages. next conversion or set of conversions. 1.2.6.5 Unipolar/Bipolar Bit 1.2.7.3 Power Consumption Control Bits The unipolar/bipolar bit is used to determine the The CS5522/24/28 devices provide three power type of conversion, unipolar or bipolar, that will be consumption modes: normal, low power, and performed with a particular Setup. sleep. The CS5521/23 provide two power con- sumption modes: normal, and sleep. The normal (default) mode is entered after a power-on reset. In normal mode, the CS5522/24/28 typically con- 28 DS317F8

CS5521/22/23/24/28 sume 9.0mW. The CS5521/23 typically consume at any time by writing a logic 1 to the RS bit in the 6.0mW. The low-power mode is an alternate mode configuration register. After a system reset cycle is in the CS5522/24/28 that reduces the consumed complete, the reset valid (RV) bit is set indicating power to 5.5mW. It is entered by setting bit D8 that the internal logic was properly reset. The RV (the low-power mode bit) in the configuration reg- remains set until the configuration register is read. ister to logic 1. Slightly degraded noise or linearity Note that the user must write a logic 0 to the RS bit performance should be expected in the low-power to take the part out of the reset mode. No other bits mode. Note that the XIN clock should not exceed in the configuration register can be written at this 130kHz in low-power mode. The final two modes time. A subsequent write to the configuration reg- accommodated in all devices are referred to as the ister is necessary to write to any other bits in this power save modes. They power down most of the register. Once reset, the on-chip registers are ini- analog portion of the chip and stop filter convolu- tialized to the following states. tions. The power-save modes are entered whenever configuration register: 000040(H) the PS/R bit of the configuration register is set to offset registers: 000000(H) logic 1. The particular power-save mode entered gain registers: 400000(H) depends on state of bit D11 (PSS, the Power Save channel setup registers: 000000(H) Select bit) in the configuration register. If PSS is logic 0, the converters enters the standby mode re- 1.2.7.6 Data Conversion Error Flags ducing the power consumption to 1.2mW. If the The oscillation detect (OD) and overflow (OF) bits PSS bit (bit D11) is set to logic zero, the PD bit (bit in the configuration register are flag bits used to in- D10) must be set to one. The standby mode leaves dicate that the ADC performed a conversion on an the oscillator and the on-chip bias generator run- input signal that was not within the conversion ning. This allows the converter to quickly return to range of the ADC. For convenience, the OD and the normal or low-power mode once the PS/R bit is OF bits are also in the data conversion word of the set back to a logic 0. If PSS and PS/R in the config- CS5521/23. uration register are set to logic 1, the sleep mode is entered reducing the consumed power to around The OF bit is set to logic 1 when the input signal is: 500μW. Since the sleep mode disables the oscilla- 1) more positive than full scale tor, a 500ms oscillator start-up delay period is re- 2) more negative than zero in unipolar mode, or quired before returning to the normal or low-power mode. 3) more negative than negative full scale in bipo- lar mode. 1.2.7.4 Charge Pump Disable The OF flag is cleared to logic 0 when a conversion The pump disable (PD) bit permits the user to turn occurs which is not out of range. off the charge pump drive thus enabling the user to The OD bit is set to logic 1 any time that an oscil- reduce the radiation of digital interference from the latory condition is detected in the modulator. This CPD pin when the charge pump is not being used. does not occur under normal operating conditions, 1.2.7.5 Reset System Control Bits but may occur when the input is extremely over- ranged. The OD flag will be cleared to logic 0 when The reset system (RS) bit permits the user to per- the modulator becomes stable. form a system reset. A system reset can be initiated DS317F8 29

CS5521/22/23/24/28 D23(MSB) D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 NU NU CFS1 CFS0 NU MC LP RC DP3 DP2 DP1 DP0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PSS PD PS/R LPM RS RV OD OF NU NU NU NU BIT NAME VALUE FUNCTION D23-D22 Not Used, NU 00 R1 Must always be logic 0. D21-D20 Chop Frequency Select, 00 R 256 Hz Amplifier chop frequency. (XIN = 32.768 kHz) CFS1-CFS0 01 4,096 Hz Amplifier chop frequency. 10 16,384 Hz Amplifier chop frequency. 11 1,024 Hz Amplifier chop frequency. D19 Not Used, NU 0 R Must always be logic 0. D18 Multiple Conversion, MC 0 R Perform single-Setup conversions. MC bit is ignored during calibrations. 1 Perform multiple-Setup conversions on Setups in the channel-setup reg- ister by issuing only one command with MSB = 1. D17 Loop, LP 0 R The conversions on the single Setup (MC = 0) or multiple Setups (MC = 1) are performed only once. 1 The conversions on the single Setup (MC = 0) or multiple Setups (MC = 1) are continuously performed. D16 Read Convert, RC 0 R Don’t wait for user to finish reading data before starting new conversions. 1 The RC bit is used in conjunction with the LP bit when the LP bit is set to logic 1. If LP = 0, the RC bit is ignored. If LP = 1, the ADC waits for user to read data conversion(s) before converting again. The RC bit is ignored during calibrations. Refer to Calibration Protocol for details. D15-D12 Depth Pointer, DP3-DP0 0000 R When writing or reading the CSRs, these bits (DP3-DP0) determine the . number of CSR’s to be accessed (0000=1). They are also used to deter- . mine how many Setups are converted when MC=1 and a command byte 1111 with its MSB = 1 is issued. Note that the CS5522 has two CSRS, the CS5524 has four CSRs, and the CS5528 has 8 CSRs. D11 Power Save Select, PSS 02 R Standby Mode (Oscillator active, allows quick power-up). 1 Sleep Mode (Oscillator inactive). D10 Pump Disable, PD 0 R Charge Pump Enabled. 1 For PD = 1, the CPD pin goes to a Hi-Z output state. D9 Power Save/Run, PS/R 0 R Run. 1 Power Save. D8 Low Power Mode, LPM 0 R Normal Mode (LPM bit is only for the CS5522/24/28) 1 Reduced Power Mode D7 Reset System, RS 0 R Normal Operation. 1 Activate a Reset cycle. To return to Normal Operation write bit to zero. D6 Reset Valid, RV 0 No reset has occurred or bit has been cleared (read only). 1 R Bit is set after a Valid Reset has occurred. (Cleared when read.) D5 Oscillation Detect, OD 0 R Bit is clear when an oscillation condition has not occurred (read only). 1 Bit is set when an oscillatory condition is detected in the modulator. D4 Overrange Flag, OF 0 R Bit is clear when an overrange condition has not occurred (read only). 1 Bit is set when input signal is more positive than the positive full scale, more negative than zero (unipolar mode), or when the input is more neg- ative than the negative full scale (bipolar mode). D3-D0 Not Used, NU 0000 R Must always be logic 0. 1.R indicates the bit value after the part is reset. 2.When the chip is placed in standby mode, the PD bit (bit D10) should be set to 1. Table 4. Configuration Register 30 DS317F8

CS5521/22/23/24/28 1.3 Calibration gain register spans from 0 to (4 - 2-22). The decimal equivalent meaning of the gain register is: The CS5521/22/23/24/28 offer four different cali- bration functions including self calibration and sys- N tem calibration. However, after the devices are D = b 21+(b 20+b 2–1+…+b 2–N) = b 21+ b2–i MSB 0 1 N MSB i reset, the converter is functional and can perform i=0 measurements without being calibrated. In this where the binary numbers have a value of either case, the converter will utilize the initialized values zero or one (b corresponds to bit MSB-1, N=22). 0 of the on-chip registers (Gain=1.0, Offset = 0.0) Refer to Table 5 for details. to calculate output words for the ±100mV range. The offset and gain calibration steps each take one Any initial offset and gain errors in the internal cir- conversion cycle to complete. At the end of the cal- cuitry of the chip will remain. ibration step, SDO falls to indicate that the calibra- The gain and offset registers, which are used for tion has finished. both self and system calibration, are used to set the 1.3.1 Self Calibration zero and full-scale points of the converter’s transfer function. One LSB in the offset register is 2-24 pro- The CS5521/22/23/24/28 offer both self-offset and portion of the input span when the gain register is self-gain calibrations. For self calibration of offset set to 1.0 decimal (bipolar span is 2 times the uni- in the 25mV, 55mV, and 100mv ranges, the con- polar span). The MSB in the offset register deter- verters internally tie the inputs of the instrumenta- mines if the offset to be trimmed is positive or tion amplifier together and route them to the AIN- negative (0 positive, 1 negative). The converter can pin as shown in Figure11 (in the CS5528 they are typically trim ±50 percent of the input span. The routed to AGND). For proper self-calibration of Offset Register MSB ≈ LSB Register Sign 2-2 2-3 2-4 2-5 2-6 2-19 2-20 2-21 2-22 2-23 2-24 Reset (R) 0 0 0 0 0 0 0 0 0 0 0 0 One LSB represents 2-24 proportion of the input span when gain register is set to 1.0 decimal (bipolar span is 2 times unipolar span) Offset and data word bits align by MSB (bit MSB-4 of offset register changes bit MSB-4 of data) Gain Register MSB ≈ LSB Register 21 20 2-1 2-2 2-3 2-4 2-17 2-18 2-19 2-20 2-21 2-22 Reset (R) 0 1 0 0 0 0 0 0 0 0 0 0 The gain register span is from 0 to (4-2-22). After Reset the (MSB-1) bit is 1, all other bits are 0. Table 5. Offset and Gain Registers DS317F8 31

CS5521/22/23/24/28 offset to occur in the 25mV, 55mV, and 100mV the full-scale voltage. In addition, when self cali- ranges, the AIN- pin must be at the proper com- bration of gain is performed in the 25mV, 55mV, mon-mode voltage as specified in ‘Common Mode and 100mV input ranges, the instrumentation am- +Signal AIN+/-’ specification in the Analog Input plifier’s gain is not calibrated. These two factors section (if AIN-=0V, NBV must be between - can leave the converters with a gain error of up to 1.8V to -2.5V). For self calibration of offset in the ±20% after self calibration of gain. Therefore, a 1.0V, 2.5V, and 5V ranges, the inputs of the mod- system gain calibration is required to get better ac- ulator are connected together and then routed to the curacy, except for the 2.5V range. VREF- pin as shown in Figure12. 1.3.2 System Calibration For self calibration of gain, the differential inputs For the system calibration functions, the user must of the modulator are connected to VREF+ and supply the calibration signals to the converter which VREF- as shown in Figure 13. For any input range represent ground and full scale. When a system offset other than the 2.5V range, the converter’s gain er- calibration is performed, a ground-referenced signal ror can not be completely calibrated out when using must be applied to the converters. See self calibration. This is due to the lack of an accu- Figures14and15. rate full-scale voltage internal to the chips. The 2.5V range is an exception because the external As shown in Figures 16and17, the user must input reference voltage is 2.5V nominal and is used as a signal representing the positive full-scale point to S1 S1 OPEN OPEN AIN+ + + D AIN+ + + E X20 S3OS S2 X20 CL CLOSED AIN- - - S2 AIN- - - OPEN VREF- S4 CLOSED Figure 11. Self Calibration of Offset (Low Ranges) Figure 12. Self Calibration of Offset (High Ranges) OPEN AIN+ + + External Connections X20 + + AIN+ AIN- - - OPEN 0V +- X20 VREF+ - - Reference +- VREF- CCLLOOSSEEDD CM +- AIN- Figure 13. Self Calibration of Gain (All Ranges) Figure 14. System Calibration of Offset (Low Ranges) 32 DS317F8

CS5521/22/23/24/28 perform a system gain calibration. In either case, 2) The 1’s density of the modulator must not be the calibration signals must be within the specified greater than 80 percent (the input to the ΔΣ calibration limits for each specific calibration step modulator must not exceed the maximum input (refer to the ‘System Calibration Specifications’ in which Table 1 specifies). ANALOG CHARACTERISTICS). If a system gain 3) The input must not be so small, relative to the calibration is performed the following conditions range chosen, that the resulting gain register’s must be met: content, decoded in decimal, exceeds 3.9999998 (see the discussion of operating lim- External its on input span under the Analog Input and Connections Limitations in Calibration Range sections). + + AIN+ This requires the full-scale input voltage to the 0V +- X20 modulator to be at least 25 percent of the nom- - - inal value. AIN- CM +- The converter’s input ranges were chosen to guar- antee gain calibration accuracy to 1 LSB or 16 16 Figure 15. System Calibration of Offset (High Ranges) LSB when system gain calibration is performed. 24 This is useful when a user wants to manually scale the full-scale range of the converter and maintain External accuracy. For example, if a gain calibration is per- Connections + + formed with a 2.5V full-scale voltage and a 1.25V AIN+ Full Scale +- X20 input range is desired, the user can read the con- tents of the gain register, shift the register contents - - AIN- CM +- left by 1 bit, and then write the result back to the gain register. This multiplies the gain by 2. Figure 16. System Calibration of Gain (Low Ranges) Assuming a system can provide two known voltag- es, the following equations allow the user to manu- ally compute the calibration register’s values based External on two uncalibrated conversions (see note). The Connections offset and gain calibration registers are used to ad- + + AIN+ just a typical conversion as follows: Full Scale +- X20 - - Rc = (Ru + Co) * Cg / 222. AIN- CM +- Calibration can be performed using the following equations: Figure 17. System Calibration of Gain (High Ranges) Co = (Rc0/G - Ru0) Cg = 222 * G where G = (Rc1 - Rc0)/(Ru1-Ru0). 1) Full-scale input must not saturate the 20X in- strumentation amplifier, if the calibration is on Note: Uncalibrated conversions imply that the gain and off- an input range where the instrumentation am- set registers are at default {gain register=0x400000 (Hex) and offset register=0x000000 (Hex)}. plifier is involved. DS317F8 33

CS5521/22/23/24/28 The variables are defined below. 1.3.4 Limitations in Calibration Range V0 = First calibration voltage System calibration can be limited by signal head- room in the analog signal path inside the chip as V1 = Second calibration voltage (greater than V0) discussed under the Analog Input section of this Ru = Result of any uncalibrated conversion data sheet. For gain calibration the full-scale input Ru0 = Result of uncalibrated conversion V0 signal can be reduced to the point in which the gain (24-bit integer or 2’s complement) register reaches its upper limit of (4-2-22 decimal) Ru1 = Result of uncalibrated conversion of V1 or FFFFFF (hexadecimal). Under nominal condi- (24-bit integer or 2’s complement) tions, this occurs with a full-scale input signal Rc = Result of any conversion equal to about 1/4 the nominal full scale. With the Rc0 = Desired calibrated result of converting V0 converter’s intrinsic gain error, this full-scale input (24-bit integer or 2’s complement) signal may be higher or lower. In defining the min- Rc1 = Desired calibrated result of converting V1 imum Full Scale Calibration Range (FSCR) under (24-bit integer or 2’s complement) ANALOG CHARACTERISTICS, margin is retained Co = Offset calibration register value to accommodate the intrinsic gain error. Alterna- (24-bit 2’s complement) tively the input full-scale signal can be increased to Cg = Gain calibration register value a point in which the modulator reaches its 1’s den- (24-bit integer) sity limit of 80 percent, which under nominal con- dition occurs when the full-scale input signal is 1.5 1.3.3 Calibration Tips times the nominal full scale. With the chip’s intrin- Calibration steps are performed at the output word sic gain error, this full-scale input signal may be rate selected by the WR2-WR0 bits of the configu- higher or lower. In defining the maximum FSCR, ration register. Since higher word rates result in margin is again incorporated to accommodate the conversion words with more peak-to-peak noise, intrinsic gain error. In addition, for full-scale inputs calibration should be performed at lower output greater than the nominal full-scale value of the word rates. Also, to minimize digital noise near range selected, there is some voltage at which var- the device, the user should wait for each calibration ious internal circuits may saturate due to limited step to be completed before reading or writing to amplifier headroom. This is most likely to occur in the serial port. the 100mV range. For maximum accuracy, calibrations should be per- 1.4 Performing Conversions and Reading formed for offset and gain (selected by changing the Data Conversion FIFO the G2-G0 bits of the desired Setup). Note that only one gain range can be calibrated per physical chan- The CS5521/22/23/24/28 offers various modes of nel. If factory calibration of the user’s system is performing conversions. The sections that follow performed using the system calibration capabilities detail the differences between the conversion of the CS5521/22/23/24/28, the offset and gain reg- modes. The sections also provide examples illus- ister contents can be read by the system microcon- trating how to use the conversion modes with the troller and recorded in EEPROM. These same channel-setup registers and to acquire conversions calibration words can then be uploaded into the off- for further processing. While reading, note that the set and gain registers of the converter when power CS5521/22 have a FIFO which is four words deep. is first applied to the system, or when the gain range The CS5523/24 have a FIFO which is eight words is changed. deep and the CS5528 has a FIFO which is sixteen 34 DS317F8

CS5521/22/23/24/28 conversion words deep. Further note that the type SCLKs are then needed to read the conversion of conversion(s) performed and the way to access word from the data register. The first 8 SCLKs are the resulting data from the FIFO is determined by used to clear the SDO flag. During the last 24 the MC (multiple conversion), the LP (loop), the SCLKs, the data word will be output from the con- RC (read convert), and the DP (depth pointer) bits verter on the SDO line. The part returns to com- in the configuration register. mand mode immediately after the data word has been read, where it waits for the next command to 1.4.1 Conversion Protocol be issued. The CS552x offer six different conversion modes, 1.4.1.2 Repeated One-Setup Conversions with- which can be categorized into two main types of out Wait conversions: one-Setup conversions, which refer- ence only one Setup, and multiple-Setup conver- (LP= 1 MC= 0 RC =0) sions, which reference any number of Setups. The In this conversion mode, the ADC will repeatedly converter can be instructed to perform single con- perform conversions, referencing only one Setup. versions or repeated conversions (with or without The 8-bit command word contains the CSRP bits, wait) in either of these modes, using the MC, LP, which instruct the converter which Setup to use and RC bits in the Configuration Register. The MC when performing the conversion. Note that in this bit controls whether the part will do one-Setup or mode, the part will continually perform conver- multiple-Setup conversions. The LP bit controls sions, and the user need not read every conversion whether the part will perform a single or repeated as it becomes available. Although conversions can conversion set. When doing repeated conversion be read whenever they are needed, they must be sets, the RC bit controls whether or not the convert- read within one conversion cycle (defined by the er will wait for the data from the current conversion referenced Setup), as the data word will be over- set to be read before beginning the next conversion written when new conversion data becomes avail- able. The SDO line rises and falls to indicate the set. The sections that follow further detail the vari- availability of new conversion data. When new ous conversion modes. data is available, the current conversion data will 1.4.1.1 Single, One-Setup Conversion be lost, or in the case that the user has only read a part of the conversion word, the remainder of the (LP =0 MC= 0 RC =X) conversion word will be corrupted. In this conversion mode, the ADC will perform a To perform repeated, one-Setup conversions with single conversion, referencing only one Setup, and no wait, the MC bit must be set to '0', the LP bit return to command mode after the data word has must be set to '1', and the RC bit must be set to '0' been fully read. The 8-bit command word contains in the Configuration Register. Then, the 8-bit com- the CSRP bits, which instruct the converter which mand word that references the desired Setup must Setup to use when performing the conversion. be sent to the converter. The ADC will then begin To perform a single, one-Setup conversion, the MC performing conversions on the referenced Setup, and LP bits in the Configuration Register must be and SDO will fall to indicate when a conversion is set to '0'. Then, the 8-bit command word that refer- complete, and data is available. Thirty-two SCLKs ences the desired Setup must be sent to the convert- are then needed to read the conversion word from er. The ADC will then perform a single conversion the data register. The first 8 SCLKs are used to on the referenced Setup, and SDO will fall to indi- clear the SDO flag. During the last 24 SCLKs, the cate that the conversion is complete. Thirty-two data word will be output from the converter on the DS317F8 35

CS5521/22/23/24/28 SDO line. If, during the first 8 SCLKs, quired to read the final conversion word from the "00000000" is provided on SDI, the converter will data register and return to command mode. remain in this conversion mode, and continue to 1.4.1.4 Single, Multiple-Setup Conversions perform conversions on the selected Setup. To exit this conversion mode, "11111111" must be provid- (LP= 0 MC= 1 RC =X) ed on SDI during the first 8 SCLKs. If the user de- In this conversion mode, the ADC will perform sin- cides to exit, 24 more SCLKs are required to read gle conversions, referencing multiple Setups, and the final conversion word from the data register and return to command mode after the data for all con- return to command mode. versions have been read. The CSRP bits in the command word are ignored in this mode. Instead, 1.4.1.3 Repeated One-Setup Conversions with the Depth Pointer (DP3-DP0) bits in the Configu- Wait ration Register are accessed to determine the num- (LP =1 MC= 0 RC =1) ber of Setups to reference when collecting the data. In this conversion mode, the ADC will repeatedly The number of Setups referenced will be equal to perform conversions, referencing only one Setup. (DP3-DP0) + 1, and will be accessed in order, be- The 8-bit command word contains the CSRP bits, ginning with Setup1. which instruct the converter which Setup to use To perform single, multiple-Setup conversions, the when performing the conversion. Note that in this MC bit must be set to '1', and the LP bit must be set mode, every conversion word must be read. The to '0' in the Configuration Register. Then, the 8-bit part will wait for the current conversion word to be command word to start a conversion must be sent read before performing the next conversion. to the converter. Because the CSRP bits of the To perform repeated, one-Setup conversions with command word are ignored in this mode, a "start wait, the MC bit must be set to '0', the LP bit must convert" command referencing any of the available be set to '1', and the RC bit must be set to '1' in the Setups will begin the conversions. The ADC will Configuration Register. Then, the 8-bit command then perform conversions using the appropriate word that references the desired Setup must be sent number of Setups (as dictated by the DP bits in the to the converter. The ADC will then begin per- Configuration Register), beginning with Setup1. forming conversions on the referenced Setup, and The SDO line will fall after the final conversion to SDO will fall to indicate when a conversion is com- indicate that the data is ready. Eight SCLKs, plus plete, and data is available. Thirty-two SCLKs are 24 SCLKs for each Setup referenced are required to then needed to read the conversion word from the read the conversion words from the data FIFO. The data register. The first 8 SCLKs are used to clear first 8 SCLKs are used to clear the SDO flag. Ev- the SDO flag. During the last 24 SCLKs, the data ery 24 bits thereafter consist of the data words of word will be output from the converter on the SDO each Setup that was referenced, until all of the data line. If, during the first 8 SCLKs, "00000000" is has been read from the part. The data word from provided on SDI, the converter will remain in this Setup1 is output first, followed by the data word conversion mode, and continue to perform conver- from Setup2, and so on for the appropriate number sions on the selected Setup after each data word is of Setups. The part returns to command mode im- read. To exit this conversion mode, "11111111" mediately after the final data word has been read, must be provided on SDI during the first 8 SCLKs. and waits for the next command to be issued. If the user decides to exit, 24 more SCLKs are re- 36 DS317F8

CS5521/22/23/24/28 1.4.1.5 Repeated Multiple-Setup Conversions has been read from the part. If, during the first 8 without Wait SCLKs, "00000000" is provided on SDI, the con- verter will remain in this conversion mode, and (LP =1 MC= 1 RC =0) continue to perform conversions on the desired In this conversion mode, the ADC will repeatedly number of Setups. To exit this conversion mode, perform conversions, referencing multiple Setups. "11111111" must be provided on SDI during the The CSRP bits in the command word are ignored in first 8 SCLKs. If the user decides to exit, 24 more this mode. Instead, the Depth Pointer (DP3-DP0) SCLKs for each referenced Setup are required to bits in the Configuration Register are accessed to read the final conversion data set from the FIFO determine the number of Setups to reference when and return to command mode. collecting the data. The number of Setups refer- 1.4.1.6 Repeated Multiple-Setup Conversions enced will be equal to (DP3-DP0) + 1, and will be with Wait accessed in order, beginning with Setup1. Note that in this mode, the part will continually perform con- (LP= 1 MC= 1 RC =1) versions, looping back to Setup1 when finished In this conversion mode, the ADC will repeatedly with each set, and the user need not read every con- perform conversions, referencing multiple Setups. version set as it becomes available. The SDO line The CSRP bits in the command word are ignored in rises and falls to indicate the availability of new this mode. Instead, the Depth Pointer (DP3-DP0) conversion data sets. When new data is available, bits in the Configuration Register are accessed to the current conversion data set will be lost, or in the determine the number of Setups to reference when case that the user has only read a part of the conver- collecting the data. The number of Setups refer- sion set, the remainder of the conversion set will be enced will be equal to (DP3-DP0) + 1, and will be corrupted. accessed in order, beginning with Setup1. Note that To perform repeated, multiple-Setup conversions in this mode, every conversion data set must be with no wait, the MC bit must be set to '1', the LP read. The part will wait for the current conversion bit must be set to '1', and the RC bit must be set to data set to be read before performing the next set of '0' in the Configuration Register. Then, the 8-bit conversions. command word to start a conversion must be sent To perform repeated, multiple-Setup conversions to the converter. Because the CSRP bits of the with wait, the MC bit must be set to '1', the LP bit command word are ignored in this mode, a "start must be set to '1', and the RC bit must be set to '1' convert" command referencing any of the available in the Configuration Register. Then, the 8-bit com- Setups will begin the conversions. The ADC will mand word to start a conversion must be sent to the then perform conversions using the appropriate converter. Because the CSRP bits of the command number of Setups (as dictated by the DP bits in the word are ignored in this mode, a "start convert" Configuration Register), beginning with Setup1. command referencing any of the available Setups The SDO line will fall after the final conversion to will begin the conversions. The ADC will then per- indicate that the data is ready. Eight SCLKs, plus form conversions using the appropriate number of 24 SCLKs for each Setup referenced are required to Setups (as dictated by the DP bits in the Configura- read the conversion words from the data FIFO. The tion Register), beginning with Setup1. The SDO first 8 SCLKs are used to clear the SDO flag. Ev- line will fall after the final conversion to indicate ery 24 bits thereafter consist of the data words of that the data is ready. Eight SCLKs, plus 24 each Setup that was referenced, until all of the data DS317F8 37

CS5521/22/23/24/28 SCLKs for each Setup referenced are required to 1.4.3 Example of Using the CSRs to Perform read the conversion words from the data FIFO. The Conversions and Calibrations first 8 SCLKs are used to clear the SDO flag. Ev- Any time a calibration command is issued (CB=1 ery 24 bits thereafter consist of the data words of and proper CC2-CC0 bits set) or any time a normal each Setup that was referenced, until all of the data conversion command is issued (CB=1, has been read from the part. If, during the first 8 CC2=CC1=CC0=0, MC=0), the bits D6-D3 (or SCLKs, "00000000" is provided on SDI, the con- CSRP3 - CSRP0) in the command byte are used as verter will remain in this conversion mode, and be- pointers to address one of the Setups in the chan- gin performing the next set of conversions. To exit nel-setup registers (CSRs). Five example situations this conversion mode, "11111111" must be pro- that a user might encounter when acquiring a con- vided on SDI during the first 8 SCLKs. If the user version or calibrating the converter follow. These decides to exit, 24 more SCLKs for each referenced examples assume that the user is using a CS5528 Setup are required to read the final conversion data (16 Setups) and that its CSRs are programmed with set from the FIFO and return to command mode. the following physical channel order: 1.4.2 Calibration Protocol 6, 1, 6, 2, 6, 3, 6, 4, 6, 5, 6, 2, 6, 7, 6, 8. To perform a calibration, the user must send a com- Example 1: mand byte with its MSB=1, its pointer bits The configuration register has the following bits as (CSRP3-CSRP0) set to address the desired Setup to shown: DP3-DP0=‘XXXX’, MC= 0, L= 0, be calibrated, and the appropriate calibration bits RC =X. The command issued is ‘11110000’. (CC2-CC0) set to choose the type of calibration to These settings instruct the converter to convert the be performed. Proper calibration assumes that the 15th Setup once, as CPB3 - CPB0= ‘1110’ (which CSRs have been previously initialized because the happens to be physical channel 6 in this example). information concerning the physical channel, its SDO falls after physical channel 6 is converted. To filter rate, gain range, and polarity, comes from the read the conversion results, 32 SCLKs are then re- channel-setup register being addressed by the quired. Once acquired, the serial port returns to the pointer bits in the command byte. command mode. Once the CSRs are initialized, all future calibra- Example 2: tions can be performed with one command byte. The configuration register has the following bits as Once a calibration cycle is complete, SDO falls and shown: DP3-DP0=‘XXXX’, MC =0, LP= 1, the results are stored in either the gain or offset reg- RC =1. The command byte issued is ‘10011000’. ister for the physical channel being calibrated. Note These settings instruct the converter to repeatedly that if additional calibrations are performed on the convert the fourth Setup as CPB3-CPB0= ‘0011’ same physical channel referenced by a different (which happens to be physical channel 2 in this ex- Setup with different filter rates, gain ranges, or con- ample). SDO falls after physical channel 2 is con- version modes, the last calibration results will re- verted. To read the conversion results 32 SCLKs place the effects from the previous calibration as are required. The first 8 SCLKs are needed to clear only one offset and gain register is available per the SD0 flag. If ‘00000000’ is provided to the SDI physical channel. One final note is that only one pin during the first 8 SCLKs, the conversion is per- calibration is performed with each command byte. formed again on physical channel 2. The converter To calibrate all the channels additional calibration will remain in data mode until ‘11111111’ is pro- commands are necessary. vided during the first 8 SCLKs following the fall of 38 DS317F8

CS5521/22/23/24/28 SD0. After ‘11111111’ is provided, 24 additional corresponds to 10th Setup which here is physical SCLKs are required to transfer the last 3 bytes of channel 5. Since the Setups are converted in the conversion data before the serial port will return to background, while the data is being read, the user the command mode. must finish reading the conversion data FIFO be- fore it is updated with new conversions. To exit this Example 3: conversion mode the user must provide The configuration register has the following bits as ‘11111111’ to SDI during the first 8 SCLKs. If a shown: DP3-DP= ‘0101’, MC= 1, LP= 0, byte of 1’s is provided, the serial port returns to the RC= X. The command issued is ‘1XXXX000’. command mode only after the conversion data These settings instruct the converter to perform a FIFO is emptied (in this case 10 conversions are single conversion on six Setups once. The order in performed). Note that in this example physical which the channels are converted is 6, 1, 6, 2, 6, and channel 6 is converted five times. Each conversion 3. SDO falls after physical channel 3 is converted. could be with the same or different filter rates de- To read the 6 conversion results 8 SCLKs are re- pending on the setting of Setups 1, 3, 5, 7 and 9. quired to clear the SD0 flag. Then 144 additional Note that there is only one offset and one gain reg- SCLKs are required to read the conversion data ister per physical channel. Therefore, any physical from the FIFO. Again, the order in which the data channel can only be calibrated for the gain range is provided is the same as the order in which the selected during calibration. Specifying a different channels are converted. After the last 3 bytes of the gain range in the Setup other than the range that conversion data corresponding to physical channel was calibrated will result in a gain error. 3 is read, the serial port automatically returns to the Example 5: command mode where it will remain until the next valid command byte is received. The configuration register has the following bits as shown: DP3-DP0= ‘XXXX’, MC =X, LP= X, Example 4: RC =X. The command issued is ‘10101101’. The configuration register has the following bits as These settings instruct the converter to perform a shown: DP3-DP0=‘1001’, MC= 1, LP= 1, system offset calibration of the 6th Setup (which is RC= 0. The command byte issued is physical channel 3 in this example). During cali- ‘1XXXX000’. These settings instruct the convert- bration, the serial port remains in the command er to repeatedly perform multiple-setup conver- mode. Once the calibration is completed, SDO sions using ten Setups. The order in which the falls. To perform additional calibrations, more channels are converted is: 6, 1, 6, 2, 6, 3, 6, 4, 6, 5. commands have to be issued. SDO falls after physical channel 5 is converted. To Notes: 1)The configuration register must be written before read the 10 conversion results 8 SCLKs with channel-setup registers (CSRs) because the depth SDI = 0 are required to clear the SD0 flag. Then information contained in the configuration regis- 240 more SCLKs are required to read the conver- ter defines how many of the CSRs to use. sion data from the FIFO. The order in which the 2) The CSRs need to be written regardless of single data is provided is the same as the order in which conversion or multiple single conversion mode. the channels are converted. The first 3 bytes of data 3) When single-Setup conversions (MC=0) are de- correspond to the first Setup which in this example sired, the channel address is embedded in the command byte. In the multiple-Setup conversion is physical channel 6; the next 3 bytes of data cor- mode (MC=1), channels are selected in a pre- respond to the second Setup which in this example programmed order based on information con- is physical channel 1; and, the last 3 bytes of data tained in the CSRs and the depth bits (DP3-DP0) DS317F8 39

CS5521/22/23/24/28 of the configuration register. the conversions MSB first. The last byte of the con- 4) Once the CSRs are programmed, repeated conver- version data word (CS5521/23 only) contains data sions on up to 16 Setups can be performed by is- monitoring flags. The channel indicator (CI) bits suing only one command byte. keep track of which physical channel was convert- 5) The single conversion mode also requires only one ed, and the overrange flag (OF) and the oscillation command, but whenever another or a different detect (OD) bits monitor conversions to determine single conversion is wanted, this command or a modified version of it has to be issued again. if a valid conversion was performed. Refer to the Conversion Data FIFO Descriptions section for 6) The NULL command is used to keep the serial port in command mode, once it is in command mode. more details. 1.5 Conversion Output Coding The CS5521/22/23/24/28 output data conversions in binary format when operating in unipolar mode The CS5521/22/23/24/28 devices output 16-bit and in two's complement when operating in bipolar (CS5521/23) and 24-bit (CS5522/24/28) data con- mode. Refer to the Conversion Data FIFO De- version words. To read a conversion word, the user scriptions section for more details. must read the conversion data FIFO. The conver- sion data FIFO is up to 192 bits long and outputs CS5521/23 16-Bit Output Coding CS5522/24/28 24-Bit Output Coding Unipolar Input Offset Bipolar Input Two's Unipolar Input Offset Bipolar Input Two's Voltage Binary Voltage Complement Voltage Binary Voltage Complement >(VFS-1.5 LSB) FFFF >(VFS-1.5 LSB) 7FFF >(VFS-1.5 LSB) FFFFFF >(VFS-1.5 LSB) 7FFFFF VFS-1.5 LSB FFFF 7FFF VFS-1.5 LSB FFFFFF 7FFFFF ------ VFS-1.5 LSB ------ ------ VFS-1.5 LSB ------ FFFE 7FFE FFFFFE 7FFFFE VFS/2-0.5 LSB 8000 0000 VFS/2-0.5 LSB 800000 000000 ------ -0.5 LSB ------ ------ -0.5 LSB ------ 7FFF FFFF 7FFFFF FFFFFF +0.5 LSB 0001 8001 +0.5 LSB 000001 800001 ------ -VFS+0.5 LSB ------ ------ -VFS+0.5 LSB ------ 0000 8000 000000 800000 <(+0.5 LSB) 0000 <(-VFS+0.5 LSB) 8000 <(+0.5 LSB) 000000 <(-VFS+0.5 LSB) 800000 Note: VFS in the table equals the voltage between ground and full scale for any of the unipolar gain ranges, or the voltage between ±full scale for any of the bipolar gain ranges. See text about error flags under overrange conditions. Table 6. Output Coding for 16-bit CS5521/23 and 24-bit CS5522/24/28 40 DS317F8

CS5521/22/23/24/28 1.5.1 Conversion Data FIFO Descriptions CS5521/23 (EACH 16-BIT CONVERSIONS) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 MSB 14 13 12 11 10 9 8 7 6 5 4 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 3 2 1 LSB 1 1 1 0 CI1 CI0 OD OF CS5522/24/28 (EACH 24-BIT CONVERSION LEVELS) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 MSB 22 21 20 19 18 17 16 15 14 13 12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 11 10 9 8 7 6 5 4 3 2 1 LSB Conversion Data Bits [23:8 for CS5521/23; 23:0 for CS5522/24/28] These bits depict the latest output conversion. OD (Oscillation detect Flag Bit) 0 Bit is clear when oscillatory condition in modulator does not exist (bit is read only). 1 Bit is set any time an oscillatory condition is detected in the modulator. This does not occur under normal operation conditions, but may occur when the input is extremely overranged. The OD flag will be cleared to logic 0 when the modulator becomes stable. OF (Over-range Flag Bit) 0 Bit is clear when over-range condition has not occurred (bit is read only). 1 Bit is set when input signal is more positive than the positive full scale, more negative than zero (unipolar mode) or when the input is more negative than the negative full scale (bipolar mode). CI (Channel Indicator Bits) [1:0] These bits indicate which physical input channel was converted. 00 Physical Channel 1 (CS5521/23 only) 01 Physical Channel 2 (CS5521/23 only) 10 Physical Channel 3 (CS5523 only) 11 Physical Channel 4 (CS5523 only) DS317F8 41

CS5521/22/23/24/28 1.6 Digital Filter The converters will operate with an external (CMOS compatible) clock with frequencies up to The CS5521/22/23/24/28 have eight different lin- 130kHz (CS5521/23) or 200kHz (CS5522/24/28). ear phase digital filters which set the output word Figures 19and20 detail the CS5521/23 and rates (OWRs) shown in Table 3. These rates as- CS5522/24/28’s performance (respectively) at in- sume that XIN is 32.768kHz. Each of the filters creased clock rates. has a magnitude response similar to that shown in Figure 18. The filters are optimized to settle to full The 32.768kHz crystal is normally specified as a accuracy every conversion and yield better than time-keeping crystal with tight specifications for 80dB rejection for both 50 and 60Hz with output both initial frequency and for drift over tempera- word rates at or below 15.0Sps. ture. To maintain excellent frequency stability, these crystals are specified only over limited oper- The converter’s digital filters scale with XIN. For ating temperature ranges (i.e. -10° C to +60° C). example with an output word rate of 15Sps, the fil- However, applications with the ter’s corner frequency is typically 12.7Hz using a CS5521/22/23/24/28 don’t generally require such 32.768kHz clock. If XIN is increased to tight tolerances. 65.536kHz the OWR doubles and the filter’s cor- ner frequency moves to 25.4Hz. 0.002 1.7 Clock Generator 0.0018 S) F 0.0016 The CS5521/22/23/24/28 include a gate which can % be connected with an external crystal to provide the Error ( 00..00001124 master clock for the chip. The chips are designed to y rit 0.001 operate using a low-cost 32.768kHz “tuning fork” ea 0.0008 n type crystal. One lead of the crystal should be con- Li 0.0006 nected to XIN and the other to XOUT. Lead lengths 0.0004 30 50 70 90 110 130 should be minimized to reduce stray capacitance. XIN (kHz) Note that the oscillator circuit will also operate with a 100kHz “tuning fork” type crystal. Figure 19. Typical Linearity Error for CS5521/23 0 0.0013 -10 -20 for OWR = 15.0 Sps 0.0012 -30 ff12 == 4675..55 HHzz FS) 0.0011 fS/2 = XIN/4 % uation (dB) -----4567800000 earity Error ( 000...0000.000000007891 Atten -90 Lin 00..00000056 -100 f2 -110 f1 0.0004 20 40 60 80 100 120 140 160 180 200 -120 15 Sps -130 XIN (kHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Figure 18. Filter Response (Normalized to Output Word Figure 20. Typical Linearity Error for CS5522/24/28 Rate = 15 Sps) 42 DS317F8

CS5521/22/23/24/28 1.8 Power Supply Arrangements on the converter. For the 25mV, 55mV, and 100mV ranges, the signals being digitized must The CS5521/22/23/24/28 A/D converters are de- have a common mode between +1.85 to +2.65V signed to operate from a single +5V analog supply (NBV =0V). and a single +5V or +3V digital supply. A -2.1V supply is usually generated from the charge pump Although CS5521/22/23/24/28 are optimized for drive to provide power to the instrumentation am- the measurement of thermocouple outputs, they are plifier’s NBV (negative bias voltage) pin. also well suited for the measurement of ratiometric Figure 21 illustrates the CS5522 connected with a bridge transducer outputs. Figure23 illustrates the +5V analog supply and with the external compo- CS5522 connected to measure the output of a rati- nents required for the charge pump drive. This en- ometric differential bridge transducer while operat- ables the CS5522 to measure ground-referenced ing from a single +5V supply. Bridge outputs may signals with magnitudes down to ±100mV. range from 5mV to 400mV. See “Digital Gain Scaling” on page 45 section about manipulating the Figure 22 illustrates the CS5522 connected to mea- gain register to achieve optimum gain scaling. sure ground-referenced unipolar signals of a posi- tive polarity using the 1V, 2.5V, and 5V ranges +5V 10 Ω Analog 0.1 μF 0.1 μF Supply 2 14 VA+ VD+ 11 2.5V 20 VREF+ XOUT 32.768 ~ 100 kHz 19 VREF- Optional 10 Up to ± 100 mV Input XIN Clock 10 kΩ CS5522 Source BAV199 3 AIN1+ 0.1 μF 9 4 CS AIN1- 15 10 kΩ 1 AGND SCLK Serial 8 Data SDI 18 Interface Cold Junction AIN2+ 12 17 SDO +5V AIN2- 16 LAMbs3o3l4ute V+R 6 AA10 NBV CPD DGND Logic Outputs: 5 7 13 A0 -A1 Switch from Current 499 Ω VA+ to AGND. Reference V- 0.033 μF 301 Ω 1N4148 Charge-pump network BAT85 10 μF 1N4148 forVD+ = 5V only and + XIN = 32.768 kHz. Figure 21. CS5522 Configured to use on-chip charge pump to supply NBV DS317F8 43

CS5521/22/23/24/28 +5V 10 Ω Analog 0.1 μF 0.1 μF Supply 2 14 VA+ VD+ 11 20 VREF+ XOUT 32.768 ~ 100 kHz 19 Optional VREF- 10 XIN Clock Source CS5522 3 AIN1+ 9 0 to +5V Input 4 CS AIN1- 15 1 AGND SCLK Serial 18 8 Data + AIN2+ SDI 17 Interface - AIN2- 12 CM = 0 to VA+ 16 A1 SDO 6 A0 NBV CPD DGND 5 7 13 Figure 22. CS5522 Configured for ground-referenced Unipolar Signals +5V 10 Ω Analog 0.1 μF 0.1 μF Supply 2 14 VA+ VD+ 11 20 XOUT 32.768 ~ 100kHz VREF+ 19 VREF- Optional 10 - XIN Clock + 3 AIN1+ Source CS5522 9 CS 41 AIN1- SCLK 15 Serial AGND 18 8 Data AIN2+ SDI 17 Interface AIN2- 12 16 SDO A1 6 A0 NBV CPD DGND 5 7 13 Figure 23. CS5522 Configured for Single Supply Bridge Measurement 44 DS317F8

CS5521/22/23/24/28 1.8.1 Charge Pump Drive Circuits 10μF ensures very low ripple on NBV. Intrinsic safety requirements prohibit the use of electrolytic The CPD (Charge Pump Drive) pin of the converter capacitors. In this case, four 0.47μF ceramic ca- can be used with external components (shown in pacitors in parallel can be used. Figure 21) to develop an appropriate negative bias voltage for the NBV pin. When CPD is used to gen- Note: The charge pump is designed to nominally provide erate the NBV, the NBV voltage is regulated with 400μA of current for the instrumentation amplifier when a 0.033μF pumping capacitor is used an internal regulator loop referenced to VA+. (XIN=32.768kHz). When a larger pumping capaci- Therefore, any change on VA+ results in a propor- tor is used, the charge pump can source more current tional change on NBV. With VA+ =5V, NBV’s to power external loads. Refer to Applications Note regulation is set proportional to VA+ at approxi- 152 “Using the CS5521/23, CS5522/24/28, and mately -2.1V. CS5525/26 Charge Pump Drive for External Loads” for more details on using the charge pump with exter- Figure 24 illustrates a charge pump circuit when nal loads. the converters are powered from a +3.0V digital 1.9 Digital Gain Scaling supply. Alternatively, the negative bias supply can be generated from a negative supply voltage or a The CS5521/22/23/24 and CS5528 all feature a resistive divider as illustrated in Figure 25. gain register capable of being scaled from 0.6 to 4- For ground-based signals with the instrumentation 2-22 in decimal. The specified ranges of the con- amplifier engaged (when in the 25mV, 55mV, or verter are defined with a voltage reference of 2.5V 100mV ranges), the voltage on the NBV pin and the gain register set at approximately 1.0. The should at no time be less negative than -1.8V or gain register can be manipulated to scale the input more negative than -2.5V. To prevent excessive for ranges other than those specified. For example, voltage stress to the chip when the instrumentation when using a 2.5V voltage reference, and the amplifier isn’t engaged (when in the 1V, 2.5V, or 25mV input range setting, the gain register can be 5V ranges) the NBV voltage should not be more changed from 1.000 to 2.000 (shift the entire regis- negative than -2.5V. ter contents to the left one position) to achieve an input span of 12.5mV. Under this condition the The components in Figure 21 are the preferred full span of the converter codes will appear across components for the CPD filter. However, smaller a 12.5mV span. The amount of noise in the con- capacitors can be used with acceptable results. The 2N5087 + or similar 34.8KΩ 2.0KΩ 10 μF NBV 10μF NBV BAT85 + 30.1KΩ BAT85 2.1KΩ -5V -5V Figure 24. Charge Pump Drive Circuit for VD+ = 3 V Figure 25. Alternate NBV Circuits DS317F8 45

CS5521/22/23/24/28 verter stays constant but the number of codes af- 1.10 Getting Started fected is doubled because the code size has been The CS5521/22/23/24/28 have many features. reduced by half. From a software programmer’s perspective, what The converter input ranges are specified with a should be done first? To begin, a 32.768kHz crys- voltage reference of 2.5V. The device can be op- tal takes approximately 500ms to start-up. To ac- erated with the reference tied directly to the +5V commodate for this, it is recommended that a supply. When this is done, the input span of the in- software delay greater than 500ms precede the put ranges is doubled; the 25mV range actually be- processor’s ADC initialization code before any comes a 50mV range. The gain register can be set registers are accessed in the ADC. This delay time to 2.0 (shift contents left one bit) and the input is dependent on the start-up delay of the clock range will be scaled back to 25mV. Since the gain source. If a CMOS clock source with no start-up register can actually be as great as 4-2-22 decimal, delay is being used to drive the ADC, then this de- one could scale the input span on the 25mV range lay is not necessary. to accept an analog full-scale span of about Once the oscillator is started, the following se- 6.25mV. This is useful for ratiometric bridge mea- quence of instructions should be performed to surement of low-level differential outputs. guarantee the converter begins proper operation: The gain register can also be scaled manually to a 1) After power is applied, initialize the serial port value lower than 1.0. It is not recommended to use using the serial port synchronization sequence. the devices with the gain register scaled lower than 2) Write a ‘1’ to the reset bit (RS) of the configu- 0.6. This can enable the converter to accept a ration register to reset the converter. 40mV input signal on the 25mV range when using a voltage reference of 2.5V. Caution though in 3) Read the configuration register to determine if scaling the gain register below 1.0 on the 100mV, the reset valid bit (RV) is set to ‘1’. If the RV 2.5 and 5 volt ranges as the analog signal path into bit is not set, the configuration register should the converter may saturate before the expected be read again. full-scale code output is produced by the converter. 4) When the RV bit has been set to ‘1’, reset the Note that digital gain scaling will directly influence RS bit back to ‘0’ by writing 0x000000 to the the number of digital output codes affected by configuration register. Note that while the RS noise. The effects can be analytically determined bit is set to ‘1’ all other register bits in the ADC by calculating the size of the codes (V/Count) will be reset to their default state, and the RS bit which result from a given gain scaling condition must be set to ‘0’ for normal operation of the and relating the amount of noise in the converter converters. relative to the determined code size. The evalua- Once the RS bit has been set to ‘0’, the ADC is tion board for the converter is a useful tool to aid placed in the command state were it waits for a val- the assessment of noise performance with various id command to execute. The next step is to load the voltage reference values, input range settings, and configuration register and then the channel setup gain register settings. The evaluation board sup- registers with conditions that you have decided. If ports noise analysis through data capture and noise you need to do a factory calibration, perform offset histogram analysis. and gain calibrations for each channel that is to be used. Then off-load the offset and gain register contents into EEPROM. These registers can then 46 DS317F8

CS5521/22/23/24/28 be initialized to these conditions when the instru- the mode you have selected via the configuration ment is used in normal operation. Once calibration register bits. Monitor the SDO pin for a flag that the is ready, input the command to start conversions in data is ready and read conversion data. DS317F8 47

CS5521/22/23/24/28 1.11 PCB Layout The CS5521/22/23/24/28 should be placed entirely plies are used, it is recommended that a diode be over an analog ground plane with both the AGND placed between them (the cathode of the diode and DGND pins of the device connected to the an- should point to VA+). If the digital supply comes alog plane. Place the analog-digital plane split im- up before the analog supply, the ADC may not start mediately adjacent to the digital portion of the chip. up properly. If separate digital (VD+) and analog (VA+) sup- 48 DS317F8

CS5521/22/23/24/28 2. PIN DESCRIPTIONS Analog Ground AGND 1 20 VREF+ Voltage Reference Input Positive Analog Supply VA+ 2 19 VREF- Voltage Reference Input Differential Analog Input AIN1+ 3 CS5521 18 AIN2+ Differential Analog Input Differential Analog Input AIN1- 4 CS5522 17 AIN2- Differential Analog Input Negative Bias Voltage NBV 5 16 A1 Logic Output Logic Output A0 6 15 SCLK Serial Clock Input Charge Pump Drive CPD 7 14 VD+ Positive Digital Supply Serial Data Input SDI 8 13 DGND Digital Ground Chip Select CS 9 12 SDO Serial Data Output Crystal In XIN 10 11 XOUT Crystal Out Analog Ground AGND 1 24 VREF+ Voltage Reference Input Positive Analog Supply VA+ 2 23 VREF- Voltage Reference Input Differential Analog Input AIN1+ 3 CS5523 22 AIN2+ Differential Analog Input Differential Analog Input AIN1- 4 CS5524 21 AIN2- Differential Analog Input Differential Analog Input AIN3+ 5 20 AIN4+ Differential Analog Input Differential Analog Input AIN3- 6 19 AIN4- Differential Analog Input Negative Bias Voltage NBV 7 18 A1 Logic Output Logic Output A0 8 17 SCLK Serial Clock Input Charge Pump Drive CPD 9 16 VD+ Positive Digital Supply Serial Data Input SDI 10 15 DGND Digital Ground Chip Select CS 11 14 SDO Serial Data Output Crystal In XIN 12 13 XOUT Crystal Out Analog Ground AGND 1 24 VREF+ Voltage Reference Input Positive Analog Supply VA+ 2 23 VREF- Voltage Reference Input Single-ended Analog Input AIN1+ 3 22 AIN3+ Single-ended Analog Input CS5528 Single-ended Analog Input AIN2+ 4 21 AIN4+ Single-ended Analog Input Single-ended Analog Input AIN5+ 5 20 AIN7+ Single-ended Analog Input Single-ended Analog Input AIN6+ 6 19 AIN8+ Single-ended Analog Input Negative Bias Voltage NBV 7 18 A1 Logic Output Logic Output A0 8 17 SCLK Serial Clock Input Charge Pump Drive CPD 9 16 VD+ Positive Digital Supply Serial Data Input SDI 10 15 DGND Digital Ground Chip Select CS 11 14 SDO Serial Data Output Crystal In XIN 12 13 XOUT Crystal Out DS317F8 49

CS5521/22/23/24/28 2.1 Clock Generator XIN; XOUT - Crystal In; Crystal Out. A gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock can be supplied into the XIN pin to provide the master clock for the device. 2.2 Control Pins and Serial Data I/O CS - Chip Select. When active low, the port will recognize SCLK. When high the SDO pin will output a high impedance state. CS should be changed when SCLK= 0. SDI - Serial Data Input. SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK. SDO - Serial Data Output. SDO is the serial data output. It will output a high impedance state if CS= 1. SCLK - Serial Clock Input. A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin will recognize clocks only when CS is low. A0, A1 - Logic Outputs. The logic states of A0-A1 mimic the states of the D22/D10-D23/D11 bits of the channel-setup register. Logic Output 0= AGND, and Logic Output 1= VA+. 2.3 Measurement and Reference Inputs AIN1+, AIN1-, AIN2+, AIN2- AIN3+, AIN3-, AIN4+, AIN4- - Differential Analog Input. Differential input pins into the CS5522 and CS5524 devices. AIN1+, AIN2+, AIN3+, AIN4+, AIN5+, AIN6+, AIN7+, AIN8+ - Single-Ended Analog Input. Single-ended input pins into the CS5528. VREF+, VREF- - Voltage Reference Input. Fully differential inputs which establish the voltage reference for the on-chip modulator. 50 DS317F8

CS5521/22/23/24/28 NBV - Negative Bias Voltage. Input pin to supply the negative supply voltage for the 20X gain instrumentation amplifier and coarse/fine charge buffers. May be tied to AGND if AIN+ and AIN- inputs are centered around +2.5V; or it may be tied to a negative supply voltage (-2.1V typical) to allow the amplifier to handle low level signals more negative than ground. When using the CS5528 in either the 25 mV, 55mV or 100 mV range, the analog inputs are expected to be ground referenced; therefore, NBV must be between -1.8 to -2.5 to ensure proper operation. CPD - Charge Pump Drive. Square wave output used to provide energy for the charge pump. 2.4 Power Supply Connections VA+ - Positive Analog Power. Positive analog supply voltage. Nominally +5V. VD+ - Positive Digital Power. Positive digital supply voltage. Nominally +3.0V or +5V. AGND - Analog Ground. Analog Ground. DGND - Digital Ground. Digital Ground. DS317F8 51

CS5521/22/23/24/28 3. SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two endpoints of the A/D Converter transfer function. One endpoint is located 1/2 LSB below the first code transition and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in percent of full-scale. Differential Nonlinearity The deviation of a code's width from the ideal width. Units in LSBs. Full Scale Error The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3/2 LSB]. Units are in LSBs. Unipolar Offset The deviation of the first code transition from the ideal (1/2 LSB above the voltage on the AIN- pin.). When in unipolar mode (U/B bit =1). Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). When in bipolar mode (U/B bit= 0). Units are in LSBs. 52 DS317F8

CS5521/22/23/24/28 4. ORDERING INFORMATION Model Number Bits Channels Linearity Error (Max) Package Temperature Range CS5521-ASZ 16 ±0.003% 2 20-pin 0.2" Plastic SSOP (Lead Free) CS5522-ASZ 24 ±0.0015% CS5523-ASZ 16 ±0.003% -40°C to +85°C 4 CS5524-ASZ 24-pin 0.2" Plastic SSOP (Lead Free) 24 ±0.0015% CS5528-ASZ 8 5. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Package MSL Rating* Peak Reflow Temp Max Floor Life CS5521-ASZ 20-pin 0.2" Plastic SSOP (Lead Free) CS5522-ASZ CS5523-ASZ 3 260 °C 7 Days CS5524-ASZ 24-pin 0.2" Plastic SSOP (Lead Free) CS5528-ASZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS317F8 53

CS5521/22/23/24/28 6. PACKAGE DIMENSION DRAWINGS 20L SSOP PACKAGE DRAWING N D E11 E A2 A ∝ A1 e b2 L END VIEW SEATING PLANE SIDE VIEW 1 2 3 TOP VIEW INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A -- -- 0.084 -- -- 2.13 A1 0.002 0.006 0.010 0.05 0.13 0.25 A2 0.064 0.068 0.074 1.62 1.73 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 D 0.272 0.2834 0.295 6.90 7.20 7.50 1 E 0.291 0.307 0.323 7.40 7.80 8.20 E1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 L 0.025 0.03 0.041 0.63 0.75 1.03 ∝ 0° 4° 8° 0° 4° 8° JEDEC #: MO-150 Controling Dimension is Millimeters. Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25mm from lead tips. 54 DS317F8

CS5521/22/23/24/28 24L SSOP PACKAGE DRAWING N D E11 E A2 A ∝ A1 e b2 L END VIEW SEATING PLANE SIDE VIEW 1 2 3 TOP VIEW INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A -- -- 0.084 -- -- 2.13 A1 0.002 0.006 0.010 0.05 0.13 0.25 A2 0.064 0.068 0.074 1.62 1.73 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 D 0.311 0.323 0.335 7.90 8.20 8.50 1 E 0.291 0.307 0.323 7.40 7.80 8.20 E1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 L 0.025 0.03 0.041 0.63 0.75 1.03 ∝ 0° 4° 8° 0° 4° 8° JEDEC #: MO-150 Controling Dimension is Millimeters. Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25mm from lead tips. DS317F8 55

CS5521/22/23/24/28 7. REVISION HISTORY Revision Date Changes F8 JUL 2009 Leaded (Pb) and PDIP-packaged devices removed from ordering information. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUS- TOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. 56 DS317F8

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: C irrus Logic: CS5521-ASZ CS5521-ASZR CS5522-ASZ CS5522-ASZR CS5523-ASZ CS5523-ASZR CS5524-ASZ CS5524- ASZR CS5528-ASZ CS5528-ASZR