Draft CS5343/4 3/10/15 98 dB, 96 kHz, Multi-Bit Audio A/D Converter Features General Description  Advanced Multi-Bit  Architecture The CS5343/4 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analog-  24-bit Conversion to-digital conversion, and anti-alias filtering, generating  Supports Audio Sample Rates Up to 108kHz 24-bit values for both left and right inputs in serial form at sample rates up to 108kHz per channel.  98 dB Dynamic Range at 5 V The CS5343/4 uses a 3rd-order, multi-bit Delta-Sigma  -92 dB THD+N at 5 V modulator followed by a digital filter, which removes the need for an external anti-alias filter.  Low-Latency Digital Filter The CS5343/4 also features a high-impedance sam-  High-Pass Filter to Remove DC Offsets pling network which eliminates costly external  Single +3.3 V or +5 V Power Supply components such as op-amps. The CS5343/4 is available in a 10-pin TSSOP package  Power Consumption < 40 mW at 3.3 V for both Commercial (-40° to +85° C) and Automotive  Master or Slave Operation grades (-40° to +105° C). The CDB5343 Customer Demonstration Board is also available for device evalu-  Slave Mode Speed Auto-Detect ation and implementation suggestions. Please refer to  Master Mode Default Settings the “Ordering Information” on page19 for complete details.  256x or 384x MCLK/LRCK Ratio The CS5343/4 is ideal for audio systems requiring wide  CS5343 Supports I²S Audio Format dynamic range, negligible distortion and low noise, such as set-top boxes, DVD-karaoke players, DVD record-  CS5344 Supports Left-Justified Audio Format ers, A/V receivers, and automotive applications. VA 3.3 V to 5 V High-Z Single-Ended AINL Sampling Low-Latency Auto-detect Master Analog Input HHiigghh--PPaassss Digital Filters MCLK Divider Clock Network FFiilltteerr FILT+ rt Internal o P Slave Mode SCLK Reference al Auto-detect VQ Voltages ri LRCK e S High-Z Single-Ended AINR Sampling Low-Latency SDOUT Analog Input High-Pass Digital Filters Network Filter Copyright  Cirrus Logic, Inc. 2006–2015 MAR '15 http://www.cirrus.com (All Rights Reserved) DS687F5

Draft 3/10/15 CS5343/4 TABLE OF CONTENTS 1. PIN DESCRIPTIONS ..............................................................................................................................3 2. CHARACTERISTICS AND SPECIFICATIONS ......................................................................................4 RECOMMENDED OPERATING CONDITIONS .....................................................................................4 ABSOLUTE MAXIMUM RATINGS .........................................................................................................4 ANALOG CHARACTERISTICS - COMMERCIAL GRADE (-CZZ) .........................................................5 ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE (-DZZ) .........................................................6 DIGITAL FILTER CHARACTERISTICS ................................................................................................7 DC ELECTRICAL CHARACTERISTICS ................................................................................................7 DIGITAL CHARACTERISTICS ...............................................................................................................8 SYSTEM CLOCKING AND SERIAL AUDIO INTERFACE .....................................................................9 3. TYPICAL CONNECTION DIAGRAM ...................................................................................................11 4. APPLICATIONS ...................................................................................................................................12 4.1 Operation as Clock Master or Slave ...............................................................................................12 4.1.1 Slave Mode Operation ...........................................................................................................12 4.1.2 Master Mode Operation .........................................................................................................13 4.1.2.1 Master Mode Speed Selection ...................................................................................13 4.1.3 Master Clock .........................................................................................................................13 4.2 Serial Audio Interface .....................................................................................................................14 4.3 Digital Interface ...............................................................................................................................14 4.4 Analog Connections .......................................................................................................................14 4.4.1 Component Values ................................................................................................................15 4.5 Grounding and Power Supply Decoupling ......................................................................................15 4.6 Synchronization of Multiple Devices ...............................................................................................16 5. FILTER PLOTS - ALL SPEED MODES ...............................................................................................16 6. PARAMETER DEFINITIONS ................................................................................................................17 7. PACKAGE DIMENSIONS ....................................................................................................................18 THERMAL CHARACTERISTICS ..........................................................................................................18 8. ORDERING INFORMATION ................................................................................................................19 9. REVISION HISTORY ............................................................................................................................20 2 DS687F5

Draft 3/10/15 CS5343/4 1. PIN DESCRIPTIONS SDOUT 1 10 VA SCLK 2 9 GND LRCK 3 8 AINR MCLK 4 7 VQ FILT+ 5 6 AINL Pin Name Pin # Pin Description Serial Audio Data Output (Output) - Output for two’s complement serial audio data. Also selects Master SDOUT 1 or Slave Mode; See Section 4.1 on page 12 for details. SCLK 2 Serial Clock (Input/Output) - Serial clock for the serial audio interface. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the LRCK 3 serial audio data line. MCLK 4 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. FILT+ 5 Positive Voltage Reference (Output) - Positive reference voltage for the internal samplingcircuits. AINL 6 Analog Input (Input) - The full-scale analog input level is specified in the Analog Characteristics specifi- AINR 8 cation table. VQ 7 Quiescent Voltage (Output) - Filter connection for the internal quiescent referencevoltage. GND 9 Ground (Input) - Ground reference. Must be connected to analog ground. VA 10 Power (Input) - Positive power supply for the digital and analog sections. DS687F5 3

Draft 3/10/15 CS5343/4 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0V, all voltages with respect to GND. Parameter Symbol Min Typ Max Unit Power Supplies 3.1 3.3 3.5 V VA 4.75 5.0 5.25 V Ambient Operating Temperature Commercial (-CZZ) T -40 - 85 °C AC Automotive (-DZZ) T -40 - 105 °C AD ABSOLUTE MAXIMUM RATINGS GND = 0 V, all voltages with respect to GND. (Note 1) Parameter Symbol Min Max Unit DC Power Supplies VA -0.3 +6.0 V Input Current (Note 2) I -10 10 mA in Input Voltage (Note 3) V -0.7 VA+0.7 V IN Ambient Operating Temperature (Power Applied) T -50 +115 C A Storage Temperature T -65 +150 C stg Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transient currents of up to ±100mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current. 4 DS687F5

Draft 3/10/15 CS5343/4 ANALOG CHARACTERISTICS - COMMERCIAL GRADE (-CZZ) Test conditions (unless otherwise specified): T = 25C; Input test signal is a 997Hz sine wave through recom- A mended inputs as seen in Figure 6 on page 14; source impedance less than or equal to 2.5 k; valid with FILT+ and VQ components as shown in Figure 3 on page 11; measurement bandwidth is 10 Hz to 20 kHz; Fs=48kHz or 96kHz. Dynamic Performance for Commercial Grade VA = 3.3 V VA = 5.0 V Symbol Min Typ Max Min Typ Max Unit Dynamic Range A-weighted 91 94 - 95 98 - dB unweighted 88 91 - 92 95 - dB Total Harmonic Distortion + Noise (Note 4) -1dB - -89 -86 - -92 -89 dB THD+N -20dB - -71 - - -75 - dB -60dB - -31 - - -35 - dB Dynamic Performance for Commercial Grade VA=3.3V and VA=5.0V Min Typ Max Unit Interchannel Isolation - 90 - dB DC Accuracy Interchannel Gain Mismatch - - 0.1 dB Gain Error -3 - +3 % Gain Drift - 100 - ppm/°C Analog Input Characteristics Full-scale Input Voltage VA = 3.3V nom 0.560*VA 0.568*VA 0.575*VA Vpp Full-scale Input Voltage VA = 5V nom 0.552*VA 0.559*VA 0.567*VA Vpp Input Impedance - 7.5 - M Notes: 4. Referred to the typical full-scale input voltage DS687F5 5

Draft 3/10/15 CS5343/4 ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE (-DZZ) Test conditions (unless otherwise specified): T = -40C to 85C; Input test signal is a 997Hz sine wave through A recommended inputs as seen in Figure 6 on page 14; source impedance less than or equal to 2.5 k; valid with FILT+ and VQ components as shown in Figure 3 on page 11; measurement bandwidth is 10 Hz to 20 kHz; Fs=48kHz or 96kHz. Dynamic Performance for Automotive Grade VA = 3.1 to 3.5 V VA = 4.75 to 5.25 V Symbol Min Typ Max Min Typ Max Unit Dynamic Range A-weighted 86 94 - 90 98 - dB unweighted 83 91 - 87 95 - dB Total Harmonic Distortion + Noise (Note 5) -1dB - -88 -76 - -91 -84 dB THD+N -20dB - -71 - - -75 - dB -60dB - -31 - - -35 - dB Dynamic Performance for Automotive Grade VA=3.1V to 3.5V and VA=4.75V to 5.25V Min Typ Max Unit Interchannel Isolation - 90 - dB DC Accuracy Interchannel Gain Mismatch - - 0.1 dB Gain Error -3 - +3 % Gain Drift - 100 - ppm/°C Analog Input Characteristics Full-scale Input Voltage VA = 3.1V to 3.5V 0.523*VA 0.567*VA 0.612*VA Vpp Full-scale Input Voltage VA = 4.75V to 5.25V 0.543*VA 0.560*VA 0.573*VA Vpp Input Impedance - 7.5 - M Notes: 5. Referred to the typical full-scale input voltage 6 DS687F5

Draft 3/10/15 CS5343/4 DIGITAL FILTER CHARACTERISTICS Parameter Symbol Min Typ Max Unit All Speed Modes Passband (-0.1 dB) 0 - 0.489 Fs Passband Ripple -0.031 - 0.031 dB Stopband 0.560 - - Fs Stopband Attenuation 60 - - dB Total Group Delay (Fs = Output Sample Rate) t - 12/Fs - s gd High-Pass Filter Characteristics Frequency Response -3.0 dB - 1 - Hz -0.13 dB (Note 6) 20 - Hz Phase Deviation @ 20Hz (Note 6) - 10 - Deg Passband Ripple - - 0 dB Notes: 6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. DC ELECTRICAL CHARACTERISTICS GND = 0 V, all voltages with respect to 0V. MCLK=12.288 MHz; Master Mode. VA = 3.3 V VA = 5.0 V Parameter Symbol Min Typ Max Min Typ Max Unit Power Supply Current (Normal Operation) I - 11 15 - 12 17 mA A Power Supply Current (Power-Down Mode) (Note 7) I - 10 - - 40 - uA A Power Consumption (Normal Operation) - - 36 50 - 60 85 mW (Power-Down Mode) (Note 7) - - <1 - - <1 - mW Parameter Symbol Min Typ Max Unit Power Supply Rejection Ratio (1 kHz) (Note 8) PSRR - 65 - dB V Nominal Voltage - 0.44xVA - V Q Output Impedance - 25 - k Filt+ Nominal Voltage - VA - V Output Impedance - 220 - k Maximum allowable DC current source/sink - 2.5 - uA Notes: 7. Device enters power-down mode when MCLK is held static. 8. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram. DS687F5 7

Draft 3/10/15 CS5343/4 DIGITAL CHARACTERISTICS Parameter Symbol Min Typ Max Units High-Level Input Voltage (% of VA) V 60 - - % IH Low-Level Input Voltage (% of VA) V - - 30 % IL High-Level Output Voltage at I = 500 A (% of VA) V 70 - - % o OH Low-Level Output Voltage at I =500 A (% of VA) V - - 15 % o OL Input Leakage Current I -10 - 10 A in 8 DS687F5

Draft 3/10/15 CS5343/4 SYSTEM CLOCKING AND SERIAL AUDIO INTERFACE Logic “0” = GND = 0 V; Logic “1” = VA, C = 20 pF. L Parameter Symbol Min Typ Max Unit Master Mode MCLK Period (Double-Speed, 384x Mode) t 24 - 30 ns clkw (Double-Speed, 192x Mode) 48 - 60 ns (Double-Speed, 256x Mode) 36 - 45 ns (Double-Speed, 128x Mode) 72 - 90 ns (Single-Speed, 768x Mode) 24 - 30 ns (Single-Speed, 384x Mode) 48 - 60 ns (Single-Speed, 384x Mode) 108 - 651 ns (Single-Speed, 512x Mode) 36 - 45 ns (Single-Speed, 256x Mode) 72 - 90 ns (Single-Speed, 256x Mode) 162 - 977 ns MCLK Duty Cycle 40 50 60 % Output Sample Rate (Single-Speed) 4 - 24 kHz (Single-Speed) Fs 43 - 54 kHz (Double-Speed) 86 - 108 kHz LRCK Duty Cycle - 50 - % SCLK Duty Cycle - 50 - % SDOUT valid before SCLK rising t 10 - - ns stp SDOUT valid after SCLK rising t 40 - - ns hld SCLK falling to LRCK edge t -20 - 20 ns slrd Slave Mode MCLK Period (Double-Speed, 384x Mode) t 24 - 30 ns clkw (Double-Speed, 192x Mode) 48 - 60 ns (Double-Speed, 256x Mode) 36 - 45 ns (Double-Speed, 128x Mode) 72 - 90 ns (Single-Speed, 768x Mode) 24 - 325 ns (Single-Speed, 384x Mode) 48 - 651 ns (Single-Speed, 512x Mode) 36 - 488 ns (Single-Speed, 256x Mode) 72 - 976 ns MCLK Duty Cycle 40 50 60 % Input Sample Rate (Single-Speed) 4 - 54 kHz Fs (Double-Speed) 86 - 108 kHz LRCK Duty Cycle 40 50 60 % SCLK Period t 1 - - ns sclkw ------------------ 64Fs SCLK Duty Cycle 45 50 55 % SDOUT valid before SCLK rising t 10 - - ns stp SDOUT valid after SCLK rising t 40 - - ns hld SCLK falling to LRCK edge t -20 - 20 ns slrd DS687F5 9

Draft 3/10/15 CS5343/4 t slrd LRCK t sclkw SCLK SDOUT MSB MSB-1 t t stp hld Figure 1. CS5343 I²S Serial Audio Interface t slrd LRCK t sclkw SCLK SDOUT MSB MSB-1 t t stp hld Figure 2. CS5344 Left-Justified Serial Audio Interface 10 DS687F5

Draft 3/10/15 CS5343/4 3. TYPICAL CONNECTION DIAGRAM 3.3 V to 5 V 0.1 µF 1 µF VA or 10 GND VA VA 5 FILT+ 1 2 2    CS5343/4 k k k 0 0 0 1 µF 0.1 µF 1 1 1 9 GND 1 µF 0.1 µF SDOUT 1 7 VQ SCLK Audio 2 Processor/ LRCK System 3 6 AINL Clocks Analog Input MCLK 4 Conditioning See Figure 6 on 1 Pull-up to VA for Master Mode page 14 Pull-down to GND for Slave Mode AINR 8 2 Optional pull-up resistor for config- uring clocks in Master Mode as described in the “Master Mode Speed Selection” section on page13 Figure 3. Typical Connection Diagram DS687F5 11

Draft 3/10/15 CS5343/4 4. APPLICATIONS 4.1 Operation as Clock Master or Slave The CS5343/4 supports operation as either a clock master or slave. As a clock master, the left/right and serial clocks are synchronously generated on-chip and output on the LRCK and SCLK pins, respectively. As a clock slave, the LRCK and SCLK pins are always inputs and require external generation of the left/right and serial clocks. The selection of clock master or slave is made via a 10 k pull-up resistor from SDOUT to VA for Master Mode selection or via a 10 kpull-down resistor from SDOUT to GND for Slave Mode se- lection, as shown in Table1. Mode Selection Master Mode 10 k pull-up resistor from SDOUT to VA Slave Mode 10 kpull-down resistor from SDOUT to GND Table 1. Master/Slave Mode Selection 4.1.1 Slave Mode Operation A unique feature of the CS5343/4 is the automatic selection of either Single- or Double-Speed Mode when acting as a clock slave. The auto-mode selection feature supports all standard audio sample rates from 4 to 108kHz. Please refer to Table2 for supported sample rate ranges in Slave Mode. MCLK/LRCK SCLK/LRCK Speed Mode Input Sample Rate Range (kHz) Ratio Ratio 256x 64 4 - 54 512x 64 4 - 54 Single-Speed Mode 384x 48, 64 4 - 54 768x 48, 64 4 - 54 128x 64 86 - 108 256x 64 86 - 108 Double-Speed Mode 192x 48, 64 86 - 108 384x 48, 64 86 - 108 Table 2. Speed Modes and the Associated Sample Rates (Fs) in Slave Mode 12 DS687F5

Draft 3/10/15 CS5343/4 4.1.2 Master Mode Operation As clock Master, the CS5343/4 generates LRCK and SCLK synchronously on-chip. Table3 shows the available sample rates and associated clock ratios in Master Mode. MCLK/LRCK SCLK/LRCK Speed Mode Input Sample Rate Range (kHz) Ratio Ratio 256x 64 4 - 24, 43 - 54 512x 64 43 - 54 Single-Speed Mode 384x 64 4 - 24, 43 - 54 768x 64 43 - 54 128x 64 86 - 108 256x 64 86 - 108 Double-Speed Mode 192x 64 86 - 108 384x 64 86 - 108 Table 3. Speed Modes and the Associated Sample Rates (Fs) in Master Mode 4.1.2.1 Master Mode Speed Selection During power-up in Master Mode, the LRCK and SCLK pins are inputs to configure speed mode and the output clock ratio. The LRCK pin is pulled low internally to select Single-Speed Mode by default, but Dou- ble-Speed Mode is accessed with a 10 k pull-up resistor from LRCK to VA as shown in Table4. Simi- larly, the SCLK pin is internally pulled-low by default to select a 256x/512x MCLK/LRCK ratio, but a MCLK/LRCK ratio of 348x/768x is accessed with a 10 k pull-up resistor from SCLK to VA as shown in Table4. Following the power-up routine, the LRCK and SCLK pins become clock outputs. Pin Resistor Option Clock Configuration Internal Pull-Down to GND (100 k) Single-Speed Mode (default) LRCK External Pull-Up to VA (10 k) Double-Speed Mode Internal Pull-Down to GND (100 k) 128x/256x/512x MCLK/LRCK (default) SCLK External Pull-Up to VA (10 k) 192x/384x/768x MCLK/LRCK Table 4. Speed Mode Selection in Master Mode 4.1.3 Master Clock The CS5343/4 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters. There is an internal automatic MCLK divider which is activated based on the input frequency of MCLK. This divider selection allows the high and low MCLK speeds in a given speed mode (i.e. 256x and 512x in SSM). Table4 lists some common audio output sample rates and the required MCLK frequency. Master and Slave Mode MCLK(MHz) MCLK (MHz) Sample Rate (kHz) Speed Mode 256x 512x 384x 768x 32 (*Slave Mode Only) SSM *8.192 *16.384 *12.288 *24.576 44.1 SSM 11.289 22.579 16.934 33.868 48 SSM 12.288 24.576 18.432 36.864 MCLK(MHz) MCLK (MHz) Sample Rate (kHz) Speed Mode 128x 256x 192x 384x 88.2 DSM 11.289 22.579 16.934 33.868 96 DSM 12.288 24.576 18.432 36.864 Table 5. Common MCLK Frequencies in Master and Slave Modes DS687F5 13

Draft 3/10/15 CS5343/4 4.2 Serial Audio Interface The CS5343 output is serial data in I²S audio format and the CS5344 output is serial data in Left-Justified audio format. Figures4 and 5 show the I²S and Left-Justified data relative to SCLK and LRCK. Additionally, Figures1 and 2 display more information on the required timing for the serial audio interface format. For an overview of serial audio interface formats, please refer to Cirrus Application Note AN282. LRCK LeftChannel RightChannel SCLK SDATA 23 22 9 8 7 6 5 4 3 2 1 0 23 22 9 8 7 6 5 4 3 2 1 0 23 22 Figure 4. CS5343 I²S Serial Audio Interface LRCK LeftChannel RightChannel SCLK SDATA 23 22 9 8 7 6 5 4 3 2 1 0 23 22 9 8 7 6 5 4 3 2 1 0 23 22 Figure 5. CS5344 Left-Justified Serial Audio Interface 4.3 Digital Interface VA supplies power to both the analog and digital sections of the ADC, and also powers the serial port. Con- sequently, the digital interface logic level must equal VA to within the limits specified under “Digital Charac- teristics” on page8. 4.4 Analog Connections The analog modulator samples the input signal at half of the internal master clock rate, or 6.144MHz when MCLK = 12.288 MHz. The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are multiples of the input sampling frequency (n6.144MHz), where n=0,1,2,... Refer to Figure6 which shows the recommended topology of the analog input network. The ex- ternal shunt capacitor and internal input impedance form a single-pole RC filter to provide the appropriate filtering of noise at the modulator sampling frequency. Additionally, the 180 pF capacitor acts as a charge source for the internal sampling circuits. Capacitors of NPO or other high-quality dielectric will produce the best results while capacitors with a large voltage coefficient (such as general-purpose ceramics) can de- grade signal linearity. CS5343/4 R1 1 µF Input AIN R2 180pF C0G Figure 6. CS5343/4 Analog Input Network 14 DS687F5

Draft 3/10/15 CS5343/4 4.4.1 Component Values Three parameters determine the values of resistors R1 and R2 as shown in Figure6: source impedance, attenuation, and input impedance. Table6 shows the design equation used to determine these values. • Source Impedance: Source impedance is defined as the impedance as seen from the ADC looking back into the signal network. The ADC achieves optimal THD+N performance with a source imped- ance less than or equal to 2.5 k. • Attenuation: The required attenuation factor depends on the magnitude of the input signal. The full- scale input voltage is specified under “Analog Characteristics - Commercial Grade (-CZZ)” on page5. The user should select values for R1 and R2 such that the magnitude of the incoming signal multiplied by the attenuation factor is less than or equal to the full-scale input voltage of the device. • Input Impedance: Input impedance is the impedance from the signal source to the ADC analog input pins, including the ADC. Because the ADC’s input impedance (see the “Analog Characteristics - Com- mercial Grade (-CZZ)” table on page5) is several orders of magnitude larger than the resistor values typically used for the input attenuator, its contribution can be neglected when calculating the input im- pedance. Table6 shows the input parameters and the associated design equations for the input at- tenuator. R1R2 Source Impedance ------------------------- R1+R2 R2 Attenuation Factor ------------------------- R1+R2 Input Impedance R1+R2 Table 6. Analog Input Design Parameters Figure7 illustrates an example configuration using two 4.99 kresistors in place of R1 and R2. Based on the discussion above, this circuit provides an optimal interface for both the ADC and the signal source. First, consumer equipment frequently requires an input impedance of 10 kwhich the 4.99 kresistors provide. Second, this circuit will attenuate a typical line level voltage, 2 Vrms, to the full-scale input of the ADC, 1 Vrms when VA = 5 V. Finally, at 2.5 kthe source impedance optimizes analog performance of the ADC. CS5343/4 4.99 k 1 µF Input AIN 4.99 k 180pF C0G Figure 7. CS5343/4 Example Analog Input Network 4.5 Grounding and Power Supply Decoupling As with any high-resolution converter, designing with the CS5343/4 requires careful attention to power sup- ply and grounding arrangements if its potential performance is to be realized. Figure3 shows the recom- mended power arrangements, with VA connected to a clean supply. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the mod- ulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1µF, must be positioned to minimize the electrical path from FILT+ to GND. The CDB5343 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs. DS687F5 15

Draft 3/10/15 CS5343/4 4.6 Synchronization of Multiple Devices In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK, SCLK, and LRCK signals must be the same for all of the CS5343 and CS5344 devices in the system. 5. FILTER PLOTS - ALL SPEED MODES 0 0 -10 -10 -20 -20 -30 -30 B) -40 B) -40 d -50 d -50 e ( -60 e ( -60 d -70 d -70 u u plit --9800 plit --9800 m m A -100 A -100 -110 -110 -120 -120 -130 -130 -140 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Frequency (normalized to Fs) Frequency (normalized to Fs) Figure 8. Stopband Rejection Figure 9. Transition Band 0 0.10 -1 0.08 -2 0.06 B) -3 B) 0.04 d d e ( -4 e ( 0.02 d -5 d 0.00 u u plit -6 plit -0.02 m m -7 -0.04 A A -8 -0.06 -9 -0.08 -10 -0.10 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (normalized to Fs) Frequency (normalized to Fs) Figure 10. Transition Band (Detail) Figure 11. Passband Ripple 16 DS687F5

Draft 3/10/15 CS5343/4 6. PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measure- ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Measured at -1 and -20dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10Hz to 20kHz relative to the amplitude response at 1kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci- bels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog input for a full-scale digital output. Gain Drift The change in gain value with temperature. Units in ppm/°C. DS687F5 17

Draft 3/10/15 CS5343/4 7. PACKAGE DIMENSIONS 10LD TSSOP (3 mm BODY) PACKAGE DRAWING (Note 1) N D E11 c E A2 A  A1 e b L END VIEW SEATING SIDE VIEW PLANE L1 1 2 3 TOP VIEW INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A -- -- 0.0433 -- -- 1.10 A1 0 -- 0.0059 0 -- 0.15 A2 0.0295 -- 0.0374 0.75 -- 0.95 b 0.0059 -- 0.0118 0.15 -- 0.30 4, 5 c 0.0031 -- 0.0091 0.08 -- 0.23 D -- 0.1181 BSC -- -- 3.00 BSC -- 2 E -- 0.1929 BSC -- -- 4.90 BSC -- E1 -- 0.1181 BSC -- -- 3.00 BSC -- 3 e -- 0.0197 BSC -- -- 0.50 BSC -- L 0.0157 0.0236 0.0315 0.40 0.60 0.80 L1 -- 0.0374 REF -- -- 0.95 REF -- µ 0° -- 8° 0° -- 8° Controlling Dimension is Millimeters Notes: 1. Reference document: JEDEC MO-187 2. D does not include mold flash or protrusions, which is 0.15 mm max. per side. 3. E1 does not include inter-lead flash or protrusions, which is 0.15 mm max per side. 4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max. 5. Exceptions to JEDEC dimension. THERMAL CHARACTERISTICS Parameter Symbol Min Typ Max Unit Allowable Junction Temperature T - - 135 C J Junction to Ambient Thermal Impedance (4-layer PCB)  - 100 - C/W JA-4 (2-layer PCB) JA-2 - 170 - C/W 18 DS687F5

Draft 3/10/15 CS5343/4 8. ORDERING INFORMATION Product Description Package Pb-Free Grade Temp Range Container Order # 98 dB, Multi-Bit Audio Rail CS5343-CZZ CS5343 A/D Converter, 10-TSSOP Yes Commercial -40° to +85° C Tape & Reel CS5343-CZZR I²S Audio Format 98 dB, Multi-Bit Audio Rail CS5343-DZZ CS5343 A/D Converter, 10-TSSOP Yes Automotive -40° to +105° C Tape & Reel CS5343-DZZR I²S Audio Format 98 dB, Multi-Bit Audio Rail CS5344-CZZ CS5344 A/D Converter, 10-TSSOP Yes Commercial -40° to +85° C Tape & Reel CS5344-CZZR Left-Justified Audio Format 98 dB, Multi-Bit Audio Rail CS5344-DZZ CS5344 A/D Converter, 10-TSSOP Yes Automotive -40° to +105° C Tape & Reel CS5344-DZZR Left-Justified Audio Format CDB5343 CS5343 Evaluation Board - No - - - CDB5343 DS687F5 19

Draft 3/10/15 CS5343/4 9. REVISION HISTORY Release Changes Updated “Recommended Operating Conditions” on page4 Updated specifications and limits for “Analog Characteristics - Commercial Grade (-CZZ)” on page5 Updated specifications and limits for “Analog Characteristics - Automotive Grade (-DZZ)” on page6 F1 Corrected “Power Supply Current (Normal Operation)” on page7 Increased specification for Slave-Mode “SDOUT valid after SCLK rising” on page9 Corrected Section 4.1.2.1 on page 13 Updated Section 4.1.3 on page 13 Removed Fs < 43kHz from master mode operation: -Updated master mode timing specifications in the “System Clocking and Serial Audio Interface” on page9 F2 -Updated Input Sample Rate Range in Table3 on page13 -Added note for “slave mode only” for Fs=32kHz in Table5 on page13. Updated Passband Ripple, Stopband Attenuation and Total Group Delay specs in “Digital Filter Characteristics” F3 on page7. Corrected a typographical error in Table5, “Common MCLK Frequencies in Master and Slave Modes,” on F4 page13. Changed 8.912 MHz to 8.192 MHz. Updated master mode MCLK period and output sample rate in “System Clocking and Serial Audio Interface” on page9. F5 Updated input sample rate range in “Master Mode Operation” on page13. Updated legal text. 20 DS687F5

Draft 3/10/15 CS5343/4 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (collectively either "Cirrus" or "Cirrus Logic") are sold subject to Cirrus's terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Cirrus to verify that the information is current and complete. Testing and other quality control techniques are utilized to the extent Cirrus deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Cirrus products. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied, under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Any provision or publication of any third party's products or services does not constitute Cirrus's approval, license, warranty or endorsement thereof. Cirrus gives consent for copies to be made of the information contained herein only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus, and only if the reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice). This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. This document and its information is provided "AS IS" without warranty of any kind (express or implied). All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design and SoundClear are among the trademarks of Cirrus. Other brand and product names may be trademarks or service marks of their respective owners. Copyright © 2006–2015 Cirrus Logic, Inc. All rights reserved. DS687F5 21

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