CS470xx CS470xx Data Sheet Features The CS470xx family is a new generation of audio system-on-a-chip (ASOC) processors targeted at high  Cost-effective, High-performance 32-bit DSP fidelity, cost sensitive designs. Derived from the highly successful CS48500 32-bit fixed-point audio enhancement  300,000,000 MAC/S (multiply accumulates per second) processor family, the CS470xx further simplifies system  Dual MAC cycles per clock design and reduces total system cost by integrating the S/  72-bit accumulators are the highest precision in the PDIF Rx, S/PDIF Tx, analog inputs, analog outputs, and industry SRCs. For example, a hardware SRC can down-sample a 192 kHz S/PDIF stream to a lower Fs to reduce memory  32K x 32-bit SRAM with three 2K blocks assignable to and MIPS requirements for processing. This integration either Y data or program memory effectively reduces the chip count from 3 to 1, which allows  Integrated DAC and ADC Functionality smaller, less expensive board designs.  8† Channels of 24-bit DAC output: 108dB DR, –98 dB Target applications include: THD+N  Automotive head units and outboard amplifiers  4† Channels of 24-bit ADC input: 105dB DR, –98 dB THD+N  Automotive processors and automotive integration hubs  Integrated 5:1 analog mux feeds one stereo ADC  Digital TV  Configurable Serial Audio Inputs and Outputs  MP3 docking stations  Integrated 192 kHz S/PDIF Rx  AVR and DVD RX  Integrated 192 kHz S/PDIF Tx  DSP controlled speakers (subwoofers, sound bars)  Supports 32-bit serial data @ 192 kHz The CS470xx is programmed using the simple yet powerful  Supports 32-bit audio sample I/O between DSP chips Cirrus proprietary DSP Composer™ GUI development and pre-production tuning tool. Processing chains can be  TDM I/O modes designed using a drag-and-drop interface to place/utilize  Supports Different Sample Rates (Fs) functional macro audio DSP primitives and custom audio filtering blocks. The end result is a software image that is  Three integrated hardware SRC blocks downloaded to the DSP via serial control port.  Output can be master or slave The Cirrus Framework™ programming environment offers  Supports dual-domain Fs on S/PDIF vs. I²S inputs Assembly and C language compilers and other software  DSP Tool Set with Private Keys Protect Customer IP development tools for porting existing code to the CS470xx family platform.  Integrated Clock Manager/PLL The CS470xx is available in a 100-pin LQFP package with  Flexibility to operate from internal PLL, external crystal, exposed pad for better thermal characteristics. Both external oscillator Commercial (0°C to +70°C) and Automotive (–40°C to  Input Fs Auto Detection w/ µC Acknowledgement +85°C) temperature grades.  Host Control and Boot via I²C™ or SPI™ Serial Interface Ordering Information:  Configurable GPIOs and External Interrupt Input See Section6 for ordering information.  1.8V Core and a 3.3V I/O that is tolerant to 5V input  Low-power Mode “†” features differ on CS47024, CS47028, or CS47048. See Table3-1. Copyright  Cirrus Logic, Inc. 2012 DS787PP9 http://www.cirrus.com (All Rights Reserved) JUL '12

ADC’s & DAC’s operate in Single ended or DBC Clock PLL Timers GPIO Differential mode (I2C Slave) Manager DAC0 DAC1 I2S / DAC2 S S/PDIF R DAC3 8ch C DAC4 x4 2 DAC5 Coyote 32-bit Core I2S DAC6 text in the CS47048 DSP DAC7 S SRC3 has 8 x8 ADC0/1 R independent Channels S DMA ROM Bus 8ch C for In or Out SOtne rAenoa Ilnopgu itns R 4ch Bus X ral 3 C PIC ry RAM he o p 1 em eri x2 MUX ADC2/3 ROM M ROM P I2S Y P RAM RAM SPI / I2C x2 Control I2S / S/PDIF 32K x 32-bit SRAM with three 2K blocks Assignable to Program or Y Data memory CS47048 Block Diagram DS787PP9 2

Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, Framerwork, and DSP Composer are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. I²C is a trademark of Philips Semiconductor. Dolby, Pro Logic, Dolby Headphone, Virtual Speaker and the double-D symbol are registered trademarks of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories. SRS CircleSurround II technology is incorporated under license from SRS Labs, Inc. The SRS Circle Surround II technology/solution rights incorporated in the Cirrus Logic CS470xx products are owned by SRS Labs, a U.S. Corporation and licensed to Cirrus Logic, Inc. Purchaser of the Cirrus Logic CS470xx products must sign a license for use of the chip and display of the SRS Labs trademarks. Any products incorporating the Cirrus Logic CS470xx products must be sent to SRS Labs for review. SRS CircleSurround II is protected under US and foreign patents issued and/or pending. SRS Circle Surround II, SRS and (O) symbol are trademarks of SRS Labs, Inc. in the United States and selected foreign countries. Neither the purchase of the Cirrus Logic CS470xx products, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any SRS technology/solution. SRS Labs requires all set makers to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual. 3 DS787PP9

1 Documentation Strategy 1 Documentation Strategy The CS470xx Data Sheet describes the CS47048, CS47028, and CS47024 audio processors. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS470xx processors. Table1-1. CS470xx Related Documentation Document Name Description CS470xx Data Sheet This document CS470xx Hardware User’s Manual Guide Includes detailed system design information such as typical connection diagrams, boot-proce- dures, and pin descriptions AN333 - CS470xx Firmware User’s Manual Includes a list of firmware modules available on the CS470xx family platform and detailed firm- ware design information including signal processing flow diagrams and control API information DSP Composer User’s Manual Includes detailed configuration and usage information for the GUI development tool CDB470xx User’s Manual Includes detailed instructions on the use of the CDB470xx development board The scope of the CS470xx Data Sheet is primarily the hardware specifications of the CS470xx family of devices. This includes hardware functionality, characteristic data, pinout, and packaging information. The intended audience for the CS470xx Data Sheet is the system PCB designer, MCU programmer, and the quality control engineer. 2 Overview The CS470xx DSP is designed to provide high-performance post-processing and mixing of analog and digital audio. Dual clock domains are supported when the DAI and SPDIF RX inputs are used together. Integrated sample rate converters (SRCs) allow audio streams with different sample rates to be mixed. The low-power standby preserves battery life for applications that are always on, but not necessarily processing audio, such as automotive audio systems. The CS470xx uses voltage-out DACs and is capable of supporting dual input clock domains through the use of the internal SRCs. The CS470xx is available in a 100-pin LQFP package. Refer to Table3-1 and Table3-2 for the input, output, and firmware configurations for the CS470xx DSP. 2.1 Licensing Licenses are required for any third-party audio processing algorithms provided for the CS470xx. Contact your local Cirrus Logic Sales representative for more information. DS787PP9 4

3 Code Overlays 3 Code Overlays The suite of software available for the CS470xx family consists of an operating system (OS) and a library of overlays. The software components for the CS470xx family include: 1. OS/Kernel—Encompasses all non-audio processing tasks, including loading data from external serial memory, processing host messages, calling audio-processing subroutines, error concealment, etc. 2. Decoder—Any module that performs a compressed audio decode on IEC61937-packed data delivered via S/PDIF Rx or I²S input, such as Dolby Digital (AC3). 3. Matrix-processor—Any Module that performs a matrix decode on PCM data to produce more output channels than input channels (2Æn channels). Examples are Dolby® Pro Logic® IIx and SRS Circle Surround II®. Generally speaking, these modules increase the number of valid channels in the audio I/O buffer. 4. Virtualizer-processor—Any module that encodes PCM data into fewer output channels than input channels (nÆ2 channels) with the effect of providing “phantom” speakers to represent the physical audio channels that were eliminated. Examples are Dolby Headphone® 2 and Dolby® Virtual Speaker® 2. Generally speaking, these modules reduce the number of valid channels in the audio I/O buffer. 5. Post-processors—Any module that processes audio I/O buffer PCM data. Examples are bass management, audio manager, tone control, EQ, delay, customer-specific effects, and any post-processing algorithms available for the CS470xx DSP. The bulk of standard overlays are stored in ROM within the CS470xx, but a small image is required to configure the overlays and boot the DSP. This small image can either be stored in an external serial flash/EEPROM, or downloaded via a host controller through the SPI/I²C serial port. The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a different post-processor is selected, the OS, does not need to be reloaded—only the new post-processor. Table3-1 lists the different configuration options available. Refer to the CS470xx Firmware User’s Manual for the latest listing of application codes and Cirrus Framework™ modules available. See Table3-2, which provides a summary of the available channels for each type of input and output communication mode for members of the CS470xx family of DSPs. 5 DS787PP9

3 Code Overlays Table3-1. CS470xx Device Selection Guide CS47048-CQZ CS47028-CQZ CS47024-CQZ Features CS47048-DQZ CS47028-DQZ CS47024-DQZ Primary Applications • 4-In/8-Out Car Audio • 2-In/8-Out Car Audio • 2-In/4-Out Car Audio • High-end Digital TV • Sound Bar • Digital TV • Dual Source/Dual Zone • DVD Receiver • Portable Audio Docking Station • Portable DVD • DVD Mini / Receiver • Multimedia PC Speakers Package 100-pin LQFP with Exposed Pad DSP Core Cirrus Logic 32-bit Core SRAM 32K x 32-bit SRAM with three 2K blocks x 32-bit SRAM, assignable to either Y data or program memory Integrated DAC and ADC • 2 Channels of ADC input: with inte- • 2 channels of ADC input: with inte- • 2 channels of ADC input: with inte- grated 5:1 analog mux grated 5:1 analog mux grated 5:1 analog mux • 2 additional channels of ADC in- • 8 channels of DAC output • 4 channels of DAC output put: without mux • 8 channels of DAC output Configurable Serial Audio • Integrated 192 kHz S/PDIF Rx, 2 Integrated 192 kHz S/PDIF Tx Inputs/Outputs • I2S support for 32-bit Samples @ 192 kHz • TDM Input modes (Up to 8 channels) • TDM Output modes (Up to 8 channels) Supports Different Fs • Integrated hardware SRC blocks for all ADC and DAC channels Sample Rates • Additional 8-channel hardware SRC block • Dual-domain Fs on inputs (I2S and S/PDIF Rx) • Output can be master or slave Other Features • Integrated Clock Manager/PLL with flexibility to operate from internal PLL, external crystal, external oscillator • Host Control and Boot via SPI/I²C Serial Interface • DSP Tool Set w/ Private Keys Protect Customer IP • Configurable GPIOs and External Interrupts • Hardware Watchdog Timer Table3-2. CS470xx Channel Count S/PDIF In S/PDIF PCM ADC with 5:1 ADC with- DAC Product PCM/TDM In1 TDM Out1 (Stereo Out (Ste- Out Input Mux out Mux Out Pairs) reo Pairs) CS47048 • Up to 5 I2S lines, 2 channels per Up to 8 chan- line or nels 8 2 2 8 1 2 • 1 TDM line, up to 8 channels per line. CS47028 • Up to 5 I2S lines, 2 channels per Up to 8 chan- line or nels 8 2 0 8 1 2 • 1 TDM line, up to 8 channels per line. CS47024 • Up to 5 I2S lines, 2 channels per Up to 8 chan- line or nels 8 2 0 4 1 2 • 1 TDM line, up to 8 channels per line. 1. Contact your Cirrus Logic representative to determine the TDM modes that are supported. The CS470xx can support up to 8 channels per line, but the DSP software provided for the IC can restrict this capability. DS787PP9 6

4 Hardware Functional Description 4 Hardware Functional Description The CS470xx family, which includes the CS47048, CS47028, and CS47024 DSPs, is a true system-on-a-chip that combines a powerful 32-bit DSP engine with analog/digital audio inputs and analog/digital audio outputs. It can be integrated into a complex multi-DSP processing system, or stand alone in an audio product that requires analog-in and analog-out. A top level block diagram for the CS47048, CS47028, and CS47024 products are shown in Fig.4-1, Fig.4-2, and Fig.4-3 respectively. ADC’s & DAC’s operate in Single ended or DBC PLL Clock Timers GPIO Differential mode (I2C Slave) Manager DAC0 DAC1 I2S / S DAC2 S/PDIF R DAC3 8ch C DAC4 x4 2 DAC5 32-bit Core I2S DAC6 text in the CS47048 DSP DAC7 S SRC3 has 8 x8 ADC0/1 R independent Channels S DMA ROM Bus 8ch C for In or Out SOtne rAeon aInlopgu tisn RC 4ch PIC ory Bus X RAM pheral 3 MUX ADC2/3 1 ROM Mem ROM Peri x2 I2S Y P RAM RAM SPI / I2C x2 Control I2S / S/PDIF 32K x 32-bit SRAM with three 2K blocks Assignable to Program or Y Data memory Figure4-1. CS47048 Top-level Block Diagram 7 DS787PP9

4 Hardware Functional Description ADC’s & DAC’s operate in Single ended or DBC PLL Clock Timers GPIO Differential mode (I2C Slave) Manager DAC0 DAC1 I2S / S DAC2 S/PDIF R DAC3 8ch C DAC4 x4 2 DAC5 I2S 32-bit Core DAC6 text in the CS47028 DSP DAC7 S SRC3 has 8 x8 R independent Channels S DMA ROM Bus 8ch C for In or Out SOtne rAeon aInlopgu tisn RC 4ch PIC ory Bus X RAM pheral 3 MUX ADC2/3 1 ROM Mem ROM Peri x2 I2S Y P RAM RAM SPI / I2C x2 Control I2S / S/PDIF 32K x 32-bit SRAM with three 2K blocks Assignable to Program or Y Data memory Figure4-2. CS47028 Top-level Block Diagram ADC’s & DAC’s operate in Single ended or DBC PLL Clock Timers GPIO Differential mode (I2C Slave) Manager I2S / S DAC0 S/PDIF R DAC1 8ch C DAC2 x4 2 DAC3 I2S 32-bit Core text in the CS47024 DSP S SRC3 has 8 x8 R independent Channels S DMA ROM Bus 8ch C for In or Out SOtne rAeon aInlopgu tisn RC 4ch PIC ory Bus X RAM pheral 3 MUX ADC2/3 1 ROM Mem ROM Peri x2 I2S Y P RAM RAM SPI / I2C x2 Control I2S / S/PDIF 32K x 32-bit SRAM with three 2K blocks Assignable to Program or Y Data memory Figure4-3. CS47024 Top-level Block Diagram DS787PP9 8

4.1 Cirrus Logic 32-bit DSP Core 4.1 Cirrus Logic 32-bit DSP Core The CS470xx comes with a Cirrus Logic 32-bit core with separate X and Y data and P code memory spaces. The DSP core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eight 72-bit accumulators, four X-data and four Y-data registers, and 12 index registers. The DSP core is coupled to a flexible 8-channel DMA engine. The DMA engine can move data between peripherals such as the serial control port (SCP), digital audio input (DAI) and digital audio output (DAO), sample rate converters (SRC), analog-to-digital converters (ADC), digital-to-analog converters (DAC), or any DSP core memory, all without the intervention of the DSP. The DMA engine off-loads data move instructions from the DSP core, leaving more MIPS available for signal processing instructions. CS470xx functionality is controlled by application codes that are stored in on-chip ROM or downloaded to the CS470xx from a host controller or external serial flash/EEPROM. Users can develop applications using the DSP Composer™ tool to create the processing chain and then compile the image into a series of commands that are sent to the CS470xx through the SCP. The processing application can either load modules (post-processors) from the DSPs on-chip ROM, or custom firmware can be downloaded through the SCP. The CS470xx is suitable for a variety of audio post-processing applications where sound quality via sound enhancement and speaker/cabinet tuning is required to achieve the sound quality consumers expect. Examples of such applications include automotive head-ends, automotive amplifiers, docking stations, sound bars, subwoofers, and boom boxes. 4.2 DSP Memory The DSP core has its own on-chip data and program RAM and ROM and does not require external memory for post-processing applications. The Y-RAM and P-RAM share a single block of memory that includes three 2K word blocks (32 bits/word) that are assignable to either Y-RAM or P-RAM as shown in Table 4. Table4-1. Memory Configurations for the C470xx P-RAM X-RAM Y-RAM 14K words 10K words 8K words 12K words 10K words 10K words 10K words 10K words 12K words 8K words 10K words 14K words 4.2.1 DMA Controller The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment controls. The service intervals for each DMA channel, as well as up to 6 interrupt events, are programmable. 4.3 On-chip DSP Peripherals 4.3.1 Analog to Digital Converter Port (ADC) The ADCs in the CS470xx devices feature dynamic range performance in excess of 100 dB. See Section5.16 for more details on CS470xx ADC performance. The CS47024 and CS47028 devices support up to 2 simultaneous channels of analog-to-digital conversion with the input source selectable using an integrated 5:1 stereo analog mux (analog inputs AIN_2A/B through AIN_6A/B). The CS47048 device adds a second pair of ADCs that are directly connected to input pins AIN_1A/B providing a total of 4 simultaneous channels of analog-to-digital conversion. This feature gives the CS47048 the ability to select from a total of six stereo pairs of analog input. A single programmable bit selects single-ended or differential mode signals for all inputs. The conversions are performed with Fs=96 kHz. 9 DS787PP9

4.3 On-chip DSP Peripherals 4.3.2 Digital to Analog Converter Port (DAC) The DACs in the CS470xx devices feature dynamic range performance in excess of 100 dB. See Section5.17 for more details on CS470xx DAC performance. The CS47024 device supports four simultaneous channels of digital-to-analog conversion. The CS47028 and CS47048 devices provide eight simultaneous channels of digital-to-analog conversion. The DACs have voltage mode outputs that can be connected either as single-ended or differential signals. The conversions are performed with Fs=96 kHz. 4.3.3 Digital Audio Input Port (DAI) The input capabilities for each version of the CS470xx are summarized in Table3-1 and Table3-2. Up to five DAI ports are available. Two of the DAI ports can be programmed to implement other functions. If the SPI mode is used, the DAI_DATA4 pin becomes the SCP_CS input. The integrated S/PDIF receiver can be used to take over the DAI_DATA3 pin. The DAI port PCM inputs have a single slave-only clock domain. The S/PDIF receiver, if used, is a separate clock domain. The output of the S/PDIF Rx can then be converted through one of the internal SRC blocks to synchronize with the PCM input. The sample rate of the input clock domains can be determined automatically by the DSP, off-loading the task of monitoring the S/PDIF Rx from the host. A time-stamping feature provides the ability to also sample-rate convert the input data via software.The DAI port supports PCM format with word lengths up to 32 bits and sample rates as high as 192 kHz. The DAI also supports a time division multiplexed (TDM) mode that packs up to 10 PCM audio channels on a single data line. 4.3.4 S/PDIF RX Input Port (DAI) One of the PCM pins of the DAI can also be used as a DC-coupled, TTL-level S/PDIF Rx input capable of receiving and demodulating bi-phase encoded S/PDIF signals with Fs < 192 kHz. 4.3.5 Digital Audio Output Port (DAO) DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as 192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a clock slave if an external MCLK or SCLK/ LRCLK source is available. The DAO also supports a time division multiplexed (TDM) mode, that packs up to 8 channels of PCM audio on a single data line. 4.3.6 S/PDIF TX Output Port (DAO) Two of the serial audio pins can be re-configured as S/PDIF TX pins that drive a bi-phase encoded S/PDIF signal (data with embedded clock on a single line). 4.3.7 Sample Rate Converters (SRC) All CS470xx devices have at least two internal hardware SRC modules. One is directly associated with the ADCs and normally serves to convert data from the 96 kHz sampling rate of the ADCs to another Fs appropriate for mixing with other audio in the system. The other SRC module is directly associated with the DACs and normally serves to convert data from the DSP into the 96 kHz sample rate needed by the DACs. The CS47024, CS47028, and CS47048 devices have an additional stand-alone 8-channel SRC module. This SRC module can be used to make independent input clock domains synchronous (different Fs on PCM input and S/PDIF Rx). DS787PP9 10

4.4 DSP I/O Description 4.3.8 Serial Control Port (I2C or SPI) The on-chip serial control port is capable of operating as master or slave in either SPI or I2C modes. Master/Slave operation is chosen by mode select pins when the CS470xx comes out of reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock speed must always be < (DSP Core Frequency/2)). The CS470xx serial control port also includes a pin for flow control of the communications interface (SCP_BSY) and a pin to indicate when the DSP has a message for the host (SCP_IRQ). 4.3.9 GPIO Many of the CS470xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high. 4.3.10 PLL-based Clock Generator The low-jitter PLL generates integer or fractional multiples of a reference frequency, which is used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS470xx defaults to running from the external reference frequency and is switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external flash or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1. 4.3.11 Hardware Watchdog Timer The CS470xx has an integrated watchdog timer that acts as a “health” monitor for the DSP. The watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This peripheral ensures that the CS470xx resets itself in the event of a temporary system failure. In stand-alone mode (where there is no host MCU), the DSP reboots from external flash. In slave mode (where the host MCU is present), a GPIO is used to signal the host that the watchdog has expired and the DSP should be rebooted and re-configured. 4.4 DSP I/O Description 4.4.1 Multiplexed Pins Many of the CS470xx pins are multifunctional. For details on pin functionality, see Section 10.5, “Pin Assignments”, in the CS470xx Hardware User’s Manual. 4.4.2 Termination Requirements Open-drain pins on the CS470xx must be pulled high for proper operation. See the CS470xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. Mode select pins on CS470xx are used to select the boot mode on the rising edge from reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS470xx Hardware User’s Manual. 4.4.3 Pads The CS470xx Digital I/Os operate from the 3.3 V supply and are 5 V tolerant. 4.5 Application Code Security The external program code can be encrypted by the programmer to protect any intellectual property it contains. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. Contact your local Cirrus representative for details. 11 DS787PP9

5 Characteristics and Specifications 5 Characteristics and Specifications Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following conditions: T = 25°C, VDD = 1.8 V, VDDIO = VDDA = 3.3 V, GND = GNDIO = GNDA = 0 V. 5.1 Absolute Maximum Ratings (GND = GNDIO = GNDA = 0V; all voltages with respect to 0V) Parameter Symbol Min Max Unit DC power supplies: Core supply VDD –0.3 2.0 V Analog supply VDDA –0.3 3.6 V I/O supply VDDIO –0.3 3.6 V |VDDA–VDDIO| — 0.3 V Input pin current, any pin except supplies I — ±10 mA in Input voltage on PLL_REF_RES V –0.3 3.6 V filt Input voltage on digital I/O pins V –0.3 5.0 V inio Analog Input Voltage V AGND–0.7 VA+0.7 V in Storage temperature T –65 150 °C stg WARNING: Operation at or beyond these limits can result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 5.2 Recommended Operating Conditions (GND = GNDIO = GNDA = 0V; all voltages with respect to 0V) Parameter Symbol Min Typ Max Unit DC power supplies: Core supply VDD 1.71 1.8 1.89 V Analog supply VDDA 3.13 3.3 3.46 V I/O supply VDDIO 3.13 3.3 3.46 V |VDDA – VDDIO| 0 V Ambient operating temperature Commercial—CQZ (147 MHz) TA 0 — +70 °C Automotive—DQZ (131 MHz) –40 +85 Automotive—DQZ (113 MHz) –40 +105 Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply. 5.3 Digital DC Characteristics (Measurements performed under static conditions.) Parameter Symbol Min Typ Max Unit High-level input voltage V 2.0 — — V IH Low-level input voltage, except XTI V — — 0.8 V IL Low-level input voltage, XTI V — — 0.6 V ILKXTI Input Hysteresis V — 0.4 — V hys High-level output voltage (I = –2mA), except XTO V VDDIO*0.9 — — V O OH Low-level output voltage (I = 2mA), except XTO V — — VDDIO*0.1 V O OL Input leakage XTI I — — 5 μA LXTI Input leakage current (all digital pins with internal I — — 70 μA LEAK pull-up resistors enabled) DS787PP9 12

5.4 Power Supply Characteristics 5.4 Power Supply Characteristics Note: Measurements performed under operating conditions Parameter Min Typ Max Unit Operational Power Supply Current: VDD: Core and I/O operating1 — 325 — mA VDDA: PLL operating current — 16 — mA VDDA: DAC operating current (all 8 channels enabled) — 56 — mA VDDA: ADC operating current (all 4 channels enabled) — 34 — mA VDDIO: With most ports operating — 27 — mA Total Operational Power Dissipation: 1025 mW Standby Power Supply Current: VDD: Core and I/O not clocked — 410 — μA VDDA: PLLs halted — 26 — μA VDDA: DAC disabled — 40 — μA VDDA: ADC disabled — 24 — μA μA VDDIO: All connected I/O pins 3-stated by other ICs in system — 215 — μW Total Standby Power Dissipation: 1745 1. Dependent on application firmware and DSP clock speed. 5.5 Thermal Data (100-pin LQFP with Exposed Pad) Parameter Symbol Min Typ Max Unit Thermal Resistance (Junction to Ambient)  °C/Watt ja Two-layer Board1 — 34 — Four-layer Board2 — 18 — Thermal Resistance (Junction to Top of Package)  °C/Watt jt Two-layer Board1 — 0.54 — Four-layer Board2 — .28 — 1. To calculate the die temperature for a given power dissipation:  = Ambient temperature + [ (Power Dissipation in Watts) *  ] j ja 2. To calculate the case temperature for a given power dissipation:  =  - [ (Power Dissipation in Watts) *  ] c j jt Note: Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% of the top and bottom layers. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% of the top and bottom layers and 0.5-oz. copper covering 90% of the internal power plane and ground plane layers. 5.6 Digital Switching Characteristics–RESET Parameter Symbol Min Max Unit RESET minimum pulse width low1 T 1 — s rstl All bidirectional pins high-Z after RESET low T — 200 ns rst2z Configuration pins setup before RESET high T 50 — ns rstsu Configuration pins hold after RESET high T 20 — ns rsthld 1. The rising edge of RESET must not occur before the power supplies are stable at the recommended operating values as described in Section5.2. In addition, for the configuration pins to be read correctly, the RESET Trstl requirement must be met. 13 DS787PP9

5.7 Digital Switching Characteristics–XTI All supplies at recommended operating values. VDD1 Trstl RESET HS[3:0] Trstsu Trsthld 1 Refers to all power supplies. Figure5-1. RESET Timing at Power-on RESET HS[3:0] All Bidirectional Pins T T rstsu rsthld T rst2z T rstl Figure5-2. RESET Timing after Power is Stable 5.7 Digital Switching Characteristics–XTI Parameter Symbol Min Max Unit External Crystal operating frequency1 F 12.288 24.576 MHz xtal XTI period T 41 81 ns clki XTI high time T 13.3 — ns clkih XTI low time T 13.3 — ns clkil External Crystal Load Capacitance (parallel resonant)2 C 10 18 pF L External Crystal Equivalent Series Resistance ESR — 50  1. Part characterized with the following crystal frequency values: 12.288 and 24.576 MHz. 2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals that require a CL outside this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s recommendation for load capacitor selection. XTI t t clkih clkil T clki Figure5-3. XTI Timing DS787PP9 14

5.8 Digital Switching Characteristics–Internal Clock 5.8 Digital Switching Characteristics–Internal Clock Min (2- Min (4- Max (2- Max (4- Parameter Symbol Unit layer Boards) layer Boards) layer Boards) layer Boards) Internal DSP_CLK frequency1 F (See Footnote 2) MHz dclk CS47048-CQZ F 147 147 xtal CS47048-DQZ F 131 147 xtal CS47028-CQZ F 147 147 xtal CS47028-DQZ F 131 147 xtal CS47024-CQZ F 147 147 xtal CS47024-DQZ F 131 147 xtal Internal DSP_CLK period1 DCLKP ns CS47048-CQZ 6.8 6.8 1/F xtal CS47048-DQZ 7.6 6.8 1/F xtal CS47028-CQZ 6.8 6.8 1/F xtal CS47028-DQZ 7.6 6.8 1/F xtal CS47024-CQZ 6.8 6.8 1/F xtal CS47024-DQZ 7.6 6.8 1/F xtal 1. After initial power-on reset, Fdclk = Fxtal. After initial kick-start commands, the PLL is locked to max Fdclk and remains locked until the next power-on reset. 2. See Section5.7. for all references to Fxtal. 5.9 Digital Switching Characteristics–Serial Control Port–SPI Slave Mode Parameter Symbol Min Typical Max Unit SCP_CLK frequency1 f — — 25 MHz spisck SCP_CS falling to SCP_CLK rising t 24 — — ns spicss SCP_CLK low time t 20 — — ns spickl SCP_CLK high time t 20 — — ns spickh Setup time SCP_MOSI input t 5 — — ns spidsu Hold time SCP_MOSI input t 5 — — ns spidh SCP_CLK low to SCP_MISO output valid t — — 11 ns spidov SCP_CLK falling to SCP_IRQ rising t — — 27 ns spiirqh SCP_CS rising to SCP_IRQ falling t 0 — — ns spiirql SCP_CLK low to SCP_CS rising t 24 — — ns spicsh SCP_CS rising to SCP_MISO output high-Z t — 20 — ns spicsdz SCP_CLK rising to SCP_BSY falling t — 3*DCLKP+20 — ns spicbsyl 1. fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port can be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is Fxtal/3. 15 DS787PP9

5.10 Digital Switching Characteristics–Serial Control Port–SPI Master t spicss SCP_CS t spickl t 0 1 2 6 7 0 5 6 7 spicsh SCP_CLK 1/f t spisck spickh SCP_MOSI A6 A5 A0 R/W MSB LSB t spidsu tspidh tspidov tspicsdz SCP_MISO MSB LSB t spiirqh t spiirql SCP_IRQ t spibsyl SCP_BSY Figure5-4. Serial Control Port–SPI Slave Mode Timing 5.10 Digital Switching Characteristics–Serial Control Port–SPI Master Mode Parameter Symbol Min Typical Max Units SCP_CLK frequency1,2 f — — F /2 MHz spisck xtal EE_CS falling to SCP_CLK rising3 t — 11*DCLKP+(SCP_CLK PERIOD)/2 — ns spicss SCP_CLK low time t 18 — — ns spickl SCP_CLK high time t 18 — — ns spickh Setup time SCP_MISO input t 9 — — ns spidsu Hold time SCP_MISO input t 5 — — ns spidh SCP_CLK low to SCP_MOSI output valid t — — 8 ns spidov SCP_CLK low to EE_CS falling t 7 — — ns spicsl SCP_CLK low to EE_CS rising t — 11*DCLKP+(SCP_CLK PERIOD)/2 — ns spicsh Bus free time between active EE_CS t — 3*DCLKP — ns spicsx SCP_CLK falling to SCP_MOSI output high-Z t — — 20 ns spidz 1. fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port can be limited by the firmware application. 2. See Section 5.7. 3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter. DS787PP9 16

5.11 Digital Switching Characteristics–Serial Control Port I2C Slave Mode t spicsx t spicss EE_CS t tspicsl 0 1 2 spickl 6 7 0 5 6 7 tspicsh SCP_CLK 1/f t spisck spickh SCP_MISO A6 A5 A0 R/W MSB LSB t spidsu tspidh tspidov tspidz SCP_MOSI MSB LSB Figure5-5. Serial Control Port–SPI Master Mode Timing 5.11 Digital Switching Characteristics–Serial Control Port I2C Slave Mode Parameter Symbol Min Typical Max Units SCP_CLK frequency1 f — — 400 kHz iicck SCP_CLK rise time t — — 150 ns iicr SCP_CLK fall time t — — 150 ns iicf SCP_CLK low time t 1.25 — — µs iicckl SCP_CLK high time t 1.25 — — µs iicckh SCP_CLK rising to SCP_SDA rising or falling for START or STOP condition t 1.25 — — µs iicckcmd START condition to SCP_CLK falling t 1.25 — — µs iicstscl SCP_CLK falling to STOP condition t 2.5 — — µs iicstp Bus free time between STOP and START conditions t 3 — — µs iicbft Setup time SCP_SDA input valid to SCP_CLK rising t 110 — — ns iicsu Hold time SCP_SDA input after SCP_CLK falling t 100 — — ns iich SCP_CLK low to SCP_SDA out valid t — — 18 ns iicdov SCP_CLK falling to SCP_IRQ rising t — — 3*DCLKP+40 ns iicirqh NAK condition to SCP_IRQ low t — 3*DCLKP+20 — ns iicirql SCP_CLK rising to SCB_BSY low t — 3*DCLKP+20 — ns iicbsyl 1. fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port can be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer. I2C Slave Address = 0x82 17 DS787PP9

5.12 Digital Switching Characteristics–Serial Control Port–I2C Master t t t t t iicckcmd iicckl iicr iicf iicckcmd Start Condition Stop Condition 0 1 6 7 8 0 1 6 7 8 SCP_CLK t iicstp t t t 1/f t iicstscl iicckh iicdov iicck iicbft SCP_SDA A6 A0 R/W ACK MSB LSB ACK t iicirqh t iicirql t t iicsu iich SCP_IRQ t iiccbsyl SCP_BSY Figure5-6. Serial Control Port–I2C Slave Mode Timing 5.12 Digital Switching Characteristics–Serial Control Port–I2C Master Mode Parameter Symbol Min Max Units SCP_CLK frequency1 f — 400 kHz iicck SCP_CLK rise time t — 150 ns iicr SCP_CLK fall time t — 150 ns iicf SCP_CLK low time t 1.25 — µs iicckl SCP_CLK high time t 1.25 — µs iicckh SCP_CLK rising to SCP_SDA rising or falling for START or STOP condition t 1.25 — µs iicckcmd START condition to SCP_CLK falling t 1.25 — µs iicstscl SCP_CLK falling to STOP condition t 2.5 — µs iicstp Bus free time between STOP and START conditions t 3 — µs iicbft Setup time SCP_SDA input valid to SCP_CLK rising t 110 — ns iicsu Hold time SCP_SDA input after SCP_CLK falling t 100 — ns iich SCP_CLK low to SCP_SDA out valid t — 36 ns iicdov 1. fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port can be limited by the firmware application. t t t t t iicckcmd iicckl iicr iicf iicckcmd 0 1 6 7 8 0 1 6 7 8 SCP_CLK t tiicstscl tiicckh tiicdov 1/fiicck iicstp tiicbft SCP_SDA A6 A0 R/W ACK MSB LSB ACK t t iicsu iich Figure5-7. Serial Control Port–I2C Master Mode Timing DS787PP9 18

5.13 Digital Switching Characteristics–Digital Audio Slave Input Port 5.13 Digital Switching Characteristics–Digital Audio Slave Input Port Parameter Symbol Min Max Unit DAI_SCLK period T 20 — ns daiclkp DAI_SCLK duty cycle — 45 55 % Setup time DAI_DATAn t 8 — ns daidsu Hold time DAI_DATAn t 5 — ns daidh DAI_SCLK tdaidsu tdaidh DAI_DATAn Figure5-8. Digital Audio Input (DAI) Port Timing Diagram 5.14 Digital Switching Characteristics–Digital Audio Output Port Parameter Symbol Min Max Unit DAO_MCLK period T 20 — ns daomclk DAO_MCLK duty cycle — 45 55 % DAO_SCLK period for Master or Slave mode1 T 20 — ns daosclk DAO_SCLK duty cycle for Master or Slave mode1 — 40 60 % Master Mode (Output A1 Mode)1,2 DAO_SCLK delay from DAO_MCLK rising edge, DAO MCLK as an input t — 19 ns daomsck DAO_LRCLK to DAO_SCLK inactive edge3. See Fig.5-9. t — 8 ns daomlrts DAO_SCLK inactive edge3 to DAO_LRCLK. See Fig.5-10. t — 8 ns daomstlr DAO_DATA[3:0] delay from DAO_SCLK inactive edge3 t — 8 ns daomdy Slave Mode (Output A0 Mode)4 DAO_SCLK active edge to DAO_LRCLK transition. See Fig.5-11. t 10 — ns daosstlr DAO_LRCLK transition to DAO_SCLK active edge. See Fig.5-12. t 10 — ns daoslrts DAO_Dx delay from DAO_SCLK inactive edge t — 11 ns daosdv 1. Master mode timing specifications are characterized, not production tested. 2. Master mode is defined as the CS47048 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_ LRCLK. 3. The DAO_LRCLK transition can occur on either side of the edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the data is valid. 4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source. t daomclk DAO_MCLK t daomsck DAO_SCLK t daomlrts DAO_LRCLK t daomdv DAO_DATAn Figure5-9. DAO_LRCLK Transition before DAO_SCLK Inactive Edge 19 DS787PP9

5.14 Digital Switching Characteristics–Digital Audio Output Port t daomclk DAO_MCLK t daomsck DAO_SCLK t daomstlr DAO_LRCLK t daomdv DAO_DATAn Figure5-10. DAO_LRCLK Transition after DAO_SCLK Inactive Edge DAO_LRCLK t daoslrts DAO_SCLK t daosclk DAO_Dx Figure5-11. DAO_LRCLK Transition before DAO_SCLK Inactive Edge t daosclk DAO_LRCLK DAO_SCLK t daosstlr t daosdv DAO_Dx Figure5-12. DAO_LRCLK Transition after DAO_SCLK Inactive Edge DS787PP9 20

5.15 Digital Switching Characteristics–S/PDIF RX Port 5.15 Digital Switching Characteristics–S/PDIF RX Port (Inputs: Logic 0 = V , Logic 1 = V , C = 20 pF) IL IH L Parameter Symbol Min Typ Max Units PLL Clock Recovery Sample Rate Range — 30 — 200 kHz 5.16 ADC Characteristics 5.16.1 Analog Input Characteristics (Commercial) Test Conditions (unless otherwise specified): T = 0–+70°C; VDD = 1.8V±5%, VDDA (VA) = 3.3V±5%, 1kHz sine wave A driven through the passive input filter (R = 10 k) in Fig.5-13 or Fig.5-14; DSP running test application; Measurement i Bandwidth is 10–20kHz. Differential Single-ended Parameter Min Typ Max Min Typ Max Unit Fs = 96 kHz Dynamic Range1,6,7 A-weighted 99 105 — 96 102 — dB Unweighted 96 102 — 93 99 — dB 40 kHz bandwidth unweighted — 99 — — 96 — dB Total Harmonic Distortion + Noise6,7 –1 dB — –98 –92 — –95 –89 dB –20 dB — –82 — — –79 — dB –60 dB — –42 — — –39 — dB 40 kHz bandwidth –1 dB — –90 — — –90 — dB AIN_1A/B Interchannel Isolation10 — 95 — — 95 — dB AID_[2.6]A/B MUX Interchannel Isolation — 95 — — 95 — dB DC Accuracy Interchannel Gain Mismatch — 0.1 — — 0.1 — dB Gain Drift — ±120 — — ±120 — ppm/°C Analog Input Full-scale Input Voltage2,3 3.3 3.7•VA 3.9 1.65 1.85•VA 1.95 V PP Differential Input Impedance4 — 400 — — — —  Single-ended Input Impedance5 — — — — 200 —  Common Mode Rejection Ratio (CMRR)8 — 60 — — — — dB Parasitic Load Capacitance (C )9 — — 20 — — 20 pF L 1. dB units referred to the typical full-scale voltage. 2. These full-scale values were measured with Ri=10k for both the single-ended and differential mode input circuits. 3. The full-scale voltage can be changed by scaling Ri. Differential Full-Scale (Vpp) = 3.7*VDDA*(Ri+200)/(10k+200) Single-Ended Full-Scale (Vpp) = 1.85*VDDA*(Ri+200)/(10k+200) 4. Measured between AIN_xx+ and AN_xx–. 5. Measured between AIN_xx+ and AGND. 6. Decreasing full-scale voltage by reducing Ri causes the noise floor to increase. 7. Common mode input current should be kept to less than ±160uA to avoid performance degradation: |(Iip+Iin)/2| < 160uA. This corresponds to ±1.6V for Ri=10 k in the differential case. 8. This number was measured using perfectly matched external resistors (Ri). Mismatch in the external resistors typically reduces CMRR by 20 log  (| Ri|/Ri + 0.001). 9. CL represents the parasitic load capacitance between Ri on the input circuit and the input pin of the CS47048 package. 10. This measurement is not applicable to the CS47028 and CS47024 devices. 21 DS787PP9

5.16 ADC Characteristics 5.16.2 Analog Input Characteristics (Automotive) Test Conditions (unless otherwise specified): TA = –40–85°C; VDD = 1.8V±5%, VDDA (VA) = 3.3V±5%; kHz sine wave driven through the passive input filter (R = 10 k) in Fig.5-13 or Fig.5-14; DSP running test application; Measurement i Bandwidth is 10 Hz–20 kHz. Differential Single-ended Parameter Min Typ Max Min Typ Max Unit Fs = 96 kHz Dynamic Range1,6,7 A-weighted 97 105 — 94 102 — dB Unweighted 94 102 — 91 99 — dB 40 kHz bandwidth unweighted — 99 — — 96 — dB Total Harmonic Distortion + Noise6,7 –1 dB — –98 –90 — –95 –87 dB –20 dB — –82 — — –79 — dB –60 dB — –42 — — –39 — dB 40 kHz bandwidth –1 dB — –90 — — –90 — dB AIN_1A/B Interchannel Isolation10 — 95 — — 95 — dB AID_[2.6]A/B MUX Interchannel Isolation — 95 — — 95 — dB DC Accuracy Interchannel Gain Mismatch — 0.1 — — 0.1 — dB Gain Drift — ±120 — — ±120 — ppm/°C Analog Input Full-scale Input Voltage2,3 3.3 3.7•VA 3.9 1.65 1.85•VA 1.95 V PP Differential Input Impedance4 — 400 — — — —  Single-ended Input Impedance5 — — — — 200 —  Common Mode Rejection Ratio (CMRR)8 — 60 — — — — dB Parasitic Load Capacitance (C )9 — — 20 — — 20 pF L 1. dB units referred to the typical full-scale voltage. 2. These full-scale values were measured with Ri=10k for both the single-ended and differential mode input circuits. 3. The full-scale voltage can be changed by scaling Ri. Differential Full-Scale (Vpp) = 3.7*VDDA*(Ri+200)/(10k+200) Single-Ended Full-Scale (Vpp) = 1.85*VDDA*(Ri+200)/(10k+200) 4. Measured between AIN_xx+ and AN_xx–. 5. Measured between AIN_xx+ and AGND. 6. Decreasing full-scale voltage by reducing Ri causes the noise floor to increase. 7. Common mode input current should be kept to less than ±160uA to avoid performance degradation: |(Iip+Iin)/2| < 160uA. This corresponds to ±1.6V for Ri=10 k in the differential case. 8. This number was measured using perfectly matched external resistors (Ri). Mismatch in the external resistors typically reduces CMRR by 20 log  (| Ri|/Ri + 0.001). 9. CL represents the parasitic load capacitance between Ri on the input circuit and the input pin of the CS47048 package. 10. This measurement is not applicable to the CS47028 and CS47024 devices. 10µF R AIN + i AIN_xA+ or 100K C AIN_xB+ L Figure5-13. ADC Single-ended Input Test Circuit DS787PP9 22

5.17 DAC Characteristics 10µF R AIN- + i AIN_xA- or AIN_xB- 100K C L 10µF R AIN+ + i AIN_xA+ or AIN_xB+ 100K C L Figure5-14. ADC Differential Input Test Circuit 5.16.3 ADC Digital Filter Characteristics Parameter1,2 Min Typ Max Unit Fs = 96 kHz Passband (Frequency Response) to –0.1 dB corner 0 — 0.4896 Fs Passband Ripple — — 0.08 dB Stopband 0.5688 — — Fs Stopband Attenuation 70 — — dB Total Group Delay — 12/Fs — s High-pass Filter Characteristics Frequency Response: –3.0 dB — 1 — Hz –0.13 dB — 20 — Hz Phase Deviation @ 20 Hz — 10 — Deg Passband Ripple — — 0 dB Filter Settling Time — 105/Fs 0 s 1. Filter response is guaranteed by design. 2. Response is clock-dependent and scales with Fs. 5.17 DAC Characteristics 5.17.1 Analog Output Characteristics (Commercial) Test Conditions (unless otherwise specified): TA = 0–+70°C; VDD = 1.8V±5%, VDDA(VA) = 3.3V±5%; 1 kHz sine wave driven through a filter shown in Fig.5-15 or Fig.5-16; DSP running test application; Measurement Bandwidth is 20 Hz–20 kHz. Differential Single-ended Parameter Min Typ Max Min Typ Max Unit Fs = 96 kHz Dynamic Range A-weighted 102 108 — 99 105 — dB Unweighted 99 105 — 96 102 — dB Total Harmonic Distortion + Noise 0 dB — –98 –90 — –95 –87 dB –20 dB — –88 — — –85 — dB –60 dB — –48 — — –45 — dB Interchannel Isolation (1 kHz) — 95 — — 95 — dB 23 DS787PP9

5.17 DAC Characteristics Differential Single-ended Parameter Min Typ Max Min Typ Max Unit Analog Input Full-scale Output 1.20 1.40•VA 1.60 0.60 0.70•VA 0.80 V PP Interchannel Gain Mismatch — 0.1 — — 0.1 — dB Gain Drift — ±120 — — ±120 — ppm/°C Output Impedance — 100 — — 100 —  DC Current Draw from an AOUT Pin1 — — 10 — — 10 A AC-load Resistance (R )2 3 — — 3 — — k L Load Capacitance (C )2 — — 100 — — 100 pF L 5.17.2 Analog Output Characteristics (Automotive) Test Conditions (unless otherwise specified): T =–40 to +85C; VDD = 1.8V±5%, VDDA(VA) = 3.3V±5%; 1 kHz sine A wave driven through a filter shown in Fig.5-15 or Fig.5-16; DSP running test application; Measurement Bandwidth is 20Hz–20kHz. Differential Single-ended Parameter Min Typ Max Min Typ Max Unit Fs = 96 kHz Dynamic Range A-weighted 100 108 — 97 105 — dB Unweighted 97 105 — 94 102 — dB Total Harmonic Distortion + Noise 0 dB — –98 –90 — –95 –87 dB –20 dB — –88 — — –85 — dB –60 dB — –48 — — –45 — dB Interchannel Isolation (1 kHz) — 95 — — 95 — dB Analog Input Full-scale Output 1.20 1.40•VA 1.60 0.60 0.70•VA 0.80 VPP Interchannel Gain Mismatch — 0.1 — — 0.1 — dB Gain Drift — ±120 — — ±120 — ppm/°C Output Impedance — 100 — — 100 —  DC Current Draw from an AOUT Pin1 — — 10 — — 10 A AC-load Resistance (R )2 3 — — 3 — — k L Load Capacitance (C )2 — — 100 — — 100 pF L 1. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC-blocking capacitors. 2. Guaranteed by design. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp’s stability and signal integrity. In this circuit topology, CL represents any capacitive loading that appears before the 560  series resistor (typically parasitic), and effectively moves the dominant pole of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pF can cause the internal op-amp to become unstable. 3.3 µF 560 AOUT_x+ + AOUT CL RL 2200 pF 10 k Figure5-15. DAC Single-ended Output Test Circuit DS787PP9 24

5.17 DAC Characteristics 4.87 k 1800 pF 470 pF 4.87 k 2.43 k AOUT_x- - 560 + 1.96 k 953 AOUT AOUT_x+ + 22 µF k 6 9 CL CL 1. 10 k 4700 pF + 1200 pF 22 µF P output: R = 1.96k + ( [2F*4700pF]-1 || (1.96k + [2F*22µF- ]-1 ) || (953 + [2F*1200pF ]-1 )) L N output: R = 4.87k + ( [2F*1800pF]-1 || ((2.43k + [2F*470pF]-1 ) || 4.87k )) L Figure5-16. DAC Differential Output Test Circuit 125 ) F 100 p ( L C - 75 - d a o L Safe Operating 50 e Region v ti i c a p 25 a C 2.5 5 10 15 20 3 Resistive Load -- R (k) L Figure5-17. Maximum Loading 5.17.3 Combined DAC Interpolation and On-chip Analog Filter Response Parameter Min Typ Max Unit Passband (Frequency Response) to 0.22 dB corner 0 — 0.4125 Fs to –3 dB corner 0 — 0.4979 Fs Frequency Response 10 Hz–20 kHz –0.02 — +0.02 dB StopBand 0.5465 — — Fs StopBand Attenuation 100 — — dB Group Delay — 10/Fs — s 25 DS787PP9

6 Ordering Information 6 Ordering Information The CS470xx DSP part numbers are described as follows: Example: CS47048I-XYZR where I–ROM ID Letter X–Product Grade Y–Package Type Z–Lead (Pb) Free R–Tape and Reel Packaging Table6-1. Ordering Information Part No. Grade Temp. Range Package CS47048C-CQZ Commercial 0–+70°C 100-pin LQFP CS47048C-DQZ Automotive –40–+85°C CS47048C-EQZ Extended Automotive –40–+105°C CS47028C-CQZ Commercial 0–+70°C CS47028C-DQZ Automotive –40–+85°C CS47028C-EQZ Extended Automotive –40–+105°C CS47024C-CQZ Commercial 0–+70°C CS47024C-DQZ Automotive –40–+85°C CS47024C-EQZ Extended Automotive –40–+105°C Note: Contact the factory for availability of the –D (automotive grade) package. 7 Environmental, Manufacturing, and Handling Information Table7-1. Environmental, Manufacturing, and Handling Information Model Number Peak Reflow Temp. MSL1 Rating Max Floor Life CS47048C-CQZ 260° C 3 7 days CS47048C-DQZ CS47048C-EQZ CS47028C-CQZ 260° C 3 7 days CS47028C-DQZ CS47028C-EQZ CS47024C-CQZ 260° C 3 7 days CS47024C-DQZ CS47024C-EQZ 1. Moisture Sensitivity Level as specified by IPC/JEDEC J-STD-020. 26 DS787PP9

8 Device Pinout Diagrams 8 Device Pinout Diagrams 8.1 CS47048, 100-pin LQFP Pinout Diagram ET T_1+ T_1- A7 A7 T_2+ T_2- T_3+ T_3- A6 A6 T_4+ T_4- T_5+ T_5- A5 A5 T_6+ T_6- T_7+ T_7- A4 A4 T_8+ T_8- S U U D D U U U U D D U U U U D D U U U U D D U U E O O D N O O O O D N O O O O D N O O O O D N O O R A A V G A A A A V G A A A A V G A A A A V G A A 100 95 90 85 80 76 DBCK 1 75 VDD_DAC DBDA GND_DAC GPIO15, DAI_LRCLK VDD_ADC_MON GPIO17, DAI_SCLK REXT VDDIO1 5 VQ GNDIO1 70 BIASREF_DAC GPIO16, DAI_DATA0, TM0 GNDA3 GPIO0, DAI_DATA1, TM1 AIN_1A+ GPIO1, DAI_DATA2, TM2 AIN_1A- GPIO2, DAI_DATA3, TM3, SPDIF RX 10 AIN_1B+ VDD1 65 AIN_1B- GND1 CS47048 VDDA3 GPIO7, DAO_LRCLK BIASREF_ADC GPIO14, DAO_SCLK 100-Pin LQFP VDDA2 GNDIO2 15 (Thermal Pad Package) GNDA2 VDDIO2 60 AIN_2A+ GPIO18, DAO_MCLK, HS4 AIN_2A- GPIO6, DAO_DATA0, HS0 AIN_3A+ GPIO3, DAO_DATA1, HS1 AIN_3A- GPIO4, DAO_DATA2, HS2, S/PDIF TXb 20 AIN_4A+ GPIO5, DAO_DATA3, HS3, S/PDIF TXa 55 AIN_4A- VDD2 AIN_5A+ GND2 AIN_5A- GPIO9, SCP_MOSI AIN_6A+ GPIO10, SCP_MISO, SCP_SDA 25 51 AIN_6A- 6 0 5 0 5 0 2 3 3 4 4 5 GPIO11, SCP_CLK SCP_CS, DAI_DATA4 GPIO12, SCP_IRQ 13, SCP_BSY, EE_CS VDDIO3 GNDIO3 GND_SUB XTAL_OUT, TEST GND3 VDD3 XTI XTO GNDA_PLL PLL_REF_RES VDDA_PLL AIN_6B- AIN_6B+ AIN_5B- AIN_5B+ AIN_4B- AIN_4B+ AIN_3B- AIN_3B+ AIN_2B- AIN_2B+ O8, PIO PI G G Figure8-1. CS47048 Pinout Diagram 27 DS787PP9

8.2 CS47028, 100-pin LQFP Pinout Diagram 8.2 CS47028, 100-pin LQFP Pinout Diagram ET T_1+ T_1- A7 A7 T_2+ T_2- T_3+ T_3- A6 A6 T_4+ T_4- T_5+ T_5- A5 A5 T_6+ T_6- T_7+ T_7- A4 A4 T_8+ T_8- S U U D D U U U U D D U U U U D D U U U U D D U U E O O D N O O O O D N O O O O D N O O O O D N O O R A A V G A A A A V G A A A A V G A A A A V G A A 100 95 90 85 80 76 DBCK 1 75 VDD_DAC DBDA GND_DAC GPIO15, DAI_LRCLK VDD_ADC_MON GPIO17, DAI_SCLK REXT VDDIO1 5 VQ GNDIO1 70 BIASREF_DAC GPIO16, DAI_DATA0, TM0 GNDA3 GPIO0, DAI_DATA1, TM1 NC GPIO1, DAI_DATA2, TM2 NC GPIO2, DAI_DATA3, TM3, SPDIF RX 10 NC VDD1 65 NC GND1 CS47028 VDDA3 GPIO7, DAO_LRCLK BIASREF_ADC GPIO14, DAO_SCLK 100-Pin LQFP VDDA2 GNDIO2 15 (Thermal Pad Package) GNDA2 VDDIO2 60 AIN_2A+ GPIO18, DAO_MCLK, HS4 AIN_2A- GPIO6, DAO_DATA0, HS0 AIN_3A+ GPIO3, DAO_DATA1, HS1 AIN_3A- GPIO4, DAO_DATA2, HS2, S/PDIF TXb 20 AIN_4A+ GPIO5, DAO_DATA3, HS3, S/PDIF TXa 55 AIN_4A- VDD2 AIN_5A+ GND2 AIN_5A- GPIO9, SCP_MOSI AIN_6A+ GPIO10, SCP_MISO, SCP_SDA 25 51 AIN_6A- 6 0 5 0 5 0 2 3 3 4 4 5 GPIO11, SCP_CLK SCP_CS, DAI_DATA4 GPIO12, SCP_IRQ 13, SCP_BSY, EE_CS VDDIO3 GNDIO3 GND_SUB XTAL_OUT, TEST GND3 VDD3 XTI XTO GNDA_PLL PLL_REF_RES VDDA_PLL AIN_6B- AIN_6B+ AIN_5B- AIN_5B+ AIN_4B- AIN_4B+ AIN_3B- AIN_3B+ AIN_2B- AIN_2B+ O8, PIO PI G G Figure8-2. CS47028 Pinout Diagram 28 DS787PP9

8.3 CS47024, 100-pin LQFP Pinout Diagram 8.3 CS47024, 100-pin LQFP Pinout Diagram ET T_1+ T_1- A7 A7 T_2+ T_2- T_3+ T_3- A6 A6 T_4+ T_4- A5 A5 A4 A4 S U U D D U U U U D D U U D D D D E O O D N O O O O D N O O C C D N C C C C D N C C R A A V G A A A A V G A A N N V G N N N N V G N N 100 95 90 85 80 76 DBCK 1 75 VDD_DAC DBDA GND_DAC GPIO15, DAI_LRCLK VDD_ADC_MON GPIO17, DAI_SCLK REXT VDDIO1 5 VQ GNDIO1 70 BIASREF_DAC GPIO16, DAI_DATA0, TM0 GNDA3 GPIO0, DAI_DATA1, TM1 NC GPIO1, DAI_DATA2, TM2 NC GPIO2, DAI_DATA3, TM3, SPDIF RX 10 NC VDD1 65 NC GND1 CS47024 VDDA3 GPIO7, DAO_LRCLK BIASREF_ADC GPIO14, DAO_SCLK 100-Pin LQFP VDDA2 GNDIO2 15 (Thermal Pad Package) GNDA2 VDDIO2 60 AIN_2A+ GPIO18, DAO_MCLK, HS4 AIN_2A- GPIO6, DAO_DATA0, HS0 AIN_3A+ GPIO3, DAO_DATA1, HS1 AIN_3A- GPIO4, DAO_DATA2, HS2, S/PDIF TXb 20 AIN_4A+ GPIO5, DAO_DATA3, HS3, S/PDIF TXa 55 AIN_4A- VDD2 AIN_5A+ GND2 AIN_5A- GPIO9, SCP_MOSI AIN_6A+ GPIO10, SCP_MISO, SCP_SDA 25 51 AIN_6A- 6 0 5 0 5 0 2 3 3 4 4 5 GPIO11, SCP_CLK SCP_CS, DAI_DATA4 GPIO12, SCP_IRQ 13, SCP_BSY, EE_CS VDDIO3 GNDIO3 GND_SUB XTAL_OUT, TEST GND3 VDD3 XTI XTO GNDA_PLL PLL_REF_RES VDDA_PLL AIN_6B- AIN_6B+ AIN_5B- AIN_5B+ AIN_4B- AIN_4B+ AIN_3B- AIN_3B+ AIN_2B- AIN_2B+ O8, PIO PI G G Figure8-3. CS47024 Pinout Diagram 29 DS787PP9

D 9 100-pin LQFP with Exposed Pad Package Drawing S 7 8 7 Fig.9-1 shows the 100-pin LQFP package with exposed pad for the CS47048, CS47028, and CS47024. P P 9 Figure9-1. 100-pin LQFP Package Drawing 3 0

10 Parameter Definitions 10Parameter Definitions 10.1 Dynamic Range The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60dBFS signal. 60dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. 10.2 Total Harmonic Distortion + Noise The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 10Hz–20kHz), including distortion components. Expressed in decibels. Measured at –1 and –20dBFS as suggested in AES17-1991 Annex A. 10.3 Frequency Response A measure of the amplitude response variation from 10Hz–20kHz relative to the amplitude response at 1kHz. Units in decibels. 10.4 Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. 10.5 Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. 10.6 Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. 10.7 Gain Drift The change in gain value with temperature. Units in ppm/°C. 31 DS787PP9

11 Revision History 11Revision History Revision Date Changes PP1 August, 2009 Updated Characterization data in Section5.4, Section5.7, Section5.9, Section5.11, Section5.12, Section5.16.1, Section5.16.2, Section5.16.3, Section5.17.1, and Section5.17.2. Modified Footnote 3 in both Section5.16.1 and Section5.16.2. Added Footnote 5 to Section5.14. Updated Section2.1. Modified Section4.3.6 and Section4.3.8. Modified references to TDM in various sections of the data sheet. PP2 January, 2010 Updated TDM Feature description on page 1. Modified note at the bottom of the feature list on page 1. Updated table in Section5.8, specifying performance data for 2- and 4-layer boards. Updated Table3-1 and Table3-2 Updated block diagrams in Fig.4-1, Fig.4-2, and Fig.4-3. PP3 June, 2010 Table3-1: Straddled all three columns in the “Supports Different Fs Sample Rates” row to indicate that CS47024 devices have the same features as the CS47048 and CS47028. Added “The CS47024 has the 8-channel SRC block” to Section4.3.7. Added text in the following places to indicate that the CS47024 implements the S/PDIF Rx functionality: • Removed dagger from the S/PDIF Rx bullet on p. 1. • Updated bullet in “Configurable Serial Audio Inputs/Outputs” row in Table 2 Integrated 192 kHz S/PDIF Rx, 2 Integrated 192 kHz S/PDIF Tx. • Changed entry in “S/PDIF In (Stereo Pairs)” column in Table3-2. • Updated I2S block in Table3-2. • Removed text “On the CS47048 and CS47028...” from Section4.3.4. • Removed “(Not available on CS47024)” from the heading to Section5.15. • Described additional support for TDM 8-channel output mode on CS47024. • Removed dagger from the TDM I/O bullet on p. 1. • Straddled “Configurable Serial Audio Inputs/Outputs” row in Table3-1. • Changed cell in “TDM Out” column in Table3-2. • Removed text “On the CS47048 and CS47028...” from Section4.3.5. PP4 February, 2011 Added “Decoder” information to Section3. Changed the name of the core to “Cirrus Logic 32-bit core”. PP5 February, 2011 Added “SPDIF RX” to Fig.5-17. PP6 June, 2011 In Section4.3.1 and Section4.3.7, removed mention of 192 kHz sampling frequency. Updated temperature operating conditions in Section5.2. Updated pin 33 to XTAL_OUT, TEST in Fig.8-1, Fig.8-2, and Fig.8-3. PP7 April, 2012 Corrected peak reflow temperature in Table7-1. PP8 June, 2012 Added number of bits to Integrated DAC and ADC Functionality on the cover page. PP9 July, 2012 Updated frequencies in Section5.2. Added extended automotive grade information to Section6 and Section7. DS787PP9 32