Confidential Draft CS4334/5/8/9 6/6/17 8-Pin, 24-Bit, 96 kHz Stereo D/A Converter Features Description  Complete Stereo DAC System: Interpolation, The CS4334 family members are complete, stereo dig- D/A, Output Analog Filtering ital-to-analog output systems including interpolation, 1-bit D/A conversion and output analog filtering in an  24-Bit Conversion 8-pin package. The CS4334/5/8/9 support all major au- dio data interface formats, and the individual devices  96 dB Dynamic Range differ only in the supported interface format.  -88 dB THD+N The CS4334 family is based on Delta-Sigma modula- tion, where the modulator output controls the reference  Low Clock-Jitter Sensitivity voltage input to an ultra-linear analog low-pass filter. This architecture allows for infinite adjustment of sam-  Single +5 V Power Supply ple rate between 2kHz and 100kHz simply by changing the master clock frequency.  Filtered Line-Level Outputs The CS4334 family contains on-chip digital de-empha- sis, operates from a single +5V power supply, and  On-Chip Digital De-emphasis requires minimal support circuitry. These features are ideal for set-top boxes, DVD players, SVCD players,  Popguard® Technology and A/V receivers. ORDERING INFORMATION  Functionally Compatible with CS4330/31/33 See “Ordering Information” on page24 DEM/SCLK AGND VA 2 6 7 3 LRCK Serial Input De-emphasis Voltage Reference Interface 1 SDATA Analog  Interpolator DAC Low-Pass AOUTL Modulator Filter 8 Analog  Interpolator DAC Low-Pass AOUTR Modulator Filter 5 4 MCLK Copyright  Cirrus Logic, Inc. 2012–2017 JUNE '17 http://www.cirrus.com (All Rights Reserved) DS248F7

CS4334/5/8/9 TABLE OF CONTENTS 1. TYPICAL CONNECTION DIAGRAM ....................................................................................................4 2. CHARACTERISTICS AND SPECIFICATIONS .....................................................................................5 SPECIFIED OPERATING CONDITIONS..............................................................................................5 ABSOLUTE MAXIMUM RATINGS........................................................................................................5 ANALOG CHARACTERISTICS.............................................................................................................6 POWER AND THERMAL CHARACTERISTICS...................................................................................8 DIGITAL INPUT CHARACTERISTICS..................................................................................................9 SWITCHING CHARACTERISTICS.....................................................................................................10 3. GENERAL DESCRIPTION .................................................................................................................12 3.1 Digital Interpolation Filter ..............................................................................................................12 3.2 Delta-Sigma Modulator .................................................................................................................12 3.3 Switched-Capacitor DAC ..............................................................................................................12 3.4 Analog Low-Pass Filter .................................................................................................................12 4. SYSTEM DESIGN ...............................................................................................................................13 4.1 Master Clock .................................................................................................................................13 4.2 Serial Clock ..................................................................................................................................13 4.2.1 External Serial Clock Mode .................................................................................................13 4.2.2 Internal Serial Clock Mode ..................................................................................................13 4.3 De-Emphasis ................................................................................................................................14 4.4 Initialization and Power-Down ......................................................................................................14 4.5 Output Transient Control ..............................................................................................................14 4.6 Grounding and Power Supply Decoupling ....................................................................................15 4.7 Analog Output and Filtering ..........................................................................................................15 4.8 Overall Base-Rate Frequency Response .....................................................................................18 4.9 Overall High-Rate Frequency Response ......................................................................................19 4.10 Base Rate Mode Performance Plots ..........................................................................................20 4.11 High Rate Mode Performance Plots ...........................................................................................21 5. PARAMETER DEFINITIONS ...............................................................................................................22 6. REFERENCES .....................................................................................................................................22 7. PACKAGE DIMENSIONS ...................................................................................................................23 8. ORDERING INFORMATION ...............................................................................................................24 9. FUNCTIONAL COMPATIBILITY .........................................................................................................24 10. REVISION HISTORY .........................................................................................................................25 LIST OF FIGURES Figure 1. Recommended Connection Diagram.........................................................................................4 Figure 2. Output Test Load.......................................................................................................................8 Figure 3. Maximum Loading......................................................................................................................9 Figure 4. Power vs. Sample Rate.............................................................................................................9 Figure 5. External Serial Mode Input Timing...........................................................................................11 Figure 6. Internal Serial Mode Input Timing............................................................................................11 Figure 7. Internal Serial Clock Generation.............................................................................................11 Figure 8. System Block Diagram.............................................................................................................12 Figure 9. De-Emphasis Curve (Fs = 44.1kHz)........................................................................................14 Figure 10. CS4334 Data Format (I²S).......................................................................................................15 Figure 11. CS4335 Data Format...............................................................................................................15 Figure 12. CS4338 Data Format...............................................................................................................16 Figure 13. CS4339 Data Format...............................................................................................................16 Figure 14. CS4334/5/8/9 Initialization and Power-Down Sequence.........................................................17 Figure 15. Stopband Rejection..................................................................................................................18 Figure 16. Transition Band........................................................................................................................18 Figure 17. Transition Band........................................................................................................................18 2

CS4334/5/8/9 Figure 18. Passband Ripple......................................................................................................................18 Figure 19. Stopband Rejection..................................................................................................................19 Figure 20. Transition Band........................................................................................................................19 Figure 21. Transition Band........................................................................................................................19 Figure 22. Passband Ripple......................................................................................................................19 Figure 23. 0 dBFS FFT (BRM)..................................................................................................................20 Figure 24. -60 dBFS FFT (BRM)..............................................................................................................20 Figure 25. Idle Channel Noise FFT (BRM)................................................................................................20 Figure 26. Twin Tone IMD FFT (BRM)......................................................................................................20 Figure 27. THD+N vs. Amplitude (BRM)...................................................................................................20 Figure 28. THD+N vs. Frequency (BRM)..................................................................................................20 Figure 29. 0 dBFS FFT (HRM)..................................................................................................................21 Figure 30. -60 dBFS FFT (HRM)..............................................................................................................21 Figure 31. Idle Channel Noise FFT (HRM)...............................................................................................21 Figure 32. Twin Tone IMD FFT (HRM).....................................................................................................21 Figure 33. THD+N vs. Amplitude (HRM)...................................................................................................21 Figure 34. THD+N vs. Frequency (HRM)..................................................................................................21 LIST OF TABLES Table 1. Common Clock Frequencies ......................................................................................................13 PIN DESCRIPTIONS SERIAL DATA INPUT SDATA 1 8 AOUTL ANALOG LEFT CHANNEL OUTPUT DE-EMPHASIS / SCLK DEM/SCLK 2 7 VA ANALOG POWER LEFT / RIGHT CLOCK LRCK 3 6 AGND ANALOG GROUND MASTER CLOCK MCLK 4 5 AOUTR ANALOG RIGHT CHANNEL OUTPUT No. Pin Name I/O Pin Function and Description Serial Audio Data Input - Two’s complement MSB-first serial data is input on this pin. The data is 1 SDATA I clocked into the CS4334/5/8/9 via internal or external SCLK, and the channel is determined by LRCK. De-Emphasis/External Serial Clock Input - Used for de-emphasis filter control or external serial 2 DEM/SCLK I clock input. Left/Right Clock - Determines which channel is currently being input on the Audio Serial Data 3 LRCK I Input pin, SDATA. Master Clock - Frequency must be 256x, 384x, or 512x the input sample rate in BRM and either 4 MCLK I 128x or 192x the input sample rate in HRM. 5 AOUTR O Analog Right Channel Output - Typically 3.5 Vp-p for a full-scale input signal. 6 AGND I Analog Ground - Analog ground reference is 0V. 7 VA I Analog Power - Analog power supply is nominally +5V. 8 AOUTL O Analog Left Channel Output - Typically 3.5 Vp-p for a full-scale input signal. 3

CS4334/5/8/9 1. TYPICAL CONNECTION DIAGRAM +5V + 0.1µF 1 µF 7 VA 1 SDATA Audio 3.3 µF 560  2 8 Data DEM/SCLK AOUTL LeftAudio Processor + Output 3 LRCK 267k 10 k C RL CS4334 CS4335 CS4338 CS4339 3.3 µF 560  5 AOUTR RightAudio + 4 Output ExternalClock MCLK 267k 10 k C RL RL+560 C = AGND 4Fs(R 560) L 6 Figure 1. Recommended Connection Diagram 4

CS4334/5/8/9 2. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T = 25C.) A SPECIFIED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.) Parameters Symbol Min Nom Max Units DC Power Supply VA 4.75 5.0 5.5 V Ambient Operating Temperature (Power Applied) -KSZ, -KSZR T -10 - +70 C A -DSZ, -DSZR -40 - +85 C ABSOLUTE MAXIMUM RATINGS (AGND = 0V; all voltages with respect to ground.) Parameters Symbol Min Max Units DC Power Supply VA -0.3 6.0 V Input Current, Any Pin Except Supplies I - ±10 mA in Digital Input Voltage V -0.3 VA+0.4 V IND Ambient Operating Temperature (power applied) T -55 125 °C A Storage Temperature T -65 150 °C stg WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 5

CS4334/5/8/9 ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997Hz; Test load R = 10k, C = 10pF (see Figure 2). Fs for Base-Rate Mode = L L 48kHz, Measurement Bandwidth 10 Hz to 20kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz, Measurement Bandwidth 10 Hz to 40kHz, unless otherwise specified.) Base-Rate Mode High-Rate Mode Parameter Symbol Min Typ Max Min Typ Max Unit Dynamic Performance for CS4334/5/8/9-KSZ, -KZSR Dynamic Range (Note 1) 18 to 24-Bit 88 93 - - 90 - dB unweighted 91 96 - 91 96 - dB A-Weighted 86 91 - - 88 - dB 16-Bit unweighted 89 94 - 89 94 - dB A-Weighted Total Harmonic Distortion + Noise (Note 1) THD+N 18 to 24-Bit 0 dB - -88 -83 - -88 -83 dB -20 dB - -73 -68 - -70 -65 dB -60 dB - -33 -28 - -30 -25 dB 16-Bit 0 dB - -86 -81 - -86 -81 dB -20 dB - -71 -66 - -68 -63 dB -60 dB - -31 -26 - -28 -23 dB Interchannel Isolation (1kHz) - 94 - - 95 - dB Dynamic Performance for CS4334-DSZ, -DSZR Dynamic Range (Note 1) 18 to 24-Bit 85 93 - - 90 - dB unweighted 88 96 - 88 96 - dB A-Weighted 83 91 - - 88 - dB 16-Bit unweighted 86 94 - 86 94 - dB A-Weighted Total Harmonic Distortion + Noise (Note 1) THD+N 18 to 24-Bit 0 dB - -88 -82 - -88 -82 dB -20 dB - -73 -65 - -70 -62 dB -60 dB - -33 -25 - -30 -22 dB 16-Bit 0 dB - -86 -70 - -86 -80 dB -20 dB - -71 -63 - -68 -60 dB -60 dB - -31 -23 - -28 -20 dB Interchannel Isolation (1kHz) - 94 - - 95 - dB Notes: 1. One LSB of triangular PDF dither added to data. 6

CS4334/5/8/9 ANALOG CHARACTERISTICS (Continued) Base-Rate Mode High-Rate Mode Parameter Symbol Min Typ Max Min Typ Max Unit Combined Digital and On-chip Analog Filter Response (Note 2) Passband (Note 3) to -0.05dB corner 0 - .4780 - - - Fs to -0.1dB corner - - - 0 - .4650 Fs to -3dB corner 0 - .4996 0 - .4982 Fs Frequency Response 10Hz to 20kHz -.01 - +.08 -.05 - +.2 dB Passband Ripple - - ±.08 - - ±.2 dB StopBand .5465 - - .5770 - - Fs StopBand Attenuation (Note 4) 50 - - 55 - - dB Group Delay tgd - 9/Fs - - 4/Fs - s Passband Group Delay Deviation 0 - 40 kHz - ±0.36/Fs - - ±1.39/Fs - s 0 - 20 kHz - ±0.23/Fs - s De-emphasis Error Fs = 32kHz - - +1.5/+0 dB Fs = 44.1 kHz - - +.05/-.25 (Note 5) dB Fs = 48 kHz - - -.2/-.4 dB Parameters Symbol Min Typ Max Units DC Accuracy Interchannel Gain Mismatch - 0.1 0.4 dB Gain Error - ±5 - % Gain Drift - 100 - ppm/°C Analog Output Full Scale Output Voltage 3.25 3.5 3.75 Vpp Quiescent Voltage V - 2.2 - VDC Q Max AC-Load Resistance (Note 6) R - 3 - k L Max Load Capacitance (Note 6) C - 100 - pF L Notes: 2. Filter response is not tested but is guaranteed by design. 3. Response is clock dependent and will scale with Fs. Note that the response plots (Figures15-22) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 4. For Base-Rate Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For High-Rate Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. 5. De-emphasis is not available in High-Rate Mode. 6. Refer to Figure3. 7

CS4334/5/8/9 POWER AND THERMAL CHARACTERISTICS Parameters Symbol Min Typ Max Units Power Supplies Power Supply Current normal operation I - 15 19 mA A power-down state I - 40 - A A Power Dissipation (Note 7) normal operation - 75 104 mW power-down - 0.2 - mW Package Thermal Resistance  - 110 - °C/Watt JA Power Supply Rejection Ratio (1 kHz) PSRR - 79 - dB Notes: 7. Refer to Figure4. Max Power Dissipation is measured at VA=5.5V. 10 µF AOUTx Vout R C L L AGND Figure 2. Output Test Load 8

CS4334/5/8/9 125 75 pF) 100 70 RM C (L B d -- 75 W) 65 M oa m H R ve L 50 SafeR Oegpieornating wer ( 60 citi Po a p 25 Ca 55 2.5 5 10 15 20 50 30 40 50 60 70 80 90 100 3 Resistive Load -- R L (k) Sample Rate (kHz) Figure 3. Maximum Loading Figure 4. Power vs. Sample Rate DIGITAL INPUT CHARACTERISTICS Parameters Symbol Min Typ Max Units High-Level Input Voltage V 2.0 - - V IH Low-Level Input Voltage V - - 0.8 V IL Input Leakage Current (Note 8) I - - ±10 A in Input Capacitance - 8 - pF Notes: 8. I for CS433X LRCK is ±20A max. in 9

CS4334/5/8/9 SWITCHING CHARACTERISTICS Parameters Symbol Min Typ Max Units Input Sample Rate Fs 2 - 100 kHz MCLK Pulse Width High MCLK/LRCK = 512 10 - 1000 ns MCLK Pulse Width Low MCLK/LRCK = 512 10 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 384 or 192 21 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 384 or 192 21 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 256 or 128 31 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 256 or 128 31 - 1000 ns External SCLK Mode LRCK Duty Cycle (External SCLK only) 40 50 60 % SCLK Pulse Width Low t 20 - - ns sclkl SCLK Pulse Width High t 20 - - ns sclkh SCLK Period Base-Rate Mode tsclkw ----------1------------ - - ns 128Fs MCLK / LRCK = 512, 256 or 384 SCLK Period High-Rate Mode t 1 - - ns sclkw ------------------- MCLK / LRCK = 128 or 192 64Fs SCLK rising to LRCK edge delay t 20 - - ns slrd SCLK rising to LRCK edge setup time t 20 - - ns slrs SDATA valid to SCLK rising setup time t 20 - - ns sdlrs SCLK rising to SDATA hold time t 20 - - ns sdh Internal SCLK Mode LRCK Duty Cycle (Internal SCLK only) (Note 9) - 50 - % t - - ns SCLK Period (Note 10) sclkw -------1---------- SCLK t - - s sclkr SCLK rising to LRCK edge tsclkw ------------------ 2 t - - ns sdlrs SDATA valid to SCLK rising setup time ----------1------------+10 512Fs t - - ns SCLK rising to SDATA hold time sdh 1 MCLK / LRCK = 512, 256 or 128 ---5---1----2------F----s--+15 t - - ns sdh SCLK rising to SDATA hold time 1 MCLK / LRCK = 384 or 192 ----------------------+15 384Fs Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50% 1/2 MCLK Period. 10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK ratio. (See figures Figures10-13) 10

CS4334/5/8/9 LRCK t t slrs sclkh t slrd t sclkl SCLK t t sdh sdlrs SDATA Figure 5. External Serial Mode Input Timing LRCK t sclkr SDATA t sclkw t t sdlrs sdh *INTERNAL SCLK Figure 6. Internal Serial Mode Input Timing The SCLK pulses shown are internal to the CS4334/5/8/9. LRCK MCLK 1 N N 2 *INTERNAL SCLK SDATA Figure 7. Internal Serial Clock Generation * The SCLK pulses shown are internal to the CS4334/5/8/9. N equals MCLK divided by SCLK 11

CS4334/5/8/9 3. GENERAL DESCRIPTION The CS4334 family of devices offers a complete stereo digital-to-analog system including digital interpolation, fourth-order delta-sigma digital-to-analog conversion, digital de-emphasis and analog filtering, as shown in Figure8. This architecture provides a high tolerance to clock jitter. The primary purpose of using delta-sigma modulation techniques is to avoid the limitations of resistive laser trimmed digital-to-analog converter architectures by using an inherently linear 1-bit digital-to-analog converter. The advan- tages of a 1-bit digital-to-analog converter include: ideal differential linearity, no distortion mechanisms due to resis- tor matching errors and no linearity drift over time and temperature due to variations in resistor values. The CS4334 family of devices supports two modes of operation. The devices operate in Base Rate Mode (BRM) when MCLK/LRCK is 256, 384 or 512 and in High Rate Mode (HRM) when MCLK/LRCK is 128 or 192. High Rate Mode allows input sample rates up to 100 kHz. 3.1 Digital Interpolation Filter The digital interpolation filter increases the sample rate, Fs, by a factor of 4 and is followed by a 32×digital sample-and-hold (16× in HRM). This filter eliminates images of the baseband audio signal which exist at multiples of the input sample rate. The resulting frequency spectrum has images of the input signal at mul- tiples of 4Fs. These images are easily removed by the on-chip analog low-pass filter and a simple external analog filter (see Figure1). 3.2 Delta-Sigma Modulator The interpolation filter is followed by a fourth order delta-sigma modulator which converts the interpolation filter output into 1-bit data at a rate of 128Fs in BRM (or 64Fs in HRM). 3.3 Switched-Capacitor DAC The delta-sigma modulator is followed by a digital-to-analog converter which translates the 1-bit data into a series of charge packets. The magnitude of the charge in each packet is determined by sampling of a volt- age reference onto a switched capacitor, where the polarity of each packet is controlled by the 1-bit data. This technique greatly reduces the sensitivity to clock jitter and provides low-pass filtering of the output. 3.4 Analog Low-Pass Filter The final signal stage consists of a continuous-time low-pass filter which serves to smooth the output and attenuate out-of-band noise. Analog Digital Delta-Sigma Analog Interpolator DAC Low-Pass Input Modulator Output Filter Figure 8. System Block Diagram 12

CS4334/5/8/9 4. SYSTEM DESIGN The CS4334 family accepts data at standard audio sample rates including 48, 44.1 and 32kHz in BRM and 96, 88.2 and 64kHz in HRM. Audio data is input via the serial data input pin (SDATA). The Left/Right Clock (LRCK) defines the channel and delineation of data, and the Serial Clock (SCLK) clocks audio data into the input data buffer. The CS4334/5/8/9 differ in serial data formats as shown in Figures10-13. 4.1 Master Clock MCLK must be either 256x, 384x or 512x the desired input sample rate in BRM and either 128x or 192x the desired input sample rate in HRM. The LRCK frequency is equal to Fs, the frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected automatically during the initialization sequence by counting the number of MCLK transitions during a single LRCK period. Internal dividers are set to generate the proper clocks. Table1 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK and SCLK must be synchronous. MCLK (MHz) LRCK HRM BRM (kHz) 128x 192x 256x 384x 512x 32 4.0960 6.1440 8.1920 12.2880 16.3840 44.1 5.6448 8.4672 11.2896 16.9344 22.5792 48 6.1440 9.2160 12.2880 18.4320 24.5760 64 8.1920 12.2880 - - - 88.2 11.2896 16.9344 - - - 96 12.2880 18.4320 - - - Table 1. Common Clock Frequencies 4.2 Serial Clock The serial clock controls the shifting of data into the input data buffers. The CS4334 family supports both external and internal serial clock generation modes. Refer to Figures10-13 for data formats. 4.2.1 External Serial Clock Mode The CS4334 family will enter the External Serial Clock Mode when 16 low to high transitions are detected on the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Se- rial Clock Mode and de-emphasis filter cannot be accessed. The CS4334 family will switch to Internal Se- rial Clock Mode if no low to high transitions are detected on the DEM/SCLK pin for 2 consecutive frames of LRCK. Refer to Figure14. 4.2.2 Internal Serial Clock Mode In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and LRCK. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon data format. Operation in this mode is identical to operation with an external serial clock synchronized with LRCK. This mode allows access to the digital de-emphasis function. Refer to Figures10 - 14 for details. 13

CS4334/5/8/9 4.3 De-Emphasis The CS4334 family includes on-chip digital de-emphasis. Figure9 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for 5 consecutive falling edges of LRCK. This function is available only in the internal serial clock mode. Gain dB T1=50 µs 0dB T2 = 15 µs -10dB F1 F2 Frequency 3.183 kHz 10.61 kHz Figure 9. De-Emphasis Curve (Fs = 44.1kHz) 4.4 Initialization and Power-Down The Initialization and Power-Down sequence flow chart is shown in Figure14. The CS4334 family enters the Power-Down State upon initial power-up. The interpolation filters and delta-sigma modulators are reset, and the internal voltage reference, one-bit digital-to-analog converters and switched-capacitor low-pass fil- ters are powered down. The device will remain in the Power-Down mode until MCLK and LRCK are present. Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Finally, power is applied to the D/A converters and switched-capacitor filters, and the analog outputs will ramp to the quiescent voltage, V . Q 4.5 Output Transient Control The CS4334 family uses Popguard® technology to minimize the effects of output transients during power- up and power-down. This technique eliminates the audio transients commonly produced by single-ended single-supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. To make best use of this feature, it is necessary to understand its operation. When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Af- ter a short delay of approximately 1000 sample periods, each output begins to ramp towards its quiescent voltage, V . Approximately 10,000 sample cycles later, the outputs reach V and audio output begins. This Q Q gradual voltage ramping allows time for the external DC-blocking capacitor to charge to V , effectively Q blocking the quiescent DC voltage. To prevent transients at power-down, the device must first enter its power-down state. This is accomplished by removing MCLK or LRCK. When this occurs, audio output ceases and the internal output buffers are dis- connected from AOUTL and AOUTR. A soft-start current sink is substituted in place of AOUTL and AOUTR which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready for the next power-on. To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning off the power or exiting the power-down state. If full discharge does not occur, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power- 14

CS4334/5/8/9 down state is related to the value of the DC-blocking capacitance. For example, with a 3.3F capacitor, the time that the device must remain in the power-down state will be approximately 0.4 seconds. 4.6 Grounding and Power Supply Decoupling As with any high resolution converter, the CS4334 family requires careful attention to power supply and grounding arrangements to optimize performance. Figure 1 shows the recommended power arrangement with VA connected to a clean +5V supply. For best performance, decoupling capacitors should be located as close to the device package as possible with the smallest capacitor closest. 4.7 Analog Output and Filtering The analog filter present in the CS4334 family is a switched-capacitor filter followed by a continuous time low pass filter. Its response, combined with that of the digital interpolator, is given in Figures15 - 22. LRCK Left Channel Right Channel SCLK SDATA MSB-1 -2 -3 -4 -5 +5+4+3+2+1LSB MSB-1 -2 -3 -4 +5+4+3+2+1LSB Internal SCLK Mode External SCLK Mode I²S, 16-Bit data and INT SCLK = 32 Fs if I²S, up to 24-Bit Data MCLK/LRCK = 512, 256 or 128 Data Valid on Rising Edge of SCLK I²S, Up to 24-Bit data and INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192 Figure 10. CS4334 Data Format (I²S) LRCK Left Channel Right Channel SCLK SDATA MSB-1 -2 -3 -4 -5 +5+4+3+2+1LSB MSB-1 -2 -3 -4 +5+4+3+2+1LSB Internal SCLK Mode External SCLK Mode Left Justified, up to 24-Bit Data Left Justified, up to 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 Data Valid on Rising Edge of SCLK INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192 Figure 11. CS4335 Data Format 15

CS4334/5/8/9 LRCK Left Channel Right Channel SCLK SDATA 151413121110 9 8 7 6 5 4 3 2 1 0 151413121110 9 8 7 6 5 4 3 2 1 0 32 clocks Internal SCLK Mode External SCLK Mode Right Justified, 16-Bit Data Right Justified, 16-Bit Data INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128 Data Valid on Rising Edge of SCLK INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192 SCLK Must Have at Least 32 Cycles per LRCK Period Figure 12. CS4338 Data Format LRCK Left Channel Right Channel SCLK SDATA 1 0 1716151413121110 9 8 7 6 5 4 3 2 1 0 17 16151413121110 9 8 7 6 5 4 3 2 1 0 32 clocks Internal SCLK Mode External SCLK Mode Right Justified, 18-Bit Data Right Justified, 18-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 Data Valid on Rising Edge of SCLK INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192 SCLK Must Have at Least 36 Cycles per LRCK Period Figure 13. CS4339 Data Format 16

CS4334/5/8/9 Figure 14. CS4334/5/8/9 Initialization and Power-Down Sequence 17

CS4334/5/8/9 4.8 Overall Base-Rate Frequency Response Figure 15. Stopband Rejection Figure 16. Transition Band Figure 17. Transition Band Figure 18. Passband Ripple 18

CS4334/5/8/9 4.9 Overall High-Rate Frequency Response Figure 19. Stopband Rejection Figure 20. Transition Band Figure 21. Transition Band Figure 22. Passband Ripple 19

CS4334/5/8/9 4.10 Base Rate Mode Performance Plots ++0+00 ++0+00 -1-1-0100 -1-1-0100 -2-2-0200 -2-2-0200 -3-3-0300 -3-3-0300 -4-4-0400 -4-4-0400 -5-5-0500 -5-5-0500 dBr ABAdr dBr A---678---876---000876000000 dBr ABAdr dBr A---678---876---000876000000 -9-9-0900 -9-9-0900 -1-10-010000 -1-10-010000 -1-11-110100 -1-11-110100 -1-12-210200 -1-12-210200 -1-13-310300 -1-13-310300 -1-14-410400 222kkk 444kkk 666kkk 888kkk 11H1HH000zkkzzk 111222kkk 111444kkk 111666kkk 111888kkk 22220000kkkk -1-14-410400 222kkk 444kkk 666kkk 888kkk 1H11HH000zzkzkk 111222kkk 111444kkk 111666kkk 111888kkk 222000kkk (16k FFT of a 1 kHz input signal) (16k FFT of a 1 kHz input signal) Figure 23. 0 dBFS FFT (BRM) Figure 24. -60 dBFS FFT (BRM) +++000 +++000 -1-1-0100 -1-1-1000 -2-2-0200 -2-2-2000 -3-3-0300 -3-3-3000 -4-4-0400 -4-4-4000 -5-5-0500 -5-5-5000 dBr ABAdr dBr A---678---876---000876000000 BAdr dBr AdBr A---678---876---876000000000 -9-9-0900 --99-9000 -1-10-100000 -1-1-0100000 -1-11-110100 -1-1-1111000 -1-12-120200 -1-1-2122000 -1-13-130300 -1-1-3133000 -1-14-140400 222kkk 444kkk 666kkk 888kkk 1H11HH000zkzzkk 111222kkk 111444kkk 111666kkk 111888kkk 222000kkk -1-1-4144000 22k2kk 444kkk 666kkk 888kkk 1H11HH000zzzkkk 111222kkk 111444kkk 111666kkk 111888kkk 2202k00kk (16k FFT with no input signal) (16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals) Figure 25. Idle Channel Noise FFT (BRM) Figure 26. Twin Tone IMD FFT (BRM) -6-600 +++000 -1-1-1000 -7-700 -2-2-2000 -3-3-3000 d -8-800 -4-4-4000 BAdBr Ar -9-900 dBr ABAd rdBAr --56--65--65000000 -7-7-7000 -8-8-8000 -1-10000 -9-9-9000 -1-10-010000 -1-11100 --6600 --5500 --4400 dd-BB-33FF00SS --2200 --1100 ++00 -1-11-110100222000 555000 111000000 222000000 555000000HHHzzz 111kkk 222kkk 555kkk 111000kkk 222000kkk (THD+N plots measured using a 1kHz 24-bit dithered input signal) (THD+N plots measured using a 1kHz 24-bit dithered input signal) Figure 27. THD+N vs. Amplitude (BRM) Figure 28. THD+N vs. Frequency (BRM) All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain System Two Cascade. 20

CS4334/5/8/9 4.11 High Rate Mode Performance Plots ++0+00 +++000 -1-1-0100 -1-1-0100 -2-2-0200 -2-2-0200 -3-3-0300 -3-3-0300 -4-4-0400 -4-4-0400 -5-5-0500 -5-5-0500 dBr ABAdr dBr A---678---876---000876000000 dBr ABAdr dBr A---678---876---000876000000 -9-9-0900 -9-9-0900 -1-10-010000 -1-10-100000 -1-11-110100 -1-11-110100 -1-12-210200 -1-12-120200 -1-13-310300 -1-13-130300 -1-14-410400 222kkk 444kkk 666kkk 888kkk 11HH1H000zzkzkk 111222kkk 111444kkk 111666kkk 111888kkk 222000kkk -1-14-140400 222kkk 444kkk 666kkk 888kkk 111HHH00z0kzkzk 111222kkk 111444kkk 111666kkk 11188k8kk 222000kkk (16k FFT of a 1 kHz input signal) (16k FFT of a 1 kHz input signal) Figure 29. 0 dBFS FFT (HRM) Figure 30. -60 dBFS FFT (HRM) Audio Precision D-A CCIF IMD vs AMPLITUDE 08/05/99 11:11:36 ++0+00 +++000 -1-10-100 -1--11000 -2-20-200 -2--22000 -3-30-300 -3--33000 -4-40-400 -4--44000 -5-50-500 -5--55000 dBr ABAdr dBr A---678---876000---876000000 BAdr dBr AdBr A---678------876876000000000 -9-90-900 -9--99000 -1-10-010000 -1-1-0100000 -1-11-110100 -1-1-1111000 -1-12-210200 -1-1-2122000 -1-13-310300 -1-1-3133000 -1-14-410400 222kkk 444kkk 666kkk 888kkk 11HH1H000zzkkzk 111222kkk 111444kkk 111666kkk 111888kkk 222000kkk -1-1-4144000 222kkk 444kkk 666kkk 888kkk 111HH000zkzkkHz 111222kkk 111444kkk 111666kkk 11188k8kk 22200k0kk (16k FFT with no input signal) (16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals) Figure 31. Idle Channel Noise FFT (HRM) Figure 32. Twin Tone IMD FFT (HRM) -6-600 +++000 -1--11000 -7-700 -2--22000 -3--33000 d -8-800 d -4--44000 BdBr Ar Br dBr Ar dAB--56----6565000000 A -9-900 A --7-77000 --8-88000 -1-10000 -9--99000 -1--11000000 -1-11100--6600 --5500 --4400 --3300 --2200 --1100 ++00 -1--11111000222000 555000 111000000 222000000 555000000 111kkk 222kkk 555kkk 111000kkk 222000kkk ddBBFFSS HHHzzz (THD+N plots measured using a 1kHz 24-bit dithered input signal) (THD+N plots measured using a 1kHz 24-bit dithered input signal) Figure 33. THD+N vs. Amplitude (HRM) Figure 34. THD+N vs. Frequency (HRM) All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain System Two Cascade. 21

CS4334/5/8/9 5. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17- 1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in deci- bels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 6. REFERENCES 1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. CDB4334/5/8/9 Evaluation Board Datasheet 22

CS4334/5/8/9 7. PACKAGE DIMENSIONS 8L SOIC (150 MIL BODY) PACKAGE DRAWING E H 1 b D c SEATING  PLANE A L e A1 INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 b 0.013 0.020 0.33 0.51 c 0.007 0.010 0.19 0.25 D 0.189 0.197 4.80 5.00 E 0.150 0.157 3.80 4.00 e 0.040 0.060 1.02 1.52 H 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27  0° 8° 0° 8° JEDEC # : MS-012 23

CS4334/5/8/9 8. ORDERING INFORMATION Model Temperature Package Container Serial Interface CS4334-KSZ -10 to +70 °C 8-pin Plastic SOIC, lead free Rail 16 to 24-bit, I²S CS4335-KSZ -10 to +70 °C 8-pin Plastic SOIC, lead free Rail 16 to 24-bit, left justified CS4338-KSZ -10 to +70 °C 8-pin Plastic SOIC, lead free Rail 16-bit, right justified CS4339-KSZ -10 to +70 °C 8-pin Plastic SOIC, lead free Rail 18-bit, right justified, 32 F Internal SCLK mode s CS4334-KSZR -10 to +70 °C 8-pin Plastic SOIC, lead free Tape & reel 16 to 24-bit, I²S CS4335-KSZR -10 to +70 °C 8-pin Plastic SOIC, lead free Tape & reel 16 to 24-bit, left justified CS4338-KSZR -10 to +70 °C 8-pin Plastic SOIC, lead free Tape & reel 16-bit, right justified CS4339-KSZR -10 to +70 °C 8-pin Plastic SOIC, lead free Tape & reel 18-bit, right justified, 32 F Internal SCLK mode s CS4334-DSZ -40 to +85 °C 8-pin Plastic SOIC, lead free Rail 16 to 24-bit, I²S CS4334-DSZR -40 to +85 °C 8-pin Plastic SOIC, lead free Tape & reel 16 to 24-bit, I²S 9. FUNCTIONAL COMPATIBILITY CS4330-KS  CS4339-KSZx CS4331-KS  CS4334-KSZx CS4333-KS  CS4338-KSZx 24

CS4334/5/8/9 10.REVISION HISTORY Revision Changes Corrected “B” to “b” and “C” to “c” to match drawing in Package Dimensions. F5 Updated legal text. Changed “One-half LSB...” to “One LSB of triangular PDF dither added to data” in footnote to Analog Charac- teristics specification table. F6 Added tape and reel options to the Ordering Information section and updated references to -KSZ and -DSZ in specification tables to show -KSZR and -DSZR options. Removed CS4335-DSZ, CS4338-DSZ, CS4339-DSZ, CS4335-DSZR, CS4338-DSZR, and CS4339-DSZR in F7 and Analog Characteristics specification table and Ordering Information. Removed CS4330-BS, CS4331-BS, and CS4333-BS from Functional Compatibility. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Cirrus Logic products. Use of Cirrus Logic products may entail a choice between many different modes of operation, some or all of which may require action by the user, and some or all of which may be optional. Nothing in these materials should be interpreted as instructions or suggestions to choose one mode over another. Likewise, description of a single mode should not be interpreted as a suggestion that other modes should not be used or that they would not be suitable for operation. Features and operations described herein are for illustrative purposes only. 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Cirrus Logic, Cirrus, the Cirrus Logic logo design, and SoundClear are among the trademarks of Cirrus Logic. Other brand and product names may be trademarks or service marks of their respective owners. Copyright © 2012–2017 Cirrus Logic, Inc. All rights reserved. 25

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: C irrus Logic: CS4334-DSZ CS4334-KSZ CS4334-KSZR CS4335-KSZ CS4338-KSZ CS4338-KSZR CS4339-KSZR CS4339- KSZ CS4334-DSZR CS4335-KSZR CS4334-BS CS4334-DSR CS4334-BSR