CS2000-CP Fractional-N Clock Synthesizer & Clock Multiplier Features General Description  Delta-Sigma Fractional-N Frequency Synthesis The CS2000-CP is an extremely versatile system – Generates a Low Jitter 6 - 75 MHz Clock clocking device that utilizes a programmable phase from an 8 - 75 MHz Reference Clock lock loop. The CS2000-CP is based on a hybrid ana-  Clock Multiplier / Jitter Reduction log-digital PLL architecture comprised of a unique – Generates a Low Jitter 6 - 75 MHz Clock combination of a Delta-Sigma Fractional-N Frequency from a Jittery or Intermittent 50 Hz to Synthesizer and a Digital PLL. This architecture allows 30 MHz Clock Source for both frequency synthesis/clock generation from a  Highly Accurate PLL Multiplication Factor stable reference clock as well as generation of a low- jitter clock relative to an external noisy synchronization – Maximum Error Less Than 1 PPM in High- Resolution Mode clock. The design is also unique in that it can generate low-jitter clocks relative to noisy external synchroniza-  I²C™ / SPI™ Control Port tion clocks at frequencies as low as 50 Hz. The  Configurable Auxiliary Output CS2000-CP supports both I²C and SPI for full software  Flexible Sourcing of Reference Clock control. – External Oscillator or Clock Source The CS2000-CP is available in a 10-pin MSOP pack- – Supports Inexpensive Local Crystal age in Commercial (-10°C to +70°C) and Automotive  Minimal Board Space Required (-40°C to +85°C) grades. Customer development kits – No External Analog Loop-filter are also available for device evaluation. Please see Components “Ordering Information” on page36 for complete details. 3.3 V Timing Reference I²C/SPI I²C / SPI Frequency Reference Software Control Auxiliary PLL Output Output Lock Indicator 8 MHz to 75 MHz Fractional-N 6 to 75 MHz Low-Jitter Timing Frequency Synthesizer PLL Output Reference N Output to Input Clock Ratio 50 Hz to 30 MHz Digital PLL & Fractional Frequency N Logic Reference Output to Input Clock Ratio Copyright  Cirrus Logic, Inc. 2010 MAY '10 http://www.cirrus.com (All Rights Reserved) DS761F2

CS2000-CP TABLE OF CONTENTS 1. PIN DESCRIPTION .................................................................................................................................5 2. TYPICAL CONNECTION DIAGRAM .....................................................................................................6 3. CHARACTERISTICS AND SPECIFICATIONS ......................................................................................7 RECOMMENDED OPERATING CONDITIONS ....................................................................................7 ABSOLUTE MAXIMUM RATINGS ........................................................................................................7 DC ELECTRICAL CHARACTERISTICS ................................................................................................7 AC ELECTRICAL CHARACTERISTICS ................................................................................................8 PLL PERFORMANCE PLOTS ...............................................................................................................9 CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT .................................................10 CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ...............................................11 4. ARCHITECTURE OVERVIEW .............................................................................................................12 4.1 Delta-Sigma Fractional-N Frequency Synthesizer .........................................................................12 4.2 Hybrid Analog-Digital Phase Locked Loop ....................................................................................12 4.2.1 Fractional-N Source Selection for the Frequency Synthesizer ..............................................13 5. APPLICATIONS ...................................................................................................................................14 5.1 Timing Reference Clock Input ........................................................................................................14 5.1.1 Internal Timing Reference Clock Divider ...............................................................................14 5.1.2 Crystal Connections (XTI and XTO) ......................................................................................15 5.1.3 External Reference Clock (REF_CLK) ..................................................................................15 5.2 Frequency Reference Clock Input, CLK_IN ...................................................................................15 5.2.1 CLK_IN Skipping Mode .........................................................................................................15 5.2.2 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................17 5.3 Output to Input Frequency Ratio Configuration .............................................................................19 5.3.1 User Defined Ratio (RUD), Frequency Synthesizer Mode ....................................................19 5.3.2 User Defined Ratio (RUD), Hybrid PLL Mode .......................................................................19 5.3.3 Ratio Modifier (R-Mod) ..........................................................................................................20 5.3.4 Effective Ratio (REFF) ..........................................................................................................20 5.3.5 Fractional-N Source Selection ...............................................................................................21 5.3.6 Ratio Configuration Summary ...............................................................................................22 5.4 PLL Clock Output ...........................................................................................................................23 5.5 Auxiliary Output ..............................................................................................................................23 5.6 Clock Output Stability Considerations ............................................................................................24 5.6.1 Output Switching ...................................................................................................................24 5.6.2 PLL Unlock Conditions ..........................................................................................................24 5.7 Required Power Up Sequencing ....................................................................................................24 6. SPI / I²C CONTROL PORT ...................................................................................................................24 6.1 SPI Control .....................................................................................................................................25 6.2 I²C Control ......................................................................................................................................25 6.3 Memory Address Pointer ...............................................................................................................27 6.3.1 Map Auto Increment ..............................................................................................................27 7. REGISTER QUICK REFERENCE ........................................................................................................27 8. REGISTER DESCRIPTIONS ................................................................................................................28 8.1 Device I.D. and Revision (Address 01h) ........................................................................................28 8.1.1 Device Identification (Device[4:0]) - Read Only .....................................................................28 8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................28 8.2 Device Control (Address 02h) ........................................................................................................28 8.2.1 Unlock Indicator (Unlock) - Read Only ..................................................................................28 8.2.2 Auxiliary Output Disable (AuxOutDis) ...................................................................................28 8.2.3 PLL Clock Output Disable (ClkOutDis) ..................................................................................29 8.3 Device Configuration1 (Address 03h) ...........................................................................................29 8.3.1 R-Mod Selection (RModSel[2:0]) ...........................................................................................29 8.3.2 Ratio Selection (RSel[1:0]) ....................................................................................................29 2 DS761F2

CS2000-CP 8.3.3 Auxiliary Output Source Selection (AuxOutSrc[1:0]) .............................................................29 8.3.4 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................30 8.4 Device Configuration2 (Address 04h) ...........................................................................................30 8.4.1 Lock Clock Ratio (LockClk[1:0]) ............................................................................................30 8.4.2 Fractional-N Source for Frequency Synthesizer (FracNSrc) .................................................30 8.5 Global Configuration (Address 05h) ...............................................................................................30 8.5.1 Device Configuration Freeze (Freeze) ..................................................................................30 8.5.2 Enable Device Configuration Registers 2 (EnDevCfg2) ........................................................31 8.6 Ratio 0-3 (Address 06h - 15h) ......................................................................................................31 8.7 Function Configuration1 (Address 16h) ........................................................................................31 8.7.1 Clock Skip Enable (ClkSkipEn) .............................................................................................31 8.7.2 AUX PLL Lock Output Configuration (AuxLockCfg) ..............................................................32 8.7.3 Reference Clock Input Divider (RefClkDiv[1:0]) ....................................................................32 8.8 Function Configuration2 (Address 17h) ........................................................................................32 8.8.1 Enable PLL Clock Output on Unlock (ClkOutUnl) .................................................................32 8.8.2 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................32 8.9 Function Configuration3 (Address 1Eh) ........................................................................................33 8.9.1 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................33 9. CALCULATING THE USER DEFINED RATIO ....................................................................................34 9.1 High Resolution 12.20 Format .......................................................................................................34 9.2 High Multiplication 20.12 Format ...................................................................................................34 10. PACKAGE DIMENSIONS ..................................................................................................................35 THERMAL CHARACTERISTICS .........................................................................................................35 11. ORDERING INFORMATION ..............................................................................................................36 12. REFERENCES ....................................................................................................................................36 13. REVISION HISTORY ..........................................................................................................................36 LIST OF FIGURES Figure 1. Typical Connection Diagram ........................................................................................................6 Figure 2. CLK_IN Sinusoidal Jitter Tolerance .............................................................................................9 Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................9 Figure 4. CLK_IN Random Jitter Rejection and Tolerance .........................................................................9 Figure 5. Control Port Timing - I²C Format ................................................................................................10 Figure 6. Control Port Timing - SPI Format (Write Only) ..........................................................................11 Figure 7. Delta-Sigma Fractional-N Frequency Synthesizer .....................................................................12 Figure 8. Hybrid Analog-Digital PLL ..........................................................................................................13 Figure 9. Fractional-N Source Selection Overview ...................................................................................13 Figure 10. Internal Timing Reference Clock Divider .................................................................................14 Figure 11. REF_CLK Frequency vs. a Fixed CLK_OUT ...........................................................................14 Figure 12. External Component Requirements for Crystal Circuit ............................................................15 Figure 13. CLK_IN removed for > 223 SysClk cycles ................................................................................16 Figure 14. CLK_IN removed for < 223 SysClk cycles but > t CS ..................................................................................16 Figure 15. CLK_IN removed for < t CS ..................................................................................................................................17 Figure 16. Low bandwidth and new clock domain ....................................................................................18 Figure 17. High bandwidth with CLK_IN domain re-use ...........................................................................18 Figure 18. Ratio Feature Summary ...........................................................................................................22 Figure 19. PLL Clock Output Options .......................................................................................................23 Figure 20. Auxiliary Output Selection ........................................................................................................23 Figure 21. Control Port Timing in SPI Mode .............................................................................................25 Figure 22. Control Port Timing, I²C Write ..................................................................................................26 Figure 23. Control Port Timing, I²C Aborted Write + Read .......................................................................26 DS761F2 3

CS2000-CP LIST OF TABLES Table 1. Ratio Modifier ..............................................................................................................................20 Table 2. Example 12.20 R-Values ............................................................................................................34 Table 3. Example 20.12 R-Values ............................................................................................................34 4 DS761F2

CS2000-CP 1. PIN DESCRIPTION VD 1 10 SDA/CDIN GND 2 9 SCL/CCLK CLK_OUT 3 8 AD0/CS AUX_OUT 4 7 XTI/REF_CLK CLK_IN 5 6 XTO Pin Name # Pin Description VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections. GND 2 Ground (Input) - Ground reference. CLK_OUT 3 PLL Clock Output (Output) - PLL clock output. 4 Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks, AUX_OUT or a status signal, depending on register configuration. CLK_IN 5 Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference. 6 Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) - XTO 7 XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input XTI/REF_CLK clock. REF_CLK is an input for an externally generated low-jitter reference clock. 8 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C AD0/CS Mode. CS is the chip select signal in SPI Mode. 9 Control Port Clock (Input) - SCL/CCLK is the serial clock for the serial control port in I²C and SPI SCL/CCLK mode. 10 Serial Control Data (Input/Output) - SDA is the data I/O line in I²C Mode. CDIN is the input data SDA/CDIN line for the control port interface in SPI Mode. DS761F2 5

CS2000-CP 2. TYPICAL CONNECTION DIAGRAM Note1 Notes: +3.3 V 1. Resistors 0.1 µF 1 µF required for I2C 2 kΩ 2 kΩ operation. VD SCL/CCLK System MicroController SDA/CDIN AD0/CS CS2000-CP To circuitry which requires Frequency Reference CLK_IN CLK_OUT a low-jitter clock 1 XTI/REF_CLK AUX_OUT To other circuitry or or Microcontroller 2 XTO GND Low-Jitter REF_CLK Timing Reference 1 N.C. x XTO or Crystal XTI 2 XTO 40 pF 40 pF Figure 1. Typical Connection Diagram 6 DS761F2

CS2000-CP 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0V; all voltages with respect to ground. (Note 1) Parameters Symbol Min Typ Max Units DC Power Supply VD 3.1 3.3 3.5 V Ambient Operating Temperature (Power Applied) Commercial Grade T -10 - +70 °C AC Automotive Grade T -40 - +85 °C AD Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. ABSOLUTE MAXIMUM RATINGS GND = 0V; all voltages with respect to ground. Parameters Symbol Min Max Units DC Power Supply VD -0.3 6.0 V Input Current I - ±10 mA IN Digital Input Voltage (Note 2) V -0.3 VD + 0.4 V IN Ambient Operating Temperature (Power Applied) T -55 125 °C A Storage Temperature T -65 150 °C stg WARNING:Operation at or beyond these limits may result in permanent damage to the device. Notes: 2. The maximum over/under voltage is limited by the input current except on the power supply pin. DC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5V; T = -10°C to +70°C (Commercial Grade); A T = -40°C to +85°C (Automotive Grade). A Parameters Symbol Min Typ Max Units Power Supply Current - Unloaded (Note 3) I - 12 18 mA D Power Dissipation - Unloaded (Note 3) P - 40 60 mW D Input Leakage Current I - - ±10 µA IN Input Capacitance I - 8 - pF C High-Level Input Voltage V 70% - - VD IH Low-Level Input Voltage V - - 30% VD IL High-Level Output Voltage (I = -1.2 mA) V 80% - - VD OH OH Low-Level Output Voltage (I = 1.2 mA) V - - 20% VD OH OL Notes: 3. To calculate the additional current consumption due to loading (per output pin), multiply clock output frequency by load capacitance and power supply voltage. For example, f (49.152MHz) * C (15pF) * VD(3.3V)=2.4mA of additional current due to CLK_OUT L these loading conditions on CLK_OUT. DS761F2 7

CS2000-CP AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T = -10°C to +70°C (Commercial Grade); A T =-40°C to +85°C (Automotive Grade); C =15pF. A L Parameters Symbol Conditions Min Typ Max Units Crystal Frequency f RefClkDiv[1:0] = 10 8 - 14 MHz XTAL Fundamental Mode XTAL RefClkDiv[1:0] = 01 16 - 28 MHz RefClkDiv[1:0] = 00 32 - 50 MHz Reference Clock Input Frequency f RefClkDiv[1:0] = 10 8 - 14 MHz REF_CLK RefClkDiv[1:0] = 01 16 - 28 MHz RefClkDiv[1:0] = 00 32 - 56 MHz Reference Clock Input Duty Cycle D 45 - 55 % REF_CLK Internal System Clock Frequency f 8 14 MHz SYS_CLK Clock Input Frequency f 50 Hz - 30 MHz CLK_IN Clock Input Pulse Width (Note 4) pw f < f /96 2 - - UI CLK_IN CLK_IN SYS_CLK f > f /96 10 - - ns CLK_IN SYS_CLK Clock Skipping Timeout t (Notes 5, 6) 20 - - ms CS Clock Skipping Input Frequency f (Note 6) 50 Hz - 80 kHz CLK_SKIP PLL Clock Output Frequency f 6 - 75 MHz CLK_OUT PLL Clock Output Duty Cycle t Measured at VD/2 45 50 55 % OD Clock Output Rise Time t 20% to 80% of VD - 1.7 3.0 ns OR Clock Output Fall Time t 80% to 20% of VD - 1.7 3.0 ns OF Period Jitter t (Note 7) - 70 - ps rms JIT Base Band Jitter (100Hz to 40 kHz) (Notes 7, 8) - 50 - ps rms Wide Band JItter (100Hz Corner) (Notes 7, 9) - 175 - ps rms PLL Lock Time - CLK_IN (Note 10) t f < 200 kHz - 100 200 UI LC CLK_IN f > 200 kHz - 1 3 ms CLK_IN PLL Lock Time - REF_CLK t f = 8 to 75 MHz - 1 3 ms LR REF_CLK Output Frequency Synthesis Resolution (Note 11) f High Resolution 0 - ±0.5 ppm err High Multiplication 0 - ±112 ppm Notes: 4. 1 UI (unit interval) corresponds to t or 1/f . SYS_CLK SYS_CLK 5. t represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that CS PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen- cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will result in larger values of t . CS 6. Only valid in clock skipping mode; See “CLK_IN Skipping Mode” on page15 for more information. 7. f = 24.576MHz; Sample size = 10,000 points; AuxOutSrc[1:0]=11. CLK_OUT 8. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd order 100Hz to 40kHz bandpass filter. 9. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd order 100Hz Highpass filter. 10. 1 UI (unit interval) corresponds to t or 1/f . CLK_IN CLK_IN 11. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the reference clock. 8 DS761F2

CS2000-CP PLL PERFORMANCE PLOTS Test Conditions (unless otherwise specified): VD=3.3V; T =25°C; C =15pF; f =12.288MHz; A L CLK_OUT f =12.288MHz; Sample size=10,000 points; Base Band Jitter (100Hz to 40 kHz); AuxOutSrc[1:0]=11. CLK_IN 10,000 10 1 Hz Bandwidth 1 Hz Bandwidth 128 Hz Bandwidth 128 Hz Bandwidth 0 1,000 c) se -10 u Level ( 100 er (dB)-20 x Input Jitter 10 Jitter Transf-30 Ma -40 1 -50 0.1 -60 1 10 100 1,000 10,000 1 10 100 1000 10000 Input Jitter Frequency (Hz) Input Jitter Frequency (Hz) Figure 2. CLK_IN Sinusoidal Jitter Tolerance Figure 3. CLK_IN Sinusoidal Jitter Transfer Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz). Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz). 1000 1 Hz Bandwidth 128 Hz Bandwidth 100 c) Unlock e s n el ( 10 v e L er ut Jitt 1 p Unlock ut O 0.1 0.01 0.01 0.1 1 10 100 1000 Input Jitter Level (nsec) Figure 4. CLK_IN Random Jitter Rejection and Tolerance DS761F2 9

CS2000-CP CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT Inputs: Logic0=GND; Logic 1=VD; C =20pF. L Parameter Symbol Min Max Unit SCL Clock Frequency f - 100 kHz scl Bus Free-Time Between Transmissions t 4.7 - µs buf Start Condition Hold Time (prior to first clock pulse) t 4.0 - µs hdst Clock Low Time t 4.7 - µs low Clock High Time t 4.0 - µs high Setup Time for Repeated Start Condition t 4.7 - µs sust SDA Hold Time from SCL Falling (Note 12) t 0 - µs hdd SDA Setup Time to SCL Rising t 250 - ns sud Rise Time of SCL and SDA t - 1 µs r Fall Time SCL and SDA t - 300 ns f Setup Time for Stop Condition t 4.7 - µs susp Acknowledge Delay from SCL Falling t 300 1000 ns ack Delay from Supply Voltage Stable to Control Port Ready t 100 - µs dpor Notes: 12. Data must be held for sufficient time to bridge the transition time, t, of SCL. f VD t dpor Repeated Start Stop SDA t buf thdst thigh thdst tf tsusp SCL Stop Start tlow thdd tsud tsust tr Figure 5. Control Port Timing - I²C Format 10 DS761F2

CS2000-CP CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT Inputs: Logic 0=GND; Logic 1=VD; C =20pF. L Parameter Symbol Min Max Unit CCLK Clock Frequency f - 6 MHz ccllk CCLK Edge to CS Falling (Note 13) t 500 - ns spi CS High Time Between Transmissions t 1.0 - µs csh CS Falling to CCLK Edge t 20 - ns css CCLK Low Time t 66 - ns scl CCLK High Time t 66 - ns sch CDIN to CCLK Rising Setup Time t 40 - ns dsu CCLK Rising to DATA Hold Time (Note 14) t 15 - ns dh Rise Time of CCLK and CDIN (Note 15) t - 100 ns r2 Fall Time of CCLK and CDIN (Note 15) t - 100 ns f2 Delay from Supply Voltage Stable to Control Port Ready t 100 - µs dpor Notes: 13. t is only needed before first falling edge of CS after power is applied. t = 0 at all other times. spi spi 14. Data must be held for sufficient time to bridge the transition time of CCLK. 15. For f < 1MHz. cclk VD t dpor CS t t t t spi css scl sch t csh CCLK t t r2 f2 CDIN t t dsu dh Figure 6. Control Port Timing - SPI Format (Write Only) DS761F2 11

CS2000-CP 4. ARCHITECTURE OVERVIEW 4.1 Delta-Sigma Fractional-N Frequency Synthesizer The core of the CS2000 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolu- tion for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to quickly tune to a new frequency. In very simplistic terms, the Fractional-N Frequency Synthesizer multiplies the Timing Reference Clock by the value of N to generate the PLL output clock. The desired output to input clock ratio is the value of N that is applied to the delta-sigma modulator (see Figure7). The analog PLL based frequency synthesizer uses a low-jitter timing reference clock as a time and phase reference for the internal voltage controlled oscillator (VCO). The phase comparator compares the fraction- al-N divided clock with the original timing reference and generates a control signal. The control signal is fil- tered by the internal loop filter to generate the VCO’s control voltage which sets its output frequency. The delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio between the reference clock and the VCO output (thus the one’s density of the modulator sets the fractional value). This allows the design to be optimized for very fast lock times for a wide range of output frequencies without the need for external filter components. As with any Fractional-N Frequency Synthesizer the timing reference clock should be stable and jitter-free. Timing Reference Phase Internal Voltage Controlled PLL Output Clock Comparator Loop Filter Oscillator Fractional-N Divider Delta-Sigma Modulator N Figure 7. Delta-Sigma Fractional-N Frequency Synthesizer 4.2 Hybrid Analog-Digital Phase Locked Loop The addition of the Digital PLL and Fractional-N Logic (shown in Figure8) to the Fractional-N Frequency Synthesizer creates the Hybrid Analog-Digital Phase Locked Loop with many advantages over classical an- alog PLL techniques. These advantages include the ability to operate over extremely wide frequency ranges without the need to change external loop filter components while maintaining impressive jitter reduction per- formance. In the Hybrid architecture, the Digital PLL calculates the ratio of the PLL output clock to the fre- quency reference and compares that to the desired ratio. The digital logic generates a value of N which is then applied to the Fractional-N frequency synthesizer to generate the desired PLL output frequency. Notice that the frequency and phase of the timing reference signal do not affect the output of the PLL since the digital control loop will correct for the PLL output. A major advantage of the Digital PLL is the ease with which the loop filter bandwidth can be altered. The PLL bandwidth is automatically set to a wide-bandwidth mode to quickly achieve lock and then reduced for optimal jitter rejection. 12 DS761F2

CS2000-CP Delta-Sigma Fractional-N Frequency Synthesizer Timing Reference Phase Internal Voltage Controlled PLL Output Clock Comparator Loop Filter Oscillator Fractional-N Divider Delta-Sigma Modulator N Digital PLL and Fractional-N Logic Digital Filter Frequency Reference Frequency Clock Comparator for Frac-N Generation Output to Input Ratio for Hybrid mode Figure 8. Hybrid Analog-Digital PLL 4.2.1 Fractional-N Source Selection for the Frequency Synthesizer The fractional-N value for the frequency synthesizer can be sourced from either a static ratio or a dynamic ratio generated from the digital PLL (see Figure9). This allows for the selection between operating in the static ratio based Frequency Synthesizer Mode as a simple frequency synthesizer (for frequency gener- ation from the Timing Reference Clock) and in the dynamic ratio based Hybrid PLL Mode (for jitter reduc- tion and clock multiplication). Selection between these two modes can either be made automatically based on the presence of the Frequency Reference Clock or manually through register controls. . Fractional-N Timing Reference Clock PLL Output Frequency Synthesizer N Output to Input Ratio for Synthesizer Mode Frequency Reference Clock Digital PLL & Fractional-N Logic Output to Input ratio for Hybrid Mode Figure 9. Fractional-N Source Selection Overview DS761F2 13

CS2000-CP 5. APPLICATIONS 5.1 Timing Reference Clock Input The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an external crystal in conjunction with the internal oscillator. In order to maintain a stable and low-jitter PLL out- put the timing reference clock must also be stable and low-jitter; the quality of the timing reference clock directly affects the performance of the PLL and hence the quality of the PLL output. 5.1.1 Internal Timing Reference Clock Divider The Internal Timing Reference Clock (SysClk) has a smaller maximum frequency than what is allowed on the XTI/REF_CLK pin. The CS2000 supports the wider external frequency range by offering an internal divider for RefClk. The RefClkDiv[1:0] bits should be set such that SysClk, the divided RefClk, then falls within the valid range as indicated in “AC Electrical Characteristics” on page8. Timing Reference Clock Divider Internal Timing Fractional-N Timing Reference Clock ÷ Reference Clock XTI/REF_CLK 1 Frequency PLL Output 8 MHz < RefClk < 5508 MMHHzz ((RXTEIF)_CLK) ÷2 8 MHz < SysClk < 14 MHz Synthesizer ÷ 4 RefClkDiv[1:0] N Figure 10. Internal Timing Reference Clock Divider It should be noted that the maximum allowable input frequency of the XTI/REF_CLK pin is dependent upon its configuration as either a crystal connection or external clock input. See the “AC Electrical Char- acteristics” on page8 for more details. For the lowest possible output jitter, attention should be paid to the absolute frequency of the Timing Ref- erence Clock relative to the PLL Output frequency (CLK_OUT). To minimize output jitter, the Timing Ref- erence Clock frequency should be chosen such that f is at least +/-15kHz from f *N/32 RefClk CLK_OUT where N is an integer. Figure11 shows the effect of varying the RefClk frequency around f *N/32. CLK_OUT It should be noted that there will be a jitter null at the zero point when N=32 (not shown in Figure11). An example of how to determine the range of RefClk frequencies around 12MHz to be used in order to achieve the lowest jitter PLL output at a frequency of 12.288 MHz is as follows: f ≤f ≤f where: L RefClk H CLK__OUT Jitter 180 31 fC LK__OUT*32/N fL = fCLK_OUT×3---2---+15kHz ec) 160 = 12.288MHz×0.96875+15kHz er (ps 140 d Jitt 120 = 11.919MHz an B 100 e and Bas 80 -15 kHz +15 kHz al fH = fCLK_OUT×33---22---–15kHz Typic 60 40 = 12.288MHz×1+15kHz 20 = 12.273MHz -80 -60 -40 -20 0 20 40 60 80 Normalized REF__CLK Frequency (kHz) Figure 11. REF_CLK Frequency vs. a Fixed CLK_OUT Referenced Control Register Location RefClkDiv[1:0].......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page32 14 DS761F2

CS2000-CP 5.1.2 Crystal Connections (XTI and XTO) An external crystal may be used to generate RefClk. To accomplish this, a 20pF fundamental mode par- allel resonant crystal must be connected between the XTI and XTO pins as shown in Figure12. As shown, nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer to the “AC Electrical Characteristics” on page8 for the allowed crystal frequency range. XTI XTO 40 pF 40 pF Figure 12. External Component Requirements for Crystal Circuit 5.1.3 External Reference Clock (REF_CLK) For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the reference clock source and XTO should be left unconnected or pulled low through a 47kΩ resistor to GND. 5.2 Frequency Reference Clock Input, CLK_IN The frequency reference clock input (CLK_IN) is used in Hybrid PLL Mode by the Digital PLL and Fractional- N Logic block to dynamically generate a fractional-N value for the Frequency Synthesizer (see “Hybrid An- alog-Digital PLL” on page13). The Digital PLL first compares the CLK_IN frequency to the PLL output. The Fractional-N logic block then translates the desired ratio based off of CLK_IN to one based off of the internal timing reference clock (SysClk). This allows the low-jitter timing reference clock to be used as the clock which the Frequency Synthesizer multiplies while maintaining synchronicity with the frequency reference clock through the Digital PLL. The allowable frequency range for CLK_IN is found in the “AC Electrical Char- acteristics” on page8. 5.2.1 CLK_IN Skipping Mode CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses for up to 20ms (t ) at a time (see “AC Electrical Characteristics” on page8 for specifications). CLK_IN CS skipping mode can only be used when the CLK_IN frequency is below 80 kHz and CLK_IN is reapplied within 20ms of being removed. The ClkSkipEn bit enables this function. DS761F2 15

CS2000-CP Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 223 SysClk cycles (466ms to 1048ms) after CLK_IN is removed (see Figure13). This is true as long as CLK_IN does not glitch or have an effective change in period as the clock source is removed, otherwise the PLL will interpret this as a change in frequency causing clock skipping and the 223 SysClk cycle time-out to be bypassed and the PLL to immediately unlock. If the prior conditions are met while CLK_IN is removed and 223 SysClk cycles pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See “PLL Clock Output” on page23. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified time listed in the “AC Electrical Characteristics” on page8 after which lock will be acquired and the PLL output will resume. 223 SysClk cycles 223 SysClk cycles Lock Time Lock Time CLK_IN CLK_IN ClkSkipEn=0 or 1 PLL_OUT ClkSkipEn=0 or 1 PLL_OUT ClkOutUnl=0 ClkOutUnl=1 UNLOCK UNLOCK = invalid clocks Figure 13. CLK_IN removed for > 223 SysClk cycles If it is expected that CLK_IN will be removed and then reapplied within 223 SysClk cycles but later than t , the ClkSkipEn bit should be disabled. If it is not disabled, the device will behave as shown in CS Figure14; note that the lower figure shows that the PLL output frequency may change and be incorrect without an indication of an unlock condition. tCS 223 SysClk cycles tCS 223 SysClk cycles Lock Time Lock Time CLK_IN CLK_IN ClkSkipEn=0 or 1 PLL_OUT ClkSkipEn=0 or 1 PLL_OUT ClkOutUnl=0 ClkOutUnl=1 UNLOCK UNLOCK = invalid clocks 223 SysClk cycles tCS Lock Time CLK_IN ClkSkipEn= 1 PLL_OUT ClkOutUnl= 0 or 1 UNLOCK = invalid clocks Figure 14. CLK_IN removed for < 223 SysClk cycles but > t CS 16 DS761F2

CS2000-CP If CLK_IN is removed and then re-applied within t , the ClkSkipEn bit determines whether PLL_OUT CS continues while the PLL re-acquires lock (see Figure15). When ClkSkipEn is disabled and CLK_IN is re- moved the PLL output will continue until CLK_IN is re-applied at which point the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl bit during this time. When ClkSkipEn is enabled and CLK_IN is removed the PLL output clock will remain continuous throughout the missing CLK_IN period including the time while the PLL re-acquires lock. tCS Lock Time tCS CLK_IN CLK_IN ClkSkipEn=1 PLL_OUT ClkSkipEn=0 PLL_OUT ClkOutUnl=0 or 1 ClkOutUnl=1 UNLOCK UNLOCK = invalid clocks tCS Lock Time CLK_IN ClkSkipEn=0 PLL_OUT ClkOutUnl=0 UNLOCK Figure 15. CLK_IN removed for < t CS Referenced Control Register Location ClkSkipEn..............................“Clock Skip Enable (ClkSkipEn)” on page31 ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page32 5.2.2 Adjusting the Minimum Loop Bandwidth for CLK_IN The CS2000 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and 128 Hz using the ClkIn_BW[2:0] bits. The minimum loop bandwidth of the Digital PLL directly affects the jitter transfer function; specifically, jitter frequencies below the loop bandwidth corner are passed from the PLL input directly to the PLL output without attenuation. In some applications it is desirable to have a very low minimum loop bandwidth to reject very low jitter frequencies, commonly referred to as wander. In others it may be preferable to remove only higher frequency jitter, allowing the input wander to pass through the PLL without attenuation. DS761F2 17

CS2000-CP Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other sys- tem clocks and associated data are derived will benefit from the maximum jitter and wander rejection of the lowest PLL bandwidth setting. See Figure16. CLK_IN PLL PLL_OUT Wander and Jitter > 1 Hz Rejected BW = 1 Hz Wander > 1 Hz Jitter MCLK MCLK or Subclocks generated from new clock domain. LRCK LRCK SCLK SCLK SDATA D0 D1 SDATA D0 D1 Figure 16. Low bandwidth and new clock domain Systems in which some clocks and data are derived from the PLL_OUT signal while other clocks and data are derived from the CLK_IN signal will often require phase alignment of all the clocks and data in the system. See Figure17. If there is substantial wander on the CLK_IN signal in these applications, it may be necessary to increase the minimum loop bandwidth allowing this wander to pass through to the CLK_OUT signal in order to maintain phase alignment. For these applications, it is advised to experiment with the loop bandwidth settings and choose the lowest bandwidth setting that does not produce system timing errors due to wandering between the clocks and data synchronous to the CLK_IN domain and those synchronous to the PLL_OUT domain. PLL Jitter > 128 Hz Rejected CLK_IN PLL_OUT Wander < 128 Hz Passed to Output BW = 128 Hz MCLK Wander < 128 Hz Jitter MCLK or Subclocks and data re-used from previous clock domain. LRCK LRCK SCLK SCLK SDATA D0 D1 SDATA D0 D1 Figure 17. High bandwidth with CLK_IN domain re-use It should be noted that manual adjustment of the minimum loop bandwidth is not necessary to acquire lock; this adjustment is made automatically by the Digital PLL. While acquiring lock, the digital loop band- width is automatically set to a large value. Once lock is achieved, the digital loop bandwidth will settle to the minimum value selected by the ClkIn_BW[2:0] bits. Referenced Control Register Location ClkIn_BW[2:0].......................“Clock Input Bandwidth (ClkIn_BW[2:0])” on page33 18 DS761F2

CS2000-CP 5.3 Output to Input Frequency Ratio Configuration 5.3.1 User Defined Ratio (R ), Frequency Synthesizer Mode UD The User Defined Ratio, R , is a 32-bit un-signed fixed-point number which determines the basis for the UD desired input to output clock ratio. Up to four different ratios, Ratio , can be stored in the CS2000 register 0-3 space. The ratio pointed to by the RSel[1:0] bits is the currently selected ratio for the static ratio based Frequency Synthesizer Mode. The 32-bit R is represented in a high-resolution 12.20 format where the UD 12 MSBs represent the integer binary portion while the remaining 20 LSBs represent the fractional binary portion. The maximum multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See “Calculating the User Defined Ratio” on page34 for more information. The status of internal dividers, such as the internal timing reference clock divider, are automatically taken into account. Therefore R is simply the desired ratio of the output to input clock frequencies. UD Referenced Control Register Location Ratio0-3.................................“Ratio 0-3 (Address 06h - 15h)” on page31 Rsel[1:0]................................“Ratio Selection (RSel[1:0])” on page29 5.3.2 User Defined Ratio (R ), Hybrid PLL Mode UD The same four ratio locations, Ratio , are used to store the User Defined Ratios for Hybrid PLL Mode. 0-3 The User Defined Ratio pointed to by the LockClk[1:0] bits is the currently selected ratio for the dynamic ratio based Hybrid PLL Mode. In addition to the High-Resolution format, a High-Multiplication format is also available. In the High-Multi- plication Format Mode, the 32-bit R is represented in a 20.12 format where the 20 MSBs represent the UD integer binary portion while the remaining 12 LSBs represent the fractional binary portion. In this config- uration, the maximum multiplication factor is approximately 1,048,575 with a resolution of 244 PPM. The ratio format default is 20.12. The 20.12 ratio format is only available when both the LFRatioCfg bit is cleared (20.12) and the FracNSrc bit is set (dynamic ratio). In Auto Fractional-N Source Mode (see section 5.3.5.2 on page21) when CLK_IN is not present the LFRatioCfg bit is ignored and the ratio format is 12.20. It is recommended that the 12.20 High-Resolution format be utilized whenever the desired ratio is less than 4096 since the output frequency accuracy of the PLL is directly proportional to the accuracy of the timing reference clock and the resolution of the R . UD Referenced Control Register Location LockClk[1:0]..........................“Lock Clock Ratio (LockClk[1:0])” section on page30 LFRatioCfg............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page32 FracNSrc...............................“Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page30 DS761F2 19

CS2000-CP 5.3.3 Ratio Modifier (R-Mod) The Ratio Modifier is used to internally multiply/divide the currently addressed R (the Ratio stored in UD 0-3 the register space remain unchanged). The available options for R are summarized in Table1 on MOD page20. The R-Mod value selected by RModSel[2:0] is always used in the calculation for the Effective Ratio (R ), see “Effective Ratio (REFF)” on page20. If R-Mod is not desired, RModSel[2:0] should be left at EFF its default value of ‘000’, which corresponds to an R-Mod value of 1, thereby effectively disabling the ratio modifier. RModSel[2:0] Ratio Modifier 000 1 001 2 010 4 011 8 100 0.5 101 0.25 110 0.125 111 0.0625 Table 1. Ratio Modifier Referenced Control Register Location Ratio0-3.................................“Ratio 0-3 (Address 06h - 15h)” on page31 RModSel[2:0]........................“R-Mod Selection (RModSel[2:0])” section on page29 5.3.4 Effective Ratio (R ) EFF The Effective Ratio (R ) is an internal calculation comprised of R and the appropriate modifiers, as EFF UD previously described. R is calculated as follows: EFF • R = R R EFF UD MOD To simplify operation the device handles some of the ratio calculation functions automatically (such as when the internal timing reference clock divider is set). For this reason, the Effective Ratio does not need to be altered to account for internal dividers. Ratio modifiers which would produce an overflow or truncation of R should not be used; For example EFF if R is 1024 an R of 8 would produce an R value of 8192 which exceeds the 4096 limit of the UD MOD EFF 12.20 format. In all cases, the maximum and minimum allowable values for R are dictated by the fre- EFF quency limits for both the input and output clocks as shown in the “AC Electrical Characteristics” on page8. Selection of the user defined ratio from the four stored ratios is made by using the RSel[1:0] bits unless auto clock switching is enabled in which case the LockClk[1:0] bits also select the ratio (see “Manual Frac- tional-N Source Selection for the Frequency Synthesizer” on page21). Referenced Control Register Location RSel[1:0]...............................“Ratio Selection (RSel[1:0])” on page29 LockClk[1:0]..........................“Lock Clock Ratio (LockClk[1:0])” section on page30 20 DS761F2

CS2000-CP 5.3.5 Fractional-N Source Selection To select between the static ratio based Frequency Synthesizer Mode and the dynamic ratio based Hybrid PLL Mode, the source for the fractional-N value for the Frequency Synthesizer must be changed. The Fractional-N value can either be sourced directly from the Effective Ratio (static ratio) or from the output of the Digital PLL (dynamic ratio) (see Figure 18 on page 22). The setting of this function can be made manual or automatically depending on the presence of CLK_IN. 5.3.5.1 Manual Fractional-N Source Selection for the Frequency Synthesizer Manual selection of the fractional-N source for the frequency synthesizer is made by setting the FracNSrc bit to select the desired ratio source. The LockClk[1:0] bits (even if unused) must be set to the same value as the RSel[1:0] bits in order to maintain manual selectability of this function (see Section 5.3.5.2 on page 21). Referenced Control Register Location Rsel[1:0]................................“Device Configuration1 (Address 03h)” on page29 LockClk[1:0]..........................“Device Configuration2 (Address 04h)” section on page30 FracNSrc...............................“Device Configuration2 (Address 04h)” section on page30 5.3.5.2 Automatic Fractional-N Source Selection for the Frequency Synthesizer Automatic source selection allows for the selection of the frequency synthesizer’s fractional-N value to be made dependent on the presence of the CLK_IN signal. When CLK_IN is present the device will use the dynamic ratio generated from the Digital PLL and CLK_IN for Hybrid PLL Mode. When CLK_IN is not present, the device will use RefClk and the static ratio for Frequency Synthesizer Mode. Before switching to SysClk and re-acquiring lock the CS2000 will wait for 223 SysClk cycles after losing CLK_IN (see “CLK_IN Skipping Mode” on page15). The User Defined Ratio pointed to by RSel[1:0] should contain the desired CLK_OUT to RefClk ra- tio to be used when CLK_IN is not present. The User Defined Ratio pointed to by LockClk[1:0] should contain the desired CLK_OUT to CLK_IN ratio to be used when CLK_IN is present. Auto- matic source selection is enabled when the LockClk[1:0] bits are set to point to a different User De- fined Ratio from the one pointed to by the RSel[1:0] bits. When automatic source selection is enabled, the FracNSrc bit (used for manual clock selection) will be ignored. To disable the automatic source selection feature, set the LockClk[1:0] bits and the RSel[1:0] bits to the same value. The FracNSrc bit must then be used to select the desired clock used for the PLL’s frequency reference. Referenced Control Register Location RSel[1:0]...............................“Ratio Selection (RSel[1:0])” on page29 LockClk[1:0]..........................“Lock Clock Ratio (LockClk[1:0])” section on page30 FracNSrc...............................“Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page30 DS761F2 21

CS2000-CP 5.3.6 Ratio Configuration Summary The R is the user defined ratio for which up to four different values (Ratio ) can be stored in the reg- UD 0-3 ister space. The RSel[1:0] or LockClk[1:0] bits then select the user defined ratio to be used (depending on if static or dynamic ratio mode is to be used). The resolution for the R is selectable, for the dynamic UD ratio mode, by setting LFRatioCfg. R-Mod is applied if selected. The user defined ratio, and ratio modifier make up the effective ratio R , the final calculation used to determine the output to input clock ratio. The EFF effective ratio is then corrected for the internal dividers. The frequency synthesizer’s fractional-N source selection is made between the static ratio (in frequency synthesizer mode) or the dynamic ratio generated from the digital PLL (in Hybrid PLL mode) by either the FracNSrc bit for manual mode or the presence of CLK_IN in automatic mode. The conceptual diagram in Figure18 summarizes the features involved in the calculation of the ratio values used to generate the fractional-N value which controls the Frequency Syn- thesizer. Timing Reference Clock (XTI/REF_CLK) RSel[1:0]≠LockClk[1:0] C(aLuKto_ IsNe lseecntiosen ) Divide RefClkDiv[1:0] Effective Ratio REFF RSel[1:0] = LockClk[1:0] F(mraacnNuSalr cselection) RSel[1:0] User Defined Ratio RUD Frequency PLL Output Ratio 0 RModSel[2:0] RefClkDiv[1:0] SysClk Synthesizer Ratio Format RRaattiioo 12 1o2n.2ly0 MRoadtifioie r R Correction Static Ratio N Dynamic Ratio Ratio 3 12.20 Ratio Digital PLL & 20.12 Modifier R Correction Fractional N Logic LFRatioCfg Frequency Reference Clock LockClk[1:0] (CLK_IN) Figure 18. Ratio Feature Summary Referenced Control Register Location Ratio0-3.................................“Ratio 0-3 (Address 06h - 15h)” on page31 RSel[1:0]...............................“Ratio Selection (RSel[1:0])” on page29 LockClk[1:0]..........................“Lock Clock Ratio (LockClk[1:0])” section on page30 LFRatioCfg............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page32 RModSel[2:0]........................“R-Mod Selection (RModSel[2:0])” section on page29 RefClkDiv[1:0].......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page32 FracNSrc...............................“Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page30 22 DS761F2

CS2000-CP 5.4 PLL Clock Output The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer. The driver can be set to high-impedance with the ClkOutDis bit. The output from the PLL automatically drives a static low condition while the PLL is un-locked (when the clock may be unreliable). This feature can be disabled by setting the ClkOutUnl bit, however the state CLK_OUT may then be unreliable during an unlock condition. ClkOutUnl PLL Locked/Unlocked 0 0 2:1 Mux 0 ClkOutDis 1 2:1 Mux PLL Clock Output PLL Clock Output Pin PLLClkOut (CLK_OUT) PLL Output 1 Figure 19. PLL Clock Output Options Referenced Control Register Location ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page32 ClkOutDis..............................“PLL Clock Output Disable (ClkOutDis)” on page29 5.5 Auxiliary Output The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure20, to one of four signals: refer- ence clock (RefClk), input clock (CLK_IN), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is controlled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is then used to control the output driver type and polarity of the LOCK signal (see section 8.7.2 on page32). If AUX_OUT is set to CLK_OUT the phase of the PLL Clock Output signal on AUX_OUT may differ from the CLK_OUT pin. The driver for the pin can be set to high-impedance using the AuxOutDis bit. AuxOutSrc[1:0] Timing Reference Clock (RefClk) AuxOutDis Frequency Reference Clock (CLK_IN) Auxiliary Output Pin 4:1 Mux (AUX_OUT) PLL Clock Output (PLLClkOut) AuxLockCfg PLL Lock/Unlock Indication (Lock) Figure 20. Auxiliary Output Selection Referenced Control Register Location AuxOutSrc[1:0]......................“Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page29 AuxOutDis.............................“Auxiliary Output Disable (AuxOutDis)” on page28 AuxLockCfg...........................“AUX PLL Lock Output Configuration (AuxLockCfg)” section on page32 DS761F2 23

CS2000-CP 5.6 Clock Output Stability Considerations 5.6.1 Output Switching CS2000 is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an output, changing the auxiliary output source between REF_CLK and CLK_OUT, changing between Fre- quency Synthesizer and Hybrid PLL Mode, and the automatic disabling of the output(s) during unlock will not cause a runt or partial clock period. The following exceptions/limitations exist: • Enabling/disabling AUX_OUT when AuxOutSrc[1:0] = 11 (unlock indicator). • Switching AuxOutSrc[1:0] to or from 01 (PLL clock input) and to or from 11 (unlock indicator) (Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch). • Changing the ClkOutUnl bit while the PLL is in operation. When any of these exceptions occur, a partial clock period on the output may result. 5.6.2 PLL Unlock Conditions Certain changes to the clock inputs and registers can cause the PLL to lose lock which will affect the pres- ence the clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un- locked: • Changes made to the registers which affect the Fraction-N value that is used by the Frequency Syn- thesizer. This includes all the bits shown in Figure 18 on page 22. • Any discontinuities on the Timing Reference Clock, REF_CLK. • Discontinuities on the Frequency Reference Clock, CLK_IN, except when the Clock Skipping feature is enabled and the requirements of Clock Skipping are satisfied (see “CLK_IN Skipping Mode” on page15). • Gradual changes in CLK_IN frequency greater than ±30% from the starting frequency. • Step changes in CLK_IN frequency. 5.7 Required Power Up Sequencing • Apply power to the device. The output pins will remain low until the device is configured with a valid ratio via the control port. • Write the desired operational configurations. The EnDevCfg1 and EnDevCfg2 bits must be set to 1 dur- ing the initialization register writes; the order does not matter. – The Freeze bit may be set prior to this step and cleared afterward to ensure all settings take effect at the same time. 6. SPI / I²C CONTROL PORT The control port is used to access the registers and allows the device to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to device inputs and outputs. However, to avoid potential interference problems, the control port pins should remain static if no op- eration is required. 24 DS761F2

CS2000-CP The control port operates with either the SPI or I²C interface, with the CS2000 acting as a slave device. SPI Mode is selected if there is a high-to-low transition on the AD0/CS pin after power-up. I²C Mode is selected by connecting the AD0/CS pin through a resistor to VD or GND, thereby permanently selecting the desired AD0 bit address state. In both modes the EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation. WARNING:All “Reserved” registers must maintain their default state to ensure proper functional operation. Referenced Control Register Location EnDevCfg1............................“Enable Device Configuration Registers 1 (EnDevCfg1)” on page30 EnDevCfg2............................“Enable Device Configuration Registers 2 (EnDevCfg2)” section on page31 6.1 SPI Control In SPI Mode, CS is the chip select signal; CCLK is the control port bit clock (sourced from a microcontroller), and CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The device only supports write operations. Figure21 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The first eight bits on CDIN form the chip address and must be 10011110. The next eight bits form the Memory Ad- dress Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. There is MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will automatically incre- ment after each byte is read or written, allowing block writes of successive registers. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CCLK CHIP ADDRESS MAP BYTE DATA DATA +n CDIN 1 0 0 1 1 1 1 0 INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 Figure 21. Control Port Timing in SPI Mode 6.2 I²C Control In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL. There is no CS pin. The AD0 pin forms the least-significant bit of the chip address and should be connected to VD or GND as appropriate. The state of the AD0 pin should be maintained throughout operation of the device. The signal timings for a read and write cycle are shown in Figure22 and Figure23. A Start condition is de- fined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS2000 after a Start condition consists of the 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 6 bits of the 7-bit address field are fixed at 100111 followed by the logic state of the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Point- er (MAP) which selects the register to be read or written. If the operation is a read, the contents of the reg- ister pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS2000 after each input byte is read and is input from the microcontroller after each transmitted byte. DS761F2 25

CS2000-CP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1 DATA +n SDA 1 0 0 1 1 1 AD0 0 INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 ACK ACK ACK ACK START STOP Figure 22. Control Port Timing, I²C Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCL STOP CHIP ADDRESS (WRITE) MAP BYTE CHIP ADDRESS (READ) DATA DATA +1 DATA + n SDA 1 0 0 1 1 1 AD0 0 INCR 6 5 4 3 2 1 0 1 0 0 1 1 1 AD0 1 7 0 7 0 7 0 ACK ACK ACK ACK NO START START ACKSTOP Figure 23. Control Port Timing, I²C Aborted Write + Read Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown in Figure22, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con- dition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 100111x0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 100111x1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. 26 DS761F2

CS2000-CP 6.3 Memory Address Pointer The Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be read or written. Refer to the pseudocode above for implementation details. 6.3.1 Map Auto Increment The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is read or written, allowing block reads or writes of successive regis- ters. 7. REGISTER QUICK REFERENCE This table shows the register and bit names with their associated default values. EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation. WARNING:All “Reserved” registers must maintain their default state to ensure proper functional operation. Adr Name 7 6 5 4 3 2 1 0 01h Device ID Device4 Device3 Device2 Device1 Device0 Revision2 Revision1 Revision0 p28 0 0 0 0 0 x x x 02h Device Ctrl Unlock Reserved Reserved Reserved Reserved Reserved AuxOutDis ClkOutDis p28 x x x 0 0 0 0 0 03h Device Cfg1 RModSel2 RModSel1 RModSel0 RSel1 RSel0 AuxOutSrc1 AuxOutSrc0 EnDevCfg1 p29 0 0 0 0 0 0 0 0 04h Device Cfg2 Reserved Reserved Reserved Reserved Reserved LockClk1 LockClk0 FracNSrc p30 0 0 0 0 0 0 0 0 05h Global Cfg Reserved Reserved Reserved Reserved Freeze Reserved Reserved EnDevCfg2 p30 0 0 0 0 0 0 0 0 MSB ........................................................................................................................... MSB-7 06h 32-Bit MSB-8 ........................................................................................................................... MSB-15 - Ratio0 LSB+15 ........................................................................................................................... LSB+8 09h LSB+7 ........................................................................................................................... LSB MSB ........................................................................................................................... MSB-7 0Ah 32-Bit MSB-8 ........................................................................................................................... MSB-15 - Ratio1 LSB+15 ........................................................................................................................... LSB+8 0Dh LSB+7 ........................................................................................................................... LSB MSB ........................................................................................................................... MSB-7 0Eh 32-Bit MSB-8 ........................................................................................................................... MSB-15 - Ratio2 LSB+15 ........................................................................................................................... LSB+8 11h LSB+7 ........................................................................................................................... LSB MSB ........................................................................................................................... MSB-7 12h 32-Bit MSB-8 ........................................................................................................................... MSB-15 - Ratio3 LSB+15 ........................................................................................................................... LSB+8 15h LSB+7 ........................................................................................................................... LSB 16h FunctCfg1 ClkSkipEn AuxLockCfg Reserved RefClkDiv1 RefClkDiv0 Reserved Reserved Reserved p31 0 0 0 0 0 0 0 0 17h FunctCfg2 Reserved Reserved Reserved ClkOutUnl LFRatioCfg Reserved Reserved Reserved p32 0 0 0 0 0 0 0 0 1Eh FunctCfg3 Reserved ClkIn_BW2 ClkIn_BW1 ClkIn_BW0 Reserved Reserved Reserved Reserved p32 0 0 0 0 0 0 0 0 DS761F2 27

CS2000-CP 8. REGISTER DESCRIPTIONS In I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All “Re- served” registers must maintain their default state to ensure proper functional operation. The default state of each bit after a power-up sequence or reset is indicated by the shaded row in the bit decode table and in the “Register Quick Reference” on page27. Control port mode is entered when the device recognizes a valid chip address input on its I²C/SPI serial control pins and the EnDevCfg1 and EnDevCfg2 bits are set to 1. 8.1 Device I.D. and Revision (Address 01h) 7 6 5 4 3 2 1 0 Device4 Device3 Device2 Device1 Device0 Revision2 Revision1 Revision0 8.1.1 Device Identification (Device[4:0]) - Read Only I.D. code for the CS2000. Device[4:0] Device 00000 CS2000. 8.1.2 Device Revision (Revision[2:0]) - Read Only CS2000 revision level. REVID[2:0] Revision Level 100 B2 and B3 110 C1 8.2 Device Control (Address 02h) 7 6 5 4 3 2 1 0 Unlock Reserved Reserved Reserved Reserved Reserved AuxOutDis ClkOutDis 8.2.1 Unlock Indicator (Unlock) - Read Only Indicates the lock state of the PLL. Unlock PLL Lock State 0 PLL is Locked. 1 PLL is Unlocked. 8.2.2 Auxiliary Output Disable (AuxOutDis) This bit controls the output driver for the AUX_OUT pin. AuxOutDis Output Driver State 0 AUX_OUT output driver enabled. 1 AUX_OUT output driver set to high-impedance. Application: “Auxiliary Output” on page23 28 DS761F2

CS2000-CP 8.2.3 PLL Clock Output Disable (ClkOutDis) This bit controls the output driver for the CLK_OUT pin. ClkOutDis Output Driver State 0 CLK_OUT output driver enabled. 1 CLK_OUT output driver set to high-impedance. Application: “PLL Clock Output” on page23 8.3 Device Configuration 1 (Address 03h) 7 6 5 4 3 2 1 0 RModSel2 RModSel1 RModSel0 RSel1 RSel0 AuxOutSrc1 AuxOutSrc0 EnDevCfg1 8.3.1 R-Mod Selection (RModSel[2:0]) Selects the R-Mod value, which is used as a factor in determining the PLL’s Fractional N. RModSel[2:0] R-Mod Selection 000 Left-shift R-value by 0 (x1). 001 Left-shift R-value by 1 (x2). 010 Left-shift R-value by 2 (x4). 011 Left-shift R-value by 3 (x8). 100 Right-shift R-value by 1 (÷2). 101 Right-shift R-value by 2 (÷4). 110 Right-shift R-value by 3 (÷8). 111 Right-shift R-value by 4 (÷16). Application: “Ratio Modifier (R-Mod)” on page20 8.3.2 Ratio Selection (RSel[1:0]) Selects one of the four stored User Defined Ratios for use in the static ratio based Frequency Synthesizer Mode. RSel[1:0] Ratio Selection 00 Ratio0. 01 Ratio1. 10 Ratio2. 11 Ratio3. Application: “User Defined Ratio (RUD), Frequency Synthesizer Mode” on page19 8.3.3 Auxiliary Output Source Selection (AuxOutSrc[1:0]) Selects the source of the AUX_OUT signal. AuxOutSrc[1:0] Auxiliary Output Source 00 RefClk. 01 CLK_IN. 10 CLK_OUT. 11 PLL Lock Status Indicator. Application: “Auxiliary Output” on page23 Note: When set to 11, AuxLckCfg sets the polarity and driver type. See “AUX PLL Lock Output Config- uration (AuxLockCfg)” on page32. DS761F2 29

CS2000-CP 8.3.4 Enable Device Configuration Registers 1 (EnDevCfg1) This bit, in conjunction with EnDevCfg2, configures the device for control port mode. These EnDevCfg bits can be set in any order and at any time during the control port access sequence, however they must both be set before normal operation can occur. EnDevCfg1 Register State 0 Disabled. 1 Enabled. Application: “SPI / I²C Control Port” on page24 Note: EnDevCfg2 must also be set to enable control port mode. See “SPI / I²C Control Port” on page24. 8.4 Device Configuration 2 (Address 04h) 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved LockClk1 LockClk0 FracNSrc 8.4.1 Lock Clock Ratio (LockClk[1:0]) Selects one of the four stored User Defined Ratios for use in the dynamic ratio based Hybrid PLL Mode. LockClk[1:0] CLK_IN Ratio Selection 00 Ratio0. 01 Ratio1. 10 Ratio2. 11 Ratio3. Application: Section 5.3.2 on page 19 8.4.2 Fractional-N Source for Frequency Synthesizer (FracNSrc) Selects static or dynamic ratio mode when auto clock switching is disabled. FracNSrc Fractional-N Source Selection 0 Static Ratio directly from REFF for Frequency Synthesizer Mode 1 Dynamic Ratio from Digital PLL for Hybrid PLL Mode Application: “Fractional-N Source Selection” on page21 8.5 Global Configuration (Address 05h) 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Freeze Reserved Reserved EnDevCfg2 8.5.1 Device Configuration Freeze (Freeze) Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h-04h) but keeps them from taking effect until this bit is cleared. FREEZE Device Control and Configuration Registers 0 Register changes take effect immediately. Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without 1 the changes taking effect until after the FREEZE bit is cleared. 30 DS761F2

CS2000-CP 8.5.2 Enable Device Configuration Registers 2 (EnDevCfg2) This bit, in conjunction with EnDevCfg1, configures the device for control port mode. These EnDevCfg bits can be set in any order and at any time during the control port access sequence, however they must both be set before normal operation can occur. EnDevCfg2 Register State 0 Disabled. 1 Enabled. Application: “SPI / I²C Control Port” on page24 Note: EnDevCfg1 must also be set to enable control port mode. See “SPI / I²C Control Port” on page24. 8.6 Ratio 0 - 3 (Address 06h - 15h) 7 6 5 4 3 2 1 0 MSB ................................................................................................................................................... MSB-7 MSB-8 ................................................................................................................................................... MSB-15 LSB+15 ................................................................................................................................................... LSB+8 LSB+7 ................................................................................................................................................... LSB These registers contain the User Defined Ratios as shown in the “Register Quick Reference” section on page27. Each group of 4 registers forms a single 32-bit ratio value as shown above. See “Output to Input Frequency Ratio Configuration” on page19 and “Calculating the User Defined Ratio” on page34 for more details. 8.7 Function Configuration 1 (Address 16h) 7 6 5 4 3 2 1 0 ClkSkipEn AuxLockCfg Reserved RefClkDiv1 RefClkDiv0 Reserved Reserved Reserved 8.7.1 Clock Skip Enable (ClkSkipEn) This bit enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the CLK_IN has missing pulses. ClkSkipEn PLL Clock Skipping Mode 0 Disabled. 1 Enabled. Application: “CLK_IN Skipping Mode” on page15 Note: f must be < 80kHz and re-applied within 20ms to use this feature. CLK_IN DS761F2 31

CS2000-CP 8.7.2 AUX PLL Lock Output Configuration (AuxLockCfg) When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this bit is disregarded. AuxLockCfg AUX_OUT Driver Configuration 0 Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition). 1 Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition). Application: “Auxiliary Output” on page23 Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There- fore, the pin polarity is defined relative to the unlock condition. 8.7.3 Reference Clock Input Divider (RefClkDiv[1:0]) Selects the input divider for the timing reference clock. RefClkDiv[1:0] Reference Clock Input Divider REF_CLK Frequency Range 00 ÷4. 32 MHz to 56MHz (50MHz with XTI) 01 ÷2. 16 MHz to 28MHz 10 ÷1. 8 MHz to 14MHz 11 Reserved. Application: “Internal Timing Reference Clock Divider” on page14 8.8 Function Configuration 2 (Address 17h) 7 6 5 4 3 2 1 0 Reserved Reserved Reserved ClkOutUnl LFRatioCfg Reserved Reserved Reserved 8.8.1 Enable PLL Clock Output on Unlock (ClkOutUnl) Defines the state of the PLL output during the PLL unlock condition. ClkOutUnl Clock Output Enable Status 0 Clock outputs are driven ‘low’ when PLL is unlocked. 1 Clock outputs are always enabled (results in unpredictable output when PLL is unlocked). Application: “PLL Clock Output” on page23 8.8.2 Low-Frequency Ratio Configuration (LFRatioCfg) Determines how to interpret the currently indexed 32-bit User Defined Ratio when the dynamic ratio based Hybrid PLL Mode is selected (either manually or automatically, see section 5.3.5 on page21). LFRatioCfg Ratio Bit Encoding Interpretation when Input Clock Source is CLK_IN 0 20.12 - High Multiplier. 1 12.20 - High Accuracy. Application: “User Defined Ratio (RUD), Hybrid PLL Mode” on page19 Note: When the static ratio based Frequency Synthesizer Mode is selected (either manually or auto- matically), the currently indexed User Defined Ratio will always be interpreted as a 12.20 fixed point value, regardless of the state of this bit. 32 DS761F2

CS2000-CP 8.9 Function Configuration 3 (Address 1Eh) 7 6 5 4 3 2 1 0 Reserved ClkIn_BW2 ClkIn_BW1 ClkIn_BW0 Reserved Reserved Reserved Reserved 8.9.1 Clock Input Bandwidth (ClkIn_BW[2:0]) Sets the minimum loop bandwidth when locked to CLK_IN. ClkIn_BW[2:0] Minimum Loop Bandwidth 000 1 Hz 001 2 Hz 010 4 Hz 011 8 Hz 100 16 Hz 101 32 Hz 110 64 Hz 111 128 Hz Application: “Adjusting the Minimum Loop Bandwidth for CLK_IN” on page17 Note: In order to guarantee that a change in minimum bandwidth takes effect, these bits must be set prior to acquiring lock (removing and re-applying CLK_IN can provide the unlock condition necessary to initiate the setting change). In production systems these bits should be configured with the desired values prior to setting the EnDevCfg bits; this guarantees that the setting takes effect prior to acquiring lock. DS761F2 33

CS2000-CP 9. CALCULATING THE USER DEFINED RATIO Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User Defined Ratio. This section is for those who are not interested in the software or who are developing their systems without the aid of the evaluation kit. Most calculators do not interpret the fixed point binary representation which the CS2000 uses to define the output to input clock ratio (see Section 5.3.1 on page 19); However, with a simple conversion we can use these tools to generate a binary or hex value which can be written to the Ratio registers. 0-3 9.1 High Resolution 12.20 Format To calculate the User Defined Ratio (R ) to store in the register(s), divide the desired output clock frequen- UD cy by the given input clock (CLK_IN or RefClk). Then multiply the desired ratio by the scaling factor of 220 to get the scaled decimal representation; then use the decimal to binary/hex conversion function on a cal- culator and write to the register. A few examples have been provided in Table2. Scaled Decimal Desired Output to Input Clock Ratio Representation= Hex Representation of (output clock/input clock) (output clock/input clock) • 220 Binary RUD 12.288MHz/10MHz=1.2288 1288490 00 13 A9 2A 11.2896MHz/44.1kHz=256 268435456 10 00 00 00 Table 2. Example 12.20 R-Values 9.2 High Multiplication 20.12 Format To calculate the User Defined Ratio (R ) to store in the register(s), divide the desired output clock frequen- UD cy by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 212 to get the scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and write to the register. A few examples have been provided in Table3. Scaled Decimal Desired Output to Input Clock Ratio Representation= Hex Representation of (output clock/input clock) (output clock/input clock) • 212 Binary RUD 12.288MHz/60 Hz=204,800 838860800 32 00 00 00 11.2896MHz/59.97Hz=188254.127... 771088904 2D F5 E2 08 Table 3. Example 20.12 R-Values 34 DS761F2

CS2000-CP 10.PACKAGE DIMENSIONS 10L MSOP (3 mm BODY) PACKAGE DRAWING (Note 1) N D E11 c E A2 A ∝ A1 e b L END VIEW SEATING SIDE VIEW PLANE L1 1 2 3 TOP VIEW INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A -- -- 0.0433 -- -- 1.10 A1 0 -- 0.0059 0 -- 0.15 A2 0.0295 -- 0.0374 0.75 -- 0.95 b 0.0059 -- 0.0118 0.15 -- 0.30 4, 5 c 0.0031 -- 0.0091 0.08 -- 0.23 D -- 0.1181 BSC -- -- 3.00 BSC -- 2 E -- 0.1929 BSC -- -- 4.90 BSC -- E1 -- 0.1181 BSC -- -- 3.00 BSC -- 3 e -- 0.0197 BSC -- -- 0.50 BSC -- L 0.0157 0.0236 0.0315 0.40 0.60 0.80 L1 -- 0.0374 REF -- -- 0.95 REF -- Notes: 1. Reference document: JEDEC MO-187 2. D does not include mold flash or protrusions which is 0.15 mm max. per side. 3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. 4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max. 5. Exceptions to JEDEC dimension. THERMAL CHARACTERISTICS Parameter Symbol Min Typ Max Units Junction to Ambient Thermal Impedance JEDEC 2-Layer θ - 170 - °C/W JA JEDEC 4-Layer θ - 100 - °C/W JA DS761F2 35

CS2000-CP 11.ORDERING INFORMATION Product Description Package Pb-Free Grade Temp Range Container Order# CS2000-CP Clocking Device 10L-MSOP Yes -10° to +70°C Rail CS2000CP-CZZ Commercial Tape and CS2000-CP Clocking Device 10L-MSOP Yes -10° to +70°C CS2000CP-CZZR Reel CS2000-CP Clocking Device 10L-MSOP Yes -40° to +85°C Rail CS2000CP-DZZ Automotive Tape and CS2000-CP Clocking Device 10L-MSOP Yes -40° to +85°C CS2000CP-DZZR Reel CDK2000 Evaluation Platform - Yes - - - CDK2000-CLK 12.REFERENCES 1. Audio Engineering Society AES-12id-2006: “AES Information Document for digital audio measurements - Jitter performance specifications,” May 2007. 2. Philips Semiconductor, “The I²C-Bus Specification: Version 2,” Dec. 1998. http://www.semiconductors.philips.com 13.REVISION HISTORY Release Changes F1 Updated Period Jitter specification in “AC Electrical Characteristics” on page8. Updated Crystal and Ref Clock Frequency specifications in “AC Electrical Characteristics” on page8. Added “PLL Performance Plots 9” section on page2. Updated “Internal Timing Reference Clock Divider” on page14 and added Figure 11 on page 14. Updated use conditions for “CLK_IN Skipping Mode” section on page15 and page31. Updated Figure 13 on page 16. Removed FsDetect and Auto R-Mod features per ER758rev2. F2 Updated to add Automotive Grade temperature ranges and ordering options. 36 DS761F2

CS2000-CP DS761F2 37

CS2000-CP Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM- ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. 38 DS761F2

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