CM2030 HDMI Transmitter Port Protection and Interface Device Product Description The CM2030 HDMI Transmitter Port Protection and Interface http://onsemi.com Device is specifically designed for next generation HDMI Host interface protection. An integrated package provides all ESD, level shifting/isolation, overcurrent output protection and backdrive protection for an HDMI port in a single 38−pin TSSOP package. The CM2030 also incorporates a silicon overcurrent protection device for +5 V supply voltage output to the connector. CM2030 is ideal for applications which do not require HDMI TSSOP 38 certification but can benefit from level shifters and backdrive TR SUFFIX CASE 948AG protection. Features MARKING DIAGRAM • Supports Thin Dielectric and 2−layer Boards • Minimizes TMDS Skew with 0.05 pF Matching • Long HDMI Cable Support with Integrated I2C Accelerator CM2030−A0TR • Supports Direct Connection to CEC Microcontroller • Integrated I2C Level Shifting to CMOS Level Including Low CM2030−A0TR = Specific Device Code Logic Level Voltages • ORDERING INFORMATION Integrated 8 kV ESD Protection and Backdrive Protection on All External I/O Lines Device Package Shipping† • Multiport I2C Support Eliminates Need for Analog Mux on DDC CM2030−A0TR TSSOP−38 2500/Tape & Reel (Pb−Free) Lines • †For information on tape and reel specifications, Simplified Layout with Matched 0.5 mm Trace Spacing including part orientation and tape sizes, please • These Devices are Pb−Free and are RoHS Compliant refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Applications • PC and Consumer Electronics • Set Top Box, DVD RW, PC, Graphics Cards © Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: March, 2012 − Rev. 8 CM2030/D

CM2030 ELECTRICAL SCHEMATIC 5V_SUPPLY TMDS_D2+ TMDS_D1+ TMDS_D0+ TMDS_CK+ TMDS_GND TMDS_GND TMDS_GND TMDS_GND TMDS_D2− TMDS_D1− TMDS_D0− TMDS_CK− 55VV SSUUPPPPLLYY 5V SUPPLY LV SUPPLY LV SUPPLY Dynamic Dynamic Pullup Pullup CMOS/I2C CMOS/I2C Level Shift Level Shift DDC_CLK_IN DDC_CLK_OUT DDC_DAT_IN DDC_DAT_OUT CE_SUPPLY LV SUPPLY CE_SUPPLY Active Slew Rate Limiting IS HOTPLUG_DET_OUT CE_REMOTE_IN HOTPLUG_DET_IN 3IS CE_REMOTE_OUT 55 mA 5V_SUPPLY Overcurrent 5V_OUT Switch PACKAGE / PINOUT DIAGRAM Top View 5V_SUPPLY 1 38 5V_OUT LV_SUPPLY 2 37 CE_SUPPLY GND 3 36 GND TMDS_D2+ 4 35 TMDS_D2+ TMDS_GND 5 34 TMDS_GND TMDS_D2− 6 33 TMDS_D2− TMDS_D1+ 7 32 TMDS_D1+ TMDS_GND 8 31 TMDS_GND TMDS_D1− 9 30 TMDS_D1− TMDS_D0+ 10 29 TMDS_D0+ TMDS_GND 11 28 TMDS_GND TMDS_D0− 12 27 TMDS_D0− TMDS_CK+ 13 26 TMDS_CK+ TMDS_GND 14 25 TMDS_GND TMDS_CK− 15 24 TMDS_CK− CE_REMOTE_IN 16 23 CE_REMOTE_OUT DDC_CLK_IN 17 22 DDC_CLK_OUT DDC_DAT_IN 18 21 DDC_DAT_OUT HOTPLUG_DET_IN 19 20 HOTPLUG_DET_OUT 38−Pin TSSOP Package http://onsemi.com 2

CM2030 Table 1. PIN DESCRIPTIONS Pins Name ESD Level Description 4, 35 TMDS_D2+ 8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1) 6, 33 TMDS_D2− 8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1) 7, 32 TMDS_D1+ 8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1) 9, 30 TMDS_D1− 8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1) 10, 29 TMDS_D0+ 8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1) 12, 27 TMDS_D0− 8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1) 13, 26 TMDS_CK+ 8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1) 15, 24 TMDS_CK− 8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1) 16 CE_REMOTE_IN 2 kV (Note 4) CE_SUPPLY Referenced Logic Level In 23 CE_REMOTE_OUT 8 kV(Note 3) 5V_SUPPLY Referenced Logic Level Out plus 10 pF ESD (Note 6) 17 DDC_CLK_IN 2 kV (Note 4) LV_SUPPLY Referenced Logic Level In 22 DDC_CLK_OUT 8 kV (Note 3) 5V_SUPPLY Referenced Logic Level Out plus 10 pF ESD (Note 6) 18 DDC_DAT_IN 2 kV (Note 4) LV_SUPPLY Referenced Logic Level In 21 DDC_DAT_OUT 8 kV (Note 3) 5V_SUPPLY Referenced Logic Level Out plus 10 pF ESD (Note 6) 19 HOTPLUG_DET_IN 2 kV (Note 4) LV_SUPPLY Referenced Logic Level In 20 HOTPLUG_DET_OUT 8 kV (Note 3) 5V_SUPPLY Referenced Logic Level Out plus 10 pF ESD. A 0.1 (cid:2)F Bypass Ceramic Capacitor is Recommended on this Pin (Note 2). 2 LV_SUPPLY 2 kV (Note 4) Bias for CE / DDC / HOTPLUG Level Shifters 37 CE_SUPPLY 2 kV CEC Bias Voltage. Previously CM2020 ESD_BYP Pin. (Notes 2 & 4) 1 5V_SUPPLY 2 kV (Note 4) Current Source for 5V_OUT, VREF for DDC I2C Voltage References, and Bias for 8kV ESD Pins. 38 5V_OUT 8 kV (Note 3) 55 mA Minimum Overcurrent Protected 5 V Output. This Output Must be Bypassed with a 0.1 (cid:2)F Ceramic Capacitor. 3, 5, 8, 11, GND / TMDS_GND N/A GND Reference 14, 25, 28, 31, 34, 36 1. These 2 pins need to be connected together in−line on the PCB. See recommended layout diagram. 2. This output can be connected to an external 0.1 (cid:2)F ceramic capacitor/pads to maintain backward compatibility with the CM2020. 3. Standard IEC 61000−4−2, CDISCHARGE = 150 pF, RDISCHARGE = 330 (cid:3), 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND = 0 V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1 (cid:2)F ceramic capacitor connected to GND. 4. Human Body Model per MIL−STD−883, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 k(cid:3), 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND = 0 V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1 (cid:2)F ceramic capacitor connected to GND. 5. These pins should be routed directly to the associated GND pins on the HDMI connector with single point ground vias at the connector. 6. The slew−rate control and active acceleration circuitry dynamically offsets the system capacitive load on these pins. http://onsemi.com 3

CM2030 BACKDRIVE PROTECTION AND ISOLATION Backdrive current is defined as the undesirable current may not reset properly when the DVD player is turned back flow through an I/O pin when that I/O pin’s voltage exceeds on. the related local supply voltage for that circuitry. This is If any SOC devices are incorporated in the design which apotentially common occurrence in multimedia have built−in level shifter and/or ESD protection structures, entertainment systems with multiple components and there can be a risk of permanent damage due to backdrive. several power plane domains in each system. In this case, backdrive current can forward bias the on−chip For example, if a DVD player is switched off and an ESD protection structure. If the current flow is high enough, HDMI connected TV is powered on, there is a possibility of even as little as a few milliamps, it could destroy one of the reverse current flow back into the main power supply rail of SOC chip’s internal DRC diodes, as they are not designed for the DVD player from pull−ups in the TV. As little as a few passing DC. milliamps of backdrive current flowing back into the power To avoid either of these situations, the CM2030 was rail can charge the DVD player’s bulk bypass capacitance on designed to block backdrive current, guaranteeing less than the power rail to some intermediate level. If this level rises 5(cid:2)A into any I/O pin when the I/O pin voltage exceeds its above the power−on−reset (POR) voltage level of some of related operating CM2030 supply voltage. the integrated circuits in the DVD player, then these devices Figure 1. Backdrive Protection Diagram. DISPLAY DATA CHANNEL (DDC) LINES The DDC interface is based on the I2C serial bus protocol against a discrete NFET common−gate level shifter circuit for EDID configuration. with a typical 1.5kW pullup at the source (top.) Both are shown driving an off−spec, but unfortunately readily Dynamic Pullups available 31m HDMI cable which exceeds the 700pF Based on the HDMI specification, the maximum HDMI specification. Some widely available HDMI cables capacitance of the DDC line can approach 800pF (50pF have been measured at over 4nF. from source, 50pF from sink, and 700pF from cable). At When the standard I/OD cell releases the NFET discrete the upper range of capacitance values (i.e. long cables), it shifter, the risetime is limited by the pullup and the parasitics becomes impossible for the DDC lines to meet the I2C of the cable, source and sink. For long cables, this can extend timing specifications with the minimum pull−up resistor of the risetime and reduce the margin for reading a valid “high” 1.5kΩ. level on the data line. In this case, an HDMI source may not For this reason, the CM2030 was designed with an be able to read uncorrupted data and will not be able to internal I2C accelerator to meet the AC timing specification initiate a link. even with very long and non−compliant cables. With the CM2030’s dynamic pullups, when the ASIC The internal accelerator increases the positive slew rate of driver releases its DDC line and the “OUT” line reaches at the DDC_CLK_OUT and DDC_DAT_OUT lines whenever least 0.3*VDD (of 5V_SUPPLY), then the “OUT” active the sensed voltage level exceeds 0.3*5V_SUPPLY pullups are enabled and the CM2030 takes over driving the (approximately 1.5V). This provides faster overall risetime cable until the “OUT” voltage approaches the 5V_SUPPLY in heavily loaded situations without overloading the rail. multi−drop open drain I2C outputs elsewhere. The internal pass element and the dynamic pullups also Figure 2 demonstrates the “worst case” operation of the work together to damp reflections on the longer cables and dynamic CM2030 DDC level shifting circuitry (bottom) keep them from glitching the local ASIC. http://onsemi.com 4

CM2030 Figure 2. Dynamic DDC Pullups (Discrete − Top, CM2030 − Bottom; 3.3 V ASIC − Left, 5 V Cable − Right) I2C Low Level Shifting When I2C devices are driving the external cable, an In addition to the Dynamic Pullups described in the internal pulldown on DDC_XX_IN guarantees that the VOL previous section, the CM2030 also incorporates improved seen by the ASIC on DDC_XX_IN is equal to or lower than I2C low−level shifting on the DDC_CLK_IN and DDC_XX_OUT. DDC_DAT_IN lines for enhanced compatibility. Typical discrete NFET level shifters can advertise Multiport DDC Multiplexing specifications for low R [on], but usually state relatively By switching LV_SUPPLY, the DDC/HPD blocks can be DS high V test parameters, requiring a ‘switch’ signal (gate independently disabled by engaging their inherent [GS] voltage) as high as 10V or more. At a sink current of 4mA “backdrive” protection. This allows N:1 multiplexing of the for the ASIC on DDC_XX_IN, the CM2030 guarantees no low−speed HDMI signals without any additional FET more than 140mV increase to DDC_XX_OUT, even with switches. aswitching control of 2.5V on LV_SUPPLY. CONSUMER ELECTRONICS CONTROL (CEC) The Consumer Electronics Control (CEC) line is a high To limit possible EMI and ringing in this potentially level command and control protocol, based on a single wire complex connection topology, the rise− and fall−time of this multidrop open drain communication bus running at line are limited by the specification. However, meeting the approximately 1kHz (See Figure 3). While the HDMI link slew−rate limiting requirements with additional discrete provides only a single point−to−point connection, up to ten circuitry in this bi−directional block is not trivial without an (10) CEC devices may reside on the bus, and they may be additional RX/TX control line to limit the output slew−rate daisy chained out through other physical connectors without affecting the input sensing (See Figure 4). including other HDMI ports or other dedicated CEC links. The high level protocol of CEC can be implemented in CEC asimple microcontroller or other interface with any I/OD RX (input/open−drain) GPIO. Slew Rate TX Limited CEC 3−State Buffer RX TX_EN I/OD GPIO Figure 4. Three−Pin External Buffer Control TX Simple CMOS buffers cannot be used in this application since the load can vary so much (total pullup of 27kW to less Figure 3. Typical (cid:2)C I/OD Driver http://onsemi.com 5

CM2030 than 2kW, and up to 7.3nF total capacitance.) The CM2030 targets an output drive slew−rate of less than 100mV/ms regardless of static load for the CEC line. Additionally, the same internal circuitry will perform active termination, thus reducing ringing and overshoot in entertainment systems connected to legacy or poorly designed CEC nodes. The CM2030’s bi−directional slew rate limiting is integrated into the CEC level−shifter functionality thus allowing the designer to directly interface a simple low voltage CMOS GPIO directly to the CEC bus and simultaneously guarantee meeting all CEC output logic levels and HDMI slew−rate and isolation specifications (See Figure5). CEC Figure 6. CM2030 CEC Output HDMI certification requires capacitance measurement of the CEC line to be less than 150 pF per device. Due to the active circuit inside the CM2030 CEC line, CM2030 may CEC I/F cause false readings during the CEC capacitance (cid:2)P CM2030 measurement and not pass the test. The active circuit of the CM2030 CEC line would react with the LCR meter and Figure 5. Integrated CM2030 Solution cause false capacitance readings. There is no issue with the operation of the CM2030 CEC line during normal The CM2030 also includes an internal backdrive operations. In fact, CM2030 CEC has shown to improve the protected static pullup 120(cid:2)A current source from the signal integrity of the CEC line. CM2030 can be used for CE_SUPPLY rail in addition to the dynamic slew rate applications which do not require HDMI certification or control circuitry. applications which do not use the CEC line. Figure 6 shows a typical shaped CM2030 CEC output (bottom) against a ringing uncontrolled discrete solution (top). HOTPLUG DETECT LOGIC The CM2030 ensures that the local ASIC will properly CM2030 detect an HDMI compliant Sink. The current sink maintains 5V_SUPPLY a local logic “low” when no system is connected. A valid pullup on the HDMI connector pin will overdrive LV SUPPLY the internal pulldown and deliver a logic “high” to the local ASIC. HP_IN IS HP_OUT 3IS 19 HDMI CONN Figure 7. Hotplug Detect Circuit A 15 K(cid:3) pull down resistor should be connected between HP_OUT and ground as required by HDMI specification. There should be no pull up on the HP_IN, ASIC side of CM2030. http://onsemi.com 6

CM2030 SPECIFICATIONS Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units VCC5, VCCLV 6.0 V DC Voltage at any Channel Input [GND − 0.5] to [VCC + 0.5] V Storage Temperature Range −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. STANDARD (RECOMMENDED) OPERATING CONDITIONS Symbol Parameter Min Typ Max Units 5V_SUPPLY Operating Supply Voltage − 5 5.5 V LV_SUPPLY Bias Supply Voltage 1.0 3.3 5.5 V CE_SUPPLY Bias Supply Voltage 3.0 3.3 3.6 V − Operating Temperature Range –40 − 85 °C Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 7) Symbol Parameter Conditions Min Typ Max Units ICC5 Operating Supply Current 5V_SUPPLY = 5.0 V, 300 350 (cid:2)A CEC_OUT = 3.3 V, LV_SUPPLY = 3.3V, CE_SUPPLY = 3.3 V, DDC = 5 V (Note 12) ICCLV Bias Supply Current LV_SUPPLY = 3.3 V (Note 12) 60 150 (cid:2)A ICCCE Bias Supply Current CE_SUPPLY = 3.3 V, CEC_OUT = 0 V 60 150 (cid:2)A (Notes 12 and 13) ICEC Current Source on CEC Pin CE_SUPPLY = 3.3 V, 111 120 128 mA VDROP 5V_OUT Overcurrent Out Put Drop 5V_SUPPLY = 5.0 V, IOUT = 55 mA 65 100 mV ISC 5V_OUT Short Circuit Cur Rent Limit 5V_SUPPLY = 5.0 V, 5V_OUT = GND 90 135 175 mA IOFF OFF State Leakage Current, Level Shifting LV_SUPPLY = 0 V 0.1 5 (cid:2)A NFET IBACKDRIVE, Current Through CE−REMOTE_OUT when CE−REMOTE_IN = CE_SUPPLY < 0.1 1.8 (cid:2)A CEC Powered Down CE_REMOTE_OUT IBACKDRIVE, Current Through TMDS Pins when Powered All Supplies = 0 V, 0.1 5 (cid:2)A TMDS Down TMDS_[2:0]+/, TMDS_CK+/ = 4 V IBACKDRIVE, Current Through 5V_OUT when Powered All Supplies = 0 V, 0.1 5 (cid:2)A 5V_OUT Down 5V_OUT_PIN = 5 V IBACKDRIVE, Current Through DDC_DAT/CLK_OUT when All Supplies = 0 V, 0.1 5 (cid:2)A DDC Powered Down DDC_DAT/CLK_OUT = 5 V, DDC_DAT/CLK_IN = 0 V IBACKDRIVE, Current Through HOTPLUG_DET_OUT when All Supplies = 0 V, 0.1 5 (cid:2)A HOTPLUG Powered Down HOTPLUG_DET_OUT = 5 V, HOTPLUG_IN = 0 V CECSL CEC Slew Limit Measured from 10−90% or 90−10% 0.26 0.65 V/(cid:2)s 7. Operating Characteristics are over Standard Operating Conditions unless otherwise specified. 8. Standard IEC61000−4−2, CDISCHARGE = 150 pF, RDISCHARGE = 330 (cid:3), 5V_SUPPLY = 5 V, 3.3V_SUPPLY = 3.3 V, LV_SUPPLY = 3.3 V, GND = 0 V. 9. Human Body Model per MIL−STD−883, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 k(cid:3), 5V_SUPPLY = 5V, 3.3V_SUP- PLY=3.3V, LV_SUPPLY = 3.3 V, GND = 0 V. 10.Intra−pair matching, each TMDS pair (i.e. D+, D–) 11.These measurements performed with no external capacitor on VP (VP floating) 12.These static measurements do not include AC activity on controlled I/O lines. 13.This measurement does not inclue supply current for the 120 (cid:2)A current source on the CEC pin. http://onsemi.com 7

CM2030 Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 7) Symbol Parameter Conditions Min Typ Max Units CECRT CEC Rise Time Measured from 10−90% 26.4 250 (cid:2)s Assumes a signal swing from 0−3.3 V CECFT CEC Fall Time Measured from 90−10% 4 50 (cid:2)s Assumes a signal swing from 0−3.3 V VACC Turn On Threshold of I2C / DDC Accelerator Voltage is 0.3 ±10% X 5 V_Supply 1.35 1.5 1.65 V (Note 8) VON(DDC_OUT) Voltage Drop across DDC Level Shifter LV_SUPPLY = 3.3 V, 3 mA Sink at 150 225 mV DDCIN, DDCOUT < VACC VOL(DDC_IN) Logic Level (ASIC side) when I2C / DDC Logic DDC_OUT = 0.4 V, 0.3 0.4 V Low Applied (I2C Pass−through Compatibility) LV_SUPPLY = 3.3 V, 1.5 k(cid:3) pullup on DDC_OUT to 5.0 V (Note 8) tr(DDC) DDC_OUT Line Risetime, DDC_IN floating, LV_SUPPLY = 3.3 V, 1 (cid:2)s VACC < VDDC_OUT < (5V_Supply − 0.5 V) 1.5 k(cid:3) pullup on DDC_OUT to 5.0 V, Bus Capacitance = 1500 pF VF Diode Forward Voltage IF = 8 mA, TA = 25°C V Top Diode 0.6 0.85 0.95 Bottom Diode 0.6 0.85 0.95 VESD ESD Withstand Voltage (IEC) Pins 4, 7, 10, 13, 20, 21, 22, 23, 24, 27, ±8 kV 30, 33, TA = 25°C (Note 8) VESD ESD Withstand Voltage (HBM) Pins 1, 2, 16, 17, 18, 19, 37, 38, ±2 kV TA = 25°C VCL Channel Clamp Voltage TA = 25°C, IPP = 1 A, tP = 8/20 (cid:2)S V Positive Transients (Note 11) 11.0 Negative Transients 2.0 RDYN Dynamic Resistance TA = 25°C, IPP = 1 A, tP = 8/20 (cid:2)S (cid:3) Positive Transients Any I/O pin to Ground (Note 11) 1.4 Negative Transients 0.9 ILEAK TMDS Channel Leakage Current TA = 25°C 0.01 1 (cid:2)A CIN, TMDS TMDS Channel Input Capacitance 5V_SUPPLY = 5.0 V, Measured at 0.9 1.2 pF 1MHz, VBIAS = 2.5 V (cid:4)C , TMDS TMDS Channel Input Capacitance Matching 5V_SUPPLY = 5.0 V, Measured at 0.05 pF IN 1MHz, VBIAS = 2.5 V (Note 10) CMUTUAL Mutual Capacitance between Signal Pin and 5V_SUPPLY = 0 V, 0.07 pF Adja Cent Signal Pin Measured at 1MHz, VBIAS = 2.5 V CIN, DDCOUT Level Shifting Input Capacitance, Capacitance 5V_SUPPLY = 0 V, 10 pF to GND Measured at 100 kHz, VBIAS = 2.5 V CIN, CECOUT Level Shifting Input Capacitance, Capacitance 5V_SUPPLY = 0 V, 10 pF to GND Measured at 100 kHz, VBIAS = 1.65 V CIN, HPOUT Level Shifting Input Capacitance, Capacitance 5V_SUPPLY = 0 V, 10 pF to GND Measured at 100 kHz, VBIAS = 2.5 V 7. Operating Characteristics are over Standard Operating Conditions unless otherwise specified. 8. Standard IEC61000−4−2, CDISCHARGE = 150 pF, RDISCHARGE = 330 (cid:3), 5V_SUPPLY = 5 V, 3.3V_SUPPLY = 3.3 V, LV_SUPPLY = 3.3 V, GND = 0 V. 9. Human Body Model per MIL−STD−883, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 k(cid:3), 5V_SUPPLY = 5V, 3.3V_SUP- PLY=3.3V, LV_SUPPLY = 3.3 V, GND = 0 V. 10.Intra−pair matching, each TMDS pair (i.e. D+, D–) 11.These measurements performed with no external capacitor on VP (VP floating) 12.These static measurements do not include AC activity on controlled I/O lines. 13.This measurement does not inclue supply current for the 120 (cid:2)A current source on the CEC pin. http://onsemi.com 8

CM2030 PERFORMANCE INFORMATION Typical Filter Performance (TA = 25°C, DC Bias = 0 V, 50 (cid:3) Environment) Figure 8. Insertion Loss vs. Frequency (TMDS_D1− to GND) APPLICATION INFORMATION Design Considerations 5V_OUT (pin 38) Maximum overcurrent protection output drop at 55mA on 5V_OUT is 100mV. To meet HDMI output requirements of 4.8−5.3V, an input of greater than 4.9V should be used (i.e. 5.1V ±4%) DUT On vs. DUT Off Many HDMI CTS tests require a power off condition on the System Under Test. Many discrete ESD diode configurations can be forward biased when their VDD rail is lower than the I/O pin bias, thereby exhibiting extremely high apparent (cid:2) capacitance measurements, for example. The MediaGuard backdrive isolation circuitry limits this current to less than 5mA, and will help ensure HDMI compliance. http://onsemi.com 9

CM2030 APPLICATION INFORMATION (Cont’d) LAYOUT NOTES 1) Differential TMDS Pairs should be designed as normal 100(cid:3) HDMI Microstrip. Single Ended (decoupled) TMDS traces underneath MediaGuard(cid:2), and traces between MediaGuard(cid:2) and Connector should be tuned to match chip/connector IBIS parasitics. 2) Level Shifter signals should be biased with a weak pullup to the desired local LV_SUPPLY. If the local ASIC includes sufficient pullups to register a logic high, then external pullups may not be needed. 3) Place MediaGuard(cid:2) as close to the connector as possible, and as with any controlled impedance line always avoid placing any silk−screen printing over TMDS traces. 4) CM2020/CM2030 footprint compatibility − For the CM2030, Pin 37 becomes the VCEC power supply pin for the slew−rate limiting circuitry. This can be supplied by a 0 (cid:3) jumper to VCEC which should be depopulated to utilize the CM2020. The 100nF CBYP is recommended for all applications. 5) CEC pullup isolation. The 27k RCEC and a Schottky DCEC provide the necessary isolation for the CEC pullup. Note: This circuitry is used only in the CM2020. Depopulate the components for CM2030 applications in a CM2020/ CM2030 dual footprint layout. 6) Footprint compatibility − The CM2030 has (built−in) internal backdrive protection. The CM2020 does not not have internal backdrive protection and requires the external RCEC and DCEC components. 7) (For CM2030) If CEC firmware is not implemented, do not populate with 0(cid:3) resistor. If CEC firmware is implemented, then populate with 0 (cid:3) resistor. (For CM2020) Populate with 0 (cid:3) resistor in either case. Figure 9. Typical Application for CM2030 http://onsemi.com 10

CM2030 PACKAGE DIMENSIONS TSSOP 38 CASE 948AG ISSUE O MediaGuard is a trademark of Nagra France. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com CM2030/D 11

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