CM1213A, SZCM1213A 1, 2 and 4-Channel Low Capacitance ESD Protection Arrays Product Description The CM1213A family of diode arrays has been designed to provide www.onsemi.com ESD protection for electronic components or subsystems requiring minimal capacitive loading. These devices are ideal for protecting systems with high data and clock rates or for circuits requiring low capacitive loading. Each ESD channel consists of a pair of diodes in series which steer the positive or negative ESD current pulse to either SOT23−3 SOT−143 SC−74 the positive (V ) or negative (V ) supply rail. A Zener diode is SO SUFFIX SR SUFFIX SO SUFFIX P N CASE 318 CASE 318A CASE 318F embedded between V and V , offering two advantages. First, it P N protects the V rail against ESD strikes, and second, it eliminates the CC need for a bypass capacitor that would otherwise be needed for absorbing positive ESD strikes to ground. The CM1213A will protect against ESD pulses up to 12 kV per the IEC 61000−4−2 standard. SC70−6 MSOP−10 S7 SUFFIX MR SUFFIX Features CASE 419AD CASE 846AE • One, Two, and Four Channels of ESD Protection Note: For 6 and 8−channel Devices, See the CM1213 Datasheet MARKING DIAGRAMS • Provides ESD Protection to IEC61000−4−2 Level 4 ♦ ±12 kV Contact Discharge • Low Channel Input Capacitance of 0.85 pF Typical XXXM(cid:2) XXXM(cid:2) • (cid:2) (cid:2) Minimal Capacitance Change with Temperature and Voltage • Channel Input Capacitance Matching of 0.02 pF Typical is Ideal for 1 1 Differential Dignals XXX = Specific Device Code • Each CH (I/O) Pin Can Withstand Over 1000 ESD Strikes* M = Date Code • (cid:2) = Pb−Free Package SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and 10 PPAP Capable XXXX • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS AYW(cid:2) (cid:2) Compliant 1 Applications • XXXX = Specific Device Code USB2.0 Ports at 480 Mbps in Desktop PCs, Notebooks and Peripherals A = Assembly Location • ® IEEE1394 Firewire Ports at 400 Mbps/800 Mbps Y = Year • W = Work Week DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs, (cid:2) = Pb−Free Package LCD Displays • (Note: Microdot may be in either location) Serial ATA Ports in Desktop PCs and Hard Disk Drives • PCI Express Ports • General Purpose High−Speed Data Line ESD Protection ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page2 of this data sheet. *Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to ±8 kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec after the 1000 strikes. © Semiconductor Components Industries, LLC, 2011 1 Publication Order Number: November, 2018 − Rev. 15 CM1213A/D

CM1213A, SZCM1213A BLOCK DIAGRAM VP VP CH4 VP CH3 CH1 CH1 CH2 VN VN CH1 VN CH2 CM1213A−01SO CM1213A−02SR CM1213A−04MR CM1213A−02SO CM1213A−04S7 Table 1. ORDERING INFORMATION Device Marking Package Shipping† CM1213A−01SO 231 SOT23−3 3,000 / Tape & Reel (Pb−Free) SZCM1213A−01SO* CM1213A−02SR D232 SOT143−4 3,000 / Tape & Reel (Pb−Free) SZCM1213A−02SR* CM1213A−02SO 233 SC−74 3,000 / Tape & Reel (Pb−Free) CM1213A−04S7 D38 SC70−6 3,000 / Tape & Reel (Pb−Free) CM1213A−04MR D237 MSOP−10 4,000 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. www.onsemi.com 2

CM1213A, SZCM1213A PACKAGE/PINOUT DIAGRAMS Table 2. PIN DESCRIPTIONS 1−Channel, 3−Lead SOT23−3 Package (CM1213A−01SO) Pin Name Type Description Top View 1 CH1 I/O ESD Channel CH1 (1) 1 2 VP PWR Positive Voltage Supply Rail 231 3 VN (3) 3 VN GND Negative Voltage Supply Rail VP (2) 2 3−Lead SOT23−3 2−Channel, 4−Lead SOT143−4 Package (CM1213A−02SR) Pin Name Type Description 1 VN GND Negative Voltage Supply Rail 2 CH1 I/O ESD Channel Top View 3 CH2 I/O ESD Channel VN (1) 1 4 VP (4) D 4 VP PWR Positive Voltage Supply Rail 23 2 CH1 (2) 2 3 CH2 (3) 2−Channel, SC−74 Package (CM1213A−02SO) 4−Lead SOT143−4 Pin Name Type Description 1 NC − No Connect 2 VN GND Negative Voltage Supply Rail 3 CH1 I/O ESD Channel Top View 4 CH2 I/O ESD Channel NC (1) 1 6 VP (6) 5 NC − No Connect VN (2) 2 23 5 NC (5) 3 6 VP PWR Positive Voltage Supply Rail CH1 (3) 3 4 CH2 (4) 6−Lead SC−74 4−Channel, 6−Lead SC70−6 (CM1213A−04S7) Pin Name Type Description 1 CH1 I/O ESD Channel 2 VN GND Negative Voltage Supply Rail Top View 3 CH2 I/O ESD Channel CH1 1 6 CH4 4 CH3 I/O ESD Channel D 5 VP PWR Positive Voltage Supply Rail VN 2 38 5 VP 6 CH4 I/O ESD Channel CH2 3 4 CH3 6−Lead SC70−6 4−Channel, 10−Lead MSOP−10 Package (CM1213A04MR) Pin Name Type Description 1 CH1 I/O ESD Channel 2 NC − No Connect Top View 3 VP PWR Positive Voltage Supply Rail CH1 1 10 NC 4 CH2 I/O ESD Channel NC 2 D 9 CH4 VP 3 23 8 VN 5 NC − No Connect CH2 4 8 7 NC NC 5 6 CH3 6 CH3 I/O ESD Channel 10−Lead MSOP−10 7 NC − No Connect 8 VN GND Negative Voltage Supply Rail 9 CH4 I/O ESD Channel 10 NC − No Connect www.onsemi.com 3

CM1213A, SZCM1213A SPECIFICATIONS Table 3. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units Operating Supply Voltage (VP − VN) 5.5 V Operating Temperature Range –40 to +150 °C Storage Temperature Range –65 to +150 °C DC Voltage at any channel input (VN − 0.5) to (VP + 0.5) V Package Power Rating mW SOT23−3, SOT143−4, SC−74, and SC70−6 Packages 225 MSOP−10 Package 400 ESD kV IEC 61000−4−2 Contact ±12 IEC 61000−4−2 Air ±12 ISO 10605 330 pF / 330 (cid:2) Contact ±9 ISO 10605 330 pF / 2 k(cid:2) Contact ±22 ISO 10605 150 pF / 2 k(cid:2) Contact ±25 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note1) Symbol Parameter Conditions Min Typ Max Units VP (VRWM) Operating Supply Voltage (VP−VN) 3.3 5.5 V IP Operating Supply Current VP pin to VN pin, (VP = 3.3 V, VN = 0 V) 8.0 (cid:3)A ILEAK Channel Leakage Current CH pin to VN pin, TA = 25°C; 0.1 1.0 (cid:3)A (VP = 5 V, VN = 0 V) VF Diode Forward Voltage IF = 8 mA; TA = 25°C V Top Diode 0.60 0.80 0.95 Bottom Diode 0.60 0.80 0.95 VBR Breakdown Voltage IT = 10 mA, CH pin to VN pin 6.5 9.0 V CIN Channel Input Capacitance At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V 0.85 1.2 pF (Note 2) (cid:4)CIN Channel Input Capacitance Matching At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V 0.02 pF (Note 2) VCL Channel Clamp Voltage TA = 25°C, IPP = 1A, tP = 8/20 (cid:3)s V Positive Transients (Note 2) +10 Negative Transients –1.7 RDYN Dynamic Resistance IPP = 1A, tP = 8/20 (cid:3)s (cid:2) Positive Transients Any I/O pin to Ground 0.9 Negative Transients (Note 2) 0.5 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. All parameters specified at TA = 25°C unless otherwise noted. 2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 (cid:2), VP = 3.3 V, VN grounded. 3. These measurements performed with no external capacitor on VP (VP floating). www.onsemi.com 4

CM1213A, SZCM1213A PERFORMANCE INFORMATION Input Channel Capacitance Performance Curves Figure 1. Typical Variation of C vs. V IN IN (f = 1 MHz, V = 3.3 V, V = 0 V, 0.1 (cid:2)F Chip Capacitor between V and V , 25(cid:2)C) P N P N Figure 2. Typical Variation of C vs. Temp IN (f = 1 MHz, V = 30 mV, V = 3.3 V, V = 0 V, 0.1 (cid:2)F Chip Capacitor between V and V ) IN P N P N www.onsemi.com 5

CM1213A, SZCM1213A PERFORMANCE INFORMATION (Cont’d) Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment) Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, V =3.3 V) P Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, V =3.3 V) P www.onsemi.com 6

CM1213A, SZCM1213A APPLICATION INFORMATION Design Considerations In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically aconnector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L and L . The voltage V on the line being protected is: 1 2 CL VCL = Fwd Voltage Drop of D1 + VSUPPLY + L1 x d(IESD) / dt + L2 x d(IESD) / dt where I is the ESD current pulse, and V is the positive supply voltage. ESD SUPPLY An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(I )/dt can be ESD approximated by (cid:4)IESD/(cid:4)t, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300V increment in V ! CL Similarly for negative ESD pulses, parasitic series inductance from the V pin to the ground rail will lead to drastically N increased negative voltage on the line being protected. The CM1213A has an integrated Zener diode between V and V . This greatly reduces the effect of supply rail inductance P N L on V by clamping V at the breakdown voltage of the Zener diode. However, for the lowest possible V , especially when 2 CL P CL V is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 (cid:3)F ceramic chip P capacitor be connected between V and the ground plane. P As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V pin of the Protection P Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance. Additional Information See also ON Semiconductor Application Note “Design Considerations for ESD Protection”, in the Applications section. L2 POSITIVE SUPPLY RAIL VCC VP PATH OF ESD CURRENT PULSE IESO ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ LINE BEING ÇÇÇÇÇÇ D1 L1 PROTECTED SYSTEM OR 0.22 (cid:3)F ÇÇÇÇÇÇ ÇÇCIRÇCUITÇRYÇÇ BEING ÇÇÇONÇE ÇÇCHANNEL ÇÇPRÇOTEÇCTEÇD Ç CHANNEL INPUT ÇÇDÇ2 OCMFÇ1213ÇÇ 25 A VCL ÇÇÇÇÇÇ ÇÇÇÇÇÇ 0 A GROUND RAIL VN CHASSIS GROUND Figure 5. Application of Positive ESD Pulse between Input Channel and Ground www.onsemi.com 7

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−23 (TO−236) CASE 318−08 ISSUE AS DATE 30 JAN 2018 SCALE 4:1 D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. 0.25 MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF 3 THE BASE MATERIAL. E HE T 4. DPRIMOETNRSUIOSINOSN DS, AONRD G EA DTEO BNUORTR INS.CLUDE MOLD FLASH, 1 2 MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX L A 0.89 1.00 1.11 0.035 0.039 0.044 3Xb L1 A1 0.01 0.06 0.10 0.000 0.002 0.004 b 0.37 0.44 0.50 0.015 0.017 0.020 e VIEW C c 0.08 0.14 0.20 0.003 0.006 0.008 TOP VIEW D 2.80 2.90 3.04 0.110 0.114 0.120 E 1.20 1.30 1.40 0.047 0.051 0.055 e 1.78 1.90 2.04 0.070 0.075 0.080 L 0.30 0.43 0.55 0.012 0.017 0.022 A L1 0.35 0.54 0.69 0.014 0.021 0.027 HE 2.10 2.40 2.64 0.083 0.094 0.104 T 0° −−− 10° 0° −−− 10° A1 c SIDE VIEW SEE VIEW C GENERIC END VIEW MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT XXXM(cid:2) (cid:2) 1 2.90 03.X90 XXX= Specific Device Code M = Date Code (cid:2) = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to 3X0.80 0.95 device data sheet for actual part marking. PITCH Pb−Free indicator, “G” or microdot “ (cid:2)”, DIMENSIONS: MILLIMETERS may or may not be present. STYLE 1 THRU 5: STYLE 6: STYLE 7: STYLE 8: CANCELLED PIN 1. BASE PIN 1. EMITTER PIN 1. ANODE 2. EMITTER 2. BASE 2. NO CONNECTION 3. COLLECTOR 3. COLLECTOR 3. CATHODE STYLE 9: STYLE 10: STYLE 11: STYLE 12: STYLE 13: STYLE 14: PIN 1. ANODE PIN 1. DRAIN PIN 1. ANODE PIN 1. CATHODE PIN 1. SOURCE PIN 1. CATHODE 2. ANODE 2. SOURCE 2. CATHODE 2. CATHODE 2. DRAIN 2. GATE 3. CATHODE 3. GATE 3. CATHODE−ANODE 3. ANODE 3. GATE 3. ANODE STYLE 15: STYLE 16: STYLE 17: STYLE 18: STYLE 19: STYLE 20: PIN 1. GATE PIN 1. ANODE PIN 1. NO CONNECTION PIN 1. NO CONNECTION PIN 1. CATHODE PIN 1. CATHODE 2. CATHODE 2. CATHODE 2. ANODE 2. CATHODE 2. ANODE 2. ANODE 3. ANODE 3. CATHODE 3. CATHODE 3. ANODE 3. CATHODE−ANODE 3. GATE STYLE 21: STYLE 22: STYLE 23: STYLE 24: STYLE 25: STYLE 26: PIN 1. GATE PIN 1. RETURN PIN 1. ANODE PIN 1.GATE PIN 1.ANODE PIN 1.CATHODE 2. SOURCE 2. OUTPUT 2. ANODE 2.DRAIN 2.CATHODE 2.ANODE 3. DRAIN 3. INPUT 3. CATHODE 3.SOURCE 3.GATE 3.NO CONNECTION STYLE 27: STYLE 28: PIN 1.CATHODE PIN 1.ANODE 2.CATHODE 2.ANODE 3.CATHODE 3.ANODE DOCUMENT NUMBER: 98ASB42226B Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number: October, D20E0S2C −R RIePvT. I0ON: SOT−23 (TO−236) 1 PAGE 1 OFX 2XX

DOCUMENT NUMBER: 98ASB42226B PAGE 2 OF 2 ISSUE REVISION DATE AJ ADDED STYLE 27. REQ. BY P. LEM. 07 JUL 2004 AK OBSOLETED −09 VERSION. REQ. BY D. TRUHITTE. 14 SEP 2004 AL ADDED NOMINAL VALUES AND UPDATED GENERIC MARKING DIAGRAM. REQ. 27 MAY 2005 BY HONG XIAO. AM REDREW LEAD SIDE VIEW. REQ BY DARRELL TRUHITTE. 26 AUG 2005 AN REINTRODUCED LABELS FOR DIMENSION C. REQ. BY D. TRUHITTE. 14 OCT 2005 AP ADDED THETA DEGREE VALUES TO DIMENSION TABLE. REQ. BY D. TRUHITTE. 17 NOV 2009 AR MODIFIED DIMENSIONS C AND L. REQ. BY M. YOU. 10 OCT 2016 AS ADDED STYLE 28. REQ. BY E. ESTILLER. 30 JAN 2018 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2018 Case Outline Number: January, 2018 − Rev. AS 318

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−143 CASE 318A−06 ISSUE U DATE 07 SEP 2011 SCALE 4:1 D NOTES: e 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. A D 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIM­ UM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO­ GAUGE TRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, PLANE SEATING AND GATE BURRS SHALL NOT EXCEED 0.25 PER SIDE. PLANE DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR E L2 L PROTRUSION. INTERLEAD FLASH AND PROTRUSION SHALL NOT EXCEED 0.25 PER SIDE. E1 DETAIL A 5. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 6. DATUMS A AND B ARE DETERMINED AT DATUM H. b1 MILLIMETERS DIM MIN MAX e1 B 3X b A 0.80 1.12 0.20 M C A-B D A1 0.01 0.15 TOP VIEW b 0.30 0.51 b1 0.76 0.94 c 0.08 0.20 H D 2.80 3.05 c 0.10 C c E 2.10 2.64 E1 1.20 1.40 A e 1.92 BSC A1 SIDE VIEW C SPELAATNIENG DETAIL A END VIEW eL1 0.305.20 BS0C.70 L2 0.25 BSC GENERIC RECOMMENDED MARKING DIAGRAM* SOLDERING FOOTPRINT 1.92 XXX M(cid:2) (cid:2) 1 4X 0.75 2.70 XXX= Specific Device Code M = Date Code (cid:2) = Pb−Free Package (Note: Microdot may be in either location) 0.20 3X *This information is generic. Please refer to 0.96 0.54 device data sheet for actual part marking. DIMENSIONS: MILLIMETERS Pb−Free indicator, “G” or microdot “ (cid:2)”, may or may not be present. STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: STYLE 6: PIN 1.COLLECTOR PIN 1.SOURCE PIN 1.GROUND PIN 1.OUTPUT PIN 1.SOURCE PIN 1.GND 2.EMITTER 2.DRAIN 2.SOURCE 2.GROUND 2.DRAIN 2.RF IN 3.EMITTER 3.GATE 1 3.INPUT 3.GROUND 3.GATE 1 3.VREG 4.BASE 4.GATE 2 4.OUTPUT 4.INPUT 4.SOURCE 4.RF OUT STYLE 7: STYLE 8: STYLE 9: STYLE 10: STYLE 11: PIN 1.SOURCE PIN 1.SOURCE PIN 1.GND PIN 1.DRAIN PIN 1.SOURCE 2.GATE 2.GATE 2.IOUT 2.N/C 2.GATE 1 3.DRAIN 3.DRAIN 3.VCC 3.SOURCE 3.GATE 2 4.SOURCE 4.N/C 4.VREF 4.GATE 4.DRAIN DOCUMENT NUMBER: 98ASB42227B Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number: October, D20E0S2C −R RIePvT. I0ON: SOT−143 1 PAGE 1 OFX 2XX

DOCUMENT NUMBER: 98ASB42227B PAGE 2 OF 2 ISSUE REVISION DATE U REDREW TO JEDEC STANDARDS. ADDED SOLDER FOOTPRINT. REQ. BY D. 07 SEP 2011 TRUHITTE. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2011 Case Outline Number: September, 2011 − Rev. 06U 318A

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SC−74 CASE 318F−05 6 ISSUE N 1 DATE 08 JUN 2012 SCALE 2:1 D NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM 6 5 4 THICKNESS OF BASE MATERIAL. HE E 4. 318F−01, −02, −03, −04 OBSOLETE. NEW STANDARD 318F−05. 1 2 3 MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX A 0.90 1.00 1.10 0.035 0.039 0.043 b A1 0.01 0.06 0.10 0.001 0.002 0.004 e b 0.25 0.37 0.50 0.010 0.015 0.020 c 0.10 0.18 0.26 0.004 0.007 0.010 D 2.90 3.00 3.10 0.114 0.118 0.122 (cid:2) E 1.30 1.50 1.70 0.051 0.059 0.067 c e 0.85 0.95 1.05 0.034 0.037 0.041 A L 0.20 0.40 0.60 0.008 0.016 0.024 0.05 (0.002) HE 2.50 2.75 3.00 0.099 0.108 0.118 (cid:2) 0° − 10° 0° − 10° L A1 GENERIC SOLDERING FOOTPRINT* MARKING DIAGRAM* 2.4 0.094 XXX M(cid:2) (cid:2) 0.95 1.9 0.037 XXX = Specific Device Code M = Date Code 0.074 0.95 (cid:2) = Pb−Free Package 0.7 0.037 (Note: Microdot may be in either location) 0.028 *This information is generic. Please refer to device data sheet for actual part marking. 1.0 (cid:2) mm (cid:3) Pb−Free indicator, “G” or microdot “ (cid:2)”, SCALE 10:1 may or may not be present. 0.039 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: STYLE 6: PIN 1.CATHODE PIN 1.NO CONNECTION PIN 1.EMITTER 1 PIN 1.COLLECTOR 2 PIN 1.CHANNEL 1 PIN 1.CATHODE 2.ANODE 2.COLLECTOR 2.BASE 1 2.EMITTER 1/EMITTER 2 2.ANODE 2.ANODE 3.CATHODE 3.EMITTER 3.COLLECTOR 2 3.COLLECTOR 1 3.CHANNEL 2 3.CATHODE 4.CATHODE 4.NO CONNECTION 4.EMITTER 2 4.EMITTER 3 4.CHANNEL 3 4.CATHODE 5.ANODE 5.COLLECTOR 5.BASE 2 5.BASE 1/BASE 2/COLLECTOR 3 5.CATHODE 5.CATHODE 6.CATHODE 6.BASE 6.COLLECTOR 1 6.BASE 3 6.CHANNEL 4 6.CATHODE STYLE 7: STYLE 8: STYLE 9: STYLE 10: STYLE 11: PIN 1.SOURCE 1 PIN 1.EMITTER 1 PIN 1.EMITTER 2 PIN 1.ANODE/CATHODE PIN 1.EMITTER 2.GATE 1 2.BASE 2 2.BASE 2 2.BASE 2.BASE 3.DRAIN 2 3.COLLECTOR 2 3.COLLECTOR 1 3.EMITTER 3.ANODE/CATHODE 4.SOURCE 2 4.EMITTER 2 4.EMITTER 1 4.COLLECTOR 4.ANODE 5.GATE 2 5.BASE 1 5.BASE 1 5.ANODE 5.CATHODE 6.DRAIN 1 6.COLLECTOR 1 6.COLLECTOR 2 6.CATHODE 6.COLLECTOR DOCUMENT NUMBER: 98ASB42973B Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number: October, D20E0S2C −R RIePvT. I0ON: SC−74 1 PAGE 1 OFX 2XX

DOCUMENT NUMBER: 98ASB42973B PAGE 2 OF 2 ISSUE REVISION DATE D CHANGE OF OWNERSHIP FROM MOTOROLA TO ON SEMICONDUCTOR. 14 MAR 01 DIM A WAS: 2.70−3.10 MM/0.1063−0.1220 IN. DIM C WAS: 1.000−1.30 MM/0.0394−0.0511IN DIM D WAS: 0.25−0.40 MM/0.0098−0.0157 IN. REQ. BY D. TRUHITTE E CHANGED “USED ON” WAS: SC−59, 6 LEAD. REQ.BY D. TRUHITTE. 27 MAR 01 F ADDED STYLE 3. REQ. BY S. BACHMAN. 23 APR 01 G ADDED STYLE 4. REQ. BY S. BACHMAN. 28 AUG 02 H ADDED STYLE 5. REQ. BY B. BLACKMON. 21 OCT 02 J ADDED STYLE 6. REQ. BY B. BLACKMON. 09 JAN 03 K ADDED STYLES 7 & 8. REQ. BY S. CHANG 03 JUN 03 L ADDED NOMINAL VALUES AND UPDATED GENERIC MARKING DIAGRAM. REQ. BY 27 MAY 05 HONG XIAO. M ADDED STYLE 9. REQ. BY W. MEADOWS. 11 APR 2006 N ADDED STYLES 10 & 11. REQ. BY Y. KALDERON. 08 JUN 2012 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2012 Case Outline Number: June, 2012 − Rev. N 318F

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SC−88 (SC−70 6 Lead), 1.25x2 CASE 419AD−01 ISSUE A DATE 07 JUL 2010 SYMBOL MIN NOM MAX D A 0.80 1.10 e e A1 0.00 0.10 A2 0.80 1.00 b 0.15 0.30 c 0.10 0.18 E1 E D 1.80 2.00 2.20 E 1.80 2.10 2.40 E1 1.15 1.25 1.35 e 0.65 BSC L 0.26 0.36 0.46 L1 0.42 REF L2 0.15 BSC TOP VIEW θ 0º 8º θ1 4º 10º (cid:2)1 A2 A (cid:2) L b (cid:2)1 A1 L1 c L2 SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-203. DOCUMENT NUMBER: 98AON34266E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. REFERENCE: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number: October, D20E0S2C −R RIePvT. I0ON: SC−88 (SC−70 6 LEAD), 1.25X21 PAGE 1 OFX 2XX

DOCUMENT NUMBER: 98AON34266E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION FROM POD #SC706−023−02 TO ON 19 DEC 2008 SEMICONDUCTOR. REQ. BY B. BERGMAN. A ADDED SC−88 TO DESCRIPTION AND TITLE. REQ. BY D. TRUHITTE. 07 JUL 2010 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2010 Case Outline Number: July, 2010 − Rev. 01A 419AD

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS MSOP10, 3x3 CASE 846AE SCALE 1:1 ISSUE A DATE 20 JUN 2017 A NOTES: 10 D 6 B F 12.. DCIOMNETNRSOIOLLNISN GA NDDIM TEONLSEIROANNSC: MINIGLL PIMEERT AESRMSE. Y14.5M, 1994. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. (cid:2) ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 MM IN EXCESS OF MAXIMUM MATERIAL CONDITION. 4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, E ÉÉ E1 L2 L PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PIN ONE ÉÉ L1 C MM PER SIDE. DIMENSION E DOES NOT INCLUDE INTER- INDICATOR DETAIL A LPERAODT RFULASSIOHN O SRH PARLLO TNROUTS EIOXCNE. IENDT E0R.2L5E MAMD FPLEARS SHI DOER. 1 5 e DIMENSIONS D AND E ARE DETERMINED AT DATUM F. 10Xb 56.. DA1A TISU MDESF AIN AENDD A BS T TOH EB EV EDRETTIECRAML IDNIESDT AANTC DEA TFURMOM F. THE 0.08 M C B S A S SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE TOP VIEW BODY. MILLIMETERS A DETAIL A DIM MIN NOM MAX A −−− −−− 1.10 A1 A1 0.00 0.05 0.15 A2 0.75 0.85 0.95 b 0.17 −−− 0.27 0.10 C c c 0.13 −−− 0.23 C SPELAATNIENG END VIEW DE 24..9705 34..0900 35..1005 SIDE VIEW E1 2.90 3.00 3.10 e 0.50 BSC L 0.40 0.70 0.80 L1 0.95 REF RECOMMENDED L2 0.25 BSC SOLDERING FOOTPRINT* (cid:2) 0° −−− 8° 10X 10X0.29 0.85 GENERIC MARKING DIAGRAM* 10 5.35 XXXX AYW(cid:2) (cid:2) 1 0.50 PITCH XXXX = Specific Device Code DIMENSIONS: MILLIMETERS A = Assembly Location Y = Year *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and W = Work Week Mounting Techniques Reference Manual, SOLDERRM/D. (cid:2) = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ (cid:2)”, may or may not be present and may be in either location. Some products may not follow the Generic Marking. DOCUMENT NUMBER: 98AON34098E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. REFERENCE: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number: October, D20E0S2C −R RIePvT. I0ON: MSOP10, 3X3 1 PAGE 1 OFX 2XX

DOCUMENT NUMBER: 98AON34098E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION FROM POD #MSOP10−013−01 TO ON SEMICON- 19 DEC 2008 DUCTOR. REQ. BY B. BERGMAN. A MODIFIED DRAWING TO ON SEMICONDUCTOR JEDEC STANDARD AND 20 JUN 2017 ADDED SOLDERING FOOTPRINT. REQ. BY M. PREJZEK. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2017 Case Outline Number: June, 2017 − Rev. A 846AE

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