CM1213 6 and 8-Channel Low Capacitance ESD Protection Arrays Product Description The CM1213 family of diode arrays has been designed to provide http://onsemi.com ESD protection for electronic components or sub−systems requiring minimal capacitive loading. These devices are ideal for protecting systems with high data and clock rates or for circuits requiring low capacitive loading. Each ESD channel consists of a pair of diodes in series which steer the positive or negative ESD current pulse to either SOIC−8 MSOP−8 MSOP−10 the positive (VP) or negative (VN) supply rail. A Zener diode is SM SUFFIX MR SUFFIX MR SUFFIX embedded between V and V , offering two advantages. First, it CASE 751AC CASE 846AD CASE 846AE P N protects the V rail against ESD strikes, and second, it eliminates the CC need for a bypass capacitor that would otherwise be needed for BLOCK DIAGRAMS absorbing positive ESD strikes to ground. The CM1213 will protect against ESD pulses up to ±8 kV per the IEC 61000−4−2 standard. CH6 VP CH5CH4 These devices are particularly well−suited for protecting systems ® using high−speed ports such as USB2.0, IEEE1394 (Firewire , iLink(cid:2)), Serial ATA, DVI, HDMI and corresponding ports in removable storage, digital camcorders, DVD−RW drives and other applications where extremely low loading capacitance with ESD CH1CH2 VN CH3 protection are required in a small package footprint. CM1213−06SM Features CM1213−06MR • 6 or 8 Channels of ESD Protection Note: For 1, 2, and 4 Channel Devices, See the CM1213A Datasheet CH8 CH7 VP CH6 CH5 • Provides ESD Protection to IEC61000−4−2 Level 4 • ±8 kV Contact Discharge • Low Channel Input Capacitance of 1.0 pF Typical • Minimal Capacitance Change with Temperature and Voltage • Channel Input Capacitance Matching of 0.02 pF Typical is Ideal for CH1CH2 VN CH3 CH4 Differential Signals CM1213−08MR • Mutual Capacitance between Signal Pin and Adjacent Signal Pin −0.11pF Typical • Zener Diode Protects Supply Rail and Eliminates the Need for ORDERING INFORMATION External By−pass Capacitors Device Package Shipping† • Each I/O Pin Can Withstand Over 1000 ESD Strikes* CM1213−06SM SOIC−8 2500/Tape & Reel • Available in SOIC and MSOP (Pb−Free) • These Devices are Pb−Free and are RoHS Compliant CM1213−06MR MSOP−8 4000/Tape & Reel (Pb−Free) Applications • CM1213−08MR MSOP−10 4000/Tape & Reel USB2.0 Ports at 480 Mbps in Desktop PCs, Notebooks (Pb−Free) andPeripherals • ® †For information on tape and reel specifications, IEEE1394 Firewire Ports at 400 Mbps / 800 Mbps including part orientation and tape sizes, please • DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs, refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. LCD Displays • Serial ATA Ports in Desktop PCs and Hard Disk Drives • PCI Express Ports • General Purpose High−speed Data Line ESD Protection • Handheld PCs/PDAs *Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to ±8 kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec after the 1000 strikes. © Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: June, 2013 − Rev. 5 CM1213/D

CM1213 PACKAGE / PINOUT DIAGRAMS Table 1. PIN DESCRIPTIONS 6−Channel, 8−Lead MSOP−8/SOIC−8 Packages Top View Pin Name Type Description CH1 1 8 CH6 1 CH1 I/O ESD Channel CH2 2 D1 7 VP 2 CH2 I/O ESD Channel VN 3 36 6 CH5 CH3 4 5 CH4 3 VN GND Negative voltage supply rail 8−Lead SOIC−8 4 CH3 I/O ESD Channel 5 CH4 I/O ESD Channel 6 CH5 I/O ESD Channel 7 VP PWR Positive voltage supply rail Top View 8 CH6 I/O ESD Channel CH1 1 8 CH6 CH2 2 D1 7 VP VN 3 37 6 CH5 8−Channel, 10−Lead MSOP−10 Package CH3 4 5 CH4 Pin Name Type Description 8−Lead MSOP−8 1 CH1 I/O ESD Channel 2 CH2 I/O ESD Channel 3 CH3 I/O ESD Channel Top View 4 CH4 I/O ESD Channel CH1 1 10 CH8 5 VN GND Negative voltage supply rail CH2 2 9 CH7 D 6 CH5 I/O ESD Channel CH3 3 13 8 VP CH4 4 8 7 CH6 7 CH6 I/O ESD Channel VN 5 6 CH5 8 VP PWR Positive voltage supply rail 10−Lead MSOP−10 9 CH7 I/O ESD Channel 10 CH8 I/O ESD Channel GENERIC MARKING DIAGRAMS CM1213−06SM CM1213−06MR CM1213−08MR D136 D137 D138 YYWW XXXXX XXXXX XXXX YYWW YYWW XXXXX = Lot Number YY = Year WW = Work Week http://onsemi.com 2

CM1213 SPECIFICATIONS Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units Operating Supply Voltage (VP − VN) 6.0 V Operating Temperature Range −40 to +85 °C Storage Temperature Range −65 to +150 °C DC Voltage at any channel input (VN − 0.5) to (VP + 0.5) V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. STANDARD OPERATING CONDITIONS Parameter Rating Units Operating Temperature Range −40 to +85 °C Package Power Rating mW MSOP−8 Package (CM1213−06MR) 400 MSOP−10 Package (CM1213−08MR) 400 SOIC−8 Package (CM1213−06SM) 600 Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1) Symbol Parameter Conditions Min Typ Max Units VP Operating Supply Voltage (VP−VN) 3.3 5.5 V IP Operating Supply Current (VP−VN) = 3.3 V 8.0 (cid:2)A VF Diode Forward Voltage IF = 8 mA; TA = 25°C V Top Diode 0.60 0.80 0.95 Bottom Diode 0.60 0.80 0.95 ILEAK Channel Leakage Current TA = 25°C; VP = 5 V, VN = 0 V ±0.1 ±1.0 (cid:2)A CIN Channel Input Capacitance At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V 1.0 1.5 pF (cid:3)CIN Channel Input Capacitance Matching At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V 0.02 pF CMUTUAL Mutual Capacitance between signal pin At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V 0.11 pF and adjacent signal pin VESD ESD Protection kV Peak Discharge Voltage at any channel input, in system Contact discharge per TA = 25°C (Notes 3 and 4) ±8 IEC 61000−4−2 standard VCL Channel Clamp Voltage TA = 25°C, IPP = 1 A, tP = 8/20 (cid:2)S V Positive Transients (Note 4) +8.8 Negative Transients −1.4 RDYN Dynamic Resistance IPP = 1 A, tP = 8/20 (cid:2)S (cid:4) Positive Transients Any I/O pin to Ground (Note 4) 0.7 Negative Transients 0.4 1. All parameters specified at TA = −40°C to +85°C unless otherwise noted. 2. Human Body Model per MIL−STD−883, Method 3015, CDischarge = 100 pF, RDischarge = 1.5 K(cid:4), VP = 3.3 V, VN grounded. 3. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 (cid:4), VP = 3.3 V, VN grounded. 4. These measurements performed with no external capacitor on VP (VP floating). http://onsemi.com 3

CM1213 PERFORMANCE INFORMATION Input Channel Capacitance Performance Curves Figure 1. Typical Variation of C vs. V IN IN (f = 1 MHz, V = 3.3 V, V = 0 V, 0.1 (cid:2)F Chip Capacitor between V and V , 25(cid:2)C) P N P N Figure 2. Typical Variation of C vs. Temp IN (f = 1 MHz, V = 30 mV, V = 3.3 V, V = 0 V, 0.1 (cid:2)F Chip Capacitor between V and V ) IN P N P N http://onsemi.com 4

CM1213 PERFORMANCE INFORMATION (Cont’d) Typical Filter Performance (Nominal Conditions unless Specified Otherwise, 50 Ohm Environment) Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, V =3.3 V) P Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, V =3.3 V) P http://onsemi.com 5

CM1213 APPLICATION INFORMATION Design Considerations In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically aconnector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to power supply is represented by L and L . The voltage V on the line being protected is: 1 2 CL VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt + L2 x d(IESD ) / dt where I is the ESD current pulse, and V is the positive supply voltage. ESD SUPPLY An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(I )/dt can be ESD approximated by (cid:3)IESD/(cid:3)t, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300V increment in V ! CL Similarly for negative ESD pulses, parasitic series inductance from the V pin to the ground rail will lead to drastically N increased negative voltage on the line being protected. The CM1213 has an integrated Zener diode between V and V . This greatly reduces the effect of supply rail inductance P N L on V by clamping V at the breakdown voltage of the Zener diode. However, for the lowest possible V , especially when 2 CL P CL V is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 (cid:2)F ceramic chip P capacitor be connected between V and the ground plane. P As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V pin of the Protection P Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance. Additional Information See also ON Semiconductor Application Note, “Design Considerations for ESD Protection”, in the Applications section. L2 POSITIVE SUPPLY RAIL VCC VP PATH OF ESD CURRENT PULSE IESO ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ LINE BEING ÇÇDÇ1 ÇÇÇ L1 PROTECTED ÇÇSYÇSTEMÇ ORÇÇ 0.22 (cid:2)F CIRCUITRY ÇÇÇOÇNE ÇÇCHANNEL ÇÇBEÇINGÇÇÇ PROTECTED ÇÇDÇ2 COCHMÇFA1N21N3ÇEL Ç INPUT25 A VCL ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ 0 A GROUND RAIL VN CHASSIS GROUND Figure 5. Application of Positive ESD Pulse between Input Channel and Ground http://onsemi.com 6

CM1213 PACKAGE DIMENSIONS SOIC−8 EP CASE 751AC ISSUE B 2 X NOTES: 0.10 C A-B 1. DIMENSIONS AND TOLERANCING PER D ASME Y14.5M, 1994. D DETAIL A 2. DIMENSIONS IN MILLIMETERS (ANGLES A EXPOSED F 3. IDNI MDEENGSRIOEENS b) .DOES NOT INCLUDE 8 5 PAD 5 8 DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 MM TOTAL IN EXCESS OF THE “b” DIMENSION AT MAXIMUM MATERIAL CONDITION. E1 ÉÉ E G 4. DATUMS A AND B TO BE DETERMINED AT DATUM PLANE H. 2 X ÉÉ MILLIMETERS 0.10 C D 2 X h DIM MIN MAX A 1.35 1.75 1 4 0.20 C 4 1 A1 0.00 0.10 PIN ONE LOCATION e BOTTOM VIEW A2 1.35 1.65 8 X b A A b 0.31 0.51 B 0.25 C A-B D b1 0.28 0.48 END VIEW c 0.17 0.25 c1 0.17 0.23 TOP VIEW c D 4.90 BSC H ÉÇÉÇ E 6.00 BSC 0.10 C A E1 3.90 BSC 8 X A2 b1ÉÇÉÇ(b) LLe1 0.114..02074 BRSE1CF.27 0.10 C GAUGE ÉÇÉÇ F 2.24 3.20 PLANE SEATING L G 1.55 2.51 PLANE 0.25 (cid:3) c1 h(cid:3) 0.02 5 (cid:3) 0.85 0(cid:3) SIDE VIEW A1 (L1) C DETAIL A SECTION A−A SOLDERING FOOTPRINT* 2.72 0.107 1.52 0.060 Exposed Pad 7.0 2.03 4.0 0.275 0.08 0.155 0.6 1.270 0.024 0.050 (cid:2) (cid:3) mm SCALE 6:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7

CM1213 PACKAGE DIMENSIONS MSOP 8, 3x3 CASE 846AD ISSUE O SYMBOL MIN NOM MAX A 1.10 A1 0.05 0.10 0.15 A2 0.75 0.85 0.95 b 0.22 0.38 c 0.13 0.23 E E1 D 2.90 3.00 3.10 E 4.80 4.90 5.00 E1 2.90 3.00 3.10 e 0.65 BSC L 0.40 0.60 0.80 L1 0.95 REF L2 0.25 BSC θ 0º 6º TOP VIEW D A A2 DETAIL A A1 e b c SIDE VIEW END VIEW (cid:5) L2 Notes: L (1) All dimensions are in millimeters. Angles in degrees. L1 (2) Complies with JEDEC MO-187. DETAIL A http://onsemi.com 8

CM1213 PACKAGE DIMENSIONS MSOP 10, 3x3 CASE 846AE ISSUE O SYMBOL MIN NOM MAX A 1.10 A1 0.00 0.05 0.15 A2 0.75 0.85 0.95 b 0.17 0.27 c 0.13 0.23 D 2.90 3.00 3.10 E E1 E 4.75 4.90 5.05 E1 2.90 3.00 3.10 e 0.50 BSC L 0.40 0.60 0.80 L1 0.95 REF L2 0.25 BSC θ 0º 8º DETAIL A TOP VIEW D A A2 END VIEW c A1 e b (cid:5) SIDE VIEW L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. L (2) Complies with JEDEC MO-187. L1 DETAIL A FireWire is a registered trademark of Apple Computer, Inc. Optiguard is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com CM1213/D 9

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