(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:7)(cid:8)(cid:9)(cid:4)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:7)(cid:16)(cid:11)(cid:5) (cid:17)(cid:18)(cid:1) (cid:16)(cid:19)(cid:11)(cid:2)(cid:1)(cid:7)(cid:13)(cid:20)(cid:6)(cid:13)(cid:19) (cid:21)(cid:20)(cid:16)(cid:22) (cid:11)(cid:23)(cid:24)(cid:18)(cid:1)(cid:16)(cid:11)(cid:17)(cid:5)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16) (cid:6)(cid:15)(cid:5)(cid:16)(cid:11)(cid:25)(cid:13) (cid:11)(cid:2)(cid:23) (cid:8)(cid:12)(cid:1)(cid:16)(cid:11)(cid:16)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16)(cid:1) SCAS773A − JUNE 2004 − REVISED MARCH 2005 (cid:1) (cid:1) Controlled Baseline ESD Protection Exceeds JESD 22 − One Assembly/Test Site, One Fabrication − 2000-V Human-Body Model (A114-A) Site − 200-V Machine Model (A115-A) (cid:1) Enhanced Diminishing Manufacturing − 1000-V Charged-Device Model (C101) Sources (DMS) Support (cid:1) Enhanced Product-Change Notification DB, DW, OR PW PACKAGE (cid:1) Qualification Pedigree† (TOP VIEW) (cid:1) Bidirectional Voltage Translator V 1 24 V CCA CCB (cid:1) 2.3 V to 3.6 V on A Port and 3 V to 5.5 V on DIR 2 23 NC B Port A1 3 22 OE (cid:1) A2 4 21 B1 Control Inputs V /V Levels Are IH IL Referenced to V Voltage A3 5 20 B2 CCA (cid:1) A4 6 19 B3 Latch-Up Performance Exceeds 250 mA Per A5 7 18 B4 JESD 17 A6 8 17 B5 †Component qualification in accordance with JEDEC and industry A7 9 16 B6 standards to ensure reliable operation over an extended A8 10 15 B7 temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature GND 11 14 B8 cycle, autoclave or unbiased HAST, electromigration, bond GND 12 13 GND intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component NC − No internal connection beyond specified performance and environmental limits. description/ordering information This 8-bit (octal) noninverting bus transceiver contains two separate supply rails. The B port is designed to track VCCB, which accepts voltages from 3 V to 5.5 V, and the A port is designed to track VCCA, which operates at 2.3 V to 3.6 V. This allows for translation from a 3.3-V to a 5-V system environment and vice versa, from a 2.5-V to a 3.3-V system environment and vice versa. The SN74LVCC3245A is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are isolated. The control circuitry (DIR, OE) is powered by V . CCA ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING SOIC − DW Reel of 2000 CLVCC3245AIDWREP LVCC3245A −−4400°CC ttoo 8855°CC SSOP − DB Reel of 2000 CLVCC3245AIDBREP LH245AEP TSSOP − PW Reel of 2000 CLVCC3245AIPWREP LH245AEP †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:14)(cid:19)(cid:15)(cid:23)(cid:18)(cid:7)(cid:16)(cid:20)(cid:15)(cid:2) (cid:23)(cid:11)(cid:16)(cid:11) (cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"(cid:26)(cid:29)(cid:27) (cid:26)# $%(cid:30)(cid:30)&(cid:27)" !# (cid:29)(cid:28) ’%()(cid:26)$!"(cid:26)(cid:29)(cid:27) *!"&+ Copyright  2005, Texas Instruments Incorporated (cid:14)(cid:30)(cid:29)*%$"# $(cid:29)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31) "(cid:29) #’&$(cid:26)(cid:28)(cid:26)$!"(cid:26)(cid:29)(cid:27)# ’&(cid:30) ",& "&(cid:30)(cid:31)# (cid:29)(cid:28) (cid:16)&-!# (cid:20)(cid:27)#"(cid:30)%(cid:31)&(cid:27)"# #"!(cid:27)*!(cid:30)* .!(cid:30)(cid:30)!(cid:27)"/+ (cid:14)(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:7)(cid:8)(cid:9)(cid:4)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:7)(cid:16)(cid:11)(cid:5) (cid:17)(cid:18)(cid:1) (cid:16)(cid:19)(cid:11)(cid:2)(cid:1)(cid:7)(cid:13)(cid:20)(cid:6)(cid:13)(cid:19) (cid:21)(cid:20)(cid:16)(cid:22) (cid:11)(cid:23)(cid:24)(cid:18)(cid:1)(cid:16)(cid:11)(cid:17)(cid:5)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16) (cid:6)(cid:15)(cid:5)(cid:16)(cid:11)(cid:25)(cid:13) (cid:11)(cid:2)(cid:23) (cid:8)(cid:12)(cid:1)(cid:16)(cid:11)(cid:16)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16)(cid:1) SCAS773A − JUNE 2004 − REVISED MARCH 2005 FUNCTION TABLE (each transceiver) INPUTS OOPPEERRAATTIIOONN OE DIR L L B data to A bus L H A data to B bus H X Isolation logic diagram (positive logic) 2 DIR 22 OE 3 A1 21 B1 To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V and V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V CCA CCB Input voltage range, V: All A ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V I CCA All B ports (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V CCB Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V CCA Output voltage range, V (see Note 2): All A ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V O CCA All B ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V CCB Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA IK I Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA OK O Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA O Continuous current through V , V , or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA CCA CCB Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. This value is limited to 4.6 V maximum. 2. This value is limited to 6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:7)(cid:8)(cid:9)(cid:4)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:7)(cid:16)(cid:11)(cid:5) (cid:17)(cid:18)(cid:1) (cid:16)(cid:19)(cid:11)(cid:2)(cid:1)(cid:7)(cid:13)(cid:20)(cid:6)(cid:13)(cid:19) (cid:21)(cid:20)(cid:16)(cid:22) (cid:11)(cid:23)(cid:24)(cid:18)(cid:1)(cid:16)(cid:11)(cid:17)(cid:5)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16) (cid:6)(cid:15)(cid:5)(cid:16)(cid:11)(cid:25)(cid:13) (cid:11)(cid:2)(cid:23) (cid:8)(cid:12)(cid:1)(cid:16)(cid:11)(cid:16)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16)(cid:1) SCAS773A − JUNE 2004 − REVISED MARCH 2005 recommended operating conditions (see Note 4) VCCA VCCB MIN NOM MAX UNIT VCCA Supply voltage 2.3 3.3 3.6 V VCCB Supply voltage 3 5 5.5 V 2.3 V 3 V 1.7 2.7 V 3 V 2 VVIIHHAA HHiigghh--lleevveell iinnppuutt vvoollttaaggee VV 3 V 3.6 V 2 3.6 V 5.5 V 2 2.3 V 3 V 2 2.7 V 3 V 2 VVIIHHBB HHiigghh--lleevveell iinnppuutt vvoollttaaggee VV 3 V 3.6 V 2 3.6 V 5.5 V 3.85 2.3 V 3 V 0.7 2.7 V 3 V 0.8 VVIILLAA LLooww--lleevveell iinnppuutt vvoollttaaggee VV 3 V 3.6 V 0.8 3.6 V 5.5 V 0.8 2.3 V 3 V 0.8 2.7 V 3 V 0.8 VVIILLBB LLooww--lleevveell iinnppuutt vvoollttaaggee VV 3 V 3.6 V 0.8 3.6 V 5.5 V 1.65 2.3 V 3 V 1.7 HHiigghh--lleevveell iinnppuutt vvoollttaaggee ((ccoonnttrrooll ppiinnss)) 2.7 V 3 V 2 VVIIHH ((RReeffeerreenncceedd ttoo VVCCCCAA)) 3 V 3.6 V 2 VV 3.6 V 5.5 V 2 2.3 V 3 V 0.7 LLooww--lleevveell iinnppuutt vvoollttaaggee ((ccoonnttrrooll ppiinnss)) 2.7 V 3 V 0.8 VVIILL ((RReeffeerreenncceedd ttoo VVCCCCAA)) 3 V 3.6 V 0.8 VV 3.6 V 5.5 V 0.8 VIA Input voltage 0 VCCA V VIB Input voltage 0 VCCB V VOA Output voltage 0 VCCA V VOB Output voltage 0 VCCB V NOTE 4: All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:7)(cid:8)(cid:9)(cid:4)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:7)(cid:16)(cid:11)(cid:5) (cid:17)(cid:18)(cid:1) (cid:16)(cid:19)(cid:11)(cid:2)(cid:1)(cid:7)(cid:13)(cid:20)(cid:6)(cid:13)(cid:19) (cid:21)(cid:20)(cid:16)(cid:22) (cid:11)(cid:23)(cid:24)(cid:18)(cid:1)(cid:16)(cid:11)(cid:17)(cid:5)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16) (cid:6)(cid:15)(cid:5)(cid:16)(cid:11)(cid:25)(cid:13) (cid:11)(cid:2)(cid:23) (cid:8)(cid:12)(cid:1)(cid:16)(cid:11)(cid:16)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16)(cid:1) SCAS773A − JUNE 2004 − REVISED MARCH 2005 recommended operating conditions (see Note 4) (continued) VCCA VCCB MIN NOM MAX UNIT 2.3 V 3 V −8 IIOOHHAA HHiigghh--lleevveell oouuttppuutt ccuurrrreenntt 2.7 V 3 V −12 mmAA 3.3 V 3 V −24 2.3 V 3.3 V −12 IIOOHHBB HHiigghh--lleevveell oouuttppuutt ccuurrrreenntt 2.7 V 3.3 V −12 mmAA 3.3 V 3 V −24 2.3 V 3 V 8 IIOOLLAA LLooww--lleevveell oouuttppuutt ccuurrrreenntt 2.7 V 3 V 12 mmAA 3.3 V 3 V 24 2.3 V 3.3 V 12 IIOOLLBB LLooww--lleevveell oouuttppuutt ccuurrrreenntt 2.7 V 3.3 V 12 mmAA 3.3 V 3 V 24 ∆t/∆v Input transition rise or fall rate 10 ns/V TA Operating free-air temperature −40 85 °C NOTE 4: All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:7)(cid:8)(cid:9)(cid:4)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:7)(cid:16)(cid:11)(cid:5) (cid:17)(cid:18)(cid:1) (cid:16)(cid:19)(cid:11)(cid:2)(cid:1)(cid:7)(cid:13)(cid:20)(cid:6)(cid:13)(cid:19) (cid:21)(cid:20)(cid:16)(cid:22) (cid:11)(cid:23)(cid:24)(cid:18)(cid:1)(cid:16)(cid:11)(cid:17)(cid:5)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16) (cid:6)(cid:15)(cid:5)(cid:16)(cid:11)(cid:25)(cid:13) (cid:11)(cid:2)(cid:23) (cid:8)(cid:12)(cid:1)(cid:16)(cid:11)(cid:16)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16)(cid:1) SCAS773A − JUNE 2004 − REVISED MARCH 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCA VCCB MIN TYP MAX UNIT IOH = −100 µA 3 V 3 V 2.9 3 IOH = −8 mA 2.3 V 3 V 2 2.7 V 3 V 2.2 2.5 VVOOHHAA IIOOHH == −−1122 mmAA VV 3 V 3 V 2.4 2.8 3 V 3 V 2.2 2.6 IIOOHH == −−2244 mmAA 2.7 V 4.5 V 2 2.3 IOH = −100 µA 3 V 3 V 2.9 3 2.3 V 3 V 2.4 IIOOHH == −−1122 mmAA VVOOHHBB 2.7 V 3 V 2.4 2.8 VV 3 V 3 V 2.2 2.6 IIOOHH == −−2244 mmAA 2.7 V 4.5 V 3.2 4.2 IOL = 100 µA 3 V 3 V 0.1 IOL = 8 mA 2.3 V 3 V 0.6 VVOOLLAA IOL = 12 mA 2.7 V 3 V 0.1 0.5 VV 3 V 3 V 0.2 0.5 IIOOLL == 2244 mmAA 2.7 V 4.5 V 0.2 0.5 IOL = 100 µA 3 V 3 V 0.1 IOL = 12 mA 2.3 V 3 V 0.4 VVOOLLBB VV 3 V 0.2 0.5 IIOOLL == 2244 mmAA 33 VV 4.5 V 0.2 0.5 3.6 V ±0.1 ±1 IIII CCoonnttrrooll iinnppuuttss VVII == VVCCCCAA oorr GGNNDD 33..66 VV 5.5 V ±0.1 ±1 µAA IOZ† A or B ports VO = VCCA/B or GND, VI = VIL or VIH 3.6 V 3.6 V ±0.5 ±5 µA A port = VCCA or GND, IO = 0 3.6 V Open 5 50 IICCCCAA BB ttoo AA 3.6 V 5 50 µµAA BB ppoorrtt == VVCCCCBB oorr GGNNDD,, IIOO == 00 33..66 VV 5.5 V 5 50 3.6 V 5 50 IICCCCBB AA ttoo BB AA ppoorrtt == VVCCCCAA oorr GGNNDD,, IIOO == 00 33..66 VV µAA 5.5 V 8 80 VI = VCCA − 0.6 V, Other inputs at VCCA or GND, A port 3.6 V 3.6 V 0.35 0.5 OE at GND and DIR at VCCA ∆ICCA‡ OE DVII R= aVtC VCCAC −A 0.6 V, Other inputs at VCCA or GND, 3.6 V 3.6 V 0.35 0.5 mA VI = VCCA − 0.6 V, Other inputs at VCCA or GND, DIR 3.6 V 3.6 V 0.35 0.5 OE at GND ∆ICCB‡ B port OVIE = a Vt CGCNBD −a n2d.1 D VI,R O atht eGrN inDputs at VCCB or GND, 3.6 V 5.5 V 1 1.5 mA Ci Control inputs VI = VCCA or GND Open Open 4 pF Cio A or B ports VO = VCCA/B or GND 3.3 V 5 V 18.5 pF †For I/O ports, the parameter IOZ includes the input leakage current. ‡This is the increase in supply current for each input that is at one of the specified voltage levels, rather than 0 V or the associated VCC. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:7)(cid:8)(cid:9)(cid:4)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:7)(cid:16)(cid:11)(cid:5) (cid:17)(cid:18)(cid:1) (cid:16)(cid:19)(cid:11)(cid:2)(cid:1)(cid:7)(cid:13)(cid:20)(cid:6)(cid:13)(cid:19) (cid:21)(cid:20)(cid:16)(cid:22) (cid:11)(cid:23)(cid:24)(cid:18)(cid:1)(cid:16)(cid:11)(cid:17)(cid:5)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16) (cid:6)(cid:15)(cid:5)(cid:16)(cid:11)(cid:25)(cid:13) (cid:11)(cid:2)(cid:23) (cid:8)(cid:12)(cid:1)(cid:16)(cid:11)(cid:16)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16)(cid:1) SCAS773A − JUNE 2004 − REVISED MARCH 2005 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 4) VCCA = 2.5 V VCCA = 2.7 V VCCA = 2.7 V ± 0.2 V, TO 3.6 V, TO 3.6 V, PARAMETER FROM TO VCCB = 3.3 V VCCB = 5 V VCCB = 3.3 V UNIT (INPUT) (OUTPUT) ± 0.3 V ± 0.5 V ± 0.3 V MIN MAX MIN MAX MIN MAX tPHL 1 9.4 1 6 1 7.1 AA BB nnss tPLH 1 9.1 1 5.3 1 7.2 tPHL 1 11.2 1 5.8 1 6.4 BB AA nnss tPLH 1 9.9 1 7 1 7.6 tPZL 1 14.5 1 9.2 1 9.7 OOEE AA nnss tPZH 1 12.9 1 9.5 1 9.5 tPZL 1 13 1 8.1 1 9.2 OOEE BB nnss tPZH 1 12.8 1 8.4 1 9.9 tPLZ 1 7.1 1 7 1 6.6 OOEE AA nnss tPHZ 1 6.9 1 7.8 1 6.9 tPLZ 1 8.8 1 7.3 1 7.5 OOEE BB nnss tPHZ 1 8.9 1 7 1 7.9 operating characteristics, VCCA = 3.3 V, VCCB = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Outputs enabled 38 CCppdd PPoowweerr ddiissssiippaattiioonn ccaappaacciittaannccee ppeerr ttrraannsscceeiivveerr CCLL == 5500,, ff == 1100 MMHHzz ppFF Outputs disabled 4.5 power-up considerations† TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. To guard against such power-up problems, take these precautions: 1. Connect ground before any supply voltage is applied. 2. Power up the control side of the device (V for all four of these devices). CCA 3. Tie OE to V with a pullup resistor so that it ramps with V . CCA CCA 4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus), ramp it with V . Otherwise, keep DIR low. CCA †Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:7)(cid:8)(cid:9)(cid:4)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:7)(cid:16)(cid:11)(cid:5) (cid:17)(cid:18)(cid:1) (cid:16)(cid:19)(cid:11)(cid:2)(cid:1)(cid:7)(cid:13)(cid:20)(cid:6)(cid:13)(cid:19) (cid:21)(cid:20)(cid:16)(cid:22) (cid:11)(cid:23)(cid:24)(cid:18)(cid:1)(cid:16)(cid:11)(cid:17)(cid:5)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16) (cid:6)(cid:15)(cid:5)(cid:16)(cid:11)(cid:25)(cid:13) (cid:11)(cid:2)(cid:23) (cid:8)(cid:12)(cid:1)(cid:16)(cid:11)(cid:16)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16)(cid:1) SCAS773A − JUNE 2004 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION FOR A PORT V = 2.5 V ± 0.2 V AND V = 3.3 V ± 0.3 V CCA CCB 2 × VCC 500 Ω S1 Open From Output TEST S1 Under Test GND tpd Open CL = 30 pF 500 Ω tPLZ/tPZL 2 × VCC (see Note A) tPHZ/tPZH GND LOAD CIRCUIT tw VCC Timing VCC Input VCC/2 VCC/2 Input VCC/2 0 V 0 V VOLTAGE WAVEFORMS PULSE DURATION tsu th IDnpautat VCC/2 VCC/2 VCC COounttpruotl VCC 0 V (low-level VCC/2 VCC/2 enabling) 0 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tPZL tPLZ Output VCC Waveform 1 VCC Input VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + 0.15 V 0 V (see Note B) VOL tPLH tPHL tPZH tPHZ Output VCC/2 VCC/2 VOH WSa1v eaOfto uGrtmpNu D2t VCC/2 VOH − 0.15 VVOH VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:7)(cid:8)(cid:9)(cid:4)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:7)(cid:16)(cid:11)(cid:5) (cid:17)(cid:18)(cid:1) (cid:16)(cid:19)(cid:11)(cid:2)(cid:1)(cid:7)(cid:13)(cid:20)(cid:6)(cid:13)(cid:19) (cid:21)(cid:20)(cid:16)(cid:22) (cid:11)(cid:23)(cid:24)(cid:18)(cid:1)(cid:16)(cid:11)(cid:17)(cid:5)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16) (cid:6)(cid:15)(cid:5)(cid:16)(cid:11)(cid:25)(cid:13) (cid:11)(cid:2)(cid:23) (cid:8)(cid:12)(cid:1)(cid:16)(cid:11)(cid:16)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16)(cid:1) SCAS773A − JUNE 2004 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION FOR B PORT V = 2.5 V ± 0.2 V AND V = 3.3 V ± 0.3 V CCA CCB 2 × VCC 500 Ω S1 Open From Output TEST S1 Under Test GND tpd Open CL = 50 pF 500 Ω tPLZ/tPZL 2 × VCC (see Note A) tPHZ/tPZH GND LOAD CIRCUIT tw VCC Timing VCC Input VCC/2 VCC/2 Input VCC/2 0 V 0 V VOLTAGE WAVEFORMS PULSE DURATION tsu th IDnpautat VCC/2 VCC/2 VCC COounttpruotl VCC 0 V (low-level VCC/2 VCC/2 enabling) 0 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tPZL tPLZ Output VCC Waveform 1 VCC Input VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + 0.15 V 0 V (see Note B) VOL tPLH tPHL tPZH tPHZ Output VCC/2 VCC/2 VOH WSa1v eaOfto uGrtmpNu D2t VCC/2 VOH − 0.15 VVOH VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:7)(cid:8)(cid:9)(cid:4)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:7)(cid:16)(cid:11)(cid:5) (cid:17)(cid:18)(cid:1) (cid:16)(cid:19)(cid:11)(cid:2)(cid:1)(cid:7)(cid:13)(cid:20)(cid:6)(cid:13)(cid:19) (cid:21)(cid:20)(cid:16)(cid:22) (cid:11)(cid:23)(cid:24)(cid:18)(cid:1)(cid:16)(cid:11)(cid:17)(cid:5)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16) (cid:6)(cid:15)(cid:5)(cid:16)(cid:11)(cid:25)(cid:13) (cid:11)(cid:2)(cid:23) (cid:8)(cid:12)(cid:1)(cid:16)(cid:11)(cid:16)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16)(cid:1) SCAS773A − JUNE 2004 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION FOR B PORT V = 3.6 V AND V = 5.5 V CCA CCB 2 × VCC From Output 500 Ω S1 Open Under Test GND TEST S1 CL = 50 pF tPLH/tPHL Open (see Note A) 500 Ω tPLZ/tPZL 2 × VCC tPHZ/tPZH Open LOAD CIRCUIT tw VCC B-Port Input 50% VCC 50% VCC 2.7 V 0 V Output 1.5 V 1.5 V Control VOLTAGE WAVEFORMS 0 V PULSE DURATION tPZL tPLZ Output Waveform 1 VCC Input 1.5 V 1.5 V VCC S(1s eaet 2N ×o tVeC BC) 50% VCC VOL + 0.3 VVOL 0 V tPZH tPHZ tPLH tPHL Output OBu-Ptpourtt 50% VCC 50% VCVVCOOHL (WsSea1ev aeNtf ooOtrepm eB n2) 50% VCC VOH − 0.3 VV≈0O VH VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:7)(cid:8)(cid:9)(cid:4)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:7)(cid:16)(cid:11)(cid:5) (cid:17)(cid:18)(cid:1) (cid:16)(cid:19)(cid:11)(cid:2)(cid:1)(cid:7)(cid:13)(cid:20)(cid:6)(cid:13)(cid:19) (cid:21)(cid:20)(cid:16)(cid:22) (cid:11)(cid:23)(cid:24)(cid:18)(cid:1)(cid:16)(cid:11)(cid:17)(cid:5)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16) (cid:6)(cid:15)(cid:5)(cid:16)(cid:11)(cid:25)(cid:13) (cid:11)(cid:2)(cid:23) (cid:8)(cid:12)(cid:1)(cid:16)(cid:11)(cid:16)(cid:13) (cid:15)(cid:18)(cid:16)(cid:14)(cid:18)(cid:16)(cid:1) SCAS773A − JUNE 2004 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION FOR A AND B PORT V AND V = 3.6 V CCA CCB 7 V From Output 500 Ω S1 Open Under Test GND TEST S1 CL = 50 pF (see Note A) 500 Ω tPLH/tPHL Open tPLZ/tPZL 7 V tPHZ/tPZH Open LOAD CIRCUIT tw 2.7 V Input 1.5 V 1.5 V 2.7 V Output 0 V 1.5 V 1.5 V Control 0 V VOLTAGE WAVEFORMS PULSE DURATION tPZL tPLZ Output Waveform 1 3.5 V 2.7 V S1 at 7 V 1.5 V Input 1.5 V 1.5 V (see Note B) VOL + 0.3 VVOL 0 V tPZH tPHZ tPLH tPHL Output VOH Waveform 2 1.5 V VOH − 0.3 VVOH Output 1.5 V 1.5 V S1 at Open VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CLVCC3245AIDBREP ACTIVE SSOP DB 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LH245AEP & no Sb/Br) CLVCC3245AIDWREP ACTIVE SOIC DW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVCC3245A & no Sb/Br) CLVCC3245AIPWREP ACTIVE TSSOP PW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LH245AEP & no Sb/Br) V62/05602-01XE ACTIVE TSSOP PW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LH245AEP & no Sb/Br) V62/05602-01YE ACTIVE SSOP DB 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LH245AEP & no Sb/Br) V62/05602-01ZE ACTIVE SOIC DW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LVCC3245A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVCC3245A-EP : •Catalog: SN74LVCC3245A NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CLVCC3245AIDBREP SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 CLVCC3245AIDWREP SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 CLVCC3245AIPWREP TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CLVCC3245AIDBREP SSOP DB 24 2000 367.0 367.0 38.0 CLVCC3245AIDWREP SOIC DW 24 2000 350.0 350.0 43.0 CLVCC3245AIPWREP TSSOP PW 24 2000 367.0 367.0 38.0 PackMaterials-Page2

PACKAGE OUTLINE PW0024A TSSOP - 1.2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 22X 0.65 24 1 2X 7.9 7.15 7.7 NOTE 3 12 13 0.30 24X B 4.5 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 0.25 GAGE PLANE 0.15 0.05 (0.15) TYP SEE DETAIL A 0.75 0 -8 0.50 DETA 20AIL A TYPICAL 4220208/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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