CDCLVD1216 www.ti.com SCAS900B–OCTOBER2010–REVISEDJANUARY2011 2:16 Low Additive Jitter LVDS Buffer CheckforSamples:CDCLVD1216 FEATURES 1 DESCRIPTION • 2:16DifferentialBuffer The CDCLVD1216 clock buffer distributes one of two • LowAdditiveJitter: <300fsRMSin selectable clock inputs (IN0, IN1) to 16 pairs of 10kHzto20MHz differential LVDS clock outputs (OUT0, OUT15) with • LowOutputSkewof55ps(Max) minimum skew for clock distribution. The • UniversalInputsAcceptLVDS,LVPECL, CDCLVD1216 can accept two clock sources into an LVCMOS input multiplexer. The inputs can either be LVDS, LVPECL,orLVCMOS. • SelectableClockInputsThroughControlPin The CDCLVD1216 is specifically designed for driving • 16LVDSOutputs,ANSIEIA/TIA-644AStandard 50 Ω transmission lines. If driving the inputs in single Compatible ended mode, the appropriate bias voltage (V ) AC_REF • ClockFrequencyupto800MHz shouldbeappliedtotheunusednegativeinputpin. • 2.375–2.625VDevicePowerSupply The IN_SEL pin selects the input which is routed to • LVDSReferenceVoltage,VAC_REF,Availablefor the outputs. If this pin is left open it disables the CapacitiveCoupledInputs outputs (static). The part supports a fail safe function. • IndustrialTemperatureRange –40°Cto85°C It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an • Packagedin7mm ×7mm48-PinQFN(RGZ) inputsignal. • ESDProtectionExceeds3kVHBM,1kVCDM The device operates in 2.5 V supply environment and is characterized from –40°C to 85°C (ambient APPLICATIONS temperature). The CDCLVD1216 is packaged in • Telecommunications/Networking small48-pin,7mm×7mmQFNpackage. • MedicalImaging • TestandMeasurementEquipment • WirelessCommunications • GeneralPurposeClocking 125MHz 125MHz PPPHHHYY2Y22 PHY2 Oscillator CDCLVD1216 PPPHHHY2YY222 LVDS Buffer PHY16 IN_SEL Figure1. ApplicationExample 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2010–2011,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

CDCLVD1216 SCAS900B–OCTOBER2010–REVISEDJANUARY2011 www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. V V V V V V CC CC CC CC CC CC V AC_REF0 Reference V Generator AC_REF1 INP0 INN0 X OUTP [0..15] U M LVDS INP1 N_ OUTN [0..15] I INN1 V CC 200 kW IN_SEL 200 kW GND GND Figure2. CDCLVD1216BlockDiagram CDCLVD1216 (TOPVIEW) 0 0 1 1 9 9 8 8 7 7 6 6 5 5 N P N P N P N P N P N P T T T T T T T T T T T T U U U U U U U U U U U U O O O O O O O O O O O O 36 35 34 33 32 31 30 29 28 27 26 25 VCC 37 24 VCC OUTP11 38 23 OUTN4 7mm x7mm OUTN11 39 48pin QFN(RGZ) 22 OUTP4 OUTP12 40 21 OUTN3 OUTN12 41 20 OUTP3 OUTP13 42 19 OUTN2 OUTN13 43 18 OUTP2 OUTP14 44 17 OUTN1 OUTN14 45 16 OUTP1 OUTP15 46 15 OUTN0 Thermal Pad(GND) OUTN15 47 14 OUTP0 VCC 48 13 VCC 1 2 3 4 5 6 7 8 9 10 11 12 GND IN_SEL INP1 INN1 VAC_REF1 VCC VCC VAC_REF0 INN0 INP0 N.C. GND 2 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLinks:CDCLVD1216

CDCLVD1216 www.ti.com SCAS900B–OCTOBER2010–REVISEDJANUARY2011 PINFUNCTIONS PIN NAME NO. TYPE DESCRIPTION 6,7,13, V Power 2.5Vsuppliesforthedevice CC 24,37,48 GND 1,12 Ground Deviceground INP0,INN0 10,9 Input Differentialinputpairorsingleendedinput INP1,INN1 3,4 Input Differentialredundantinputpairorsingleendedinput OUTP0,OUTN0 14,15 Output DifferentialLVDSoutputpairno.0 OUTP1,OUTN1 16,17 Output DifferentialLVDSoutputpairno.1 OUTP2,OUTN2 18,19 Output DifferentialLVDSoutputpairno.2 OUTP3,OUTN3 20,21 Output DifferentialLVDSoutputpairno.3 OUTP4,OUTN4 22,23 Output DifferentialLVDSoutputpairno.4 OUTP5,OUTN5 25,26 Output DifferentialLVDSoutputpairno.5 OUTP6,OUTN6 27,28 Output DifferentialLVDSoutputpairno.6 OUTP7,OUTN7 29,30 Output DifferentialLVDSoutputpairno.7 OUTP8,OUTN8 31,32 Output DifferentialLVDSoutputpairno.8 OUTP9,OUTN9 33,34 Output DifferentialLVDSoutputpairno.9 OUTP10,OUTN10 35,36 Output DifferentialLVDSoutputpairno.10 OUTP11,OUTN11 38,39 Output DifferentialLVDSoutputpairno.11 OUTP12,OUTN12 40,41 Output DifferentialLVDSoutputpairno.12 OUTP13,OUTN13 42,43 Output DifferentialLVDSoutputpairno.13 OUTP14,OUTN14 44,45 Output DifferentialLVDSoutputpairno.14 OUTP15,OUTN15 46,47 Output DifferentialLVDSoutputpairno.15 Biasvoltageoutputforcapacitivecoupledinputs.Ifused,itisrecommendedtouse V 8 Output AC_REF0 a0.1µFtoGNDonthispin. Biasvoltageoutputforcapacitivecoupledinputs.Ifused,itisrecommendedtouse V 5 Output AC_REF1 a0.1µFtoGNDonthispin. N.C. 11 Noconnect Inputwithan internal200kΩ IN_SEL 2 Inputselection–selectsinputport;(SeeTable1) pull-upandpull- down Deviceground.ThermalPadmustbesolderedtoground.Seethermalmanagement ThermalPad Ground recommendations. Table1.InputSelectionTable IN_SEL ACTIVECLOCKINPUT 0 INP0,INN0 1 INP1,INN1 Open None(1) (1) Theinputbuffersaredisabledandtheoutputsarestatic. Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:CDCLVD1216

CDCLVD1216 SCAS900B–OCTOBER2010–REVISEDJANUARY2011 www.ti.com ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1) VALUE UNIT Supplyvoltagerange,V –0.3to2.8 V CC Inputvoltagerange,V –0.2to(V +0.2) V I CC Outputvoltagerange,V –0.2to(V +0.2) V O CC Drivershortcircuitcurrent,I SeeNote (2) OSD Electrostaticdischarge(HumanBodyModel,1.5kΩ,100pF) >3000 V (1) Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditions”isnotimplied.Exposuretoabsolute–maximum–ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theoutputscanhandlepermanentshort. RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT Devicesupplyvoltage,V 2.375 2.5 2.625 V CC Ambienttemperature,T –40 85 °C A THERMAL INFORMATION CDCLVD1216 THERMALMETRIC(1) UNITS RGZ(48PINS) θ Junction-to-ambientthermalresistance 30.6 JA θ Junction-to-case(top)thermalresistance 28.5 JC(top) θ Junction-to-boardthermalresistance 10.5 JB °C/W ψ Junction-to-topcharacterizationparameter 0.4 JT ψ Junction-to-boardcharacterizationparameter 10.2 JB θ Junction-to-case(bottom)thermalresistance 3.1 JC(bottom) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. ELECTRICAL CHARACTERISTICS AtV =2.375Vto2.625V,T =–40°Cto85°C(unlessotherwisenoted) CC A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT IN_SELCONTROLINPUTCHARACTERISTICS V 3State Open 0.5×V V dI3 CC V Inputhighvoltage 0.7×V V dIH CC V Inputlowvoltage 0.2×V V dIL CC I Inputhighcurrent V =2.625V,V =2.625V 30 μA dIH CC IH I Inputlowcurrent V =2.625V,V =0V –30 μA dIL CC IL R Inputpull-up/pull-downresistor 200 kΩ pull(IN_SEL) 2.5VLVCMOS(seeFigure7)INPUTCHARACTERISTICS f Inputfrequency 200 MHz IN Externalthresholdvoltageappliedto V Inputthresholdvoltage 1.1 1.5 V th complementaryinput V Inputhighvoltage V +0.1 V V IH th CC V Inputlowvoltage 0 V –0.1 V IL th I Inputhighcurrent V =2.625V,V =2.625V 10 μA IH CC IH I Inputlowcurrent V =2.625V,V =0V –10 μA IL CC IL ΔV/ΔT Inputedgerate 20%–80% 1.5 V/ns C Inputcapacitance 2.5 pF IN 4 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLinks:CDCLVD1216

CDCLVD1216 www.ti.com SCAS900B–OCTOBER2010–REVISEDJANUARY2011 ELECTRICAL CHARACTERISTICS (continued) AtV =2.375Vto2.625V,T =–40°Cto85°C(unlessotherwisenoted) CC A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DIFFERENTIALINPUTCHARACTERISTICS f Inputfrequency Clockinput 800 MHz IN V Differentialinputvoltagepeak-to-peak V =1.25V 0.3 1.6 V IN,DIFF ICM PP V Inputcommonmodevoltagerange V >0.4V 1.0 V –0.3 V ICM IN,DIFF,PP CC I Inputhighcurrent V =2.625V,V =2.625V 10 μA IH CC IH I Inputlowcurrent V =2.625,V =0V –10 μA IL CC IL ΔV/ΔT Inputedgerate 20%–80% 0.75 V/ns C Inputcapacitance 2.5 pF IN LVDSOUTPUTCHARACTERISTICS |V | Differentialoutputvoltagemagnitude 250 450 mV OD Changeindifferentialoutputvoltage ΔV –15 15 mV OD magnitude V =0.3V,R =100Ω IN,DIFF,PP L Steady-statecommonmodeoutput V 1.1 1.375 V OC(SS) voltage Steady-statecommonmodeoutput ΔV V =0.6V,R =100Ω –15 15 mV OC(SS) voltage IN,DIFF,PP L V Outputovershootandundershoot PercentageofoutputamplitudeV 10% ring OD V Outputaccommonmode V =0.6V,R =100Ω 40 70 mV OS IN,DIFF,PP L PP I Short-circuitoutputcurrent V =0V ±24 mA OS OD t Propagationdelay V =0.3V 1.5 2.5 ns PD IN,DIFF,PP t Part-to-partskew 600 ps SK,PP t Outputskew 55 ps SK,O Crossing-point-to-crossing-point t Pulseskew(with50%dutycycleinput) –50 50 ps SK,P distortion Randomadditivejitter(with50%duty Edgespeed0.75V/ns, ps, t 0.3 RJIT cycleinput) 10kHz–20MHz RMS t /t Outputrise/falltime 20%to80%,100Ω,5pF 50 300 ps R F I Staticsupplycurrent Outputsunterminated,f=0Hz 17 28 mA CCSTAT I Supplycurrent Alloutputs,R =100Ω,f=100MHz 107 140 mA CC100 L I Supplycurrent Alloutputs,R =100Ω,f=800MHz 147 180 mA CC800 L V CHARACTERISTICS AC_REF V Referenceoutputvoltage V =2.5VI =100µA 1.1 1.25 1.35 V AC_REF CC load Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:CDCLVD1216

CDCLVD1216 SCAS900B–OCTOBER2010–REVISEDJANUARY2011 www.ti.com Typical Additive Phase Noise Characteristics for 100 MHz Clock PARAMETER MIN TYP MAX UNIT phn Phasenoiseat100Hzoffset -132.9 dBc/Hz 100 phn Phasenoiseat1kHzoffset -138.8 dBc/Hz 1k phn Phasenoiseat10kHzoffset -147.4 dBc/Hz 10k phn Phasenoiseat100kHzoffset -153.6 dBc/Hz 100k phn Phasenoiseat1MHzoffset -155.2 dBc/Hz 1M phn Phasenoiseat10MHzoffset -156.2 dBc/Hz 10M phn Phasenoiseat20MHzoffset -156.6 dBc/Hz 20M t Randomadditivejitterfrom10kHzto20MHz 171 fs,RMS RJIT Typical Additive Phase Noise Characteristics for 737.27 MHz Clock PARAMETER MIN TYP MAX UNIT phn Phasenoiseat100Hzoffset -80.2 dBc/Hz 100 phn Phasenoiseat1kHzoffset -114.3 dBc/Hz 1k phn Phasenoiseat10kHzoffset -138 dBc/Hz 10k phn Phasenoiseat100kHzoffset -143.9 dBc/Hz 100k phn Phasenoiseat1MHzoffset -145.2 dBc/Hz 1M phn Phasenoiseat10MHzoffset -146.5 dBc/Hz 10M phn Phasenoiseat20MHzoffset -146.6 dBc/Hz 20M t Randomadditivejitterfrom10kHzto20MHz 65 fs,RMS RJIT 6 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLinks:CDCLVD1216

CDCLVD1216 www.ti.com SCAS900B–OCTOBER2010–REVISEDJANUARY2011 TYPICAL CHARACTERISTICS INPUT-ANDOUTPUT-CLOCKPHASENOISES vs FREQUENCYFROMtheCARRIER (T =25°CandV =2.5V) A CC z H c/ B d e - s oi N e s a h P InputclockRMSjitteris32fsfrom10kHzto20MHzandadditiveRMSjitteris152fs Figure3.100MHzInputandOutputPhaseNoisePlot spacer 350 T = 25oC A 340 V m 2.625V − 330 e g olta 320 V 2.5V ut 310 p ut O 300 ntial 290 2.375V e r e Diff 280 − 270 D O V 260 250 0 100 200 300 400 500 600 700 800 Frequency−MHz Figure4. DifferentialOutputVoltagevsFrequency Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:CDCLVD1216

CDCLVD1216 SCAS900B–OCTOBER2010–REVISEDJANUARY2011 www.ti.com TYPICAL CHARACTERISTICS (continued) TEST CONFIGURATIONS LVDS 100W Oscilloscope Figure5. LVDSOutputDCConfigurationDuringDeviceTest Phase Noise Analyzer LVDS 50W Figure6. LVDSOutputACConfigurationDuringDeviceTest V IH V th IN V IL IN V th Figure7. DCCoupledLVCMOSInputDuringDeviceTest OUTNx VOH V OD OUTPx V OL 80% 20% VOUT,DIFF,PP(= 2 x VOD) 0 V t t r f Figure8. OutputVoltageandRise/FallTime 8 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLinks:CDCLVD1216

CDCLVD1216 www.ti.com SCAS900B–OCTOBER2010–REVISEDJANUARY2011 TYPICAL CHARACTERISTICS (continued) INNx INPx t t PLH0 PHL0 OUTN0 OUTP0 tPLH1 tPHL1 OUTN1 OUTP1 t t PLH2 PHL2 OUTN2 OUTP2 t t PLH15 PHL15 OUTN15 OUTP15 A. Output skew is calculated as the greater of the following: As of the difference between the fastest and the slowest t orthedifferencebetweenthefastestandtheslowestt (n=0,1,2,..15) PLHn PHLn B. Parttopartskewiscalculatedasthegreaterofthefollowing:Asthedifferencebetweenthefastestandtheslowest t orthedifferencebetweenthefastestandtheslowestt acrossmultipledevices(n=0,1,2,..15) PLHn PHLn Figure9. OutputSkewandPart-to-PartSkew V ring OUTNx V OD 0 V Differential OUTPx Figure10. OutputOvershootandUndershoot Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:CDCLVD1216

CDCLVD1216 SCAS900B–OCTOBER2010–REVISEDJANUARY2011 www.ti.com TYPICAL CHARACTERISTICS (continued) V OS GND Figure11. OutputACCommonMode APPLICATION INFORMATION THERMAL MANAGEMENT Forreliabilityandperformancereasons,thedietemperatureshouldbelimitedtoamaximumof+125°C. The device package has an exposed pad that provides the primary heat removal path to the printed circuit board (PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be soldered down to ensure adequate heat conduction to of the package. Check the mechanical data at the end of thedatasheetforlandandviapatternexamples. POWER SUPPLY FILTERING High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when jitter/phasenoiseiscriticaltotheapplication. Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must be placed close to the power-supply pins and laid out with short loops to minimize inductance. It is recommended to add as many high-frequency (for example, 0.1 μF) bypass capacitors as there are supply pins inthepackage.Itisrecommended,butnotrequired,toinsertaferritebeadbetweentheboardpowersupplyand the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with low dc resistance because it is imperative to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for properoperation. Board Chip Ferrite Bead Supply Supply 1µF 10µF 0.1µF (x6) Figure12. PowerSupplyFiltering 10 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLinks:CDCLVD1216

CDCLVD1216 www.ti.com SCAS900B–OCTOBER2010–REVISEDJANUARY2011 LVDS OUTPUT TERMINATION The proper LVDS termination for signal integrity over two 50 Ω lines is 100 Ω between the outputs on the receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is recommended to place termination resister close to the receiver. If the receiver is internally biased to a voltage different than the output common mode voltage of the CDCLVD1216, ac-coupling should be used. If the LVDS receiverhasinternal100Ω termination,externalterminationmustbeomitted. Unusedoutputscanbeleftopenwithoutconnectinganytracetotheoutputpins. Z = 50W CDCLVD1216 100W LVDS Z = 50W Figure13. LVDSOutputDCTermination 100 nF Z = 50W CDCLVD1216 100W LVDS Z = 50W 100 nF Figure14. LVDSOutputACTerminationwithReceiverInternallyBiased Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:CDCLVD1216

CDCLVD1216 SCAS900B–OCTOBER2010–REVISEDJANUARY2011 www.ti.com INPUT TERMINATION TheCDCLVD1216inputscanbeinterfacedwithLVDS,LVPECL,orLVCMOSdrivers. LVDS Driver can be connected to CDCLVD1216 inputs with dc or ac coupling as shown Figure 15 and Figure 16 respectively. Z = 50W LVDS 100W CDCLVD1216 Z = 50W Figure15. LVDSClockDriverConnectedtoCDCLVD1216Input(DCcoupled) 100 nF Z = 50W LVDS CDCLVD1216 Z = 50W 100 nF 50W 50W V AC_REF Figure16. LVDSClockDriverConnectedtoCDCLVD1216Input(ACcoupled) Figure 17 shows how to connect LVPECL inputs to the CDCLVD1216. The series resistors are required to reducetheLVPECLsignalswingifthesignalswingis >1.6V . PP 75W 100 nF Z = 50W LVPECL CDCLVD1216 Z = 50W 75W 100 nF 150W 150W 50W 50W V AC_REF Figure17. LVPECLClockDriverConnectedtoCDCLVD1216Input 12 SubmitDocumentationFeedback Copyright©2010–2011,TexasInstrumentsIncorporated ProductFolderLinks:CDCLVD1216

CDCLVD1216 www.ti.com SCAS900B–OCTOBER2010–REVISEDJANUARY2011 Figure 18 illustrates how to couple a 2.5 V LVCMOS clock input to the CDCLVD1216 directly. The series resistance (R ) should be placed close to the LVCMOS driver if needed. 3.3 V LVCMOS clock input swing needs S tobelimitedtoV ≤V . IH CC R S LVCMOS Z = 50W (2.5V) CDCLVD1216 Vth=VIH+VIL 2 Figure18. 2.5VLVCMOSClockDriverConnectedtoCDCLVD1216Input Forunusedinputs,itisrecommendedtogroundbothinputpins(INP,INN)using1kΩ resistors. Spacer REVISION HISTORY ChangesfromOriginal(October2010)toRevisionA Page • ChangedFeature-LowOutputSkewof45ps(Max)To:LowOutputSkewof55ps(Max) .............................................. 1 • Changedt OutputSkewFrom:45ps(Max)To:55ps(Max) ........................................................................................ 5 SK,O • DeletedtheRecommendedPCBLayoutillustration .......................................................................................................... 10 ChangesfromRevisionA(November2010)toRevisionB Page • ChangedthedevicestatusFrom:ProductPreviewTo:Production ..................................................................................... 1 Copyright©2010–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:CDCLVD1216

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CDCLVD1216RGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 CDCLVD & no Sb/Br) 1216 CDCLVD1216RGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 CDCLVD & no Sb/Br) 1216 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CDCLVD1216RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 CDCLVD1216RGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CDCLVD1216RGZR VQFN RGZ 48 2500 350.0 350.0 43.0 CDCLVD1216RGZT VQFN RGZ 48 250 213.0 191.0 55.0 PackMaterials-Page2

GENERIC PACKAGE VIEW RGZ 48 VQFN - 1 mm max height 7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224671/A www.ti.com

PACKAGE OUTLINE RGZ0048B VQFN - 1 mm max height SCALE 2.000 PLASTIC QUAD FLATPACK - NO LEAD B 7.15 A 6.85 PIN 1 INDEX AREA 7.15 6.85 1 MAX C SEATING PLANE 0.05 0.00 0.08 C 2X 5.5 4.1 0.1 (0.2) TYP EXPOSED 13 24 44X 0.5 THERMAL PAD 12 25 2X 49 SYMM 5.5 0.30 36 48X 1 0.18 0.1 C B A 48 37 0.05 PIN 1 ID SYMM 0.5 (OPTIONAL) 48X 0.3 4218795/B 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGZ0048B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 4.1) (1.115) TYP (0.685) TYP 48 37 48X (0.6) 1 36 48X (0.24) (1.115) TYP 44X (0.5) (0.685) SYMM 49 TYP ( 0.2) TYP (6.8) VIA (R0.05) TYP 12 25 13 24 SYMM (6.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING EXPOSED METAL EXPOSED METAL SOLDER MASK METAL UNDER OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218795/B 02/2017 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGZ0048B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD (1.37) TYP 48 37 48X (0.6) 1 36 48X (0.24) 44X (0.5) (1.37) TYP SYMM 49 (R0.05) TYP (6.8) 9X METAL ( 1.17) TYP 12 25 13 24 SYMM (6.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:12X 4218795/B 02/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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