(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:1)(cid:6)(cid:3)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:1)(cid:6)(cid:3)(cid:7)(cid:8) (cid:10)(cid:1)(cid:6)(cid:11)(cid:12) (cid:6)(cid:13)(cid:11)(cid:14)(cid:15)(cid:16)(cid:11)(cid:13)(cid:17)(cid:14)(cid:6) (cid:2)(cid:18)(cid:6)(cid:19)(cid:16)(cid:17) (cid:12)(cid:11)(cid:6)(cid:1)(cid:5)(cid:17)(cid:15) (cid:20)(cid:21)(cid:6)(cid:5) (cid:8)(cid:18)(cid:15)(cid:6)(cid:11)(cid:6)(cid:17) (cid:10)(cid:22)(cid:6)(cid:16)(cid:22)(cid:6)(cid:15) SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 (cid:1) 4.5-V to 5.5-V VCC Operation CD54HCT573...F PACKAGE (cid:1) CD74HCT573...DB, E, OR M PACKAGE Wide Operating Temperature Range of (TOP VIEW) −55°C to 125°C (cid:1) Balanced Propagation Delays and OE 1 20 VCC Transition Times 1D 2 19 1Q (cid:1) Standard Outputs Drive Up To 10 LS-TTL 2D 3 18 2Q Loads 3D 4 17 3Q (cid:1) 4D 5 16 4Q Significant Power Reduction Compared to 5D 6 15 5Q LS-TTL Logic ICs 6D 7 14 6Q (cid:1) Inputs Are TTL-Voltage Compatible 7D 8 13 7Q 8D 9 12 8Q description/ordering information GND 10 11 LE The ’HCT573 devices are octal transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − E Tube CD74HCT573E CD74HCT573E SSOP − DB Tape and reel CD74HCT573DBR HK573 −−5555°CC ttoo 112255°CC Tube CD74HCT573M SSOOIICC −− MM HHCCTT557733MM Tape and reel CD74HCT573M96 CDIP − F Tube CD54HCT573F3A CD54HCT573F3A †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:16)(cid:13)(cid:10)(cid:2)(cid:22)(cid:1)(cid:6)(cid:21)(cid:10)(cid:14) (cid:2)(cid:11)(cid:6)(cid:11) (cid:23)(cid:24)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:23)(cid:26)(cid:24) (cid:23)(cid:31) !"(cid:27)(cid:27)#(cid:24)(cid:30) (cid:29)(cid:31) (cid:26)(cid:25) $"%&(cid:23)!(cid:29)(cid:30)(cid:23)(cid:26)(cid:24) ’(cid:29)(cid:30)#( Copyright  2004, Texas Instruments Incorporated (cid:16)(cid:27)(cid:26)’"!(cid:30)(cid:31) !(cid:26)(cid:24)(cid:25)(cid:26)(cid:27)(cid:28) (cid:30)(cid:26) (cid:31)$#!(cid:23)(cid:25)(cid:23)!(cid:29)(cid:30)(cid:23)(cid:26)(cid:24)(cid:31) $#(cid:27) (cid:30))# (cid:30)#(cid:27)(cid:28)(cid:31) (cid:26)(cid:25) (cid:6)#*(cid:29)(cid:31) (cid:21)(cid:24)(cid:31)(cid:30)(cid:27)"(cid:28)#(cid:24)(cid:30)(cid:31) (cid:10)(cid:24) $(cid:27)(cid:26)’"!(cid:30)(cid:31) !(cid:26)(cid:28)$&(cid:23)(cid:29)(cid:24)(cid:30) (cid:30)(cid:26) .(cid:21)(cid:12)(cid:18)(cid:16)(cid:13)/(cid:18)(cid:8)0(cid:3)(cid:8)(cid:3)(cid:9) (cid:29)&& $(cid:29)(cid:27)(cid:29)(cid:28)#(cid:30)#(cid:27)(cid:31) (cid:29)(cid:27)# (cid:30)#(cid:31)(cid:30)#’ (cid:31)(cid:30)(cid:29)(cid:24)’(cid:29)(cid:27)’ +(cid:29)(cid:27)(cid:27)(cid:29)(cid:24)(cid:30),( (cid:16)(cid:27)(cid:26)’"!(cid:30)(cid:23)(cid:26)(cid:24) $(cid:27)(cid:26)!#(cid:31)(cid:31)(cid:23)(cid:24)- ’(cid:26)#(cid:31) (cid:24)(cid:26)(cid:30) (cid:24)#!#(cid:31)(cid:31)(cid:29)(cid:27)(cid:23)&, (cid:23)(cid:24)!&"’# "(cid:24)&#(cid:31)(cid:31) (cid:26)(cid:30))#(cid:27)+(cid:23)(cid:31)# (cid:24)(cid:26)(cid:30)#’( (cid:10)(cid:24) (cid:29)&& (cid:26)(cid:30))#(cid:27) $(cid:27)(cid:26)’"!(cid:30)(cid:31)(cid:9) $(cid:27)(cid:26)’"!(cid:30)(cid:23)(cid:26)(cid:24) (cid:30)#(cid:31)(cid:30)(cid:23)(cid:24)- (cid:26)(cid:25) (cid:29)&& $(cid:29)(cid:27)(cid:29)(cid:28)#(cid:30)#(cid:27)(cid:31)( $(cid:27)(cid:26)!#(cid:31)(cid:31)(cid:23)(cid:24)- ’(cid:26)#(cid:31) (cid:24)(cid:26)(cid:30) (cid:24)#!#(cid:31)(cid:31)(cid:29)(cid:27)(cid:23)&, (cid:23)(cid:24)!&"’# (cid:30)#(cid:31)(cid:30)(cid:23)(cid:24)- (cid:26)(cid:25) (cid:29)&& $(cid:29)(cid:27)(cid:29)(cid:28)#(cid:30)#(cid:27)(cid:31)( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:1)(cid:6)(cid:3)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:1)(cid:6)(cid:3)(cid:7)(cid:8) (cid:10)(cid:1)(cid:6)(cid:11)(cid:12) (cid:6)(cid:13)(cid:11)(cid:14)(cid:15)(cid:16)(cid:11)(cid:13)(cid:17)(cid:14)(cid:6) (cid:2)(cid:18)(cid:6)(cid:19)(cid:16)(cid:17) (cid:12)(cid:11)(cid:6)(cid:1)(cid:5)(cid:17)(cid:15) (cid:20)(cid:21)(cid:6)(cid:5) (cid:8)(cid:18)(cid:15)(cid:6)(cid:11)(cid:6)(cid:17) (cid:10)(cid:22)(cid:6)(cid:16)(cid:22)(cid:6)(cid:15) SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 FUNCTION TABLE (each latch) INPUTS OOUUTTPPUUTT OE LE D Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) 1 OE 11 LE C1 19 2 1Q 1D 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output drain current per output, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA O O CC Continuous output source or sink current per output, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W JA E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:1)(cid:6)(cid:3)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:1)(cid:6)(cid:3)(cid:7)(cid:8) (cid:10)(cid:1)(cid:6)(cid:11)(cid:12) (cid:6)(cid:13)(cid:11)(cid:14)(cid:15)(cid:16)(cid:11)(cid:13)(cid:17)(cid:14)(cid:6) (cid:2)(cid:18)(cid:6)(cid:19)(cid:16)(cid:17) (cid:12)(cid:11)(cid:6)(cid:1)(cid:5)(cid:17)(cid:15) (cid:20)(cid:21)(cid:6)(cid:5) (cid:8)(cid:18)(cid:15)(cid:6)(cid:11)(cid:6)(cid:17) (cid:10)(cid:22)(cid:6)(cid:16)(cid:22)(cid:6)(cid:15) SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 recommended operating conditions (see Note 3) TA = 25°C TTAO = 1 −2555°°CC TATO = 8−54°0C°C UUNNIITT MIN MAX MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 2 V VIL Low-level input voltage 0.8 0.8 0.8 V VI Input voltage VCC VCC VCC V VO Output voltage VCC VCC VCC V ∆t/∆v Input transition rise or fall rate 500 500 500 ns NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC TA = 25°C TTAO = 1 −2555°°CC TATO = 8−54°0C°C UUNNIITT MIN MAX MIN MAX MIN MAX IOH = −20 µA 4.4 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL 44..55 VV VV IOH = −6 mA 3.98 3.7 3.84 IOL = 20 µA 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 44..55 VV VV IOL = 6 mA 0.26 0.4 0.33 II VI = VCC or 0 5.5 V ±0.1 ±1 ±1 µA IOZ VO = VCC or 0 5.5 V ±0.5 ±10 ±5 µA ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA 4.5 V to ∆ICC† One input at VCC − 2.1 V, Other inputs at 0 or VCC 5.5 V 360 490 450 µA Ci 10 10 10 pF Co 20 20 20 pF †Additional quiescent supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. HCT INPUT LOADING TABLE INPUT UNIT LOAD OE 1.25 Any D 0.3 LE 0.65 Unit load is ∆ICC limit specified in electrical characteristics table (e.g., 360 µA max at 25°C). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:1)(cid:6)(cid:3)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:1)(cid:6)(cid:3)(cid:7)(cid:8) (cid:10)(cid:1)(cid:6)(cid:11)(cid:12) (cid:6)(cid:13)(cid:11)(cid:14)(cid:15)(cid:16)(cid:11)(cid:13)(cid:17)(cid:14)(cid:6) (cid:2)(cid:18)(cid:6)(cid:19)(cid:16)(cid:17) (cid:12)(cid:11)(cid:6)(cid:1)(cid:5)(cid:17)(cid:15) (cid:20)(cid:21)(cid:6)(cid:5) (cid:8)(cid:18)(cid:15)(cid:6)(cid:11)(cid:6)(cid:17) (cid:10)(cid:22)(cid:6)(cid:16)(cid:22)(cid:6)(cid:15) SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 timing requirements over recommended operating free-air temperature range, V = 4.5 V (unless CC otherwise noted) (see Figure 1) TA = 25°C TTAO = 1 −2555°°CC TATO = 8−54°0C°C UUNNIITT MIN MAX MIN MAX MIN MAX tw Pulse duration, LE high 16 24 20 ns tsu Setup time, data before LE↓ 13 20 16 ns th Hold time, data after LE↓ 10 15 13 ns switching characteristics over recommended operating free-air temperature range, VCC = 4.5 V (unless otherwise noted) (see Figure 1) PPAARRAAMMEETTEERR FROM TO LOAD TA = 25°C TTAO = 1 −2555°°CC TATO = 8−54°0C°C UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) CCAAPPAACCIITTAANNCCEE MIN MAX MIN MAX MIN MAX D 35 53 44 ttppdd QQ CCLL == 5500 ppFF nnss LE 35 53 44 ten OE Q CL = 50 pF 35 53 44 ns tdis OE Q CL = 50 pF 35 53 44 ns tt Q CL = 50 pF 12 18 15 ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TYP UNIT Cpd Power dissipation capacitance 53 pF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:1)(cid:6)(cid:3)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:1)(cid:6)(cid:3)(cid:7)(cid:8) (cid:10)(cid:1)(cid:6)(cid:11)(cid:12) (cid:6)(cid:13)(cid:11)(cid:14)(cid:15)(cid:16)(cid:11)(cid:13)(cid:17)(cid:14)(cid:6) (cid:2)(cid:18)(cid:6)(cid:19)(cid:16)(cid:17) (cid:12)(cid:11)(cid:6)(cid:1)(cid:5)(cid:17)(cid:15) (cid:20)(cid:21)(cid:6)(cid:5) (cid:8)(cid:18)(cid:15)(cid:6)(cid:11)(cid:6)(cid:17) (cid:10)(cid:22)(cid:6)(cid:16)(cid:22)(cid:6)(cid:15) SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER S1 S2 tPZH Open Closed Test S1 ten Point 1 kΩ tPZL Closed Open From Output Under Test tPHZ Open Closed tdis CL S2 tPLZ Closed Open (see Note A) tpd or tt Open Open tw LOAD CIRCUIT 3 V Input 1.3 V 1.3 V 0 V VOLTAGE WAVEFORMS PULSE DURATION 3 V Reference 3 V 1.3 V CLR 1.3 V Input 0 V Input 0 V tsu th trec 3 V Data 2.7 V 2.7 V 3 V 1.3 V 1.3 V Input 1.3 V 0.3 V 0.3 V CLK 0 V 0 V tr tf VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS RECOVERY TIME SETUP AND HOLD AND INPUT RISE AND FALL TIMES 3 V 3 V Input 1.3 V 1.3 V Output 1.3 V 1.3 V 0 V Control 0 V tPLH tPHL tPZL tPLZ InO-Puhtapsuet 1.3 V 90% 90% 1.3 V VOH Output ≈VCC 10% 10% VOL Waveform 1 1.3 V 10% tr tf (see Note B) VOL tPHL tPLH tPZH tPHZ VOH Out-of-Phase 90% 1.3 V 1.3 V 90% Output VOH Output 10% 10% VOL Waveform 2 1.3 V 90% tf tr (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time, with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-8685601RA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8685601RA CD54HCT573F3A CD54HCT573F ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HCT573F CD54HCT573F3A ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8685601RA CD54HCT573F3A CD74HCT573DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HK573 & no Sb/Br) CD74HCT573E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT573E (RoHS) CD74HCT573EE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT573E (RoHS) CD74HCT573M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT573M & no Sb/Br) CD74HCT573M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT573M & no Sb/Br) CD74HCT573M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT573M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HCT573, CD74HCT573 : •Catalog: CD74HCT573 •Military: CD54HCT573 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HCT573DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 CD74HCT573M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HCT573DBR SSOP DB 20 2000 367.0 367.0 38.0 CD74HCT573M96 SOIC DW 20 2000 367.0 367.0 45.0 PackMaterials-Page2

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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