CD54/74HC365, CD54/74HCT365, CD54/74HC366 Data sheet acquired from Harris Semiconductor High Speed CMOS Logic Hex Buffer/Line Driver, SCHS180C Three-State Non-Inverting and Inverting November 1997 - Revised October 2003 Features lowpowerSchottkyTTLcircuits.Bothcircuitsare capableof driving up to 15 low power Schottky inputs. • Buffered Inputs The ’HC365 and ’HCT365 are non-inverting buffers, whereas [ /Title • High Current Bus Driver Outputs the ’HC366 is an inverting buffer. These devices have two (CD74 three-state control inputs (OE1 and OE2) which are NORed • TypicalPropagationDelaytPLH,tPHL=8nsatVCC=5V, HC365 CL = 15pF, TA = 25oC together to control all six gates. , The ’HCT365 logic families are speed, function and pin • Fanout (Over Temperature Range) compatible with the standard LS logic family. CD74 - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads Ordering Information HCT36 - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads 5, • Wide Operating Temperature Range . . .-55oC to 125oC TEMP. RANGE CD74 PART NUMBER (oC) PACKAGE • Balanced Propagation Delay and Transition Times HC366 CD54HC365F3A -55 to 125 16 Ld CERDIP • Significant Power Reduction Compared to LSTTL , CD54HC366F3A -55 to 125 16 Ld CERDIP Logic ICs CD74 CD54HCT365F3A -55 to 125 16 Ld CERDIP • HC Types HCT36 CD74HC365E -55 to 125 16 Ld PDIP - 2V to 6V Operation 6) /Sub- - High Noise Immunity: NIL = 30%, NIH = 30% of VCC CD74HC365M -55 to 125 16 Ld SOIC at VCC = 5V CD74HC365MT -55 to 125 16 Ld SOIC ject • HCT Types CD74HC365M96 -55 to 125 16 Ld SOIC (High - 4.5V to 5.5V Operation CD74HC366E -55 to 125 16 Ld PDIP Speed - Direct LSTTL Input Logic Compatibility, CD74HC366M -55 to 125 16 Ld SOIC VIL= 0.8V (Max), VIH = 2V (Min) CD74HC366M96 -55 to 125 16 Ld SOIC - CMOS Input Compatibility, Il≤1µA at VOL, VOH CD74HCT365E -55 to 125 16 Ld PDIP Description CD74HCT365M -55 to 125 16 Ld SOIC The’HC365,’HCT365,and’HC366silicongateCMOSthree- CD74HCT365MT -55 to 125 16 Ld SOIC state buffers are general purpose high-speed non-inverting CD74HCT365M96 -55 to 125 16 Ld SOIC and inverting buffers. They have high drive current outputs NOTE: When ordering, use the entire part number. The suffix 96 which enable high speed operation even when driving large denotestapeandreal.ThesuffixTdenotesasmall-quantityreelof bus capacitances. These circuits possess the low power 250. dissipationofCMOScircuitry,yethavespeedscomparableto Pinout CD54HC365, CD54HCT365, CD54HC366 (CERDIP) CD74HC365, CD74HCT365, CD74HC366 (PDIP, SOIC) TOP VIEW OE1 1 16 VCC 1A 2 15 OE2 (1Y) 1Y 3 14 6A 2A 4 13 6Y (6Y) (2Y) 2Y 5 12 5A 3A 6 11 5Y (5Y) (3Y) 3Y 7 10 4A GND 8 9 4Y (4Y) CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CD54/74HC365, CD54/74HCT365, CD54/74HC366 Functional Diagrams HC365, HCT365 HC366 OE1 1 16 VCC OE1 1 16 VCC 2 15 1A 2 15 OE2 1A OE2 3 14 1Y 3 14 6A 1Y 6A 4 13 2A 4 13 6Y 2A 6Y 5 12 2Y 5 12 5A 2Y 5A 3A 6 11 5Y 3A 6 11 5Y 7 10 3Y 7 10 4A 3Y 4A 8 9 8 9 GND 4Y GND 4Y TRUTH TABLE OUTPUTS INPUTS (Y) OE1 OE2 A HC/HCT365 HC366 L L L L H L L H H L X H X Z Z H X X Z Ζ NOTE: H = High Voltage Level L = Low Voltage Level X = Don’t Care Z = High Impedance (OFF) State 2

CD54/74HC365, CD54/74HCT365, CD54/74HC366 Logic Diagram VCC 16 ONE OF SIX IDENTICAL CIRCUITS 2 1A (NOTE) 3 1Y GND 8 1 OE1 4 15 2A 5 2Y OE2 6 3A 7 3Y 10 4A 9 4Y 12 5A 11 5Y 14 6A 13 6Y NOTE: Inverter not included in HC/HCT365. FIGURE1. LOGICDIAGRAMFORTHEHC/HCT365ANDHC366(OUTPUTSFORHC/HCT365ARECOMPLEMENTSOFTHOSE SHOWN, i.e., 1Y, 2Y, ETC.) 3

CD54/74HC365, CD54/74HCT365, CD54/74HC366 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W) DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 DC Output Diode Current, IOK Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC DC Drain Current, per Output, IO Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA (SOIC - Lead Tips Only) DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V Voltage -7.8 6 5.48 - - 5.34 - 5.2 - V TTL Loads Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V Voltage 7.8 6 - - 0.26 - 0.33 - 0.4 V TTL Loads Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND 4

CD54/74HC365, CD54/74HCT365, CD54/74HC366 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Three-State Leakage IOZ VIL or VO = 6 - - ±0.5 - ±5.0 - ±10 µA Current VIH VCC or GND HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIH or -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage VIL CMOS Loads High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIH or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage VIL CMOS Loads Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCC to 0 5.5 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per -2.1 5.5 Input Pin: 1 Unit Load (Note 2) Three-State Leakage IOZ VIL or VO = 5.5 - - ±0.5 - ±5.0 - ±10 µA Current VIH VCC or GND NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS OE1 0.6 All Others 0.55 NOTE: Unit Load is∆ICClimit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. Switching Specifications - HC/HCT365 Input tr, tf = 6ns -55oC TO 25oC -40oC TO 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC (V) TYP MAX MAX MAX UNITS HC TYPES Propagation Delay, tPLH, tPHL CL= 50pF 2 - 105 130 160 ns Data to Outputs 4.5 - 21 26 32 ns HC/HCT365 6 - 18 22 27 ns CL= 15pF 5 8 - - - ns 5

CD54/74HC365, CD54/74HCT365, CD54/74HC366 Switching Specifications - HC/HCT365 Input tr, tf = 6ns (Continued) -55oC TO 25oC -40oC TO 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC (V) TYP MAX MAX MAX UNITS Propagation Delay, tPLH, tPHL CL= 50pF 2 - 110 140 165 ns Data to Outputs 4.5 - 22 28 33 ns HC366 6 - 19 24 28 ns CL= 15pF 5 9 - - - ns Propagation Delay, tPLH, tPHL CL= 50pF 2 - 150 190 225 ns Output Enable and Disable 4.5 - 30 38 45 ns to Outputs 6 - 26 33 38 ns CL= 15pF 5 12 - - - ns Output Transition Time tTLH, tTHL CL= 50pF 2 - 60 75 90 ns 4.5 - 12 15 18 ns 6 - 10 13 15 ns Input Capacitance CI - - - 10 10 10 pF Three-State Output CO - - - 20 20 20 pF Capacitance Power Dissipation CPD - 5 40 - - - pF Capacitance (Notes 3, 4) HCT TYPES Propagation Delay, tPLH, tPHL CL= 50pF 4.5 - 25 31 38 ns Data to Outputs HC/HCT365 CL= 15pF 5 9 - - - ns Propagation Delay, tPLH, tPHL CL= 50pF 4.5 - 27 34 41 ns Data to Outputs HC366 CL= 15pF 5 11 - - - ns Propagation Delay, tPLH, tPHL CL= 50pF 4.5 - 35 44 53 ns Output Enable and Disable to Outputs CL= 15pF 5 14 - - - ns Output Transition Time tTLH, tTHL CL= 50pF 4.5 - 12 15 18 ns Input Capacitance CIN - - - 10 10 10 pF Three-State Capacitance CO - - - 20 20 20 pF Power Dissipation CPD - 5 42 - - - pF Capacitance (Notes 3, 4) NOTES: 3. CPD is used to determine the dynamic power consumption, per buffer. 4. PD= VCC2fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 6

CD54/74HC365, CD54/74HCT365, CD54/74HC366 Test Circuits and Waveforms tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% 1.3V INVERTING INVERTING 10% 10% OUTPUT OUTPUT tPHL tPLH tPHL tPLH FIGURE2. HCTRANSITIONTIMESANDPROPAGATION FIGURE3. HCTTRANSITIONTIMESANDPROPAGATION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC 6ns 6ns tr 6ns tf 6ns OUTPUT 90% VCC OUTPUT 2.7 3V DISABLE 50% DISABLE 1.3 10% 0.3 GND GND tPLZ tPZL tPLZ tPZL OUTPUT LOW OUTPUT LOW TO OFF 50% TO OFF 1.3V 10% 10% tPHZ 90% tPZH tPHZ 90% tPZH OUTPUT HIGH OUTPUT HIGH 50% TO OFF TO OFF 1.3V OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS ENABLED DISABLED ENABLED ENABLED DISABLED ENABLED FIGURE4. HCTHREE-STATEPROPAGATIONDELAY FIGURE5. HCTTHREE-STATEPROPAGATIONDELAY WAVEFORM WAVEFORM OTHER OUTPUT INPUTS IC WITH RL = 1kΩ TIED HIGH THREE- VCC FOR tPLZ AND tPZL OR LOW STATE CL GND FOR tPHZ AND tPZH OUTPUT 50pF OUTPUT DISABLE NOTE: OpendrainwaveformstPLZandtPZLarethesameasthoseforthree-stateshownontheleft.ThetestcircuitisOutputRL=1kΩto VCC, CL = 50pF. FIGURE 6. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 7

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD54HC365F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 8500101EA CD54HC365F3A CD54HC366F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8682801EA CD54HC366F3A CD54HCT365F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HCT365F3A CD74HC365E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC365E & no Sb/Br) CD74HC365M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC365M & no Sb/Br) CD74HC365M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC365M & no Sb/Br) CD74HC365M96E4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC365M & no Sb/Br) CD74HC365MT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC365M & no Sb/Br) CD74HC366E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC366E & no Sb/Br) CD74HC366M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC366M & no Sb/Br) CD74HC366M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC366M & no Sb/Br) CD74HCT365E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT365E & no Sb/Br) CD74HCT365M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT365M & no Sb/Br) CD74HCT365M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT365M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC365, CD54HC366, CD54HCT365, CD74HC365, CD74HC366, CD74HCT365 : •Catalog: CD74HC365, CD74HC366, CD74HCT365 •Automotive: CD74HC366-Q1, CD74HC366-Q1 •Military: CD54HC365, CD54HC366, CD54HCT365 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) CD74HC365M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC366M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT365M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC365M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC366M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT365M96 SOIC D 16 2500 333.2 345.9 28.6 PackMaterials-Page2

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