CD54HC32, CD74HC32, CD54HCT32, CD74HCT32 Data sheet acquired from Harris Semiconductor SCHS274C High-Speed CMOS Logic September 1997 - Revised September 2003 Quad 2-Input OR Gate Features Description • Typical Propagation Delay: 7ns at VCC = 5V, The’HC32and’HCT32containfour2-inputORgatesinone [ /Title CL = 15pF, TA = 25oC package. Logic gates utilize silicon gate CMOS technology toachieveoperatingspeedssimilartoLSTTLgateswiththe (CD54 • Fanout (Over Temperature Range) low power consumption of standard CMOS integrated cir- HCT32 - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads cuits. All devices have the ability to drive 10 LSTTL loads. - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads The HCT logic family is functionally pin compatible with the , CD74 • Wide Operating Temperature Range . . .-55oC to 125oC standard LS logic family. HC32, • Balanced Propagation Delay and Transition Times Ordering Information CD74 • Significant Power Reduction Compared to LSTTL TEMP. RANGE HCT32 Logic ICs PART NUMBER (oC) PACKAGE ) • HC Types CD54HC32F3A -55 to 125 14 Ld CERDIP /Sub- - 2V to 6V Operation ject - High Noise Immunity: NIL = 30%, NIH = 30% of VCC CD54HCT32F3A -55 to 125 14 Ld CERDIP (High at VCC = 5V CD74HC32E -55 to 125 14 Ld PDIP • HCT Types CD74HC32M -55 to 125 14 Ld SOIC - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, CD74HC32MT -55 to 125 14 Ld SOIC VIL= 0.8V (Max), VIH = 2V (Min) CD74HC32M96 -55 to 125 14 Ld SOIC - CMOS Input Compatibility, Il≤1µA at VOL, VOH CD74HCT32E -55 to 125 14 Ld PDIP CD74HCT32M -55 to 125 14 Ld SOIC CD74HCT32MT -55 to 125 14 Ld SOIC CD74HCT32M96 -55 to 125 14 Ld SOIC NOTE: Whenordering,usetheentirepartnumber.Thesuffix96 denotestapeandreel.ThesuffixTdenotesasmall-quantityreel of 250. Pinout CD54HC32, CD54HCT32 (CERDIP) CD74HC32, CD74HCT32 (PDIP, SOIC) TOP VIEW 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated. 1

CD54HC32, CD74HC32, CD54HCT, CD74HCT32 Functional Diagram 1 14 1A VCC 2 13 1B 4B 3 12 1Y 4A 4 11 2A 4Y 5 10 2B 3B 6 9 2Y 3A 7 8 GND 3Y TRUTH TABLE INPUTS OUTPUT nA nB nY L L L L H H H L H H H H H = High Voltage Level, L = Low Voltage Level HC Logic Symbol HCT Logic Symbol nA nA nY nY nB nB 2

CD54HC32, CD74HC32, CD54HCT, CD74HCT32 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W) DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 DC Output Diode Current, IOK Maximum Junction Temperature (Hermetic Package or Die) . . .175oC For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC DC Output Source or Sink Current per Output Pin, IO Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC DC VCC or Ground Current, ICC orIGND. . . . . . . . . . . . . . . . . .±50mA (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage -5.2 6 5.48 - - 5.34 - 5.2 - V TTL Loads Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage 5.2 6 - - 0.26 - 0.33 - 0.4 V TTL Loads Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 6 - - 2 - 20 - 40 µA Current GND 3

CD54HC32, CD74HC32, CD54HCT32, CD74HCT32 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIH or -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage VIL CMOS Loads High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIH or -0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage VIL CMOS Loads Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCC - 5.5 - ±0.1 - ±1 - ±1 µA Current and GND Quiescent Device ICC VCC or 0 5.5 - - 2 - 20 - 40 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 2) -2.1 5.5 Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS All 1.5 NOTE: Unit Load is∆ICClimit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. Switching SpecificationsInput tr, tf = 6ns 25oC -40oC TO 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay, Input to tPLH, tPHL CL= 50pF 2 - - 90 - 115 - 135 ns Output (Figure 1) 4.5 - - 18 - 23 - 27 ns 6 - - 15 - 20 - 23 ns PropagationDelay,DataInputto tPLH, tPHL CL= 15pF 5 - 7 - - - - - ns Output Y Transition Times (Figure 1) tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns 4

CD54HC32, CD74HC32, CD54HCT, CD74HCT32 Switching SpecificationsInput tr, tf = 6ns (Continued) 25oC -40oC TO 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS Input Capacitance CI - - - - 10 - 10 - 10 pF Power Dissipation Capacitance CPD - 5 - 22 - - - - - pF (Notes 3, 4) HCT TYPES Propagation Delay, Input to tRHL, tPHL CL= 50pF 4.5 - - 24 - 30 - 36 ns Output (Figure 2) PropagationDelay,DataInputto tPLH, tPHL CL= 15pF 5 - 9 - - - - - ns Output Y Transition Times (Figure 2) tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns Input Capacitance CI - - - - 10 - 10 - 10 pF Power Dissipation Capacitance CPD - 5 - 22 - - - - - pF (Notes 3, 4) NOTES: 3. CPD is used to determine the dynamic power consumption, per gate. 4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% INVERTING 10% INVERTING 110.%3V OUTPUT OUTPUT tPHL tPLH tPHL tPLH FIGURE1. HCANDHCUTRANSITIONTIMESANDPROPAGA- FIGURE2. HCTTRANSITIONTIMESANDPROPAGATION TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC 5

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 5962-8685201CA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-8685201CA CD54HCT32F3A CD54HC32F3A ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 8404501CA CD54HC32F3A CD54HCT32F ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 CD54HCT32F CD54HCT32F3A ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-8685201CA CD54HCT32F3A CD74HC32E ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC32E & no Sb/Br) CD74HC32EE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC32E & no Sb/Br) CD74HC32M ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC32M & no Sb/Br) CD74HC32M96 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC32M & no Sb/Br) CD74HC32MG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC32M & no Sb/Br) CD74HC32MT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC32M & no Sb/Br) CD74HC32MTG4 ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC32M & no Sb/Br) CD74HCT32E ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT32E & no Sb/Br) CD74HCT32EE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT32E & no Sb/Br) CD74HCT32M ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT32M & no Sb/Br) CD74HCT32M96 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT32M & no Sb/Br) CD74HCT32ME4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT32M & no Sb/Br) (1) The marketing status values are defined as follows: Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC32, CD54HCT32, CD74HC32, CD74HCT32 : •Catalog: CD74HC32, CD74HCT32 •Military: CD54HC32, CD54HCT32 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC32M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC32MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HCT32M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC32M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HC32MT SOIC D 14 250 210.0 185.0 35.0 CD74HCT32M96 SOIC D 14 2500 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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