CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Data sheet acquired from Harris Semiconductor SCHS173C High-Speed CMOS Logic 8-Bit Addressable Latch November 1997 - Revised October 2003 Features Description • Buffered Inputs and Outputs The ’HC259 and ’HCT259 Addressable Latch features the low-powerconsumptionassociatedwithCMOScircuitryand [ /Title • Four Operating Modes has speeds comparable to low-power Schottky. (CD74 • Typical Propagation Delay of 15ns at VCC = 5V, This latches three active modes and one reset mode. When HC259 CL = 15pF, TA = 25oC boththeLatchEnable(LE)andMasterReset(MR)inputsare , • Fanout (Over Temperature Range) low (8-line Demultiplexer mode) the output of the addressed CD74 - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads latch follows the Data input and all other outputs are forced low. When both MR and LE are high (Memory Mode), all HCT25 - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads outputsareisolated fromtheDatainput, i.e.,alllatcheshold 9) • Wide Operating Temperature Range . . .-55oC to 125oC the last data presented before the LE transition from low to /Sub- high.AconditionofLElowandMRhigh(AddressableLatch • Balanced Propagation Delay and Transition Times ject mode) allows the addressed latch’s output to follow the data • Significant Power Reduction Compared to LSTTL input; all other latches are unaffected. The Reset mode (all (High Logic ICs outputs low) results whenLE is high andMR is low. Speed CMOS • HC Types Ordering Information - 2V to 6V Operation Logic 8-Bit - Hati gVhC CN o=i s5eV Immunity: NIL = 30%, NIH = 30% of VCC PART NUMBER TEMP(.o RCA)NGE PACKAGE Addres • HCT Types CD54HC259F3A -55 to 125 16 Ld CERDIP sable - 4.5V to 5.5V Operation Latch) CD54HCT259F3A -55 to 125 16 Ld CERDIP - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) CD74HC259E -55 to 125 16 Ld PDIP - CMOS Input Compatibility, Il≤1µA at VOL, VOH CD74HC259M -55 to 125 16 Ld SOIC CD74HC259MT -55 to 125 16 Ld SOIC CD74HC259M96 -55 to 125 16 Ld SOIC CD74HCT259E -55 to 125 16 Ld PDIP CD74HCT259M -55 to 125 16 Ld SOIC CD74HCT259MT -55 to 125 16 Ld SOIC CD74HCT259M96 -55 to 125 16 Ld SOIC NOTE: Whenordering,usetheentirepartnumber.Thesuffix96 denotestapeandreel.ThesuffixTdenotesasmall-quantityreel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Pinout CD54HC259, CD54HCT259 (CERDIP) CD74HC259, CD74HCT259 (PDIP, SOIC) TOP VIEW A0 1 16 VCC A1 2 15 MR A2 3 14 LE Q0 4 13 D Q1 5 12 Q7 Q2 6 11 Q6 Q3 7 10 Q5 GND 8 9 Q4 Functional Diagram 4 Q0 1 A0 5 Q1 A1 2 DE1C-OOFD-8ER LATC8HES 6 Q2 7 Q3 3 A2 9 Q4 10 14 Q5 LE 11 15 Q6 MR 13 12 D Q7 GND = 8 VCC= 16 TRUTH TABLE LATCH SELECTION TABLE INPUTS OUTPUT OF SELECT INPUTS LATCH ADDRESS EACH OTHER A2 A1 A0 ADDRESSED MR LE LATCH OUTPUT FUNCTION L L L 0 H L D Qio Addressable L L H 1 Latch L H L 2 H H Qio Qio Memory L H H 3 L L D L 8-Line H L L 4 Demultiplexer H L H 5 L H L L Reset H H L 6 H = High Voltage Level H H H 7 L = Low Voltage Level D = The level at the data input Qio=ThelevelofQi(i=0,1...7,asappropriate)beforetheindicat- ed steady-state input conditions were established. 2

CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W) DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 DC Output Diode Current, IOK Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC DC Drain Current, per Output, IO Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA (SOIC - Lead Tips Only) DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC orIGND. . . . . . . . . . . . . . . . . .±50mA Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIHorVIL -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output - - - - - - - - - V Voltage -4 4.5 3.98 - - 3.84 - 3.7 - V TTL Loads -5.2 6 5.48 - - 5.34 - 5.2 - V Low Level Output VOL VIHorVIL 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output - - - - - - - - - V Voltage 4 4.5 - - 0.26 - 0.33 - 0.4 V TTL Loads 5.2 6 - - 0.26 - 0.33 - 0.4 V Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND 3

CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIHorVIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage CMOS Loads High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIHorVIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage CMOS Loads Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCCand 0 5.5 - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 2) -2.1 5.5 Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS A0 - A2,LE 1.5 D 1.2 MR 0.75 NOTE: UnitLoadis∆ICClimitspecifiedinDCElectricalTable,e.g., 360µA max at 25oC. Prerequisite for Switching Specifications 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC(V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS HC TYPES Pulse Width tWL LE 2 70 - - 90 - - 105 - - ns 4.5 14 - - 18 - - 21 - - ns 6 12 - - 15 - - 18 - - ns 4

CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Prerequisite for Switching Specifications (Continued) 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC(V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS MR tWL 2 70 - - 90 - - 105 - - ns 4.5 14 - - 18 - - 21 - - ns 6 12 - - 15 - - 18 - - ns Setup Time tSU D toLE 2 80 - - 100 - - 120 - - ns A toLE 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns Hold Time tH D toLE 2 0 - - 0 - - 0 - - ns A toLE 4.5 0 - - 0 - - 0 - - ns 6 0 - - 0 - - 0 - - ns HCT TYPES Pulse Width tWL 4.5 18 - - 23 - - 27 - - ns LE MR Setup Time tSU 4.5 17 - - 21 - - 26 - - ns D toLE A toLE Hold Time tH 4.5 0 - - 0 - - 0 - - ns D toLE A toLE Switching Specifications CL = 50pF, Input tr, tf= 6ns -40oC TO -55oC TO 25oC 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay tPHL CL = 50pF D to Q 2 - - 185 - 230 - 280 ns 4.5 - - 37 - 46 - 56 ns CL = 15pF 5 - 15 - - - - - ns CL = 50pF 6 - - 31 - 39 - 48 ns LE to Q tPHL CL = 50pF 2 - - 170 - 215 - 255 ns 4.5 - - 34 - 43 - 51 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 29 - 37 - 43 ns 5

CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Switching Specifications CL = 50pF, Input tr, tf= 6ns (Continued) -40oC TO -55oC TO 25oC 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS A to Q tPHL CL = 50pF 2 - - 185 - 230 - 280 ns 4.5 - - 37 - 46 - 56 ns CL = 15pF 5 - 15 - - - - - ns CL = 50pF 6 - - 31 - 39 - 48 ns MR to Q tPHL,tPLH CL = 50pF 2 - - 155 - 195 - 235 ns 4.5 - - 31 - 39 - 47 ns CL = 15pF 5 - 13 - - - - - ns CL = 50pF 6 - - 26 - 33 - 40 ns Output Transition Time tTHL, tTLH CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Power Dissipation Capacitance CPD CL = 15pF 5 - 21 - - - - - pF (Notes 3, 4) Input Capacitance CI CL = 50pF - 10 - 10 - 10 - 10 pF HCT TYPES Propagation Delay tPHL,tPLH D to Q CL = 50pF 4.5 - - 39 - 49 - 59 ns CL = 15pF 5 - 16 - - - - - ns LE to Q CL = 50pF 4.5 - - 38 - 48 - 57 ns CL = 15pF 5 - 16 - - - - - ns A to Q CL = 50pF 4.5 - - 41 - 51 - 61 ns CL = 15pF 5 - 17 - - - - - ns MR to Q CL = 50pF 4.5 - - 39 - 49 - 59 ns CL = 15pF 5 - 16 - - - - - ns Power Dissipation Capacitance CPD CL = 15pF 5 - 22 - - - - - pF (Notes 3, 4) Input Capacitance CI CL = 50pF - 10 - 10 - 10 - 10 pF Output Transition Time tTHL, tTLH CL = 50pF 4.5 - - 15 - 19 - 22 ns NOTES: 3. CPD is used to determine the dynamic power consumption, per package. 4. PD=CPDVCC2fi+∑CLVCC2fOwherefi=InputFrequency,fO=OutputFrequency,CL=OutputLoadCapacitance, VCC = Supply Voltage. 6

CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Test Circuits and Waveforms I trCL tfCL tWL+ tWH=fCIL trCL= 6ns tfCL= 6ns tWL+ tWH=fCL VCC 3V 90% 2.7V CLOCK 50% 50% 50% CLOCK 1.3V 1.3V 1.3V 10% 10% GND 0.3V 0.3V GND tWL tWH tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. FIGURE1. HCCLOCKPULSERISEANDFALLTIMESAND FIGURE2. HCTCLOCKPULSERISEANDFALLTIMESAND PULSE WIDTH PULSE WIDTH tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% 1.3V INVERTING INVERTING 10% 10% OUTPUT OUTPUT tPHL tPLH tPHL tPLH FIGURE3. HCTRANSITIONTIMESANDPROPAGATION FIGURE4. HCTTRANSITIONTIMESANDPROPAGATION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC trCL tfCL trCL tfCL 90% VCC CLOCK 2.7V 3V CLOCK 50% 1.3V INPUT 10% INPUT 0.3V GND GND tH(H) tH(L) tH(H) tH(L) VCC DATA 3V INDPAUTAT 50% INPUT 1.3V 1.3V 1.3V GND GND tSU(H) tSU(L) tSU(H) tSU(L) tTLH tTHL tTLH tTHL 90% 90% 90% 90% 50% OUTPUT OUTPUT 1.3V 1.3V 10% 10% tPLH tPHL tPLH tPHL tREM tREM VCC 3V SET, RESET 50% SET, RESET 1.3V OR PRESET GND OR PRESET GND IC IC CL CL 50pF 50pF FIGURE5. HCSETUPTIMES,HOLDTIMES,REMOVALTIME, FIGURE6. HCTSETUPTIMES,HOLDTIMES,REMOVALTIME, AND PROPAGATION DELAY TIMES FOR EDGE AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7

CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Test Circuits and Waveforms (Continued) 6ns 6ns tr 6ns tf 6ns OUTPUT 90% VCC OUTPUT 2.7 3V DISABLE 50% DISABLE 1.3 10% 0.3 GND GND tPLZ tPZL tPLZ tPZL OUTPUT LOW OUTPUT LOW TO OFF 50% TO OFF 1.3V 10% 10% tPHZ 90% tPZH tPHZ 90% tPZH OUTPUT HIGH OUTPUT HIGH 50% TO OFF TO OFF 1.3V OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS ENABLED DISABLED ENABLED ENABLED DISABLED ENABLED FIGURE7. HCTHREE-STATEPROPAGATIONDELAY FIGURE8. HCTTHREE-STATEPROPAGATIONDELAY WAVEFORM WAVEFORM OTHER OUTPUT INPUTS IC WITH RL = 1kΩ TIED HIGH THREE- VCC FOR tPLZ AND tPZL OR LOW STATE CL GND FOR tPHZ AND tPZH OUTPUT 50pF OUTPUT DISABLE NOTE: OpendrainwaveformstPLZandtPZLarethesameasthoseforthree-stateshownontheleft.ThetestcircuitisOutputRL=1kΩto VCC, CL = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 8

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 5962-8985201EA ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-8985201EA CD54HCT259F3A CD54HC259F3A ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 8551901EA CD54HC259F3A CD54HCT259F3A ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-8985201EA CD54HCT259F3A CD74HC259E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC259E & no Sb/Br) CD74HC259M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC259M & no Sb/Br) CD74HC259M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC259M & no Sb/Br) CD74HC259MT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC259M & no Sb/Br) CD74HCT259E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT259E & no Sb/Br) CD74HCT259EE4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT259E & no Sb/Br) CD74HCT259M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT259M & no Sb/Br) CD74HCT259M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT259M & no Sb/Br) CD74HCT259M96E4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT259M & no Sb/Br) CD74HCT259MT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT259M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC259, CD54HCT259, CD74HC259, CD74HCT259 : •Catalog: CD74HC259, CD74HCT259 •Military: CD54HC259, CD54HCT259 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) CD74HC259M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT259M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC259M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT259M96 SOIC D 16 2500 333.2 345.9 28.6 PackMaterials-Page2

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