CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 Data sheet acquired from Harris Semiconductor SCHS167E High-Speed CMOS Logic November 1997 - Revised October 2004 Octal Buffer/Line Drivers, Three-State Features Ordering Information • HC/HCT240 Inverting TEMP. RANGE [ /Title • HC/HCT241 Non-Inverting PART NUMBER (oC) PACKAGE (CD74 • HC/HCT244 Non-Inverting CD54HC240F3A -55 to 125 20 Ld CERDIP H, C240 • TCyLp =ic 1a5l pPFr,o TpAa g=a 2ti5oonC D feolra Hy C=2 84n0s at VCC = 5V, CD54HC244F3A -55 to 125 20 Ld CERDIP CD74 • Three-State Outputs CD54HCT240F3A -55 to 125 20 Ld CERDIP HCT24 • Buffered Inputs CD54HCT241F3A -55 to 125 20 Ld CERDIP 0, • High-Current Bus Driver Outputs CD54HCT244F3A -55 to 125 20 Ld CERDIP CD74 • Fanout (Over Temperature Range) CD74HC240E -55 to 125 20 Ld PDIP HC241 - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads , - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads CD74HC240M -55 to 125 20 Ld SOIC CD74 • Wide Operating Temperature Range . . .-55oC to 125oC CD74HC240M96 -55 to 125 20 Ld SOIC HCT24 • Balanced Propagation Delay and Transition Times CD74HC241E -55 to 125 20 Ld PDIP 1, • Significant Power Reduction Compared to LSTTL CD74HC241M -55 to 125 20 Ld SOIC CD74 Logic ICs HC244 • HC Types CD74HC241M96 -55 to 125 20 Ld SOIC , - 2V to 6V Operation CD74HC244E -55 to 125 20 Ld PDIP CD74 - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V CD74HC244M -55 to 125 20 Ld SOIC • HCT Types CD74HC244M96 -55 to 125 20 Ld SOIC - 4.5V to 5.5V Operation CD74HCT240E -55 to 125 20 Ld PDIP - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) CD74HCT240M -55 to 125 20 Ld SOIC - CMOS Input Compatibility, Il≤1µA at VOL, VOH CD74HCT240M96 -55 to 125 20 Ld SOIC Description CD74HCT240PW -55 to 125 20 Ld TSSOP The ’HC240 and ’HCT240 are inverting three-state buffers CD74HCT240PWR -55 to 125 20 Ld TSSOP having two active-low output enables. The CD74HC241, CD74HCT240PWT -55 to 125 20 Ld TSSOP ’HCT241, ’HC244 and ’HCT244 are non-inverting three- state buffers that differ only in that the 241 has one active- CD74HCT241E -55 to 125 20 Ld PDIP highandoneactive-lowoutputenable,andthe244hastwo active-low output enables. All three types have identical CD74HCT241M -55 to 125 20 Ld SOIC pinouts. CD74HCT241M96 -55 to 125 20 Ld SOIC CD74HCT244E -55 to 125 20 Ld PDIP CD74HCT244M -55 to 125 20 Ld SOIC CD74HCT244M96 -55 to 125 20 Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2004, Texas Instruments Incorporated 1

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 Pinout CD54HC240, CD54HCT240, CD54HCT241, CD54HC244, CD54HCT244 (CERDIP) CD74HC240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244 (PDIP, SOIC) CD74HCT240, (PDIP, SOIC, TSSOP) TOP VIEW 241 241 240 244 244 240 1OE 1OE 1 20 VCC VCC 1A0 1A0 2 19 2OE (241) 2OE (240, 244) 2Y3 2Y3 3 18 1Y0 1Y0 1A1 1A1 4 17 2A3 2A3 2Y2 2Y2 5 16 1Y1 1Y1 1A2 1A2 6 15 2A2 2A2 2Y1 2Y1 7 14 1Y2 1Y2 1A3 1A3 8 13 2A1 2A1 2Y0 2Y0 9 12 1Y3 1Y3 GND GND 10 11 2A0 2A0 Functional Diagram 241 AND 244 240 2 18 1A0 1Y0 1Y0 4 16 1A1 1Y1 1Y1 6 14 1A2 1Y2 1Y2 8 12 1A3 1Y3 1Y3 11 9 2A0 2Y0 2Y0 13 7 2A1 2Y1 2Y1 15 5 2A2 2Y2 2Y2 240 17 3 AND 2A3 2Y3 2Y3 244 241 1 VCC = 20 1OE 1OE GND = 10 19 2OE 2OE 2

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 69oC/W For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . 58oC/W DC Output Diode Current, IOK PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . 83oC/W For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC DC Drain Current, per Output, IO Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC DC Output Source or Sink Current per Output Pin, IO (SOIC - Lead Tips Only) For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance wIth JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V Voltage -7.8 6 5.48 - - 5.34 - 5.2 - V TTL Loads Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V Voltage 7.8 6 - - 0.26 - 0.33 - 0.4 V TTL Loads Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND 3

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Three-State Leakage IOZ VIL or - 6 - - ±0.5 - ±0.5 - ±10 µA Current VIH HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIH or -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage VIL CMOS Loads High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIH or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage VIL CMOS Loads Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCC to 0 5.5 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 2) -2.1 5.5 Input Pin: 1 Unit Load Three-State Leakage IOZ VIL or - 5.5 - - ±0.5 - ±5 - ±10 µA Current VIH NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS HCT240 nA0-A3 1.5 1OE 0.7 2OE 0.7 HCT241 nA0-A3 0.7 1OE 0.7 2OE 1.5 HCT244 nA0-A3 0.7 1OE 0.7 2OE 0.7 NOTE: Unit Load is∆ICClimit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. 4

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 Switching Specifications CL = 50pF, Input tr, tf= 6ns TEST 25oC -40oC TO 85oC -55oC TO 125oC CONDI- VCC PARAMETER SYMBOL TIONS (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS HC TYPES Propagation Delay tPLH, tPHL CL = 50pF Data to Outputs 2 - - 100 - - 125 - - 150 ns HC240 4.5 - - 20 - - 25 - - 30 ns CL = 15pF 5 - 8 - - - - - - - ns CL = 50pF 6 - - 17 - - 21 - - 26 ns Data to Outputs tPLH, tPHL CL = 50pF 2 - - 110 - - 140 - - 165 ns HC241 4.5 - - 22 - - 28 - - 33 ns CL = 15pF 5 - 9 - - - - - - - ns CL = 50pF 6 - - 19 - - 24 - - 28 ns Data to Outputs tPLH, tPHL CL = 50pF 2 - - 110 - - 140 - - 165 ns HC244 4.5 - - 22 - - 28 - - 33 ns CL = 15pF 5 - 9 - - - - - - - ns CL = 50pF 6 - - 19 - - 24 - - 28 ns Output Enable and Disable tTHL, tTLH CL = 50pF 2 - - 150 - - 190 - - 225 ns Time 4.5 - - 30 - - 38 - - 45 ns 5 - 12 - - - - - - - ns 6 - - 26 - - 33 - - 38 ns Output Transition Time tTLH, tTHL CL = 50pF 2 - - 60 - - 75 - - 90 ns 4.5 - - 12 - - 15 - - 18 ns 6 - - 10 - - 13 - - 15 ns Input Capacitance CI CL = 50pF - 10 - 10 - - 10 - - 10 pF Three-State Output CO CL = 50pF - - - 20 - - 20 - - 20 pF Capacitance Power Dissipation Capacitance CPD CL = 15pF (Notes 3, 4) HC240 5 - 38 - - - - - - - pF HC241 5 - 34 - - - - - - - pF HC244 5 - 46 - - - - - - - pF HCT TYPES Propagation Delay Data to Outputs tPHL, tPLH CL = 50pF 4.5 - - 22 - - 28 - - 33 ns HCT240 CL = 15pF 5 - 9 - - - - - - - ns Data to Outputs tPHL, tPLH CL = 50pF 4.5 - - 25 - - 31 - - 38 ns HCT241 CL = 15pF 5 - 10 - - - - - - - ns Data to Outputs tPHL, tPLH CL = 50pF 4.5 - - 25 - - 31 - - 38 ns HCT244 CL = 15pF 5 - 10 - - - - - - - ns 5

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 Switching Specifications CL = 50pF, Input tr, tf= 6ns (Continued) TEST 25oC -40oC TO 85oC -55oC TO 125oC CONDI- VCC PARAMETER SYMBOL TIONS (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Output Enable and Disable tTLH,tTHL CL = 50pF 4.5 - - 30 - - 38 - - 45 ns Times Output Transition Time tTHL, tTLH CL = 50pF 4.5 - - 12 - - 15 - - 18 ns Input Capacitance CI CL = 50pF - 10 - 10 - - 10 - - 10 pF Power Dissipation Capacitance CPD (Notes 3, 4) HCT240 - 5 - 40 - - - - - - - pF HCT241 - 5 - 38 - - - - - - - pF HCT244 - 5 - 40 - - - - - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per channel. 4. PD = VCC2 fi (CPD + CL) where fi =Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% 1.3V INVERTING INVERTING 10% 10% OUTPUT OUTPUT tPHL tPLH tPHL tPLH FIGURE1. HCTRANSITIONTIMESANDPROPAGATION FIGURE2. HCTTRANSITIONTIMESANDPROPAGATION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC 6ns 6ns tr 6ns tf 6ns OUTPUT 90% VCC OUTPUT 2.7 3V DISABLE 50% DISABLE 1.3 10% 0.3 GND GND tPLZ tPZL tPLZ tPZL OUTPUT LOW OUTPUT LOW TO OFF 50% TO OFF 1.3V 10% 10% tPHZ 90% tPZH tPHZ 90% tPZH OUTPUT HIGH OUTPUT HIGH 50% TO OFF TO OFF 1.3V OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS ENABLED DISABLED ENABLED ENABLED DISABLED ENABLED FIGURE3. HCTHREE-STATEPROPAGATIONDELAY FIGURE4. HCTTHREE-STATEPROPAGATIONDELAY WAVEFORM WAVEFORM 6

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 Test Circuits and Waveforms (Continued) OTHER OUTPUT INPUTS IC WITH RL = 1kΩ TIED HIGH THREE- VCC FOR tPLZ AND tPZL OR LOW STATE CL GND FOR tPHZ AND tPZH OUTPUT 50pF OUTPUT DISABLE NOTE: OpendrainwaveformstPLZandtPZLarethesameasthoseforthree-stateshownontheleft.ThetestcircuitisOutputRL=1kΩto VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 7

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) CD54HC240F3A ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 8407401RA CD54HC240F3A CD54HC244F ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 CD54HC244F CD54HC244F3A ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 8409601RA CD54HC244F3A CD54HCT240F3A ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 8550501RA CD54HCT240F3A CD54HCT241F3A ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 CD54HCT241F3A CD54HCT244F ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 CD54HCT244F CD54HCT244F3A ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 8513001RA CD54HCT244F3A CD74HC240E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HC240E (RoHS) CD74HC240M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC240M & no Sb/Br) CD74HC240M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC240M & no Sb/Br) CD74HC241E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HC241E (RoHS) CD74HC241M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC241M & no Sb/Br) CD74HC241M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC241M & no Sb/Br) CD74HC241M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC241M & no Sb/Br) CD74HC241MG4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC241M & no Sb/Br) CD74HC244E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HC244E (RoHS) CD74HC244EE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HC244E (RoHS) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) CD74HC244M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC244M & no Sb/Br) CD74HC244M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC244M & no Sb/Br) CD74HC244M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC244M & no Sb/Br) CD74HC244M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC244M & no Sb/Br) CD74HCT240E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT240E (RoHS) CD74HCT240EE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT240E (RoHS) CD74HCT240M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT240M & no Sb/Br) CD74HCT240M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT240M & no Sb/Br) CD74HCT240MG4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT240M & no Sb/Br) CD74HCT240PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HK240 & no Sb/Br) CD74HCT240PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HK240 & no Sb/Br) CD74HCT240PWT ACTIVE TSSOP PW 20 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HK240 & no Sb/Br) CD74HCT241E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT241E (RoHS) CD74HCT241EE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT241E (RoHS) CD74HCT241M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT241M & no Sb/Br) CD74HCT241M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT241M & no Sb/Br) CD74HCT244E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT244E (RoHS) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) CD74HCT244M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT244M & no Sb/Br) CD74HCT244M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT244M & no Sb/Br) CD74HCT244ME4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT244M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 OTHER QUALIFIED VERSIONS OF CD54HC240, CD54HC244, CD54HCT240, CD54HCT241, CD54HCT244, CD74HC240, CD74HC244, CD74HCT240, CD74HCT241, CD74HCT244 : •Catalog: CD74HC240, CD74HC244, CD74HCT240, CD74HCT241, CD74HCT244 •Military: CD54HC240, CD54HC244, CD54HCT240, CD54HCT241, CD54HCT244 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC240M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HC241M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HC244M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HCT240M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HCT240PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 CD74HCT240PWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 CD74HCT241M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HCT244M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC240M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HC241M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HC244M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT240M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT240PWR TSSOP PW 20 2000 367.0 367.0 38.0 CD74HCT240PWT TSSOP PW 20 250 367.0 367.0 38.0 CD74HCT241M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT244M96 SOIC DW 20 2000 367.0 367.0 45.0 PackMaterials-Page2

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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